LED test data monitoring method and system, computer and storage medium

Abstract

The invention provides an LED test data monitoring method and system, a computer and a storage medium, and the method comprises the following steps: dividing a plurality of first wafer regions, and obtaining a plurality of first crystal grain data sets and a plurality of reverse leakage current data sets through a plurality of first test hardware; determining a plurality of second wafer areas, and obtaining a plurality of second crystal grain data sets through second test hardware; updating the first crystal grain data set into an updated crystal grain data set; calculating a plurality of to-be-evaluated yields based on the reverse leakage current data set and the reverse leakage current threshold; judging whether abnormal first test hardware exists or not based on the to-be-evaluated yield and a yield difference threshold value; and if not, the wafer is conveyed out of the station. The distortion of the test result is reduced by updating the first crystal grain data set; by processing a plurality of to-be-evaluated yield rates, the phenomenon of abnormal yield rate statistics is identified in time, and the deviation among a plurality of test channels is monitored.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method, system, computer and storage medium for monitoring LED test data. Background Art

[0002] In the current LED wafer manufacturing process, each individual die on the wafer needs to be fully parameter tested to control the production quality of the wafer.

[0003] To improve test efficiency, mainstream test equipment typically uses multi-channel parallel technology. By integrating test hardware modules such as electrical excitation, optical sensing, and environmental monitoring, it enables efficient acquisition of parameters across multiple dimensions. Key characteristic parameters such as forward voltage, brightness, and wavelength can be collected.

[0004] However, the results of multi-channel parallel testing are affected by differences in channel hardware performance, such as variations in constant current source accuracy and temperature drift in the sampling circuit. These performance differences lead to fluctuations in electrical parameter measurements across different regions of the same wafer, resulting in systematic distortion of channel test data and inaccurate die yield statistics, which can seriously mislead process optimization decisions. During the testing process, it is difficult to capture channel hardware anomalies and errors in real time. Traditional methods rely on regular manual monitoring and calibration, which has significant lags and easily leads to a large amount of abnormal data flowing into downstream sorting processes, resulting in misjudgments of chip yield. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of the present invention is to provide an LED test data monitoring method, system, computer and storage medium, aiming to solve the problems in the existing technology that it is difficult to detect abnormalities in the test channel hardware in a timely manner, and that channel differences lead to large misjudgments of the yield of the grains on the wafer and distortion of the test data.

[0006] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0007] A method for monitoring LED test data includes the following steps:

[0008] Providing a wafer, dividing the wafer into a plurality of first wafer regions, and performing data acquisition on the plurality of first wafer regions using a plurality of first testing hardware to obtain a plurality of first die data sets and a plurality of reverse leakage current data sets;

[0009] Based on the shape of the wafer and the plurality of first wafer regions, a plurality of second wafer regions are determined, and a plurality of second die data sets are acquired in the plurality of second wafer regions using second testing hardware;

[0010] Based on the plurality of second grain data sets, updating the plurality of first grain data sets into a plurality of updated grain data sets;

[0011] Calculating a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current thresholds;

[0012] Based on the plurality of yield rates to be evaluated and yield difference thresholds, determining whether there is abnormal first test hardware;

[0013] If there is no abnormal first test hardware, the plurality of updated die data sets are combined into a product data set to be associated with the wafer, and the wafer is shipped out.

[0014] Compared with the prior art, the beneficial effects of the present invention are: by obtaining the second grain data set, the multi-channel test data of the machine on the wafer is corrected, that is, the first grain data set in the first wafer area obtained by the first test hardware is corrected, thereby reducing the test data distortion caused by the differences between the hardware of multiple test channels; by analyzing and processing the yields in multiple first wafer areas corresponding to multiple test channels, combined with the yield difference threshold, the statistical abnormality of the yield to be estimated can be identified in time, and the test channel deviation abnormality can be identified, that is, the abnormal first test hardware is identified, to prevent some qualified grains from being misjudged as defective products due to the hardware differences of the test channels, to prevent the omission of grains with actual parameters exceeding the standard, and to provide a standard for whether the machine hardware needs to be calibrated, without the need for manual monitoring and manual regular maintenance, thereby improving production efficiency.

[0015] Furthermore, the step of establishing a plurality of second wafer regions based on the shape of the wafer and the plurality of first wafer regions includes:

[0016] Establishing a reference wafer area based on the diameter of the wafer, wherein the reference wafer area covers the center of the wafer and intersects all of the first wafer areas;

[0017] An area where the reference wafer area intersects the first wafer area is established as a second wafer area, and a plurality of the second wafer areas correspond one-to-one to a plurality of the first wafer areas.

[0018] Furthermore, the step of updating the plurality of first grain data sets into a plurality of updated grain data sets based on the plurality of second grain data sets includes:

[0019] Acquire a first reference value and a second reference value through the second grain data set;

[0020] obtaining a correction coefficient based on the first reference value and the second reference value;

[0021] The first grain dataset is corrected based on the correction coefficient to obtain an updated grain dataset.

[0022] Furthermore, the reverse leakage current data set includes reverse leakage current values of all dies in the first wafer region, and the step of calculating a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current threshold includes:

[0023] Determine the grains in the first wafer region whose reverse leakage current value is less than the reverse leakage current threshold as qualified grains, and obtain the number of qualified grains;

[0024] The total number of grains in the first wafer area is obtained, and the yield to be evaluated is calculated based on the number of qualified grains and the total number of grains.

[0025] Furthermore, the step of determining whether there is abnormal first test hardware based on the plurality of yield rates to be evaluated and yield difference thresholds includes:

[0026] Selecting a maximum yield and a minimum yield from the plurality of yields to be evaluated, and calculating a yield difference based on the maximum yield and the minimum yield;

[0027] If the yield difference is less than the yield difference threshold, determining that there is no abnormal first test hardware;

[0028] If the yield difference is greater than or equal to the yield difference threshold, it is determined that abnormal first test hardware exists.

[0029] Furthermore, the reverse leakage current threshold is 0.1 μA, and the yield difference threshold is 5%.

[0030] Furthermore, after the step of determining whether there is abnormal first test hardware based on the plurality of yield rates to be evaluated and yield difference thresholds, the method further includes:

[0031] If there is any abnormal first test hardware, an alarm is issued to manually calibrate a number of the first test hardware.

[0032] The embodiment of the present invention further provides an LED test data monitoring system and an LED test data monitoring method, wherein the system includes:

[0033] a full test module, configured to provide a wafer, divide the wafer into a plurality of first wafer regions, and perform data acquisition on the plurality of first wafer regions using a plurality of first test hardware to obtain a plurality of first die data sets and a plurality of reverse leakage current data sets;

[0034] a sampling module, configured to establish a plurality of second wafer regions based on the shape of the wafer and the plurality of first wafer regions, and acquire a plurality of second die data sets in the plurality of second wafer regions using second testing hardware;

[0035] an updating module, configured to update a plurality of the first grain data sets into a plurality of updated grain data sets based on a plurality of the second grain data sets;

[0036] A calculation module, configured to calculate a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current thresholds;

[0037] a judgment module, configured to judge whether there is abnormal first test hardware based on a plurality of yield rates to be evaluated and yield difference thresholds;

[0038] The association module is configured to combine the plurality of updated die data sets into a product data set if there is no abnormal first test hardware, so as to associate the data set with the wafer and transport the wafer out of the station.

[0039] An embodiment of the present invention further provides a computer, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the LED test data monitoring method described in the above technical solution is implemented.

[0040] An embodiment of the present invention further provides a storage medium storing a computer program. When the computer program is executed by a processor, the method for monitoring LED test data as described in the above technical solution is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 1 is a flowchart of the LED test data monitoring method according to the first embodiment of the present invention;

[0042] Figure 2 This is a structural block diagram of an LED test data monitoring system in a second embodiment of the present invention;

[0043] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0044] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The drawings illustrate several embodiments of the present invention. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present invention.

[0045] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] See also Figure 1 The LED test data monitoring method in the first embodiment of the present invention includes the following steps:

[0048] Step S10: providing a wafer, dividing the wafer into a plurality of first wafer regions, and performing data acquisition on the plurality of first wafer regions using a plurality of first testing hardware to obtain a plurality of first die data sets and a plurality of reverse leakage current data sets;

[0049] Preferably, the first test hardware is the test channel hardware on the MAP machine. If the number of test channels is 8, then the number of the first test hardware settings is 8. The first test hardware includes a probe. The current source inputs current and voltage to the grain through the probe to test various performances of the grain. The area scanned by the test channel to measure the grain is the first wafer area. The number of the first wafer areas is 8. The first grain data set includes data of all grains measured by a test channel, that is, data of all grains in the first wafer area. The data are key electrical parameters such as forward voltage VF, brightness LOP and wavelength WLD.

[0050] It can be understood that all the grains on the wafer are tested once through 8 test channels, and one grain is only tested by one of the test channels. The 8 test channels obtain 8 groups of test data from 8 first wafer areas, that is, in this embodiment, 8 first grain data sets and 8 reverse leakage current data sets are obtained through MAP full test. The multiple groups of test data are discrete, and their test results are affected by the corresponding first test hardware. The 8 first test hardware are unrelated to each other and lack consistency. Traditional calibration relies on static calibration and cannot dynamically compensate for the channel hardware characteristic offset caused by temperature drift or component aging. After long-term operation, the errors of each first test hardware accumulate and increase, while the judgment standard of grain yield is consistent, resulting in false detection and missed detection when the yield statistics of the data measured by each test channel are performed, and the test data of the entire wafer deviates from the true value, thereby causing production losses and misleading process optimization decisions.

[0051] Step S20: establishing a plurality of second wafer regions based on the shape of the wafer and the plurality of first wafer regions, and acquiring a plurality of second die data sets in the plurality of second wafer regions using second testing hardware;

[0052] Preferably, the test data parameter items in the second die data set are consistent with those in the first die data set, and the second test hardware is test channel hardware on an APC machine.

[0053] The step S20 includes:

[0054] S210: Establishing a reference wafer area based on the diameter of the wafer, where the reference wafer area covers the center of the wafer and intersects with all the first wafer areas;

[0055] Preferably, based on the diameter of the wafer, a band-shaped area around the diameter is established as the reference wafer area. It can be understood that the band-shaped area passes through the center of the wafer. Further, the reference wafer area spans 8 of the first wafer areas and is the central column of the grain array on the wafer.

[0056] S220: Establishing an area where the reference wafer area intersects with the first wafer area as a second wafer area, and a plurality of the second wafer areas correspond one-to-one to a plurality of the first wafer areas.

[0057] It can be understood that the central column of the grain array on the wafer is the column with the most grains, and the grains in this column include grains from the 8 first wafer areas. The second wafer area corresponds to the first wafer area. The data measured by the second test hardware in the second wafer area can provide a correction benchmark for the data measured in the corresponding first wafer area, and the data in the 8 second wafer areas can provide a benchmark for data correction in the 8 test channels.

[0058] Step S30: Based on the plurality of second grain data sets, updating the plurality of first grain data sets into a plurality of updated grain data sets;

[0059] The eight first grain data sets obtained by the MAP full test lack consistency and accuracy. The second grain data set sampled is used as a benchmark to correct the first grain data set to obtain consistent test data for the entire wafer, thereby reducing the systematic distortion of the test data.

[0060] The step S30 includes:

[0061] S310: Acquire a first reference value and a second reference value through the second grain data set;

[0062] Preferably, the second wafer region includes a plurality of dies, the first reference value is obtained by calculating an average value of test data in the second wafer region, and the second reference value is obtained by calculating a total average value of test data in all the second wafer regions.

[0063] S320: Obtaining a correction coefficient based on the first reference value and the second reference value;

[0064] It can be understood that, through a plurality of the first reference values and the second reference values, a relationship trend between the test data in each of the first wafer regions and the overall wafer test data can be obtained.

[0065] S330: Correcting the first grain dataset based on the correction coefficient to obtain an updated grain dataset.

[0066] Preferably, the first grain data set is multiplied by the correction coefficient to increase its consistency with the overall wafer test data to prevent the numerical amplitude of a certain first grain data set from being too large. It can be understood that the consistency between several updated grain data sets can reduce the distortion of the test data of the entire wafer and make the test data more accurate.

[0067] Step S40: calculating a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current thresholds;

[0068] Whether the die is qualified is determined according to the reverse leakage current threshold, thereby obtaining the die yield of each test channel respectively, so as to analyze the confidence of the yield on the entire wafer.

[0069] The step S40 includes:

[0070] S410: Identify the grains in the first wafer region whose reverse leakage current values are less than a reverse leakage current threshold as qualified grains, and obtain the number of qualified grains;

[0071] S420: Obtain the total number of grains in the first wafer area, and calculate the yield to be evaluated based on the number of qualified grains and the total number of grains.

[0072] Preferably, eight yield rates to be evaluated are calculated. If an abnormal yield rate to be evaluated occurs, that is, the value of the yield rate to be evaluated is too large or too small, it indicates that the first test hardware has a large deviation, which can promptly reflect whether the hardware of each test channel is normal.

[0073] Step S50: Based on the plurality of yield rates to be evaluated and yield difference thresholds, determining whether there is abnormal first test hardware.

[0074] Preferably, the yield difference threshold is set to perform a unified analysis on a plurality of yield results to be evaluated, thereby providing a standard for judging abnormal test channels for the testing link in the production process.

[0075] The step S50 includes:

[0076] S510: Selecting a maximum yield and a minimum yield from the plurality of yields to be evaluated, and calculating a yield difference based on the maximum yield and the minimum yield;

[0077] S520: If the yield difference is less than the yield difference threshold, determine that there is no abnormal first test hardware;

[0078] S530: If the yield difference is greater than or equal to the yield difference threshold, it is determined that abnormal first test hardware exists.

[0079] S540: The reverse leakage current threshold is 0.1 μA, and the yield difference threshold is 5%.

[0080] Preferably, S510 to S540, for example, the wafer is fully tested, and the yields to be evaluated corresponding to the 8 test channels are 93.35%, 92.39%, 94.01%, 93.77%, 94.05%, 94.11%, 92.89%, and 93.89%, respectively. The yield difference is 1.72%, and the confidence rule of the yield to be evaluated allows a deviation of 5%, that is, when the yield difference is less than 5%, the test results of each channel are credible, and the differences between the 8 first test hardware are within the allowable range and no calibration is required.

[0081] After step S50, the method further includes:

[0082] S550: If there is any abnormal first test hardware, an alarm is issued to manually calibrate a number of the first test hardware.

[0083] Step S60 : If there is no abnormal first test hardware, a plurality of the updated die data sets are combined into a product data set to associate with the wafer, and the wafer is shipped out of the station.

[0084] It can be understood that when the hardware difference is within the allowable range, the statistical yield of the wafer can be used as a reference for subsequent process optimization, which is beneficial to improving the accuracy of process decisions, and the tested parameters can be used as product data for reference in subsequent production links. If the hardware difference is too large, an alarm will be issued to prompt manual intervention for calibration. The monitoring process of the LED test is timely and does not require long-term manual intervention, avoiding the disadvantages of frequent shutdown inspections and high operation and maintenance costs.

[0085] See also Figure 2 In a second embodiment of the present invention, a LED test data monitoring system is provided, which applies the LED test data monitoring method described in the first embodiment. The system includes:

[0086] The full test module 10 is configured to provide a wafer, divide the wafer into a plurality of first wafer regions, and perform data acquisition on the plurality of first wafer regions using a plurality of first test hardware to obtain a plurality of first die data sets and a plurality of reverse leakage current data sets;

[0087] a sampling module 20 for determining a plurality of second wafer regions based on the shape of the wafer and the plurality of first wafer regions, and acquiring a plurality of second die data sets in the plurality of second wafer regions using second testing hardware;

[0088] The sampling module 20 includes:

[0089] A first unit is configured to establish a reference wafer area based on the diameter of the wafer, where the reference wafer area covers the center of the wafer and intersects all of the first wafer areas;

[0090] The second unit is configured to establish an area where the reference wafer area intersects the first wafer area as a second wafer area, and a plurality of the second wafer areas correspond one-to-one to a plurality of the first wafer areas.

[0091] An updating module 30, configured to update a plurality of the first grain data sets into a plurality of updated grain data sets based on a plurality of the second grain data sets;

[0092] The update module 30 includes:

[0093] A third unit is configured to obtain a first reference value and a second reference value through the second grain data set;

[0094] A fourth unit is configured to obtain a correction coefficient based on the first reference value and the second reference value;

[0095] The fifth unit is configured to correct the first grain dataset based on the correction coefficient to obtain an updated grain dataset.

[0096] A calculation module 40, configured to calculate a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current thresholds;

[0097] The calculation module 40 includes:

[0098] a sixth unit, configured to identify the grains in the first wafer region whose reverse leakage current values are less than a reverse leakage current threshold as qualified grains, and obtain a number of the qualified grains;

[0099] The seventh unit is configured to obtain the total number of grains in the first wafer area, and calculate the yield to be evaluated based on the number of qualified grains and the total number of grains.

[0100] The judgment module 50 is configured to judge whether there is abnormal first test hardware based on a plurality of yield rates to be evaluated and yield difference thresholds.

[0101] The judgment module 50 includes:

[0102] An eighth unit is configured to select a maximum yield and a minimum yield from the plurality of yields to be evaluated, and calculate a yield difference based on the maximum yield and the minimum yield;

[0103] a ninth unit, configured to determine that there is no abnormal first test hardware if the yield difference is less than a yield difference threshold;

[0104] The tenth unit is configured to determine that the first test hardware is abnormal if the yield difference is greater than or equal to a yield difference threshold.

[0105] The eleventh unit is used for the reverse leakage current threshold being 0.1 μA and the yield difference threshold being 5%.

[0106] The association module 60 is configured to combine the plurality of updated die data sets into a product data set if there is no abnormal first test hardware, associate the data set with the wafer, and ship the wafer out of the station.

[0107] The association module 60 includes:

[0108] The twelfth unit is configured to issue an alarm if there is any abnormal first test hardware, so as to manually correct a number of the first test hardware.

[0109] A computer in a third embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the LED test data monitoring method described in the first embodiment is implemented.

[0110] A fourth embodiment of the present invention provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for monitoring LED test data as described in the first embodiment is implemented.

[0111] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0112] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for monitoring LED test data, characterized in that: The steps include: Providing a wafer, dividing the wafer into a plurality of first wafer regions, and performing data acquisition on the plurality of first wafer regions using a plurality of first testing hardware to obtain a plurality of first die data sets and a plurality of reverse leakage current data sets; Based on the shape of the wafer and the plurality of first wafer regions, a plurality of second wafer regions are determined, and a plurality of second die data sets are acquired in the plurality of second wafer regions using second testing hardware; Based on the plurality of second grain data sets, updating the plurality of first grain data sets into a plurality of updated grain data sets; Calculating a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current thresholds; Based on the plurality of yield rates to be evaluated and yield difference thresholds, determining whether there is abnormal first test hardware; If there is no abnormal first test hardware, the plurality of updated die data sets are combined into a product data set to be associated with the wafer, and the wafer is shipped out.

2. The LED test data monitoring method according to claim 1, characterized in that: The step of establishing a plurality of second wafer regions based on the shape of the wafer and the plurality of first wafer regions includes: Establishing a reference wafer area based on the diameter of the wafer, wherein the reference wafer area covers the center of the wafer and intersects all of the first wafer areas; An area where the reference wafer area intersects the first wafer area is established as a second wafer area, and a plurality of the second wafer areas correspond one-to-one to a plurality of the first wafer areas.

3. The LED test data monitoring method according to claim 1, characterized in that: The step of updating the plurality of first grain data sets into a plurality of updated grain data sets based on the plurality of second grain data sets includes: Acquire a first reference value and a second reference value through the second grain data set; obtaining a correction coefficient based on the first reference value and the second reference value; The first grain dataset is corrected based on the correction coefficient to obtain an updated grain dataset.

4. The LED test data monitoring method according to claim 1, wherein: The reverse leakage current data set includes reverse leakage current values of all dies in the first wafer region. The step of calculating a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and reverse leakage current thresholds includes: Determine the grains in the first wafer region whose reverse leakage current value is less than the reverse leakage current threshold as qualified grains, and obtain the number of qualified grains; The total number of grains in the first wafer area is obtained, and the yield to be evaluated is calculated based on the number of qualified grains and the total number of grains.

5. The LED test data monitoring method according to claim 4, characterized in that: The step of determining whether there is abnormal first test hardware based on the plurality of yield rates to be evaluated and yield difference thresholds includes: Selecting a maximum yield and a minimum yield from the plurality of yields to be evaluated, and calculating a yield difference based on the maximum yield and the minimum yield; If the yield difference is less than the yield difference threshold, determining that there is no abnormal first test hardware; If the yield difference is greater than or equal to the yield difference threshold, it is determined that abnormal first test hardware exists.

6. The LED test data monitoring method according to claim 5, characterized in that: The reverse leakage current threshold is 0.1 μA, and the yield difference threshold is 5%.

7. The LED test data monitoring method according to claim 1, characterized in that: After the step of determining whether there is abnormal first test hardware based on the plurality of yield rates to be evaluated and yield difference thresholds, the method further includes: If there is any abnormal first test hardware, an alarm is issued to manually calibrate a number of the first test hardware.

8. An LED test data monitoring system, applying the LED test data monitoring method according to any one of claims 1 to 7, characterized in that: The system comprises: a full test module, configured to provide a wafer, divide the wafer into a plurality of first wafer regions, and perform data acquisition on the plurality of first wafer regions using a plurality of first test hardware to obtain a plurality of first die data sets and a plurality of reverse leakage current data sets; a sampling module, configured to establish a plurality of second wafer regions based on the shape of the wafer and the plurality of first wafer regions, and acquire a plurality of second die data sets in the plurality of second wafer regions using second testing hardware; an updating module, configured to update a plurality of the first grain data sets into a plurality of updated grain data sets based on a plurality of the second grain data sets; A calculation module, configured to calculate a plurality of yields to be evaluated based on the plurality of reverse leakage current data sets and the reverse leakage current thresholds; a judgment module, configured to judge whether there is abnormal first test hardware based on a plurality of yield rates to be evaluated and yield difference thresholds; The association module is configured to combine the plurality of updated die data sets into a product data set if there is no abnormal first test hardware, so as to associate the data set with the wafer and transport the wafer out of the station.

9. A computer comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the LED test data monitoring method according to any one of claims 1 to 7 is implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the LED test data monitoring method according to any one of claims 1 to 7 is implemented.

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