Method, device and equipment for predicting single event latch-up resistance

Abstract

The invention discloses a method, a device and equipment for predicting single-particle latch-up resistance, relates to the technical field of integrated circuits, and aims to solve the problem that an existing single-particle latch-up resistance prediction method depends on a single-particle latch-up irradiation test with high cost and long period. The method comprises the following steps: acquiring latch characteristic data of a target process node; according to the process parameter combination, performing electric latch simulation and single-particle latch simulation on the CMOS standard unit to obtain an electric latch threshold simulation value and a single-particle latch threshold simulation value; constructing an electric latch function and a single particle latch function; based on the electric latch threshold test value and the electric latch function, determining a target solution of the process parameter combination by adopting an optimization method; and determining a predicted value of the single-particle latch-up threshold according to the target solution and the single-particle latch-up function. The method for predicting the single-particle latch-up resistance capability provided by the invention can be used for predicting the single-particle latch-up resistance capability of the integrated circuit without depending on a single-particle latch-up irradiation experiment.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method, device and equipment for predicting single-particle latch-up resistance. Background Art

[0002] In applications such as aerospace, nuclear power, military, and high-energy physics experiments, electronic equipment is exposed to radiation from cosmic rays, radioactive materials, or high-energy particles. When these high-energy particles penetrate CMOS circuits, they can trigger conduction in parasitic PNPN structures, leading to single-event latch-up. As CMOS process technology evolves toward smaller feature sizes, device operating voltages decrease and the size of parasitic structures shrinks, making devices more sensitive to single-event events and increasing the probability of single-event latch-up.

[0003] Single-event latch-up can cause circuit shorts, dramatically increased power consumption, or even permanent device damage, leading to system-level failures. In mission-critical applications, any component failure can have serious consequences, so evaluating the device's resistance to single-event latch-up is crucial to mitigate risk. Traditional methods for evaluating integrated circuits' resistance to single-event latch-up rely on single-event latch-up exposure testing. Such tests typically require high-energy particle radiation environments, expensive experimental equipment, complex setups, and lengthy testing cycles.

[0004] Therefore, there is an urgent need for a method, device and apparatus for predicting the ability to resist single event latch-up. Summary of the Invention

[0005] The object of the present invention is to provide a method, device and equipment for predicting the ability to resist single-particle latch-up, so as to solve the problem that the existing single-particle latch-up ability prediction method relies on the single-particle latch-up irradiation test with high cost and long period.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] The first invention provides a method for predicting single event latchup resistance, comprising:

[0008] Acquiring latch characteristic data of a target process node, wherein the latch characteristic data includes an electrical latch threshold test value and a plurality of process parameter combinations of a CMOS standard cell;

[0009] According to the process parameter combination, performing electrical latch-up simulation and single-particle latch-up simulation on the CMOS standard cell to obtain an electrical latch-up threshold simulation value and a single-particle latch-up threshold simulation value;

[0010] constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and constructing a single event latch function based on the process parameter combination and the single event latch threshold simulation value;

[0011] Determining a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function;

[0012] A predicted value of a single event latch-up threshold is determined based on the target solution and the single event latch-up function.

[0013] Optionally, constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value includes:

[0014] Calculating the Pearson correlation coefficient between each process parameter in the process parameter combination and the electrical latch threshold simulation value;

[0015] Determine the process parameters corresponding to the Pearson correlation coefficients whose absolute values are greater than a preset threshold as linear process parameters, and determine the process parameters corresponding to the Pearson correlation coefficients whose absolute values are less than or equal to the preset threshold as nonlinear process parameters;

[0016] Determining target fitting parameters using a hybrid fitting method based on the linear process parameters, the nonlinear process parameters, and a hybrid fitting model;

[0017] The target fitting parameters are substituted into the hybrid fitting model to obtain an electrical latch function.

[0018] Optionally, calculating the Pearson correlation coefficient between each process parameter in the process parameter combination and the electrical latch threshold simulation value includes:

[0019] Using the formula:

[0020]

[0021] determining a Pearson correlation coefficient between each process parameter in the process parameter combination and a simulated value of an electrical latch threshold;

[0022] Among them, r1 is the Pearson correlation coefficient, x im The value of the mth process parameter in the i-th process parameter combination, y i is x im corresponding electrical latch threshold simulation value; is the average value of different sampling points of the mth process parameter, is the average value of the corresponding electrical latch threshold simulation value, and Sm is the number of sampling points of the process parameter.

[0023] Optionally, the determining the target fitting parameters by adopting a hybrid fitting method based on the linear process parameters, the nonlinear process parameters and the hybrid fitting model includes:

[0024] According to the formula:

[0025]

[0026] Performing linear fitting on the linear process parameters and performing nonlinear fitting on the nonlinear process parameters to obtain target fitting parameters;

[0027] Among them, Y is the electrical latch threshold simulation value, β0, is the target fitting parameter, is the linear process parameter, p1 is the number of linear process parameters, is the nonlinear fitting function, X j1 is a nonlinear process parameter, and M is the number of types of process parameters.

[0028] Optionally, determining a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function includes:

[0029] Determine the gradient and Hessian matrix corresponding to the initial value of the process parameter combination according to the objective function;

[0030] Determining an iterative prediction value of the process parameter combination according to an iterative formula and a gradient and a Hessian matrix corresponding to the initial value;

[0031] Determine whether the iterative prediction value meets the convergence condition. If not, determine the next iterative prediction value based on the iterative prediction value until the determined iterative prediction value meets the convergence condition; determine the iterative prediction value that meets the convergence condition as the target solution.

[0032] Optionally, determining the gradient and Hessian matrix corresponding to the initial value of the process parameter combination according to the objective function includes:

[0033] Using the formula:

[0034]

[0035] Calculating the gradient corresponding to the initial value;

[0036] Among them, when k=1, is the gradient corresponding to the initial value, L is the objective function, and T is the transpose;

[0037] Using the formula:

[0038]

[0039] Calculating the Hessian matrix corresponding to the initial value;

[0040] When k=1, H(a k ) is the Hessian matrix corresponding to the initial value.

[0041] Optionally, determining the iterative prediction value of the process parameter combination according to the iterative formula and the gradient and Hessian matrix corresponding to the initial value includes:

[0042] According to the iterative formula:

[0043]

[0044] Determine iterative prediction value;

[0045] When k=1, a k is the initial value, a k+1 is the iterative prediction value.

[0046] Optionally, obtaining latch characteristic data of the target process node includes:

[0047] Determining process parameters related to latch-up characteristics in the CMOS standard cell and determining a value range of the process parameters;

[0048] Dividing the value range of each process parameter into equal probability intervals, and randomly selecting a sample point in each equal probability interval;

[0049] The sample points of different process parameters are combined to obtain multiple process parameter combinations.

[0050] Compared to the prior art, the present invention provides a method for predicting single-particle latch-up resistance, including: obtaining latch-up characteristic data for a target process node; performing electrical latch-up simulation and single-particle latch-up simulation on a CMOS standard cell based on a process parameter combination to obtain an electrical latch-up threshold simulation value and a single-particle latch-up threshold simulation value; constructing an electrical latch-up function based on the process parameter combination and the electrical latch-up threshold simulation value, and constructing a single-particle latch-up function based on the process parameter combination and the single-particle latch-up threshold simulation value; determining a target solution for the process parameter combination using an optimization method based on the electrical latch-up threshold test value and the electrical latch-up function; and determining a predicted single-particle latch-up threshold value based on the target solution and the single-particle latch-up function. This method, based on the consistency of the underlying principles of electrical latch-up and single-particle latch-up, establishes a correspondence between electrical latch-up and single-particle latch-up by constructing an electrical latch-up function and a single-particle latch-up function, thereby replacing traditional irradiation tests with low-cost electrical latch-up tests and enabling prediction of a circuit's single-particle latch-up resistance without relying on irradiation tests.

[0051] In a second aspect, the present invention provides a device for predicting single event latchup resistance, comprising:

[0052] A latch characteristic data acquisition module, configured to acquire latch characteristic data of a target process node, wherein the latch characteristic data includes an electrical latch threshold test value and a combination of multiple process parameters of a CMOS standard cell;

[0053] An electrical latch-up simulation and single-particle latch-up simulation module, configured to perform electrical latch-up simulation and single-particle latch-up simulation on the CMOS standard cell according to the process parameter combination, and obtain an electrical latch-up threshold simulation value and a single-particle latch-up threshold simulation value;

[0054] an electrical latch function and a single-particle latch function construction module, configured to construct an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and to construct a single-particle latch function based on the process parameter combination and the single-particle latch threshold simulation value;

[0055] a target solution determination module for a process parameter combination, configured to determine a target solution for the process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function;

[0056] A prediction module is configured to determine a predicted value of a single event latchup threshold according to the target solution and the single event latchup function.

[0057] In a third aspect, the present invention provides a device for predicting single event latchup resistance, comprising:

[0058] A communication unit / communication interface, configured to obtain latch-up characteristic data of a target process node, wherein the latch-up characteristic data includes an electrical latch-up threshold test value and a combination of multiple process parameters of a CMOS standard cell;

[0059] a processing unit / processor, configured to perform electrical latch-up simulation and single-event latch-up simulation on the CMOS standard cell according to the process parameter combination, and obtain an electrical latch-up threshold simulation value and a single-event latch-up threshold simulation value;

[0060] constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and constructing a single event latch function based on the process parameter combination and the single event latch threshold simulation value;

[0061] Determining a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function;

[0062] A predicted value of a single event latch-up threshold is determined based on the target solution and the single event latch-up function.

[0063] Compared with the prior art, the beneficial effects of the second aspect apparatus type solution and the third aspect equipment type solution provided by the present invention are the same as the beneficial effects of the single-particle latch-up resistance prediction method described in the above technical solution, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0065] Figure 1 A flowchart of a method for predicting single event latch-up resistance provided by the present invention;

[0066] Figure 2 A schematic structural diagram of a device for predicting single event latch-up resistance provided by the present invention;

[0067] Figure 3 A schematic diagram of the structure of a device for predicting the ability to resist single-particle latch-up provided by the present invention. DETAILED DESCRIPTION

[0068] To facilitate a clear description of the technical solutions of the embodiments of the present invention, the words "first" and "second" are used in the embodiments of the present invention to distinguish between identical or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are merely used to distinguish between different thresholds and do not limit their order. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0069] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0070] In the present invention, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0071] Before introducing the embodiments of the present invention, the following definitions are given for the relevant terms involved in the embodiments of the present invention:

[0072] Optimization method is a method for solving optimization problems. Optimization problem refers to the problem of determining the values of certain optional variables under certain constraints so that the selected objective function is optimized.

[0073] By evaluating the single-particle latch-up resistance of CMOS cells, designers can identify vulnerable areas in the circuit and implement appropriate reinforcement measures, such as layout optimization, device isolation, and process improvements, to enhance radiation resistance. Early assessment and improvement of single-particle latch-up resistance can reduce the high costs of repair, replacement, and mission interruption caused by device failures, especially in environments difficult to maintain, such as deep space probes. Furthermore, radiation-resistant design technology is an important research direction in integrated circuit design. Systematic evaluation can promote the development of new single-particle latch-up resistant materials, device structures, and design methods, and improve the industry's technological level. However, traditional integrated circuit single-particle latch-up resistance assessment relies on costly and time-consuming single-particle latch-up irradiation tests.

[0074] To address the above-mentioned issues, the present invention provides a method, device, and apparatus for predicting the ability to resist single-particle latch-up. Based on the consistency of the underlying principles of electrical latch-up and single-particle latch-up, electrical latch-up simulation is performed using computer-aided design tools to establish a correspondence between key process parameters of CMOS standard cells and their ability to resist electrical latch-up. The electrical latch-up voltage / current threshold for electrical latch-up resistance is quantitatively characterized. At the same time, single-particle latch-up simulation is performed on the same CMOS standard cell using computer-aided design tools to establish a correspondence between key parameters of the CMOS standard cell and their ability to resist single-particle latch-up. Furthermore, a correspondence between electrical latch-up and single-particle latch-up is established, thereby replacing traditional irradiation tests with low-cost electrical latch-up tests. This allows prediction of the circuit's ability to resist single-particle latch-up without relying on irradiation experiments, reducing the cost and cycle of single-particle latch-up prediction. This will be described below with reference to the accompanying drawings.

[0075] See also Figure 1 The present invention provides a method for predicting the ability to resist single-event latch-up, comprising the following steps:

[0076] Step 101: Obtain latch-up characteristic data of a target process node;

[0077] The latch-up characteristic data includes a plurality of process parameter combinations of a CMOS standard cell having a target process node and an electrical latch-up threshold test value obtained by performing an electrical latch-up test on a device having the target process node;

[0078] The process parameter combination is a multidimensional vector consisting of multiple different types of process parameters;

[0079] As an optional method, step 101 can be implemented based on the following steps:

[0080] Determining process parameters related to latch-up characteristics in the CMOS standard cell and determining a value range of the process parameters;

[0081] For example, the target process node is 28nm, 14nm, etc., and the design rules of the manufacturer's CMOS standard cell are given for the target process node. The CMOS standard cell can be an inverter. Process parameters related to the latch-up characteristics, such as well spacing, well depth, doping concentration, etc., are extracted, and the value range of each process parameter is determined according to the rules provided by the manufacturer.

[0082] The value range of each process parameter is divided into equal probability intervals, and a sample point is randomly selected in each equal probability interval; the sample points of different process parameters are combined to obtain the process parameter sample space, which is recorded as {X1, X2,…, X N}, there are N elements, which means there are N combinations of process parameters. i =(x i1 ,x i2 ,…,x iM ) as an example, the element is the i-th process parameter combination, the value of i is {1, 2, 3...n}, where x im is the value of the mth process parameter in the i-th combination, m can be 1 to M, M is the total number of process parameter types in the process parameter combination. The number of process parameter combinations contained in the process parameter sample space depends on the number of process parameter types M selected and the number of sampling points selected for each process parameter. Assume that the number of sampling points for the mth process parameter is S m , then the number of process parameter combinations The sample space {X1,X2,…,X N} is considered as matrix X, X i is the i-th row of the matrix, and the matrix has N rows and M columns. All elements in the process parameter sample space are process parameter combinations of the target process node to be obtained in step 101.

[0083] Step 102: performing electrical latch-up simulation and single event latch-up simulation on the CMOS standard cell according to the process parameter combination to obtain an electrical latch-up threshold simulation value and a single event latch-up threshold simulation value;

[0084] The steps of electrical latch-up simulation are: according to the process parameter combination in the process parameter sample space, use computer-aided design tools such as Sentaurus TCAD to perform electrical latch-up simulation on the CMOS standard cell. The first is geometric modeling: according to the target process node of the CMOS standard cell, such as 28nm or 14nm, design the geometric structure of the device, including the position of the P-well and N-well, the size of the source and drain, the layout of the gate, and set the key parameters in the constructed geometric structure according to the value of each process parameter in the process parameter combination, such as well spacing, well depth and contact hole position; the next is doping definition: set the doping distribution of the P-well and N-well, such as Gaussian distribution or uniform distribution, and determine the doping concentration range according to the numerical value of the process parameters related to the doping concentration range in the process parameter combination; the next is material and physical model setting: for the device material , defining parameters such as electron mobility, recombination rate, and dielectric constant for materials such as silicon and silicon dioxide, and enabling relevant physical models such as drift-diffusion models, carrier recombination models, and thermal effect models. The next step is to set boundary and initial conditions: setting the device's electrode voltages and adding bias voltages to the contacts of the N-well and P-well. Next, the excitation conditions are designed: applying a trigger event to simulate electrical latch-up behavior, gradually increasing the bias voltages of the N-well and P-well, or injecting high current pulses, observing the device's current-voltage response. If latch-up is triggered, key characteristic parameters, such as the trigger voltage or current pulse value, are extracted as the electrical latch-up threshold. Substituting the process parameter combinations in the process parameter sample space one by one into the TCAD simulation tool and performing the above process generates data pairs of N process parameter combinations and electrical latch-up threshold simulation values.

[0085] The steps for single-event latch-up simulation are as follows: Using a computer-aided design tool such as Sentaurus TCAD, single-event latch-up simulation is performed on a standard CMOS cell, based on the process parameter combinations in the process parameter sample space. The geometric modeling and doping definitions are consistent with those for electrical latch-up simulation. The physical model, based on the electrical latch-up model, incorporates a heavy ion implantation model to simulate the charge distribution deposited within the device by ions during a single-event impact. This is achieved by defining a single-event path and setting the linear energy transfer value for the particles along the path. The single-event path can be vertical or inclined. After setting the boundary and initial conditions, a transient simulation is performed to obtain the time-dependent current variation. While keeping all other conditions constant, the linear energy transfer value is gradually increased. When latch-up occurs, the applied linear energy transfer value is considered the single-event latch-up threshold; only when this value is exceeded will single-event latch-up occur. Substituting each process parameter combination in the process parameter sample space into the TCAD simulation tool and following this process, N pairs of process parameter combinations and single-event latch-up threshold simulation values are generated.

[0086] Step 103: constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and constructing a single event latch function based on the process parameter combination and the single event latch threshold simulation value;

[0087] As an optional way, constructing the electrical latch function is accomplished by the following steps:

[0088] Step 1031: Calculating the Pearson correlation coefficient between each process parameter in the process parameter combination and the electrical latch threshold simulation value;

[0089] Specifically, use formula (1):

[0090]

[0091] determining a Pearson correlation coefficient between each process parameter in the process parameter combination and a simulated value of an electrical latch threshold;

[0092] Where r1 is the first Pearson correlation coefficient, that is, the Pearson correlation coefficient between the process parameters and the electrical latch threshold simulation value, x im is the value y of the mth process parameter in the i-th process parameter combination i is x im The corresponding electrical latch threshold simulation value, is the average value of different sampling points of the mth process parameter, is the average value of the corresponding electrical latch threshold simulation value, and Sm is the number of sampling points of the process parameter.

[0093] In practical applications, the mth process parameter in the process parameter combination is selected, and the other M-1 process parameters of the process parameter combination are kept unchanged. The i of the process parameter is varied from 1 to Sm to obtain the first Pearson correlation coefficient corresponding to the process parameter. Then, the calculation of formula (1) is performed on each process parameter of the process parameter combination, that is, m is varied from 1 to M to obtain the first Pearson correlation coefficient of all process parameters.

[0094] The closer the absolute value of the Pearson correlation coefficient is to 1, the stronger the linear correlation is. If the Pearson correlation coefficient is low, a nonlinear relationship exists. A method of setting a preset threshold can be used to classify linearly and nonlinearly correlated process parameters. Specifically, process parameters corresponding to the Pearson correlation coefficients with absolute values greater than the preset threshold are determined as linear process parameters, and process parameters corresponding to the Pearson correlation coefficients with absolute values less than or equal to the preset threshold are determined as nonlinear process parameters. The preset threshold can be set as needed, for example, 0.7, 0.8, etc.

[0095] Step 1032: Based on the linear process parameters, the nonlinear process parameters, and the hybrid fitting model, a hybrid fitting method is used to determine a target fitting parameter, which is referred to as a first target fitting parameter.

[0096] Specifically, the mixed fitting model is shown in formula (2):

[0097]

[0098] Perform linear fitting on the linear process parameters and perform nonlinear fitting on the nonlinear process parameters to obtain target fitting parameters; for the sake of distinction, Formula (2) is recorded as the first mixed fitting model;

[0099] in, is a linear process parameter that is linearly correlated with the electrical latch threshold simulation value, denoted as the first linear process parameter, p1 is the number of linear process parameters, X j1 is a nonlinear process parameter that has a nonlinear correlation with the electrical latch threshold simulation value, denoted as the first nonlinear process parameter, Y is the electrical latch threshold simulation value, β0 is the intercept term, represents the linear part, represents the nonlinear part, is a nonlinear fitting function, which can be a logarithmic, power or exponential function; finally, the least square method is used to determine all the first target fitting parameters, β0, is the target fitting parameter.

[0100] Step 1033: Substitute the first target fitting parameter into the first hybrid fitting model to obtain the electrical latch function.

[0101] As an optional approach, constructing a single-event latch function is accomplished by the following steps:

[0102] Step 1034: Calculate a second Pearson correlation coefficient, where the second Pearson correlation coefficient is a Pearson correlation coefficient between each process parameter in the process parameter combination and the single event latch-up threshold simulation value;

[0103] Specifically, use formula (3):

[0104]

[0105] Calculate the second Pearson correlation coefficient;

[0106] Where r2 is the second Pearson correlation coefficient, that is, the Pearson correlation coefficient between the process parameters and the single event latch-up threshold, x im is the value of the mth process parameter in the i-th combination, x im The corresponding single event latch-up threshold simulation value is z i , is the average value of different sampling points of the mth process parameter, is the average value of the corresponding electrical latch threshold simulation value, and Sm is the number of sampling points of the process parameter.

[0107] In practical applications, the mth process parameter in the process parameter combination is selected, and the remaining M-1 parameters are kept unchanged. The i of the process parameter is varied from 1 to Sm to obtain the second Pearson correlation coefficient corresponding to the process parameter. Then, the calculation of formula (3) is performed on each process parameter in the process parameter combination, that is, m is varied from 1 to M to obtain the second Pearson correlation coefficients of all process parameters.

[0108] The preset threshold in step 1031 is used to determine process parameters that are linearly correlated and nonlinearly correlated with the single-particle latch-up threshold, and the process parameter corresponding to the second Pearson correlation coefficient whose absolute value is greater than the preset threshold is determined as a linear process parameter, and the process parameter corresponding to the second Pearson correlation coefficient whose absolute value is less than or equal to the preset threshold is determined as a nonlinear process parameter.

[0109] Step 1035: Determine second target fitting parameters using a hybrid fitting method based on the linear process parameters corresponding to the single event latch-up threshold simulation value, the nonlinear process parameters corresponding to the single event latch-up threshold simulation value, and the second hybrid fitting model;

[0110] Specifically, the second mixed fitting model is shown in formula (4):

[0111]

[0112] Performing linear fitting on the linear process parameters and performing nonlinear fitting on the nonlinear process parameters to obtain second target fitting parameters;

[0113] Among them, X t2 (t2=1,…p2) is a linear process parameter that is linearly correlated with the electrical latch threshold simulation value, and there are p2 of them in total, which are recorded as the second linear process parameter. j2 is a nonlinear process parameter that has a nonlinear correlation with the electrical latch threshold simulation value, denoted as the second nonlinear process parameter, with a total of M-p2, Z is the single-particle latch threshold simulation value, α0 is the intercept term, represents the linear part, represents the nonlinear part, It is a nonlinear fitting function, which can be a logarithmic, power or exponential function. Finally, the least square method is used to determine all the second target fitting parameters, α0, Fit parameters for the second objective.

[0114] Step 1036: Substitute the second target fitting parameters into the second hybrid fitting model to obtain the single event latch-up function.

[0115] The value of the process parameter combination needs to be solved by the known electrical latch threshold test value and the first hybrid fitting model. Considering the possibility of multiple solutions, the solution is recorded as a solution set A, which includes a series of solutions such as {A1, A2, ...}. {A1, A2, ...} = f -1 (y),f -1 is the symbol of the inverse function, indicating that the problem is an inverse problem. y is the electrical latch threshold test value. The optimization method can be used to solve the inverse problem as follows:

[0116] Step 104: Determine a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function;

[0117] As an optional method, step 104 can be implemented based on the following steps:

[0118] Step 1041: Determine the gradient and Hessian matrix corresponding to the initial value of the process parameter combination according to the objective function;

[0119] The objective function is shown in formula (5):

[0120] L(a)=(f(a)-y) 2 (5)

[0121] L is a multivariate function, a=(a1,a2,…,a n ) is an M-dimensional vector, is the solution of the objective function, y is the electrical latch threshold test value, the goal is to minimize the function, first, select the initial point a of the iteration k =(a k1 ,a k2 ,…,a kn ), where k = 1, calculate the gradient and Hessian matrix of the objective function at the current point. The initial point is the initial value of a given process parameter combination, which can be determined based on needs or experience. The gradient is the vector of partial derivatives of the objective function with respect to each variable, representing the rate of change of the objective function at that point. The Hessian matrix is the second-order derivative matrix of the objective function, containing the second-order partial derivatives of the objective function with respect to all variables.

[0122] Using formula (6):

[0123]

[0124] Calculating the gradient corresponding to the initial value;

[0125] Among them, when k=1, is the gradient corresponding to the initial value, and L is the objective function;

[0126] Using formula (7):

[0127]

[0128] Calculating the Hessian matrix corresponding to the initial value;

[0129] When k=1, H(a k ) is the Hessian matrix corresponding to the initial value.

[0130] Step 1042: determining an iterative prediction value of the process parameter combination according to the iterative formula and the gradient and Hessian matrix corresponding to the initial value;

[0131] According to the iterative formula, as shown in formula (8):

[0132]

[0133] Determine iterative prediction value;

[0134] When k=1, a k Initial value, a k+1 is the iterative prediction value.

[0135] Step 1043: Determine whether the iterative prediction value meets the convergence condition. If not, determine the next iterative prediction value based on the iterative prediction value, that is, add 1 to the value of k, and repeat steps 1041 and 1042 until the determined iterative prediction value meets the convergence condition; determine the iterative prediction value that meets the convergence condition as the target solution; the convergence condition may be that the norm of the gradient corresponding to the iterative prediction value is less than the gradient threshold or the objective function change is less than the target threshold.

[0136] In order to find all solutions and avoid finding solutions that are local optimal solutions rather than global optimal solutions, we will try to iterate from multiple initial points and eventually obtain a solution set A = {a1, a2, ...} consisting of multiple target solutions.

[0137] Step 105: Determine a predicted value of a single event latch-up threshold according to the target solution and the single event latch-up function.

[0138] The target solutions in the solution set are substituted into the single-particle latch function one by one, and the function output value corresponding to each target solution is calculated. All function output values constitute the set of predicted values of the single-particle latch threshold.

[0139] This method, based on the consistency of the underlying principles of electrical latch-up and single-particle latch-up, establishes a correspondence between electrical latch-up and single-particle latch-up by constructing electrical latch-up functions and single-particle latch-up functions. This allows for the prediction of a circuit's resistance to single-particle latch-up to be performed without irradiation testing, using a low-cost electrical latch-up test to replace traditional irradiation testing. Electrical latch-up testing simulates the occurrence of single-particle latch-up by varying the power supply voltage or using specific electrical stimuli. It does not require a high-energy particle radiation source, thus significantly reducing the high costs of experimental equipment, particle accelerators, and radiation sources. Compared to radiation latch-up testing, electrical latch-up testing offers significant advantages in cost, experimental efficiency, controllability, and resource consumption. By using electrical latch-up testing, designers can more quickly and cost-effectively evaluate and optimize a circuit's resistance to latch-up.

[0140] The embodiments of the present invention can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a single processing module. The above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present invention is illustrative and is only a logical functional division. In actual implementation, other division methods may be used.

[0141] In the case of dividing each functional module into corresponding functional modules, Figure 2 FIG. 1 shows a schematic diagram of the structure of a device for predicting the ability of anti-single-particle latch-up provided by the present invention. Figure 2 As shown, the device includes:

[0142] A latch characteristic data acquisition module 201 is configured to acquire latch characteristic data of a target process node, wherein the latch characteristic data includes an electrical latch threshold test value and a combination of multiple process parameters of a CMOS standard cell;

[0143] an electrical latch-up simulation and single event latch-up simulation module 202, configured to perform electrical latch-up simulation and single event latch-up simulation on the CMOS standard cell according to the process parameter combination, and obtain an electrical latch-up threshold simulation value and a single event latch-up threshold simulation value;

[0144] an electrical latch function and single event latch function construction module 203, configured to construct an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and to construct a single event latch function based on the process parameter combination and the single event latch threshold simulation value;

[0145] a target solution determination module 204 for a process parameter combination, configured to determine a target solution for the process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function;

[0146] The prediction module 205 is configured to determine a predicted value of a single event latch-up threshold according to the target solution and the single event latch-up function.

[0147] Optionally, the electrical latch function and single event latch function construction module 203 may specifically include:

[0148] a Pearson correlation coefficient calculation unit, configured to calculate a Pearson correlation coefficient between each process parameter in the process parameter combination and the electrical latch threshold simulation value;

[0149] a process parameter classification unit, configured to determine the process parameters corresponding to the Pearson correlation coefficients having an absolute value greater than a preset threshold as linear process parameters, and to determine the process parameters corresponding to the Pearson correlation coefficients having an absolute value less than or equal to the preset threshold as nonlinear process parameters;

[0150] a target fitting parameter determination unit, configured to determine the target fitting parameter by adopting a hybrid fitting method based on the linear process parameter, the nonlinear process parameter and the hybrid fitting model;

[0151] The electrical latch function establishing unit is used to substitute the target fitting parameters into the hybrid fitting model to obtain the electrical latch function.

[0152] Optionally, the Pearson correlation coefficient calculation unit may be specifically used to:

[0153] Using the formula:

[0154]

[0155] determining a Pearson correlation coefficient between each process parameter in the process parameter combination and a simulated value of an electrical latch threshold;

[0156] Among them, r1 is the Pearson correlation coefficient, x im The value of the mth process parameter in the i-th process parameter combination, y i is x im corresponding electrical latch threshold simulation value; is the average value of different sampling points of the mth process parameter, is the average value of the corresponding electrical latch threshold simulation value, and Sm is the number of sampling points of the process parameter.

[0157] Optionally, the target fitting parameter determination unit may be specifically configured to:

[0158] According to the formula:

[0159]

[0160] Performing linear fitting on the linear process parameters and performing nonlinear fitting on the nonlinear process parameters to obtain target fitting parameters;

[0161] Among them, Y is the electrical latch threshold simulation value, β0, is the target fitting parameter, is the linear process parameter, p1 is the number of linear process parameters, is the nonlinear fitting function, X j1 is a nonlinear process parameter, and M is the number of types of process parameters.

[0162] Optionally, the target solution determination module 204 for the process parameter combination may specifically include:

[0163] A gradient and Hessian matrix determination unit, used for determining the gradient and Hessian matrix corresponding to the initial value of the process parameter combination according to the objective function;

[0164] An iterative prediction value determination unit, configured to determine an iterative prediction value of a process parameter combination according to an iterative formula and a gradient and a Hessian matrix corresponding to the initial value;

[0165] The iterative unit is used to determine whether the iterative prediction value meets the convergence condition. If not, the next iterative prediction value is determined based on the iterative prediction value until the determined iterative prediction value meets the convergence condition; the iterative prediction value that meets the convergence condition is determined as the target solution.

[0166] Optionally, the gradient and Hessian matrix determination unit may be specifically configured to:

[0167] Using the formula:

[0168]

[0169] Calculating the gradient corresponding to the initial value;

[0170] Among them, when k=1, is the gradient corresponding to the initial value, L is the objective function, and T is the transpose;

[0171] Using the formula:

[0172]

[0173] Calculating the Hessian matrix corresponding to the initial value;

[0174] When k=1, H(a k ) is the Hessian matrix corresponding to the initial value.

[0175] Optionally, the iterative prediction value determination unit may be specifically configured to:

[0176] According to the iterative formula:

[0177]

[0178] Determine iterative prediction value;

[0179] When k=1, a k is the initial value, α k+1 is the iterative prediction value.

[0180] Optionally, the latch characteristic data acquisition module 201 may include:

[0181] a process parameter value range determining unit, configured to determine a process parameter related to a latch-up feature in the CMOS standard cell and determine a value range of the process parameter;

[0182] an equal probability interval division unit, configured to divide the value range of each process parameter into equal probability intervals, and randomly select a sample point within each equal probability interval;

[0183] The parameter combination unit is used to combine sample points of different process parameters to obtain multiple process parameter combinations.

[0184] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the interaction between the various modules. It can be understood that in order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0185] In the case of using the corresponding integrated unit, Figure 3 FIG. 1 is a schematic diagram showing the structure of a device for predicting the ability of anti-single-particle latch-up provided by the present invention. Figure 3 As shown, the device includes:

[0186] A communication unit / communication interface, configured to obtain latch-up characteristic data of a target process node, wherein the latch-up characteristic data includes an electrical latch-up threshold test value and a combination of multiple process parameters of a CMOS standard cell;

[0187] a processing unit / processor, configured to perform electrical latch-up simulation and single-event latch-up simulation on the CMOS standard cell according to the process parameter combination, and obtain an electrical latch-up threshold simulation value and a single-event latch-up threshold simulation value;

[0188] constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and constructing a single event latch function based on the process parameter combination and the single event latch threshold simulation value;

[0189] Determining a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function;

[0190] A predicted value of a single event latch-up threshold is determined based on the target solution and the single event latch-up function.

[0191] Among them, the processing unit can be a processor or controller, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It can implement or execute the various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. The processor can also be a combination that implements computing functions, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The communication module can be a transceiver, a transceiver circuit or a communication interface, and the like. The storage module can be a memory.

[0192] like Figure 3 As shown, the processor can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. There can be one or more communication interfaces. The communication interface can use any device such as a transceiver for communicating with other devices or a communication network.

[0193] like Figure 3 As shown, the terminal device may further include a communication line. The communication line may include a path for transmitting information between the components.

[0194] Optional, such as Figure 3As shown, the terminal device may further include a memory. The memory is used to store computer-executable instructions for executing the solution of the present invention, and the execution is controlled by the processor. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the present invention.

[0195] like Figure 3 As shown, the memory can be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a communication line. The memory can also be integrated with the processor.

[0196] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0197] In a specific implementation, as an embodiment, Figure 3 As shown, the processor may include one or more CPUs, such as Figure 3 CPU0 and CPU1 in.

[0198] In a specific implementation, as an embodiment, Figure 3 As shown, the terminal device may include multiple processors, such as Figure 3 Each of these processors can be a single-core processor or a multi-core processor.

[0199] In the above embodiments, all or part of the embodiments can be implemented using software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; an optical medium, such as a digital video disc (DVD); or a semiconductor medium, such as a solid-state drive (SSD).

[0200] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0201] Although the present invention has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. It will be apparent that various modifications and variations may be made to the present invention by those skilled in the art without departing from the spirit and scope of the invention. Thus, the present invention is intended to include such modifications and variations as fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A method for predicting single event latch-up resistance, characterized in that: include: Acquiring latch characteristic data of a target process node, wherein the latch characteristic data includes an electrical latch threshold test value and a plurality of process parameter combinations of a CMOS standard cell; According to the process parameter combination, performing electrical latch-up simulation and single-particle latch-up simulation on the CMOS standard cell to obtain an electrical latch-up threshold simulation value and a single-particle latch-up threshold simulation value; constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and constructing a single event latch function based on the process parameter combination and the single event latch threshold simulation value; Determining a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function; A predicted value of a single event latch-up threshold is determined based on the target solution and the single event latch-up function.

2. The method for predicting the single event latch-up resistance according to claim 1, wherein: The constructing of an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value includes: Calculating the Pearson correlation coefficient between each process parameter in the process parameter combination and the electrical latch threshold simulation value; Determine the process parameters corresponding to the Pearson correlation coefficients whose absolute values are greater than a preset threshold as linear process parameters, and determine the process parameters corresponding to the Pearson correlation coefficients whose absolute values are less than or equal to the preset threshold as nonlinear process parameters; Determining target fitting parameters using a hybrid fitting method based on the linear process parameters, the nonlinear process parameters, and a hybrid fitting model; The target fitting parameters are substituted into the hybrid fitting model to obtain an electrical latch function.

3. The method for predicting the single event latch-up resistance according to claim 2, wherein: Calculating the Pearson correlation coefficient between each process parameter in the process parameter combination and the electrical latch threshold simulation value includes: Using the formula: determining a Pearson correlation coefficient between each process parameter in the process parameter combination and a simulated value of an electrical latch threshold; Among them, r1 is the Pearson correlation coefficient, x im is the value of the mth process parameter in the i-th process parameter combination, y i is x im corresponding electrical latch threshold simulation value; is the average value of different sampling points of the mth process parameter, is the average value of the corresponding electrical latch threshold simulation value, and Sm is the number of sampling points of the process parameter.

4. The method for predicting the single event latch-up resistance according to claim 2, wherein: Determining the target fitting parameters by using a hybrid fitting method based on the linear process parameters, the nonlinear process parameters, and the hybrid fitting model includes: According to the formula: Performing linear fitting on the linear process parameters and performing nonlinear fitting on the nonlinear process parameters to obtain target fitting parameters; Among them, Y is the electrical latch threshold simulation value, β0, is the target fitting parameter, is the linear process parameter, p1 is the number of linear process parameters, is the nonlinear fitting function, X j1 is a nonlinear process parameter, and M is the number of types of process parameters.

5. The method for predicting the single event latch-up resistance according to claim 1, wherein: Determining a target solution of a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function includes: Determine the gradient and Hessian matrix corresponding to the initial value of the process parameter combination according to the objective function; Determining an iterative prediction value of the process parameter combination according to an iterative formula and a gradient and a Hessian matrix corresponding to the initial value; Determine whether the iterative prediction value meets the convergence condition. If not, determine the next iterative prediction value based on the iterative prediction value until the determined iterative prediction value meets the convergence condition; determine the iterative prediction value that meets the convergence condition as the target solution.

6. The method for predicting the single event latch-up resistance according to claim 5, wherein: The gradient and Hessian matrix corresponding to the initial value of the process parameter combination determined according to the objective function include: Using the formula: Calculating the gradient corresponding to the initial value; Among them, when k=1, is the gradient corresponding to the initial value, L is the objective function, and T is the transpose; Using the formula: Calculating the Hessian matrix corresponding to the initial value; When k=1, H(a k ) is the Hessian matrix corresponding to the initial value.

7. The method for predicting the single event latch-up resistance according to claim 5, wherein: The iterative prediction value of the process parameter combination is determined according to the iterative formula and the gradient and Hessian matrix corresponding to the initial value, including: According to the iterative formula: Determine iterative prediction value; When k=1, a k is the initial value, a k+1 is the iterative prediction value.

8. The method for predicting the single event latch-up resistance capability according to claim 1, wherein: The acquiring of latch characteristic data of the target process node includes: Determining process parameters related to latch-up characteristics in the CMOS standard cell and determining a value range of the process parameters; Dividing the value range of each process parameter into equal probability intervals, and randomly selecting a sample point in each equal probability interval; The sample points of different process parameters are combined to obtain multiple process parameter combinations.

9. A device for predicting single event latchup resistance, characterized in that: include: A latch characteristic data acquisition module, configured to acquire latch characteristic data of a target process node, wherein the latch characteristic data includes an electrical latch threshold test value and a combination of multiple process parameters of a CMOS standard cell; An electrical latch-up simulation and single-particle latch-up simulation module, configured to perform electrical latch-up simulation and single-particle latch-up simulation on the CMOS standard cell according to the process parameter combination, and obtain an electrical latch-up threshold simulation value and a single-particle latch-up threshold simulation value; an electrical latch function and a single-particle latch function construction module, configured to construct an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and to construct a single-particle latch function based on the process parameter combination and the single-particle latch threshold simulation value; a target solution determination module for a process parameter combination, configured to determine a target solution for the process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function; A prediction module is configured to determine a predicted value of a single event latchup threshold according to the target solution and the single event latchup function.

10. A device for predicting single event latch-up resistance, characterized in that: include: A communication unit / communication interface, configured to obtain latch-up characteristic data of a target process node, wherein the latch-up characteristic data includes an electrical latch-up threshold test value and a combination of multiple process parameters of a CMOS standard cell; a processing unit / processor, configured to perform electrical latch-up simulation and single-event latch-up simulation on the CMOS standard cell according to the process parameter combination, and obtain an electrical latch-up threshold simulation value and a single-event latch-up threshold simulation value; constructing an electrical latch function based on the process parameter combination and the electrical latch threshold simulation value, and constructing a single event latch function based on the process parameter combination and the single event latch threshold simulation value; Determining a target solution for a process parameter combination using an optimization method based on the electrical latch threshold test value and the electrical latch function; A predicted value of a single event latch-up threshold is determined based on the target solution and the single event latch-up function.

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