Chiplet three-dimensional integrated structure based on reconstructed chip and preparation method of Chiplet three-dimensional integrated structure

Abstract

The invention discloses a Chiplet three-dimensional integrated structure based on a reconstructed chip and a preparation method of the Chiplet three-dimensional integrated structure, and belongs to the technical field of semiconductor packaging. The Chiplet three-dimensional integrated structure comprises a substrate, embedded core particles, copper columns, functional core particles and an organic dry film; the substrate is provided with a chip embedding groove, the Pad surface of the embedded core particle is downwards arranged in the chip embedding groove, the copper column penetrates through the substrate and is connected with the embedded core particle and the functional core particle, the Pad surface of the embedded core particle is connected with one end of the copper column, the other end of the copper column is connected with the functional core particle, and the functional core particle is connected with the chip embedding groove. A chip embedding groove is formed in the substrate, a gap is formed between the embedded core particle and the inner wall of the chip embedding groove, the organic dry film is filled in the gap, vertical conductive through holes are formed in the substrate and the functional core particle and are communicated with each other, and the vertical conductive through holes of the substrate are positioned on two sides of the chip embedding groove. According to the invention, the problems that the Chiplet in the existing reconstructed chip is easy to deviate and the heat dissipation efficiency is low can be solved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor packaging technology, and particularly relates to a chiplet three-dimensional integrated structure based on a reconstructed chip and a preparation method thereof. Background Art

[0002] In the field of three-dimensional integration technology, existing technical solutions have significant structural and process limitations. Patent publication number CN111312697B discloses a three-dimensional stacked integration structure that first uses through-silicon via (TSV) technology and then embeds the chip. The chip is only embedded on one side of the silicon substrate, failing to effectively utilize the area on the other side of the silicon substrate. Although patent publication number CN 105575913B uses the technology of embedding first and then preparing through holes, it is still limited to a single-sided layout mode, utilizing only a single side of the substrate. The through holes are prepared after the chip is embedded, which can easily cause thermal stress damage to the embedded chip or cracking of the dielectric layer, resulting in a decrease in yield. Both solutions rely on adhesive to fix the chip, which has the disadvantages of insufficient interface adhesion, low thermal conductivity efficiency, and chiplet position offset.

[0003] Therefore, a three-dimensional integrated structure based on TSV (Through-Silicon Via) reconstruction technology is urgently needed to reduce chiplet offset and improve the heat dissipation efficiency of the reconstructed chip. Summary of the Invention

[0004] The purpose of the present invention is to provide a chiplet three-dimensional integrated structure based on a reconstructible chip and a preparation method thereof, so as to solve the problems of easy chiplet deviation and low heat dissipation efficiency in existing reconstructible chips.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: First, a chiplet three-dimensional integrated structure based on a reconstructed chip includes: a substrate, an embedded core particle, a copper pillar, a functional core particle, and an organic dry film; The substrate has a chip embedding groove, the Pad surface of the embedded core particle is arranged downward in the chip embedding groove, the copper column passes through the substrate and connects the embedded core particle and the functional core particle, the Pad surface of the embedded core particle is connected to one end of the copper column, and the other end of the copper column is connected to the functional core particle, there is a gap between the embedded core particle and the inner wall of the chip embedding groove, the organic dry film is filled in the gap, the substrate and the functional core particle both have vertical conductive through holes and are connected, and the vertical conductive through holes of the substrate are located on both sides of the chip embedding groove.

[0006] In some embodiments, one or more functional core particles are provided, and multiple functional core particles are stacked.

[0007] In some embodiments, the functional core particle connected to the embedded core particle via the copper pillar is a first functional core particle, and the embedded core particle is disposed in the chip embedding groove of the substrate and forms a reconstructed core particle together with the substrate; The structures of the functional core particles other than the first functional core particle are the same as the structure of the first functional core particle, or the same as the structure of the reconstructed core particle.

[0008] In some embodiments, the substrate has a metal redistribution layer on both the front and back sides.

[0009] In some embodiments, an external lead-out pad is provided on the back surface of the substrate, and a bump solder ball is provided on the external lead-out pad.

[0010] In some embodiments, the substrate is made of silicon, glass, an organic substrate, or ceramics.

[0011] In some embodiments, bottom filling is provided at the connection gap between the copper pillar and the embedded core particle Pad surface.

[0012] In some embodiments, the Pad surface of the embedded core particle is connected to one end of the copper column by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding, and the other end of the copper column is connected to the functional core particle by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding.

[0013] In some embodiments, a plurality of the functional core particles are stacked by metal welding, copper-copper bonding, copper-tin bonding, or gold-tin bonding.

[0014] In a second aspect, a method for preparing a chiplet three-dimensional integrated structure based on a reconstructed chip comprises the following steps: Vertical conductive through holes are provided on both sides of the front surface of the substrate of the reconstructed chip for electroplating filling, and copper pillars for bonding are provided on the front surface of the substrate and between the vertical conductive through holes; After a metal redistribution layer is provided on the front surface of the substrate, the front surface of the substrate is held by using temporary bonding glass; The back surface of the substrate is thinned to expose the vertical conductive through-hole, and a chip embedding groove is provided on the back surface of the substrate to expose the copper pillar; Embedding the embedded core particle into the chip embedding groove, connecting the pad surface of the embedded core particle to one end of the copper pillar, performing underfilling at the connection gap between the copper pillar and the pad surface of the embedded core particle, and then filling the gap between the embedded core particle and the inner wall of the chip embedding groove with an organic dry film; After sequentially providing a metal redistribution layer and an external lead pad on the back side of the substrate, the temporary bonding glass is removed; After connecting the functional core particle to the other end of the copper pillar, a ball is planted on the external lead pad to realize the chiplet three-dimensional integrated structure based on the reconstructed chip.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention sets the Pad surface of the embedded core particle downward in the chip embedding groove, and the copper column penetrates the substrate and connects the embedded core particle and the functional core particle, which can prevent the core particle from shifting at the bottom of the groove; the organic dry film is filled in the gap between the embedded core particle and the inner wall of the chip embedding groove, which can prevent the influence of subsequent process mechanical vibration on the embedded core particle; the present invention sets vertical conductive through holes on both the substrate and the functional core particle and connects them, which can shorten the heat conduction path based on TSV technology and improve heat dissipation efficiency. In addition, the Pad surface of the embedded core particle of the present invention is connected to one end of the copper column, and the other end of the copper column is connected to the functional core particle, realizing direct interconnection, reducing the horizontal wiring length, and reducing signal delay.

[0016] Furthermore, the functional core particles of the present invention are stacked in multiple layers, and the structures of the other functional core particles except the first functional core particle are the same as the structure of the first functional core particle, or the same as the structure of the reconstructed core particle. Different functional core particles can be flexibly combined to meet diverse needs.

[0017] Furthermore, metal redistribution layers are provided on both the front and back sides of the substrate, which can shorten the interconnection path, reduce parasitic capacitance, improve the quality of high-frequency signal transmission, and avoid signal interference.

[0018] Furthermore, bottom filling is provided at the connection gap between the copper pillar and the embedded core particle Pad surface, which can relieve thermal stress, prevent the copper pillar from cracking, and avoid electrical failure caused by metal contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of a chiplet three-dimensional integrated structure based on a reconstructed chip provided in an embodiment, wherein (a) is a schematic diagram of the integration of an embedded core particle and a first functional core particle, and (b) is a schematic diagram of the integration of a first functional core particle and a second functional core particle; Figure 2 A partial schematic diagram of the structure of an existing reconstruction chip; Figure 3 A schematic diagram of embedding a core particle into a chip embedding groove in a chiplet three-dimensional integrated structure provided in an embodiment; Figure 4 A schematic cross-sectional view of preparing a vertical conductive via for a substrate; Figure 5 A schematic cross-sectional view of the copper pillars prepared on the front side of the substrate; Figure 6A cross-sectional schematic diagram of preparing a metal redistribution layer on the front side of a substrate; Figure 7 It is a cross-sectional schematic diagram of the substrate front side after temporary bonding; Figure 8 A schematic cross-sectional view of the substrate backside being thinned to expose the vertical conductive vias (TSVs); Figure 9 A cross-sectional diagram of preparing a chip embedding groove on the back side of the substrate and exposing the copper pillars; Figure 10 This is a cross-sectional diagram of the chip embedded in the groove prepared on the back of the substrate; Figure 11 Schematic diagram of the cross section after preparing the groove on the back of the substrate and filling the gap with dielectric to embed the chip; Figure 12 A schematic cross-sectional view of preparing a multi-layer metal redistribution layer on the back side of a substrate; Figure 13 A cross-sectional diagram of the external lead pads prepared on the back of the substrate; Figure 14 Schematic diagram of the cross section of the substrate after temporary bonding; Figure 15 Schematic diagram of the cross section after metal bonding between the substrate and the functional core particle; Figure 16 This is a cross-sectional diagram of the substrate after the external lead pads are planted; Figure 17 Flowchart of the method for preparing a chiplet three-dimensional integrated structure based on a reconstructed chip provided in the embodiment.

[0020] In the figure, 1. Substrate; 2. Vertical conductive via; 3. Copper pillar; 4. Metal redistribution layer; 5. Temporary bonding glass; 6. Chip embedding groove; 7. Bottom filling; 8. Core pad; 9. Embedded core; 10. Organic dry film; 11. External lead pad; 12. Bump solder ball; 13. First functional core; 14. Second functional core; 15. Die adhesive; 100. Reconstructed core. DETAILED DESCRIPTION

[0021] Hereinafter, only certain exemplary embodiments are briefly described, and the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0022] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operate in a specific orientation, and therefore should not be understood as limiting the present invention.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0024] In the present invention, unless otherwise expressly specified or limited, terms such as "installed," "connected," "connected," and "fixed" should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or communication; direct connection or indirect connection through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0025] like Figure 2 As shown, the structure of the traditional reconstructed chip uses adhesive 15 to fix the core particle to be embedded at the bottom of the chip embedding groove, and the pad of the core particle faces upward. The embedded core particle of this structure is prone to offset in the chip embedding groove during the mounting process, which creates the risk of misalignment between the core particle Pad 8 and the metal rewiring layer 4 in subsequent processes.

[0026] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Example 1 like Figure 1 As shown, this embodiment provides a chiplet three-dimensional integrated structure based on a reconstructed chip, including: a substrate 1, a copper pillar 3, a metal redistribution layer 4, an embedded core particle 9 (i.e. Figure 1 CHIPLET 1), organic dry film 10, external lead pad 11, bump solder ball 12, first functional core particle 13 (i.e. Figure 1 CHIPLET 2) and the second functional core particle 14 (i.e. Figure 1 CHIPLET3); The substrate 1 has a chip embedding groove 6. The embedded core 9 has its pad facing downward and is bonded to the bottom of the chip embedding groove 6 through its own bump solder layer. Together with the substrate 1, it forms a reconstructed core 100. Underfill 7 is provided in the gap between the copper pillar 3 and the pad surface of the embedded core 9 to improve the reliability of the reconstructed core. The copper pillar 3 penetrates the substrate 1 and connects the embedded core particle 9 and the first functional core particle 13. The pad surface of the embedded core particle 9 is connected to one end of the copper pillar 3, and the other end of the copper pillar 3 is connected to the first functional core particle 13. There is a gap between the embedded core particle 9 and the inner wall of the chip embedding groove 6. The gap is a narrow gap with a high aspect ratio. The organic dry film 10 fills the gap and keeps the surface of the first functional core particle after the embedded core particle 9 flat. The substrate 1, the first functional core particle 13 and the second functional core particle 14 are all provided with vertical conductive through holes and are connected. The vertical conductive through holes of the substrate 1 are located on both sides of the chip embedding groove 6. The bottom filler 7 is set in the connection gap between the copper pillar 3 and the Pad surface of the embedded core particle 9; The second functional core particle 14 is stacked on the first functional core particle 13 , and the structure of the second functional core particle 14 is the same as that of the first functional core particle 13 , or the structure of the second functional core particle 14 is the same as that of the reconstructed core particle; The front and back sides of the substrate 1 are both provided with metal redistribution layers 4 . The back side of the substrate 1 is provided with external lead pads 11 , and the external lead pads 11 are provided with bump solder balls 12 .

[0028] The substrate 1 adopts an inorganic substrate or an organic substrate. The material of the inorganic substrate is an inorganic material such as silicon, glass or ceramic. The Pad surface of the embedded core particle is connected to one end of the copper column by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding, and the other end of the copper column is connected to the first functional core particle 13 by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding.

[0029] The first functional core particle 13 and the second functional core particle 14 are stacked by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding.

[0030] Figure 1 The second functional core particle 14 can be a traditionally prepared C2 bump chip, which is directly welded on the upper part of the first functional core particle 13, and forms a micro-module structure with the first functional core particle 13 and the embedded core particle 9. The number of stacking layers of the micro-module structure is not limited to three layers, and more functional chips can be stacked to form a micro-module structure according to actual needs.

[0031] Traditional reconstructed chips use adhesive to fix the core particles, with the pad facing upward. During mounting, it is easy to deviate within the groove, causing the core particle pad to be misaligned with the metal rewiring layer. In this embodiment, the embedded core particle pad faces downward and is directly bonded to the bottom of the groove through the bump soldering layer, forming a stable mechanical connection, eliminating the risk of the core particle deflecting within the groove, ensuring the precise alignment of the core particle pad and the metal rewiring layer, and significantly improving the mounting accuracy and reliability. Bottom filling is set at the connection gap between the copper pillar and the embedded core particle pad surface to fill potential gaps, effectively disperse stress, reduce the risk of mechanical failure caused by mismatch of thermal expansion coefficients, and significantly improve the mechanical strength of the reconstructed core particle. Filling the narrow gap with a high aspect ratio between the embedded core particle and the inner wall of the groove with an organic dry film not only enhances the mechanical stability of the structure, but also provides a flat surface for the subsequent stacking of functional core particles. The substrate, the first functional core particle, and the second functional core particle are electrically interconnected through vertical conductive vias, reducing the resistance and inductance in the signal transmission path and improving the signal transmission efficiency and stability. The copper pillar penetrates the substrate and connects the embedded core particle with the first functional core particle, shortening the signal transmission distance, reducing signal delay and loss, while providing a more reliable electrical connection, helping to improve the overall performance of the chip.

[0032] Furthermore, this embodiment integrates different functional cores using TSV reconstruction technology under different process steps into a three-dimensional chiplet integrated structure, resulting in a three-dimensionally integrated reconfigurable chip. This three-dimensional interconnection and integration of multiple functional cores creates a multi-layer stacked micromodule with excellent functionality. This embodiment enables integration using low-process chips and has broad application prospects and a huge market in the field of advanced electronic packaging.

[0033] Example 2 Different from the first embodiment, in this embodiment, only one functional core particle is provided, namely the first functional core particle. Figure 3 As shown, this embodiment provides a chiplet three-dimensional integrated structure based on a reconstructed chip, including: a substrate 1, a copper pillar 3, a metal redistribution layer 4, an embedded core particle 9 (i.e. Figure 1 CHIPLET 1), organic dry film 10, external lead pad 11, bump solder ball 12, first functional core particle 13 (i.e. Figure 1 CHIPLET 2); The substrate 1 has a chip embedding groove 6. The embedded core 9 has its pad facing downward and is bonded to the bottom of the chip embedding groove 6 through its own bump solder layer. Together with the substrate 1, it forms a reconstructed core 100. Underfill 7 is provided in the gap between the copper pillar 3 and the pad surface of the embedded core 9 to improve the reliability of the reconstructed core. The copper pillar 3 penetrates the substrate 1 and connects the embedded core particle 9 and the first functional core particle 13. The pad surface of the embedded core particle 9 is connected to one end of the copper pillar 3, and the other end of the copper pillar 3 is connected to the first functional core particle 13. There is a gap between the embedded core particle 9 and the inner wall of the chip embedding groove 6. The gap is a narrow gap with a high aspect ratio. The organic dry film 10 fills the gap and keeps the surface of the first functional core particle after the embedded core particle 9 flat. The substrate 1 and the first functional core particle 13 are both provided with vertical conductive through holes and are connected. The vertical conductive through holes of the substrate 1 are located on both sides of the chip embedding groove 6. The bottom filling glue 7 is set in the connection gap between the copper pillar 3 and the embedded core particle 9 Pad surface; the front and back sides of the substrate 1 are both provided with a metal redistribution layer 4, and the back side of the substrate 1 is provided with an external lead-out pad 11, and the external lead-out pad 11 has a bump solder ball 12.

[0034] The material of the substrate 1 is silicon, and the Pad surface of the embedded core particle is connected to one end of the copper column by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding, and the other end of the copper column is connected to the first functional core particle 13 by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding.

[0035] Compared with Example 1, this embodiment reduces the precise alignment, bonding and interconnection steps required for stacking multiple core particles through a single core particle structure, thereby reducing process complexity; this embodiment only includes one functional core particle, and the signal transmission path between core particles is significantly shortened, reducing the impact of signal delay, crosstalk and noise, improving signal integrity and electrical performance, and heat is more easily conducted to the external environment through the substrate and bump solder balls, reducing the risk of local hot spots.

[0036] This embodiment is suitable for application scenarios with strict requirements on power consumption and size, such as wearable devices, IoT sensors, etc. The single-chip structure achieves lower power consumption and smaller size while meeting basic functional requirements.

[0037] Example 3 like Figure 17 As shown, this embodiment provides a method for preparing a chiplet three-dimensional integrated structure based on a reconstructed chip, comprising the following steps: S1: If Figure 4 and Figure 5 As shown, vertical conductive vias 2 (i.e., blind vias) are provided on both sides of the front surface of the substrate 1 of the reconstructed chip for electroplating filling, and copper pillars 3 for bonding are provided on the front surface of the substrate 1 and between the vertical conductive vias 2, laying the foundation for subsequent high-density electrical interconnection between the die and between the substrate 1 and the external circuit. S2: If Figure 6 and Figure 7As shown, after a metal redistribution layer 4 is provided on the front surface of the substrate 1, a temporary bonding glass 5 is provided on the front surface of the substrate for holding. The metal redistribution layer 4 can flexibly adjust the signal routing to meet the requirements of complex chip design. The temporary bonding technology can effectively prevent deformation or damage of the substrate during the back thinning process, ensuring the accuracy and reliability of subsequent process steps. S3: If Figure 8 and Figure 9 As shown, the back side of the substrate 1 is thinned to expose the vertical conductive via 2, and a chip embedding groove 6 is provided on the back side of the substrate 1 to expose the copper pillar 3, which can significantly reduce the overall thickness of the chip and improve the functional density per unit area; S4: As Figure 10 and Figure 11 As shown, the embedded core particle 9 is embedded in the chip embedding groove 6, and the pad surface of the embedded core particle 9 is connected to one end of the copper pillar 3. After the bottom filling 7 is performed at the connection gap between the copper pillar 3 and the pad surface of the embedded core particle 9, the organic dry film 10 is filled into the gap between the embedded core particle 9 and the inner wall of the chip embedding groove 6, which can effectively fix the position of the embedded core particle and eliminate the offset risk in the traditional adhesive fixing method.

[0038] S5: If Figure 12 、 Figure 13 and Figure 14 As shown, after the metal rewiring layer 4 and the external lead-out pad 11 are sequentially arranged on the back side of the substrate 1, the temporary bonding glass 5 is released; wherein the metal rewiring layer 4 and the external lead-out pad 11 are arranged on the back side of the substrate 1, providing a flexible interface solution for connecting the chip 1 with the external circuit.

[0039] S6: As Figure 15 and Figure 16 As shown, after the first functional core particle 13 is connected to the other end of the copper pillar 3, a ball is planted on the external lead pad 11 to realize the chiplet three-dimensional integrated structure based on the reconstructed chip.

[0040] It is known from common technical knowledge that the present invention can be implemented by other embodiments that do not deviate from its spirit or essential features. Therefore, the embodiments disclosed above are merely illustrative in all respects and are not exclusive. All modifications within the scope of the present invention or equivalent to the scope of the present invention are intended to be encompassed by the present invention.

Claims

1. A chiplet three-dimensional integrated structure based on a reconstructed chip, characterized in that: include: Substrate, embedded core particles, copper pillars, functional core particles and organic dry films; The substrate has a chip embedding groove, the Pad surface of the embedded core particle is arranged downward in the chip embedding groove, the copper column passes through the substrate and connects the embedded core particle and the functional core particle, the Pad surface of the embedded core particle is connected to one end of the copper column, and the other end of the copper column is connected to the functional core particle, there is a gap between the embedded core particle and the inner wall of the chip embedding groove, the organic dry film is filled in the gap, the substrate and the functional core particle both have vertical conductive through holes and are connected, and the vertical conductive through holes of the substrate are located on both sides of the chip embedding groove.

2. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: There are one or more functional core particles, and multiple functional core particles are stacked.

3. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: The functional core particle connected to the embedded core particle through the copper column is a first functional core particle, and the embedded core particle is arranged in the chip embedding groove of the substrate and forms a reconstructed core particle together with the substrate; The structures of the functional core particles other than the first functional core particle are the same as the structure of the first functional core particle, or the same as the structure of the reconstructed core particle.

4. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: The front and back sides of the substrate both have metal redistribution layers.

5. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: An external lead-out pad is provided on the back side of the substrate, and a convex solder ball is provided on the external lead-out pad.

6. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: The substrate is made of silicon, glass or ceramic.

7. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: The bottom filling glue is set at the connection gap between the copper column and the embedded core particle Pad surface.

8. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 1, characterized in that: The Pad surface of the embedded core particle is connected to one end of the copper column by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding, and the other end of the copper column is connected to the functional core particle by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding.

9. The chiplet three-dimensional integrated structure based on a reconstructible chip according to claim 2, characterized in that: The plurality of functional core particles are stacked by metal welding, copper-copper bonding, copper-tin bonding or gold-tin bonding.

10. A method for preparing a chiplet three-dimensional integrated structure based on a reconstructed chip, characterized in that: The following steps are involved: Vertical conductive through holes are provided on both sides of the front surface of the substrate of the reconstructed chip for electroplating filling, and copper pillars for bonding are provided on the front surface of the substrate and between the vertical conductive through holes; After a metal redistribution layer is provided on the front surface of the substrate, a temporary bonding glass is used to hold the front surface of the substrate; The back surface of the substrate is thinned to expose the vertical conductive through-hole, and a chip embedding groove is provided on the back surface of the substrate to expose the copper pillar; Embedding the embedded core particle into the chip embedding groove, connecting the pad surface of the embedded core particle to one end of the copper pillar, performing underfilling at the connection gap between the copper pillar and the pad surface of the embedded core particle, and then filling the gap between the embedded core particle and the inner wall of the chip embedding groove with an organic dry film; After sequentially providing a metal redistribution layer and an external lead pad on the back side of the substrate, removing the temporary bonding glass; After connecting the functional core particle to the other end of the copper pillar, a ball is planted on the external lead pad to realize the chiplet three-dimensional integrated structure based on the reconstructed chip.

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