An anti-saturation integrator design method, a distributed fault location device for transmission lines, and an edge computing method

Abstract

The present invention relates to a design method for an anti-saturation integrator, a distributed fault location device for power transmission lines, and an edge computing method. The method comprises receiving a voltage signal output by a flexible Rogowski coil as an input signal; employing a peak detection circuit to detect the input signal and feeding back a corresponding control signal; performing preliminary amplitude attenuation on the input signal based on the control signal when the output voltage of the peak detection circuit exceeds a preset saturation threshold; selecting components and designing parameters for passive and active integrator circuits; and combining active and passive integrator circuits to effectively expand the bandwidth of the integrator. The method also improves the response speed of the peak detection module and achieves rapid gain control. An AGC circuit is designed to automatically adjust the integrator's gain by detecting the amplitude of the input signal, preventing the integrator from saturating due to excessive input signals.

Description

Technical Field

[0001] The present invention relates to the technical field of transmission line fault location, and in particular to a design method for an anti-saturation integrator, a distributed fault location device suitable for transmission lines, and an edge computing method. Background Art

[0002] Currently, transmission line traveling wave monitoring devices have become increasingly common in power system fault detection, but they still have limitations in signal processing and data management. In terms of signal processing, traveling wave location technology relies heavily on the precise detection of transient traveling wave signals generated by faults, particularly the accurate measurement of the arrival time of the traveling wave's head. Traditional integrators present significant design bottlenecks. Commonly used integrators employ a single active or passive design, resulting in performance shortcomings in wide dynamic range signal processing and failing to meet the full-band high-precision and robustness requirements of transmission line fault monitoring. Furthermore, integrators are prone to saturation when faced with strong signal inputs from close-range faults. This phenomenon causes the integrator output to reach its limit, rendering it unable to respond to subsequent critical reflected or transmitted wave signals. This not only results in the loss of traveling wave signal detail but also directly impacts the accurate measurement of the head's arrival time, significantly reducing location accuracy and making it difficult to meet the requirements for high-precision fault location on transmission lines. On the other hand, the traveling wave signal of the power system fault has a wide dynamic range characteristic. The short-distance fault signal is extremely strong while the long-distance fault signal is extremely weak. If the existing integrator lacks anti-saturation design, it will be in a saturated state for a long time when processing strong signals, and it will be difficult to effectively process the weak signals of medium and long-distance faults, which will seriously weaken the reliability of the monitoring device. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an anti-saturation integrator design method, a distributed fault location device suitable for transmission lines, and an edge computing method, so as to overcome the deficiencies in the above-mentioned prior art.

[0004] The present invention solves the above-mentioned technical problem with the following technical solution: A method for designing an anti-saturation integrator suitable for a distributed fault location device for a power transmission line comprises the following steps:

[0005] Step S01: Receive the voltage signal output by the flexible Rogowski coil As input signal;

[0006] Step S02: Detect the input signal using a peak detection circuit , and feedback the corresponding control signal ; When an input signal is detected Reaching the peak value of the input signal When the peak detection circuit output voltage is ,Through component selection and parameter design, the total delay of peak detection is controlled within 5ns;

[0007] Step S03: The gain pre-adjustment module receives the control signal through the voltage-controlled amplifier , when the output voltage of the peak detection circuit When the preset saturation threshold is exceeded, the For input signal Perform preliminary amplitude reduction; if not exceeded, no adjustment is required;

[0008] Step S04: integrating the low-frequency signal through a passive integration circuit, setting the low-frequency cutoff frequency of the circuit to 1 Hz, and selecting components and designing parameters of the passive integration circuit;

[0009] Step S05: amplifying and integrating the high-frequency signal through an active integration circuit, setting the high-frequency cutoff frequency of the circuit to 5 MHz, and selecting components and designing parameters of the active integration circuit;

[0010] Step S06: Based on the component selection and parameter design in the above steps, an anti-saturation integrator that outputs a stable, low-distortion signal is obtained.

[0011] The present invention has the following beneficial effects: It proposes a solution that combines active and passive integrator circuits, effectively expanding the bandwidth of the integrator. It also improves the response speed of the peak detection module to achieve rapid gain control. Furthermore, an AGC circuit is designed to automatically adjust the integrator's gain by detecting the amplitude of the input signal, preventing integrator saturation due to excessive input signals.

[0012] On the basis of the above technical solution, the present invention can also be improved as follows.

[0013] Furthermore, step S02 specifically includes the following steps:

[0014] Step S21: Output voltage of peak detection circuit , , is the peak value of the input signal, is the forward voltage drop of the diode;

[0015] Step S22: Use a high-speed operational amplifier to construct a super diode circuit, and the high-speed operational amplifier's in-phase terminal input signal , the reverse terminal is connected to the cathode of the diode, and the output terminal is connected through the resistor Connect capacitor C to form a negative feedback closed loop to obtain a peak detection circuit;

[0016] Step S23: Equivalent forward resistance of the super diode circuit Determined by the closed-loop gain of the op amp;

[0017] ;

[0018] Where, is the feedback coefficient; is the subsequent load resistance; is the forward resistance of the diode, ; Set up the op amp , , ;

[0019] Step S24: Select COG ceramic capacitor, charging time constant , charging to 90% peak time is about ;

[0020] Step S25: Connect the voltage follower OPA690 after the peak detection circuit, and its input impedance , discharge time constant ;

[0021] Step S26: Select THS3095 as the operational amplifier, with a maximum rise rate SR = 4000V / µs and a gain bandwidth ;

[0022] Step S27: Select LMH7301 as the high-speed comparator, and its delay time Only 3.5ns;

[0023] .

[0024] Furthermore, step S03 specifically includes the following steps:

[0025] Step S31: The gain pre-adjustment module receives the control signal through the voltage-controlled amplifier , the calculation formula is as follows:

[0026] ;

[0027] Where, is the maximum value of the control voltage of the voltage controlled amplifier, is the minimum value of the control voltage of the voltage controlled amplifier, is the maximum value of the expected peak value of the input signal, is the minimum value of the expected peak value of the input signal; is the output voltage of the peak detection circuit;

[0028] Step S32: Set the saturation threshold to ;

[0029] Step S33: Calculate the The control signal when , , forcing the gain to decrease; the gain of the voltage-controlled amplifier is , Gain slope, gain intercept;

[0030] Step S34: Determine the output voltage of the peak detection circuit Whether the saturation threshold is exceeded :

[0031] like , , decays proportionally to ensure ;

[0032] like , , improving small signal sensitivity.

[0033] Further, step S04 specifically includes:

[0034] Step S41: Resistor ,capacitance and input impedance A passive integration circuit is constructed to integrate the low-frequency signal and determine the low-frequency cutoff frequency of the circuit to be 1 Hz;

[0035] Step S42: According to the determined low frequency cut-off frequency, the low frequency cut-off frequency is set to 1 Hz; kΩ, µF, Hz, output voltage , input impedance .

[0036] Further, step S05 specifically includes:

[0037] Step S51: Feedback resistor , integrating capacitor and lead compensation capacitors An active integration circuit is constructed to amplify and integrate the high-frequency signal, and the high-frequency cutoff frequency of the circuit is determined to be 5MHz;

[0038] Step S52: setting the high frequency cutoff frequency to 5 MHz according to the determined high frequency cutoff frequency;

[0039] Selecting the Feedback Resistor kΩ, pF, MHz, pF; the transfer function is:

[0040] .

[0041] The present invention also discloses a distributed fault location device suitable for power transmission lines, comprising a main board, a current sensor, a voltage plate, a flexible Rogowski coil, and an integrator designed using the above-mentioned design method;

[0042] The winding carrier of the flexible Rogowski coil adopts a polyimide flexible circuit board;

[0043] The flexible Rogowski coil uses silicone rubber cable as the skeleton material and non-magnetic polyurethane enameled wire as the winding material.

[0044] The beneficial effect of the present invention is that: through this solution, the anti-saturation ability of the flexible Rogowski coil forms a synergistic effect with the anti-saturation characteristics and wide-band response characteristics of the integrator, solving the distortion problem of traditional current sensors under large currents from the hardware level, and providing high-fidelity signal input for subsequent high-precision fault feature identification of TinyML edge computing, significantly improving the core performance of the fault monitoring device.

[0045] The present invention also discloses an edge computing method applied to a distributed fault location device for a power transmission line, which uses the mainboard of the above-mentioned fault location device for calculation; the method comprises the following steps:

[0046] Step T01: collecting the initial traveling wave signal of the transmission line in real time at a high frequency through a current sensor and a voltage plate;

[0047] Step T02: performing wavelet transform decomposition on the collected initial traveling wave signal, extracting signal features at different scales, and performing preprocessing operations on features at different scales respectively;

[0048] Step T03: extracting time-frequency domain features from the pre-processed initial traveling wave signal through discrete wavelet transform;

[0049] Step T04: Use the extracted time-frequency domain features to train the TCN-LSTM model;

[0050] Step T05: Perform lightweight design on the trained TCN-LSTM model to obtain a lightweight model;

[0051] Step T06: Deploy the lightweight model to the microcontroller based on TinyML to perform edge computing.

[0052] The beneficial effects of the present invention are as follows: the present invention combines TCN-LSTM model training and lightweight design, uses TinyML to deploy to the microcontroller to perform edge computing, reduces the amount of data uploaded by the terminal, and prevents communication congestion; its advantages are efficient processing of fault signals, improved feature recognition capabilities, optimized edge computing efficiency, and reduced communication pressure.

[0053] On the basis of the above technical solution, the present invention can also be improved as follows.

[0054] Furthermore, step T04 specifically includes the following steps:

[0055] Step T41: Divide the extracted time-frequency domain features into a training set, a validation set, and a test set at a ratio of 7:2:1. The training set includes multiple types of samples, including traveling wave amplitude, traveling wave polarity, waveform distortion rate, the fault starting point corresponding to the moment of voltage and current mutation, fault characteristic frequency, and transient energy integral. Each type of sample is aligned according to the time series label.

[0056] Step T42: Input the training set into the left causal convolution module of the TCN neural network to construct an exponential expansion rate superposition structure;

[0057] The first convolution layer uses the expansion rate 1D convolution kernel to extract the short-term local features of the traveling wave signal;

[0058] The second convolution layer uses the expansion rate 1D convolution kernel, capturing feature dependencies at 2 times the time scale;

[0059] The third convolution layer uses the expansion rate 1D convolution kernel, covering the long-range correlation of 4 times the time window;

[0060] By analogy, the subsequent convolutional layer expansion rate is Exponential growth, forming a multi-level feature pyramid;

[0061] Step T43: Each convolutional layer output enters an independent instance normalization layer to eliminate the distribution differences of features at different scales. The normalization formula is:

[0062] ;

[0063] Where, is the channel dimension mean, is the channel dimension variance, and is a learnable parameter;

[0064] Step T44: The normalized data is integrated with spatiotemporal information through the feature fusion layer. After the convolutional features of each layer are aligned according to the time dimension, multi-scale fusion is achieved through weighted summation. The weights are automatically learned by the attention mechanism. The feature fusion formula is as follows:

[0065] ;

[0066] Where, For the Feature map of layer dilation rate, is the corresponding weight;

[0067] Step T45: After the fusion features are batch normalized, nonlinearity is introduced through the GeLU activation function. The formula is as follows:

[0068] ;

[0069] Where, is the cumulative distribution function of the standard normal distribution;

[0070] Step T46: The training set is synchronously input into the residual skip module on the right side of the TCN, and an identity mapping is constructed through a 1×1 convolutional layer to form a cross-layer skip connection;

[0071] Step T47: The activation output of the left TCN module is fused with the skip connection features on the right side in the addition layer. After global average pooling, it is input into the LSTM layer with 128 memory units. Through the collaborative calculation of the forget gate, input gate, and output gate, the long-range dependency characteristics of the traveling wave signal are captured.

[0072] Step T48: The LSTM output sequence enters the self-attention layer, and the attention weight of each time step is calculated through the Query, Key, and Value matrices to highlight the key time points of the time-frequency domain features. The formula is as follows:

[0073] ;

[0074] Where, is the key vector dimension;

[0075] Step T49: After the attention weighted features are reduced in dimension by the fully connected layer, they pass through the fault feature classification layer. The output dimension is the number of fault features. The cross entropy loss function is used to calculate the classification loss. The formula is as follows:

[0076] ;

[0077] Where, is the true label, is the predicted probability;

[0078] Based on the above steps, the trained TCN-LSTM model is obtained.

[0079] Furthermore, step T05 specifically includes the following steps:

[0080] Step T51: Use the TensorFlow Model Optimization Toolkit for quantization-aware training. Quantize the weights and activation values ​​in the model from high-precision 32-bit data types to low-precision data types. Quantize all layers except the sensitive layer to 16 bits. Add a calibration parameter, Scale, to the quantization-sensitive layer for dynamic adjustment.

[0081] Step T52: Use the Keras Pruning API to perform block pruning, directly remove redundant convolution kernels and LSTM units, compress model parameters, and accelerate model inference;

[0082] Step T53: Fine-tuning is used to fine-tune the pruned model to recover the accuracy lost due to structural changes;

[0083] Step T54: quantize the pruned and fine-tuned model into a format compatible with the embedded device architecture;

[0084] Step T55: Convert the model into a binary file and use a model visualization tool to check the integrity of the converted model structure;

[0085] Step T456: Deploy the checked binary file to the microcontroller ESP32.

[0086] Furthermore, the method further comprises the following steps:

[0087] Step T07: Regularly update and maintain the model on the edge computing device, and update the model online based on new fault data and characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 This is a flow chart of the integrator design method of the present invention;

[0089] Figure 2 is a circuit diagram of a peak detection circuit of the present invention;

[0090] Figure 3 is a circuit diagram of a passive integrator of the present invention;

[0091] Figure 4 is a circuit diagram of an active integrator of the present invention;

[0092] Figure 5 It is a schematic diagram of the winding structure of the flexible Rogowski coil of the present invention;

[0093] Figure 6 This is the edge computing flow chart of the present invention. DETAILED DESCRIPTION

[0094] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0095] like Figures 1 to 6 As shown, in embodiment 1, a method for designing an anti-saturation integrator suitable for a distributed fault location device for a power transmission line comprises the following steps:

[0096] Step S01: Receive the voltage signal output by the flexible Rogowski coil As input signal;

[0097] The induced electromotive force of the flexible Rogowski coil is , where mutual inductance Approximately , is the measured current. Since there is no magnetic core, It does not change with the current, thus avoiding the saturation distortion of traditional magnetic core coils under high current. The overlapping winding of the coil further suppresses the external stray magnetic field and reduces the current nonlinear error.

[0098] Step S02: Detect the input signal using a peak detection circuit , and feedback the corresponding control signal ; When an input signal is detected Reaching the peak value of the input signal When the peak detection circuit output voltage is Through component selection and parameter design, the total peak detection delay is controlled within 5ns. This improves response speed and effectively solves the saturation or distortion problem caused by the detection delay of the first peak in the transient traveling wave signal, providing a more timely control signal for the subsequent AGC circuit.

[0099] Step S03: The gain pre-adjustment module receives the control signal through the voltage-controlled amplifier (VCA1) , when the output voltage of the peak detection circuit When the preset saturation threshold is exceeded, the For input signal Perform preliminary amplitude attenuation to ensure that the subsequent integration circuit operates in the linear region; if it does not exceed the limit, no adjustment is required;

[0100] Step S04: integrating the low-frequency signal through a passive integration circuit, setting the low-frequency cutoff frequency of the circuit to 1 Hz, and selecting components and designing parameters of the passive integration circuit;

[0101] Step S05: amplifying and integrating the high-frequency signal through an active integration circuit, setting the high-frequency cutoff frequency of the circuit to 5 MHz, and selecting components and designing parameters of the active integration circuit;

[0102] Step S06: Based on the component selection and parameter design in the above steps, an anti-saturation integrator that outputs a stable, low-distortion signal is obtained.

[0103] This invention proposes a solution that combines active and passive integrator circuits, effectively expanding the integrator's bandwidth. It also improves the response speed of the peak detection module, enabling rapid gain control. Furthermore, an AGC circuit is designed to automatically adjust the integrator's gain by detecting the amplitude of the input signal, preventing integrator saturation due to excessive input signals.

[0104] Example 2: This example is a further improvement on Example 1, and its details are as follows:

[0105] Step S02 specifically includes the following steps:

[0106] The present invention uses a super diode circuit and a capacitor C to form a simple peak detection circuit to detect the peak value of the input signal;

[0107] Step S21: Output voltage of peak detection circuit , , is the peak value of the input signal, is the forward voltage drop of the diode (super diode circuit, its forward conduction voltage );

[0108] The feedforward control loop is connected to the gain pre-adjustment module of the subsequent stage, which quickly transmits the detected peak information to the voltage-controlled amplifier VCA1 to achieve real-time gain pre-adjustment of the input signal;

[0109] This loop is designed to ensure a response time of no more than 5ns, enabling fast gain control. The following is a method to improve the peak detection circuit's response speed to ensure a response time of no more than 5ns.

[0110] Step S22: Use a high-speed operational amplifier to construct a super diode circuit, and the high-speed operational amplifier's in-phase terminal input signal , the reverse terminal is connected to the cathode of the diode, and the output terminal is connected through the resistor Connect capacitor C to form a negative feedback closed loop to obtain a peak detection circuit;

[0111] Step S23: Equivalent forward resistance of the super diode circuit Determined by the closed-loop gain of the op amp;

[0112] ;

[0113] Where, is the feedback coefficient; is the subsequent load resistance; is the forward resistance of the diode, ; In order to meet the design of anti-saturation integrator with low-frequency integration accuracy and high-frequency signal response, the op amp is set , and because the present invention selects the Schottky diode BAT54 ,so , ;

[0114] Step S24: Select COG ceramic capacitor, charging time constant , charging to 90% peak time is about ; Because the charging time is proportional to the capacitance C, reducing C can shorten the charging time, but it will reduce the voltage stability during the peak hold period.

[0115] The capacitor C of the present invention is a COG ceramic capacitor with a leakage current of less than 1nA. To ensure the reliability of the circuit, it is necessary to calculate according to the worst case to avoid the voltage drop rate exceeding the design expectation when the actual leakage current is close to 1nA. COG ceramic capacitors, voltage drop rate , meeting the peak hold requirement of transient traveling waves, is the discharge current, which is equal to the leakage current of the capacitor;

[0116] Step S25: Connect the voltage follower OPA690 after the peak detection circuit, and its input impedance , discharge time constant ; The discharge effect can be almost ignored, ensuring that the peak voltage is stable during the detection period.

[0117] Step S26: To avoid the slew limit and increase delay when driving the capacitor, the present invention uses THS3095 as the operational amplifier, which has a maximum rise rate SR = 4000V / µs and a gain bandwidth ;Meet the equivalent bandwidth of transient traveling wave 5-10ns rising edge signal , there will be no phenomenon of extended charging time due to insufficient unity gain bandwidth or low slew rate of the op amp;

[0118] Step S27: In addition, the threshold judgment time of the high-speed comparator needs to be included in the total delay time; the present invention selects LMH7301 as the high-speed comparator, and its delay time Only 3.5ns;

[0119] .

[0120] This delay ensures that peak detection is completed when the first peak of the transient traveling wave arrives.

[0121] Through the above-mentioned component selection and parameter design, the total delay of peak detection can be controlled within 5ns, meeting the real-time capture requirement of 5-10ns for the rising edge of transient traveling waves.

[0122] Example 3: This example is a further improvement on Example 1, and its details are as follows:

[0123] Step S03 specifically includes the following steps:

[0124] Step S31: The gain pre-adjustment module receives the control signal through the voltage controlled amplifier (VCA1) , the calculation formula is as follows:

[0125] ;

[0126] Where, is the maximum value of the control voltage of the voltage controlled amplifier, is the minimum value of the control voltage of the voltage controlled amplifier, is the maximum value of the expected peak value of the input signal, is the minimum value of the expected peak value of the input signal; is the output voltage of the peak detection circuit;

[0127] Step S32: Set the saturation threshold to (Set according to the withstand voltage value of the back-end circuit);

[0128] Step S33: Calculate the The control signal when , , forcing the gain to decrease; the gain of the voltage-controlled amplifier is , Gain slope, Gain intercept; (different voltage controlled amplifier 、 different values);

[0129] Step S34: Determine the output voltage of the peak detection circuit Whether the saturation threshold is exceeded :

[0130] like , , decays proportionally to ensure ;

[0131] like , , improving small signal sensitivity.

[0132] Example 4: This example is a further improvement on Example 1, and its details are as follows:

[0133] Step S04 specifically includes:

[0134] Step S41: Resistor ,capacitance and input impedance A passive integration circuit is constructed to integrate the low-frequency signal and determine the low-frequency cutoff frequency of the circuit to be 1 Hz;

[0135] Step S42: According to the determined low frequency cut-off frequency, the low frequency cut-off frequency is set to 1 Hz; kΩ, µF, Hz, output voltage , input impedance .

[0136] The circuit diagram of the passive integrator circuit is shown in the attached Figure 3 .

[0137] Example 5: This example is a further improvement on Example 1, and its details are as follows:

[0138] Step S05 specifically includes:

[0139] Step S51: Feedback resistor , integrating capacitor and lead compensation capacitors An active integration circuit is constructed to amplify and integrate the high-frequency signal, and the high-frequency cutoff frequency of the circuit is determined to be 5MHz;

[0140] Step S52: setting the high frequency cutoff frequency to 5 MHz according to the determined high frequency cutoff frequency;

[0141] Selecting the Feedback Resistor kΩ, pF, MHz, pF; the transfer function is:

[0142] .

[0143] The circuit diagram of the active integrator circuit is shown in the attached Figure 4 .

[0144] Example 6, a distributed fault location device suitable for a power transmission line, comprising a current sensor electrically connected to a main board, a voltage plate, a flexible Rogowski coil, and an integrator designed using the design method of any one of Examples 1 to 5;

[0145] The winding carrier of the flexible Rogowski coil adopts a polyimide flexible circuit board;

[0146] The flexible Rogowski coil uses silicone rubber cable as the skeleton material and non-magnetic polyurethane enameled wire as the winding material.

[0147] In specific implementation, the specific structure of the flexible Rogowski coil includes:

[0148] 1) Winding carrier: polyimide flexible circuit board.

[0149] 2) Coil Material: Silicone rubber cable is used as the frame material, and non-magnetic polyurethane enameled wire is used as the coil winding material. Function: Silicone rubber maintains excellent flexibility in high and low temperature, corrosive environments; it is effectively waterproof, moisture-proof, and highly impact-resistant. Non-magnetic polyurethane enameled wire has extremely low magnetic content, which does not cause interference in the coil, maintaining measurement accuracy in actual measurement environments.

[0150] 3) Winding method: overlapping winding method. The inner winding is centered on the conductor and wound evenly and densely in a clockwise direction. Turns; the outer winding is wound in counterclockwise direction Turn ( ), forming a double-layer reverse winding structure, such as Figure 5 As shown in Figure 1. The opposite ends of the inner and outer windings are connected in series, resulting in a superposition of induced electromotive force (EMF) that cancels out the magnetic field coupling caused by the coil's own inductance. Benefit: Overlapping winding increases the coil's sensitivity to magnetic field changes. Under the same magnetic field, it generates a stronger induced electromotive force, enabling more sensitive monitoring of current changes. It also optimizes the uniformity of the magnetic field distribution, resulting in more accurate measurement results.

[0151] 4) Connection between the flexible Rogowski coil and the integrator: The white lead of the flexible Rogowski coil connects to the positive input of the integrator, and the brown lead connects to the negative input. The integrator should be installed close to the flexible Rogowski coil to reduce interference during signal transmission.

[0152] The coil wires are routed through the plug-in interface and connected to the sampling resistor module. The signal from the sampling resistor module is then connected to the subsequent integration circuit. Both ends of the sampling resistor are connected to the BNC sockets on the protective housing. These BNC sockets are connected to shielded twisted-pair cables, with the shield properly grounded to reduce interference from electrostatic and electromagnetic coupling.

[0153] Through the above solution, the anti-saturation capability of the flexible Rogowski coil forms a synergistic effect with the anti-saturation characteristics and wide-band response characteristics of the integrator, solving the distortion problem of traditional current sensors under large currents from the hardware level. It provides high-fidelity signal input for the subsequent high-precision fault feature identification of TinyML edge computing, significantly improving the core performance of the fault monitoring device.

[0154] Example 7, an edge computing method applied to a distributed fault location device for a power transmission line, using the mainboard of the fault location device of Example 6 for calculation, comprises the following steps:

[0155] Step T01: The initial traveling wave signals (including current and voltage signals) of the transmission line are collected in real time at a high frequency through current sensors and voltage plates. These signals are sampled at a high frequency to ensure that the initial traveling wave information of the fault can be captured;

[0156] Step T02: Perform wavelet transform decomposition on the collected initial traveling wave signal to extract signal features at different scales, and perform preprocessing operations on the features at different scales respectively; the preprocessing operations include filtering, denoising and normalization for subsequent processing;

[0157] Step T03: Extract time-frequency domain features from the preprocessed initial traveling wave signal through discrete wavelet transform (DWT);

[0158] Step T04: Use the extracted time-frequency domain features to train the TCN-LSTM model to improve the terminal fault feature recognition capability;

[0159] Step T05: Perform lightweight design on the trained TCN-LSTM model to make it more suitable for running on a microcontroller, thus obtaining a lightweight model.

[0160] Step T06: Based on TinyML, a specific converter is used to deploy the lightweight model to the microcontroller to perform edge computing, thereby reducing the amount of data uploaded by the terminal and preventing congestion in the communication channel. TinyML further improves the model's operating efficiency by implementing an efficient computing scheduling algorithm on the microcontroller, optimizing the model's calculation order and storage method.

[0161] The present invention combines TCN-LSTM model training and lightweight design, uses TinyML to deploy on a microcontroller to perform edge computing, reduces the amount of data uploaded by the terminal, and prevents communication congestion; its advantages lie in efficiently processing fault signals, improving feature recognition capabilities, optimizing edge computing efficiency, and reducing communication pressure.

[0162] Example 8: This example is a further improvement on Example 7, and its details are as follows:

[0163] Step T04 specifically includes the following steps:

[0164] Step T41: Divide the extracted time-frequency domain features into a training set, a validation set, and a test set at a ratio of 7:2:1. The training set includes multiple types of samples, including traveling wave amplitude, traveling wave polarity, waveform distortion rate, the fault starting point corresponding to the moment of voltage and current mutation, fault characteristic frequency, and transient energy integral. Each type of sample is aligned according to the time series label.

[0165] Step T42: Input the training set into the left causal convolution module of the TCN neural network to construct an exponential expansion rate superposition structure;

[0166] The first convolution layer uses the expansion rate 1D convolution kernel to extract the short-term local features of the traveling wave signal;

[0167] The second convolution layer uses the expansion rate 1D convolution kernel, capturing feature dependencies at 2 times the time scale;

[0168] The third convolution layer uses the expansion rate 1D convolution kernel, covering the long-range correlation of 4 times the time window;

[0169] By analogy, the subsequent convolutional layer expansion rate is Exponential growth, forming a multi-level feature pyramid;

[0170] Step T43: Each convolutional layer output enters an independent instance normalization layer to eliminate the distribution differences of features at different scales. The normalization formula is:

[0171] ;

[0172] Where, is the channel dimension mean, is the channel dimension variance, and is a learnable parameter;

[0173] Step T44: The normalized data is integrated with spatiotemporal information through the feature fusion layer. After the convolutional features of each layer are aligned according to the time dimension, multi-scale fusion is achieved through weighted summation. The weights are automatically learned by the attention mechanism. The feature fusion formula is as follows:

[0174] ;

[0175] Where, For the Feature map of layer dilation rate, is the corresponding weight;

[0176] Step T45: After the fusion features are batch normalized, nonlinearity is introduced through the GeLU activation function. The formula is as follows:

[0177] ;

[0178] Where, is the cumulative distribution function of the standard normal distribution;

[0179] Step T46: The training set is synchronously input into the residual skip module on the right side of the TCN, and an identity mapping is constructed through a 1×1 convolutional layer to form a cross-layer skip connection to avoid the vanishing gradient of the deep network;

[0180] Step T47: The activation output of the left TCN module is fused with the skip connection features on the right side in the addition layer. After global average pooling, it is input into the LSTM layer with 128 memory units. Through the collaborative calculation of the forget gate, input gate, and output gate, the long-range dependency characteristics of the traveling wave signal are captured.

[0181] Step T48: The LSTM output sequence enters the self-attention layer, and the attention weight of each time step is calculated through the Query, Key, and Value matrices to highlight the key time points of the time-frequency domain features. The formula is as follows:

[0182] ;

[0183] Where, is the key vector dimension;

[0184] Step T49: After the attention-weighted features are reduced in dimension by the fully connected layer (512 neurons), they pass through the fault feature classification layer. The output dimension is the number of fault features. The cross-entropy loss function is used to calculate the classification loss. The formula is as follows:

[0185] ;

[0186] Where, is the true label, is the predicted probability;

[0187] Based on the above steps, the trained TCN-LSTM model is obtained.

[0188] Example 9: This example is a further improvement on Example 7, and its details are as follows:

[0189] Step T05 specifically includes the following steps:

[0190] Step T51: Use the TensorFlow Model Optimization Toolkit for quantization-aware training. Quantize the weights and activation values ​​in the model from high-precision 32-bit data types to low-precision data types. Except for sensitive layers (such as the LSTM output layer), which retain 16 bits, all other layers are quantized to 8 bits. A calibration parameter, Scale, is added to the quantization-sensitive layers for dynamic adjustment. This reduces the model's storage space and computing resource consumption while ensuring accuracy.

[0191] Step T52: Use the Keras Pruning API to perform block pruning, directly remove redundant convolution kernels and LSTM units, compress model parameters, and accelerate model inference;

[0192] Step T53: Fine-tuning is used to fine-tune the pruned model to recover the accuracy lost due to structural changes;

[0193] Step T54: quantize the pruned and fine-tuned model into a format compatible with the embedded device architecture;

[0194] Step T55: Convert the model into a binary file and use a model visualization tool to check the integrity of the converted model structure;

[0195] Step T456: Deploy the checked binary file to the microcontroller ESP32.

[0196] Example 10: This example is a further improvement on Example 7, and its details are as follows:

[0197] The following steps are also included:

[0198] Step T07: Regularly update and maintain the model on the edge computing device, and update the model online based on new fault data and characteristics. Online updates allow the model to adapt to the ever-changing transmission line operating environment.

[0199] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A design method for an anti-saturation integrator suitable for a distributed fault location device for a transmission line, characterized in that: The steps include: Step S01: Receive the voltage signal output by the flexible Rogowski coil As input signal; Step S02: Detect the input signal using a peak detection circuit , and feedback the corresponding control signal ; When the input signal is detected Reaching the peak value of the input signal When the output voltage of the peak detection circuit is ,Through component selection and parameter design, the total delay of peak detection is controlled within 5ns; Step S03: The gain pre-adjustment module receives the control signal through the voltage-controlled amplifier , when the output voltage of the peak detection circuit When the preset saturation threshold is exceeded, the control signal The input signal Perform preliminary amplitude reduction; if not exceeded, no adjustment is required; Step S04: integrating the low-frequency signal through a passive integration circuit, setting the low-frequency cutoff frequency of the circuit to 1 Hz, and selecting components and designing parameters of the passive integration circuit; Step S05: amplifying and integrating the high-frequency signal through an active integration circuit, setting the high-frequency cutoff frequency of the circuit to 5 MHz, and selecting components and designing parameters of the active integration circuit; Step S06: Based on the component selection and parameter design in the above steps, an anti-saturation integrator that outputs a stable, low-distortion signal is obtained.

2. The anti-saturation integrator design method for a distributed fault location device for a power transmission line according to claim 1, characterized in that: The step S02 specifically includes the following steps: Step S21: Output voltage of peak detection circuit , , is the peak value of the input signal, is the forward voltage drop of the diode; Step S22: Use a high-speed operational amplifier to construct a super diode circuit, and the high-speed operational amplifier's in-phase terminal input signal , the reverse terminal is connected to the cathode of the diode, and the output terminal is connected through the resistor Connecting capacitor C to form a negative feedback closed loop to obtain the peak detection circuit; Step S23: Equivalent forward resistance of the super diode circuit Determined by the closed-loop gain of the op amp; ； Where, is the feedback coefficient; is the subsequent load resistance; is the forward resistance of the diode, ; Set up the op amp , , ; Step S24: Select COG ceramic capacitor, charging time constant , charging to 90% peak time is about ; Step S25: Connect a voltage follower OPA690 after the peak detection circuit, whose input impedance , discharge time constant ; Step S26: Select THS3095 as the operational amplifier, with a maximum rise rate SR = 4000V / µs and a gain bandwidth ; Step S27: Select LMH7301 as the high-speed comparator, and its delay time Only 3.5ns; 。 3. The anti-saturation integrator design method for a distributed fault location device for a power transmission line according to claim 1, characterized in that: The step S03 specifically includes the following steps: Step S31: The gain pre-adjustment module receives the control signal through the voltage-controlled amplifier , the calculation formula is as follows: ； Where, is the maximum value of the control voltage of the voltage controlled amplifier, is the minimum value of the control voltage of the voltage controlled amplifier, is the maximum value of the expected peak value of the input signal, is the minimum value of the expected peak value of the input signal; is the output voltage of the peak detection circuit; Step S32: Set the saturation threshold to ; Step S33: Calculate the The control signal when , , forcing the gain to decrease; the gain of the voltage-controlled amplifier is , Gain slope, gain intercept; Step S34: Determine the output voltage of the peak detection circuit Whether it exceeds the saturation threshold : like , , decays proportionally to ensure ; like , , improving small signal sensitivity.

4. The anti-saturation integrator design method for a distributed fault location device for a power transmission line according to claim 1, characterized in that: The step S04 specifically includes: Step S41: Resistor ,capacitance and input impedance Constructing the passive integration circuit to integrate the low-frequency signal and determine the low-frequency cutoff frequency of the circuit to be 1 Hz; Step S42: According to the determined low frequency cut-off frequency, the low frequency cut-off frequency is set to 1 Hz; kΩ, µF, Hz, output voltage , input impedance .

5. The anti-saturation integrator design method for a distributed fault location device for a power transmission line according to claim 1, characterized in that: The step S05 specifically includes: Step S51: Feedback resistor , integrating capacitor and lead compensation capacitors The active integration circuit is constructed to amplify and integrate the high-frequency signal, and the high-frequency cutoff frequency of the circuit is determined to be 5 MHz; Step S52: setting the high frequency cutoff frequency to 5 MHz according to the determined high frequency cutoff frequency; Selecting the Feedback Resistor kΩ, pF, MHz, pF; the transfer function is: 。 6. A distributed fault location device suitable for transmission lines, characterized in that: It comprises a main board, a current sensor, a voltage plate, a flexible Rogowski coil and an integrator designed by the design method according to any one of claims 1 to 5; The winding carrier of the flexible Rogowski coil adopts a polyimide flexible circuit board; The flexible Rogowski coil adopts silicone rubber cable as the skeleton material and non-magnetic polyurethane enameled wire as the winding material.

7. An edge computing method applied to a distributed fault location device for a transmission line, characterized in that: The mainboard of the fault location device of claim 6 is used for calculation; the steps include: Step T01: collecting the initial traveling wave signal of the transmission line in real time at a high frequency through a current sensor and a voltage plate; Step T02: performing wavelet transform decomposition on the collected initial traveling wave signal, extracting signal features at different scales, and performing preprocessing operations on the features at different scales respectively; Step T03: extracting time-frequency domain features from the pre-processed initial traveling wave signal through discrete wavelet transform; Step T04: training the TCN-LSTM model using the extracted time-frequency domain features; Step T05: Perform lightweight design on the trained TCN-LSTM model to obtain a lightweight model; Step T06: Deploy the lightweight model to a microcontroller based on TinyML to perform edge computing.

8. The edge computing method applied to a distributed fault location device for power transmission lines according to claim 7, characterized in that: The step T04 specifically includes the following steps: Step T41: Divide the extracted time-frequency domain features into a training set, a validation set, and a test set at a ratio of 7:2:1, wherein the training set includes multiple types of samples including traveling wave amplitude, traveling wave polarity, waveform distortion rate, fault starting point corresponding to the moment of voltage and current mutation, fault characteristic frequency, and transient energy integral. Each type of sample is aligned according to the time series label; Step T42: inputting the training set into the left causal convolution module of the TCN neural network to construct an exponential expansion rate superposition structure; The first convolution layer uses the expansion rate 1D convolution kernel to extract the short-term local features of the traveling wave signal; The second convolution layer uses the expansion rate 1D convolution kernel, capturing feature dependencies at 2 times the time scale; The third convolution layer uses the expansion rate 1D convolution kernel, covering the long-range correlation of 4 times the time window; By analogy, the subsequent convolutional layer expansion rate is Exponential growth, forming a multi-level feature pyramid; Step T43: Each convolutional layer output enters an independent instance normalization layer to eliminate the distribution differences of features at different scales. The normalization formula is: ； Where, is the channel dimension mean, is the channel dimension variance, and is a learnable parameter; Step T44: The normalized data is integrated with spatiotemporal information through the feature fusion layer. After the convolutional features of each layer are aligned according to the time dimension, multi-scale fusion is achieved through weighted summation. The weights are automatically learned by the attention mechanism. The feature fusion formula is as follows: ； Where, For the Feature map of layer dilation rate, is the corresponding weight; Step T45: After the fusion features are batch normalized, nonlinearity is introduced through the GeLU activation function. The formula is as follows: ； Where, is the cumulative distribution function of the standard normal distribution; Step T46: The training set is synchronously input into the residual skip module on the right side of the TCN, and an identity mapping is constructed through a 1×1 convolutional layer to form a cross-layer skip connection; Step T47: The activation output of the left TCN module is fused with the skip connection features on the right side in the addition layer. After global average pooling, it is input into the LSTM layer with 128 memory units. Through the collaborative calculation of the forget gate, input gate, and output gate, the long-range dependency characteristics of the traveling wave signal are captured. Step T48: The LSTM output sequence enters the self-attention layer, and the attention weight of each time step is calculated through the Query, Key, and Value matrices to highlight the key time points of the time-frequency domain features. The formula is as follows: ； Where, is the key vector dimension; Step T49: After the attention weighted features are reduced in dimension by the fully connected layer, they pass through the fault feature classification layer. The output dimension is the number of fault features. The cross entropy loss function is used to calculate the classification loss. The formula is as follows: ； Where, is the true label, is the predicted probability; Based on the above steps, the trained TCN-LSTM model is obtained.

9. The edge computing method applied to a distributed fault location device for power transmission lines according to claim 7, characterized in that: The step T05 specifically includes the following steps: Step T51: Use the TensorFlow Model Optimization Toolkit for quantization-aware training. Quantize the weights and activation values ​​in the model from high-precision 32-bit data types to low-precision data types. Quantize all layers except the sensitive layer to 16 bits. Add a calibration parameter, Scale, to the quantization-sensitive layer for dynamic adjustment. Step T52: Use the Keras Pruning API to perform block pruning, directly remove redundant convolution kernels and LSTM units, compress model parameters, and accelerate model inference; Step T53: Fine-tuning is used to fine-tune the pruned model to recover the accuracy lost due to structural changes; Step T54: quantize the pruned and fine-tuned model into a format compatible with the embedded device architecture; Step T55: Convert the model into a binary file and use a model visualization tool to check the integrity of the converted model structure; Step T456: Deploy the checked binary file to the microcontroller ESP32.

10. The edge computing method applied to a distributed fault location device for a power transmission line according to claim 7, characterized in that: The following steps are also included: Step T07: Regularly update and maintain the model on the edge computing device, and update the model online based on new fault data and characteristics.

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