Automatic frequency locking circuit based on time-to-voltage converter and phase-locked loop

Abstract

The invention provides an automatic frequency locking circuit based on a time-to-voltage converter and a phase-locked loop, and relates to the technical field of phase-locked loops, a first frequency-halving unit and a second frequency-halving unit respectively carry out frequency-halving processing on a reference signal and a frequency division signal of a current comparison period to obtain a first square wave signal and a second square wave signal; the first square wave signal and the second square wave signal are transmitted to the time-to-voltage converter; the time voltage converter comprises a phase generation unit, a first charge pump and a second charge pump, the phase generation unit generates an enable signal according to the first square wave signal and the second square wave signal, and the first charge pump and the second charge pump respond to control of the enable signal and collect single pulse signals from the first square wave signal and the second square wave signal respectively so as to supply power to the input end of the comparator; the comparator compares power supply voltages of the two input ends to achieve frequency comparison of the reference signal and the frequency division signal. And selection in a plurality of phase signals is not needed, and required digital circuit modules are reduced, so that the delay of the reference signal and the frequency division signal in the conversion process is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loops, and in particular to an automatic frequency locking circuit and a phase-locked loop based on a time-to-voltage converter. Background Art

[0002] In a traditional broadband Phase-Locked Loop (PLL), the output frequency of the Voltage-Controlled Oscillator (VCO) is affected by process, temperature, and power supply noise (PVT) and becomes unpredictable.

[0003] To achieve smaller VCO gain and thus optimize VCO phase noise, wideband PLLs typically use segmented tuning. This requires that each output frequency band exceed the target frequency band by 30% to ensure the VCO can output the target frequency under varying conditions. Segmented tuning requires a VCO band selector circuit to find the band that best suits the target frequency. When the VCO output frequency exhibits minimal PVT variation, the VCO band selector circuit can be directly implemented using an external digital code. However, this circuit lacks robustness and can cause the PLL to lose lock. Therefore, an automatic frequency calibration (AFC) circuit can be used to automatically select the frequency band.

[0004] Existing AFC circuits fall into two categories: traditional counter-type AFC circuits and time-to-voltage converters (TVC)-type AFC circuits. Traditional counter-type AFC circuits use a complex data circuit counter structure to directly compare the periods of the divided signal and the reference signal in the time domain. This results in high circuit complexity, high power consumption, and a large circuit area. TVC-type AFC circuits do not require a complex data circuit counter structure, but they do require an additional phase selection circuit to ensure that the initial phase difference between the reference signal and the divided signal is less than 90 degrees to prevent the charge pump from losing lock. To achieve this, the phase selection circuit must select the optimal signal from multiple phase signals, requiring a relatively large number of digital circuit modules, resulting in a relatively high delay during the conversion process between the reference signal and the divided signal. Summary of the Invention

[0005] The present invention provides an automatic frequency locking circuit and a phase-locked loop based on a time-to-voltage converter, which solves the problem that a phase selection circuit needs to select the best signal from multiple phase signals, and the required digital circuit modules are relatively large, resulting in a relatively high delay between the reference signal and the frequency-divided signal during the conversion process.

[0006] The present invention provides an automatic frequency locking circuit based on a time-voltage converter, comprising a first two-frequency division unit, a second two-frequency division unit, a time-voltage converter and a comparator; The first frequency-dividing unit is used to perform frequency-dividing processing on the reference signal of the current comparison period to obtain a first square wave signal, and transmit the first square wave signal to the time-to-voltage converter; The second frequency-dividing unit is used to perform frequency-dividing processing on the frequency-dividing signal of the current comparison period to obtain a second square wave signal, and transmit the second square wave signal to the time-to-voltage converter; The time-to-voltage converter includes a phase generating unit, a first charge pump, and a second charge pump. The phase generating unit is configured to generate an enable signal according to the first square wave signal and the second square wave signal. The first charge pump is configured to collect a single pulse signal from the first square wave signal in response to the control of the enable signal to supply power to one input terminal of the comparator. The second charge pump is configured to collect a single pulse signal from the second square wave signal in response to the control of the enable signal to supply power to the other input terminal of the comparator. The comparator is used to compare the supply voltages of the two input terminals to achieve frequency comparison between the reference signal and the frequency-divided signal.

[0007] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the first charge pump includes a first NAND gate and a first current mirror, the first input end of the first NAND gate is used to receive the first square wave signal, the second input end of the first NAND gate is used to receive the enable signal, the output end of the first NAND gate is connected to the control end of the first current mirror, and the circuit structure of the second charge pump is the same as the circuit structure of the first charge pump.

[0008] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the first current mirror includes a first current source and a first switching tube, the output end of the first current source is connected to the drain of the first switching tube, the gate of the first switching tube is connected to the output end of the first NAND gate, and the source of the first switching tube is connected to an input end of the comparator.

[0009] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the phase generation unit includes a first sequential logic module, a second sequential logic module, a third sequential logic module and a delay module, wherein the first sequential logic module is used to determine a first charging state signal based on a comparison period control signal and the first square wave signal, the second sequential logic module is used to determine a second charging state signal based on the comparison period control signal and the second square wave signal, the third sequential logic module is used to determine a comparison period control signal of a current comparison period based on a reference signal, a frequency division signal, a first charging state signal and a second charging state signal of a previous comparison period, the delay module is used to determine a reset signal based on the first charging state signal and the second charging state signal of the current comparison period, the reset signal being used to feed back to the first sequential logic module, the second sequential logic module and the third sequential logic module, wherein the comparison period control signal is used to indicate the start and end of each comparison period.

[0010] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the enable signal includes a first enable signal and a second enable signal, the first enable signal being determined based on the product of a comparison period control signal and the first charge state signal, and being used to control the first charge pump; the second enable signal being determined based on the product of the comparison period control signal and the second charge state signal, and being used to control the second charge pump; Among them, the first charging status signal is used to indicate whether the first charge pump has supplied power to one input terminal of the comparator in the current comparison cycle, so as to ensure that power is supplied only once in the current comparison cycle, and the second charging status signal is used to indicate whether the second charge pump has supplied power to the other input terminal of the comparator in the current comparison cycle, so as to ensure that power is supplied only once in the current comparison cycle.

[0011] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, a first capacitor discharge unit is provided at a common end of the first charge pump and the comparator, and the first charge pump supplies power to one input end of the comparator through the first capacitor discharge unit; a second capacitor discharge unit is provided at a common end of the second charge pump and the comparator, and the second charge pump supplies power to the other input end of the comparator through the second capacitor discharge unit.

[0012] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the first capacitor discharge unit and the second capacitor discharge unit are symmetrically arranged.

[0013] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the output end of the comparator is connected to a NOR gate, and the NOR gate is used to generate a reset signal according to the comparison result output by the comparator.

[0014] According to an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention, the two input terminals of the comparator are respectively connected to reset switches, and the reset switches reset the two input terminals of the comparator in response to the control of a reset signal.

[0015] The present invention further provides a phase-locked loop comprising any one of the automatic frequency locking circuits based on a time-to-voltage converter.

[0016] The present invention provides an automatic frequency locking circuit and phase-locked loop based on a time-to-voltage converter. The first two-frequency division unit and the second two-frequency division unit process the reference signal and the frequency-divided signal respectively, and transmit the first square wave signal and the second square wave signal obtained after the processing to the time-to-voltage converter. The time-to-voltage converter supplies power to the comparator according to the first square wave signal, the second square wave signal and the enable signal determined by them, and completes the time-to-voltage conversion without the need to select from multiple phase signals, reducing the required digital circuit modules, thereby reducing the delay of the reference signal and the frequency-divided signal during the conversion process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 This is a circuit schematic diagram of an existing TVC type AFC circuit.

[0019] Figure 2 This is a circuit schematic diagram of a phase selection circuit in an existing TVC type AFC circuit.

[0020] Figure 3 This is a principle block diagram of an automatic frequency locking circuit based on a time-to-voltage converter provided by the present invention.

[0021] Figure 4 It is a circuit schematic diagram of a charge pump and an RC discharge circuit in an existing TVC type AFC circuit.

[0022] Figure 5 This is a circuit diagram of the charge pump provided by the present invention.

[0023] Figure 6This is a circuit schematic diagram of the phase generating unit provided by the present invention.

[0024] Figure 7 The present invention provides a circuit schematic diagram of an automatic frequency locking circuit based on a time-to-voltage converter.

[0025] Figure 8 It is a timing diagram of the automatic frequency locking circuit based on the time-to-voltage converter provided by the present invention.

[0026] In the figure, 1 is a first frequency-dividing unit, 2 is a second frequency-dividing unit, 3 is a time-to-voltage converter, and 4 is a comparator. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0028] Figure 1 This is the circuit schematic diagram of the existing TVC type AFC circuit, such as Figure 1 As shown, the existing TVC type AFC circuit adopts the relative period calibration method by measuring the reference signal (F REF ) and the divided VCO signal (F VCO By directly extracting period difference information from the phase difference between the rising and falling edges of the two signals (a / N), rather than relying on absolute period measurement, the frequency comparison is converted into dual-edge detection of the time-domain phase difference. Relative measurement replaces absolute measurement, and by simultaneously comparing the rising and falling edge phase differences of the two signals, dual-edge phase detection technology is used to convert the period difference into the charge pump's charge and discharge operations, generating a comparable voltage difference that represents the frequency relationship. Furthermore, by optimizing the signal processing flow, each calibration cycle requires only two signal cycles to complete a complete frequency comparison. Compared to the hundreds of cycle counts required by traditional counter-type AFC circuits, the calibration speed of the TVC-type AFC circuit is increased by over an order of magnitude, enabling fast sub-microsecond frequency lock. However, existing TVC-type AFC circuits require additional phase selection circuitry to ensure that the initial phase difference between the reference signal and the divided signal is less than 90 degrees to prevent the charge pump from losing lock.

[0029] Figure 2 This is the circuit principle diagram of the phase selection circuit in the existing TVC type AFC circuit, such as Figure 2As shown, the existing TVC-type AFC circuit needs to first generate eight phase signals based on the reference signal divided by four. Then, the phase selection circuit compares the divided signal with the eight phase signals to select the optimal signal. This requires a large number of digital circuit modules, resulting in a relatively high delay in the conversion process between the reference signal and the divided signal. It also causes the AFC circuit area to increase and the energy efficiency to decrease.

[0030] To solve the above-mentioned defects, the present invention provides an automatic frequency locking circuit and a phase-locked loop based on a time-to-voltage converter, which are described in detail below with reference to the accompanying drawings.

[0031] Figure 3 This is a principle block diagram of the automatic frequency locking circuit based on the time-to-voltage converter 3 provided by the present invention, as shown in FIG. Figure 3 As shown, the present invention provides an automatic frequency locking circuit and a phase-locked loop based on a time-to-voltage converter 3 , comprising a first two-frequency division unit 1 , a second two-frequency division unit 2 , a time-to-voltage converter 3 and a comparator 4 .

[0032] The first frequency-dividing unit 1 is used to perform frequency-dividing processing on the reference signal of the current comparison period to obtain a first square wave signal, and transmit the first square wave signal to the time-to-voltage converter 3 .

[0033] The second frequency-dividing unit 2 is used to perform frequency-dividing processing on the frequency-dividing signal of the current comparison period to obtain a second square wave signal, and transmit the second square wave signal to the time-to-voltage converter 3 .

[0034] The time-to-voltage converter 3 includes a phase generating unit, a first charge pump and a second charge pump. The phase generating unit is used to generate an enable signal based on the first square wave signal and the second square wave signal. The first charge pump is used to collect a single pulse signal from the first square wave signal in response to the control of the enable signal to power one input end of the comparator 4. The second charge pump is used to collect a single pulse signal from the second square wave signal in response to the control of the enable signal to power the other input end of the comparator 4.

[0035] The comparator 4 is used to compare the supply voltages at the two input terminals to achieve frequency comparison between the reference signal and the frequency-divided signal.

[0036] The first divide-by-two unit 1 and the second divide-by-two unit 2 are used to perform divide-by-two processing on the reference signal and the divided signal in the phase-locked loop, respectively, so that the duty cycles of the processed signals are consistent. Optionally, the present invention adopts the method of inputting the reference signal and the divided signal into the first divide-by-two unit 1 and the second divide-by-two unit 2, respectively, to obtain the first square wave signal and the second square wave signal with a duty cycle of 50%.

[0037] After the first square wave signal and the second square wave signal pass through the phase generating unit, an enable signal is generated. The enable signal is used to control the opening and closing of the first charge pump and the second charge pump, and to make the first charge pump and the second charge pump respectively sample a pulse signal of one cycle, i.e., a single pulse signal, from the first square wave signal and the second square wave signal, to realize power supply to the two input terminals of the comparator 4 and realize the conversion from time to voltage, so that the comparator 4 can realize the comparison of the two frequency signals according to the power supply voltage of the two input terminals, thereby assisting the phase-locked loop in making frequency selection decisions.

[0038] It is understandable that the present invention provides a time-to-voltage converter 3 that directly supplies power to the comparator 4 based on the first square wave signal, the second square wave signal, and the enable signal determined therefrom, thereby completing the time-to-voltage conversion without having to select from multiple phase signals, thereby reducing the required digital circuit modules and thereby reducing the delay of the reference signal and the frequency-divided signal during the conversion process. The use of time-to-voltage conversion rather than a counter to achieve frequency comparison is more efficient, faster, and has a lower circuit complexity. Furthermore, the circuits through which the reference signal and the frequency-divided signal pass are fully symmetrical. This differential structure for absolute time measurement can avoid comparison errors caused by asymmetric upper and lower currents in relative time measurement, while the phase generation unit can accurately generate a single charging pulse without being affected by dead zones, thereby helping to reduce errors.

[0039] Figure 4 This is the circuit schematic diagram of the charge pump and RC discharge circuit in the existing TVC type AFC circuit, such as Figure 4 As shown, to achieve time-to-voltage conversion, a TVC-type AFC circuit requires an RC discharge circuit to generate a DC voltage. The unit follower circuit following the RC discharge circuit (comprising resistor R1 and capacitor C1) samples the maximum voltage to achieve time-to-voltage conversion. The charge pump and RC discharge circuit in existing TVC-type AFC circuits are complex, increasing circuit area and power consumption. Furthermore, the RC discharge circuit and subsequent op amp require a period of stabilization after operation, resulting in increased latency.

[0040] To this end, the present invention provides a charge pump circuit with a simpler structure, which is described in detail below with reference to the accompanying drawings.

[0041] Based on the above embodiment, as an optional embodiment, the first charge pump includes a first NAND gate and a first current mirror, the first input end of the first NAND gate is used to receive the first square wave signal, the second input end of the first NAND gate is used to receive the enable signal, the output end of the first NAND gate is connected to the control end of the first current mirror, and the circuit structure of the second charge pump is the same as the circuit structure of the first charge pump.

[0042] Optionally, the first current mirror includes a first current source and a first switching tube, the output end of the first current source is connected to the drain of the first switching tube, the gate of the first switching tube is connected to the output end of the first NAND gate, and the source of the first switching tube is connected to an input end of the comparator 4.

[0043] The second charge pump includes a second NAND gate and a second current mirror, the second input end of the second NAND gate is used to receive the second square wave signal, the second input end of the second NAND gate is used to receive the enable signal, the output end of the second NAND gate is connected to the control end of the second current mirror, the second current mirror includes a second current source and a second switching tube, the output end of the second current source is connected to the drain of the second switching tube, the gate of the second switching tube is connected to the output end of the second NAND gate, and the source of the second switching tube is connected to an input end of the comparator 4.

[0044] Figure 5 is a circuit schematic diagram of any charge pump (i.e., the first charge pump or the second charge pump) provided by the present invention, Figure 5 The input signal Fsig of the NAND gate is determined based on the charge pump. If it is the first charge pump, Fsig refers to the first square wave signal. If it is the second charge pump, Fsig refers to the second square wave signal. The other input signal of the NAND gate is the enable signal.

[0045] It can be understood that the first charge pump and the second charge pump provided by the present invention are only composed of a simple digital circuit and a current mirror. Unlike the traditional TVC single charging in the analog domain, the present invention does not require additional operational amplifiers and complex digital circuits. When the enable signal is high, the input signal Fsig directly controls the charging of the charge pump. When the enable signal is low, the charge pump does not work. Through the control of the enable signal, a single cycle of charging can be achieved, thereby realizing time-voltage conversion, facilitating subsequent comparison, and generating a single charging pulse in the digital domain, which greatly simplifies the design of the charge pump. The RC discharge circuit and the sampling unity gain amplifier in the traditional TVC circuit are not required, and the discharge speed is fast, the circuit area is small, and the power consumption is low.

[0046] Based on the above embodiment, as an optional embodiment, the phase generation unit includes a first sequential logic module, a second sequential logic module, a third sequential logic module and a delay module, wherein the first sequential logic module is used to determine the first charging state signal based on the comparison period control signal and the first square wave signal, the second sequential logic module is used to determine the second charging state signal based on the comparison period control signal and the second square wave signal, the third sequential logic module is used to determine the comparison period control signal of the current comparison period based on the reference signal, the frequency division signal, the first charging state signal and the second charging state signal of the previous comparison period, the delay module is used to determine the reset signal based on the first charging state signal and the second charging state signal of the current comparison period, and the reset signal is used to feed back to the first sequential logic module, the second sequential logic module and the third sequential logic module, wherein the comparison period control signal is used to indicate the start and end of each comparison period.

[0047] Optionally, the enable signal includes a first enable signal and a second enable signal, the first enable signal being determined based on the product of the comparison period control signal and the first charging state signal, and being used to control the first charge pump; the second enable signal being determined based on the product of the comparison period control signal and the second charging state signal, and being used to control the second charge pump.

[0048] Among them, the first charging status signal is used to indicate whether the first charge pump has supplied power to one input end of the comparator 4 in the current comparison cycle, so as to ensure that power is supplied only once in the current comparison cycle, and the second charging status signal is used to indicate whether the second charge pump has supplied power to the other input end of the comparator 4 in the current comparison cycle, so as to ensure that power is supplied only once in the current comparison cycle.

[0049] Figure 6 : is a circuit diagram of the phase generating unit provided by the present invention, such as Figure 6 As shown, the phase generation unit provided by the present invention is composed of a simple sequential logic module. B in the figure can be regarded as a reference signal, and C can be regarded as a frequency-divided signal. The two values of Q1 and Q2 respectively mark whether the two signals (B and C) charge the capacitor during this comparison process. For example, when Q1=1, it means that signal B has charged the capacitor once through the charge pump during this comparison process, and the time-to-voltage conversion has been achieved. When there are multiple signal cycles in a comparison cycle, this state value will ensure that it is only charged once. Signal A can be regarded as a comparison cycle signal. It is only high when the input signal and the reference signal are 0 and have not been converted into voltage by the charge pump.

[0050] It is understandable that the phase generating unit provided by the present invention is composed of a simple sequential logic module, which can accurately generate a single charging pulse without being affected by the dead zone, thereby reducing the circuit area and power consumption.

[0051] Figure 7 This is a circuit diagram of the automatic frequency locking circuit based on the time-to-voltage converter 3 provided by the present invention, as shown in FIG. Figure 7 As shown, based on the above embodiment, as an optional embodiment, the common end of the first charge pump and the comparator 4 is provided with a first capacitor discharge unit, and the first charge pump supplies power to one input end of the comparator 4 through the first capacitor discharge unit; the common end of the second charge pump and the comparator 4 is provided with a second capacitor discharge unit, and the second charge pump supplies power to the other input end of the comparator 4 through the second capacitor discharge unit.

[0052] Optionally, the first capacitor discharge unit and the second capacitor discharge unit are symmetrically arranged. The present invention uses a differential form rather than a single-ended charge and discharge form for comparison, and the symmetrical branches of the signal are beneficial to reducing errors.

[0053] Optionally, the output end of the comparator 4 is connected to a NOR gate, and the NOR gate is used to generate a reset signal according to the comparison result output by the comparator 4.

[0054] Optionally, the two input terminals of the comparator 4 are respectively connected to reset switches, and the reset switches reset the two input terminals of the comparator 4 in response to the control of a reset signal.

[0055] Figure 8 3 is a timing diagram of the automatic frequency locking circuit based on the time-to-voltage converter 3 provided by the present invention, as shown in FIG. Figure 8 As shown, after the start of the current comparison cycle, the first falling edge of the reference signal B and the frequency-divided signal C, that is, after the end of the first charging cycle of the current comparison cycle, the first charging state signal Q1 and the second charging state signal Q2 will be set to 1 respectively, marking the end of the time-voltage conversion, to prevent multiple charging comparison errors. When the reference signal and the frequency-divided signal have completed the time-voltage conversion, the comparator 4 is driven to work, and a reset signal is generated after a delay. , Q1, Q2, and A are all reset to zero, and the next comparison cycle begins when B and C return to a low level. The timing of the circuit of the present invention meets the expected logic, and the required comparison time depends on the slower clock signal. The required time is approximately 1 / 2 cycle of the slow clock, and the comparison speed is fast.

[0056] In summary, the present invention uses a TVC circuit to measure periods and convert them into voltage, thereby avoiding the shortcomings of traditional counting AFCs, such as slow speed, high digital circuit redundancy, high power consumption, and large area. At the same time, the charge pumps, capacitors, and other circuits through which the two signals pass are fully symmetrical. This differential structure of absolute time measurement can avoid comparison errors caused by asymmetric upper and lower currents in relative time measurement. The phase generation unit can accurately generate a single charging pulse without being affected by dead zones. The charge pump circuit design is simple, and the entire single-pulse charging TVC circuit is more power-efficient than the voltage follower circuit in traditional TVCs.

[0057] The phase-locked loop provided by the present invention is described below. The phase-locked loop described below and the automatic frequency locking circuit and phase-locked loop based on the time-to-voltage converter described above can be referred to each other.

[0058] The present invention further provides a phase-locked loop, comprising any one of the automatic frequency locking circuits based on a time-to-voltage converter and the phase-locked loop.

[0059] It should be noted that the phase-locked loop provided by the present invention, including the automatic frequency locking circuit based on the time-voltage converter described in any of the above embodiments, has the technical effect corresponding to the automatic frequency locking circuit based on the time-voltage converter, which will not be described in detail in this embodiment.

[0060] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. An automatic frequency locking circuit based on a time-to-voltage converter, characterized in that: It includes a first two-frequency dividing unit, a second two-frequency dividing unit, a time-to-voltage converter and a comparator; The first frequency-dividing unit is used to perform frequency-dividing processing on the reference signal of the current comparison period to obtain a first square wave signal, and transmit the first square wave signal to the time-to-voltage converter; The second frequency-dividing unit is used to perform frequency-dividing processing on the frequency-dividing signal of the current comparison period to obtain a second square wave signal, and transmit the second square wave signal to the time-to-voltage converter; The time-to-voltage converter includes a phase generating unit, a first charge pump, and a second charge pump. The phase generating unit is configured to generate an enable signal according to the first square wave signal and the second square wave signal. The first charge pump is configured to collect a single pulse signal from the first square wave signal in response to the control of the enable signal to supply power to one input terminal of the comparator. The second charge pump is configured to collect a single pulse signal from the second square wave signal in response to the control of the enable signal to supply power to the other input terminal of the comparator. The comparator is used to compare the supply voltages of the two input terminals to achieve frequency comparison between the reference signal and the frequency-divided signal.

2. The automatic frequency locking circuit based on time-to-voltage converter according to claim 1, characterized in that: The first charge pump includes a first NAND gate and a first current mirror, the first input end of the first NAND gate is used to receive the first square wave signal, the second input end of the first NAND gate is used to receive the enable signal, the output end of the first NAND gate is connected to the control end of the first current mirror, and the circuit structure of the second charge pump is the same as that of the first charge pump.

3. The automatic frequency locking circuit based on time-to-voltage converter according to claim 2, characterized in that: The first current mirror includes a first current source and a first switching tube, the output end of the first current source is connected to the drain of the first switching tube, the gate of the first switching tube is connected to the output end of the first NAND gate, and the source of the first switching tube is connected to an input end of the comparator.

4. The automatic frequency locking circuit based on a time-to-voltage converter according to any one of claims 1 to 3, characterized in that: The phase generation unit includes a first sequential logic module, a second sequential logic module, a third sequential logic module, and a delay module. The first sequential logic module is used to determine a first charging state signal based on a comparison period control signal and the first square wave signal. The second sequential logic module is used to determine a second charging state signal based on the comparison period control signal and the second square wave signal. The third sequential logic module is used to determine a comparison period control signal of a current comparison period based on a reference signal, a frequency division signal, a first charging state signal, and a second charging state signal of a previous comparison period. The delay module is used to determine a reset signal based on the first charging state signal and the second charging state signal of the current comparison period. The reset signal is used to feed back to the first sequential logic module, the second sequential logic module, and the third sequential logic module. The comparison period control signal is used to indicate the start and end of each comparison period.

5. The automatic frequency locking circuit based on time-to-voltage converter according to claim 4, characterized in that: The enable signal includes a first enable signal and a second enable signal, wherein the first enable signal is determined based on the product of the comparison period control signal and the first charging state signal, and is used to control the first charge pump; the second enable signal is determined based on the product of the comparison period control signal and the second charging state signal, and is used to control the second charge pump; Among them, the first charging status signal is used to indicate whether the first charge pump has supplied power to one input terminal of the comparator in the current comparison cycle, so as to ensure that power is supplied only once in the current comparison cycle, and the second charging status signal is used to indicate whether the second charge pump has supplied power to the other input terminal of the comparator in the current comparison cycle, so as to ensure that power is supplied only once in the current comparison cycle.

6. The automatic frequency locking circuit based on time-to-voltage converter according to claim 1, characterized in that: A first capacitor discharge unit is provided at a common end of the first charge pump and the comparator, and the first charge pump supplies power to one input end of the comparator through the first capacitor discharge unit; a second capacitor discharge unit is provided at a common end of the second charge pump and the comparator, and the second charge pump supplies power to the other input end of the comparator through the second capacitor discharge unit.

7. The automatic frequency locking circuit based on time-to-voltage converter according to claim 6, characterized in that: The first capacitor discharge unit and the second capacitor discharge unit are symmetrically arranged.

8. The automatic frequency locking circuit based on time-to-voltage converter according to claim 1, characterized in that: The output end of the comparator is connected to a NOR gate, and the NOR gate is used to generate a reset signal according to the comparison result output by the comparator.

9. The automatic frequency locking circuit based on time-to-voltage converter according to claim 1, characterized in that: The two input terminals of the comparator are respectively connected to reset switches, and the reset switches perform reset processing on the two input terminals of the comparator in response to the control of a reset signal.

10. A phase-locked loop, characterized in that: The automatic frequency locking circuit based on the time-to-voltage converter comprises the circuit described in any one of claims 1-9.

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