Ion beam etch with sidewall cleaning

Abstract

A patterned magnetoresistive random access memory (MRAM) stack is formed by etching through a plurality of MRAM layers disposed on a substrate by performing a main etch, wherein the main etch includes using ion beam etch (IBE). After the main etch, a gap-fill dielectric material is deposited into the spaces between the patterned MRAM stacks, and the gap-fill dielectric material is selectively etched or otherwise formed to an etch depth above the underlying depth. After forming the gap-fill dielectric material, at least some of the gap-fill dielectric material and any conductive material deposited on sidewalls of the patterned MRAM stack are removed by performing an IBE trim etch.

Description

This application is a divisional application of the invention patent application with application number 202080017660.4, application date February 26, 2020, applicant is Rum Research Company, and invention name is "Ion beam etching with sidewall cleaning". CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The PCT application form is filed concurrently with this specification as a part of this application. Each application to which this application claims the benefit of or priority as identified in the concurrently filed PCT application form is incorporated herein by reference in its entirety and for all purposes. Background Art

[0002] Magnetic random access memory (MRAM) is a type of non-volatile memory that utilizes magnetoresistive effects, such as tunneling magnetoresistance (TMR). MRAM offers the high integration density of static random access memory (SRAM) and the high-speed performance of dynamic random access memory (DRAM). Because the MRAM stack material is highly non-volatile and sensitive to reactive chemicals, ion beam etching is typically used to etch the MRAM stack.

[0003] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. No admission is made, either explicitly or implicitly, that the work of the presently designated inventors is prior art to the present disclosure to the extent that it is described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the Invention

[0004] An ion beam etching method is provided. The method includes etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer, and wherein etching through the plurality of MRAM layers includes etching through at least the tunnel barrier layer by ion beam etching (IBE). The method also includes forming a gapfill dielectric material in spaces between the patterned MRAM stacks; and performing an IBE trim etch to remove at least some of the gapfill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stacks.

[0005] In some implementations, the gapfill dielectric material is formed to a sufficient depth above an underlying layer between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not cause a recess in the underlying layer. In some implementations, the sufficient depth above the underlying layer is between about 1 nm and about 20 nm above an upper surface of the underlying layer. In some implementations, forming the gapfill dielectric material in the space between the patterned MRAM stacks includes depositing the gapfill dielectric material in the space between the patterned MRAM stacks and above the patterned MRAM stacks. In some implementations, forming the gapfill dielectric material in the space between the patterned MRAM stacks includes selectively etching the gapfill dielectric material to an etch depth above the depth of the tunnel barrier layer. In some implementations, the gapfill dielectric material includes silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof. In some implementations, etching through the plurality of MRAM layers, forming the gapfill dielectric material, and performing the IBE trim etch are performed in a manner that does not cause a vacuum break between the operations. In some implementations, ion beam etching through at least the tunnel barrier layer comprises applying a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and performing the IBE trim etch comprises applying a second ion beam having an energy between about 20 eV and about 400 eV to the substrate. In some implementations, performing the IBE trim etch is performed in a manner that does not etch through underlying layers disposed below the plurality of MRAM layers.

[0006] Another aspect relates to an apparatus for performing ion beam etching. The apparatus includes an ion beam source chamber; a process chamber coupled to the ion beam source chamber; and a controller. The controller is configured to provide instructions to: position a substrate in the process chamber, dispose a plurality of MRAM layers on the substrate, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer; etch through the plurality of MRAM layers disposed on the substrate to form a patterned MRAM stack, wherein etching through the plurality of MRAM layers includes etching through at least the tunnel barrier layer using ion beam etching (IBE); form a gapfill dielectric material in spaces between the patterned MRAM stacks; and perform an IBE trim etch to remove at least some of the gapfill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stacks.

[0007] In some implementations, the controller configured to provide instructions for forming the gapfill dielectric material is further configured to provide instructions for depositing the gapfill dielectric material in the spaces between and above the patterned MRAM stacks. In some implementations, the controller configured to provide instructions for forming the gapfill dielectric material is further configured to provide instructions for selectively etching the gapfill dielectric material to an etch depth above a depth of the tunnel barrier layer. In some implementations, the gapfill dielectric material is formed to a sufficient depth above an underlying layer between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not cause recessing in the underlying layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic cross-sectional view of an exemplary MRAM stack on a substrate, according to some implementations.

[0009] Figure 2 Schematic diagram of the cross section of the MRAM layer undergoing ion beam etching (IBE) and sidewall redeposition.

[0010] Figure 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some implementations.

[0011] Figure 4A and 4B A schematic cross-sectional view of ion beam etching through multiple MRAM layers and underlying layers is shown.

[0012] Figure 5 A flow chart is shown of an exemplary method of ion beam etching according to some implementations.

[0013] Figures 6A-6F A schematic cross-sectional view of the process of performing main etch, gap fill, planarization, etch back, IBE trim etch, and packaging operations according to some implementations is shown.

[0014] Figure 7 A block diagram of an exemplary processing system for performing deposition and ion beam etching processes is shown, according to some implementations.

[0015] Figure 8 An alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes is shown in accordance with some implementations.

[0016] Figure 9 A block diagram of an exemplary processing system for performing planarization and / or etching processes is shown, according to some implementations. DETAILED DESCRIPTION

[0017] In this disclosure, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially processed integrated circuit" are used interchangeably. It should be understood by those skilled in the art that the term "partially processed integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is implemented on a wafer. However, the present disclosure is not limited to this. The workpiece can have a variety of shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various articles of manufacture, such as printed circuit boards. introduce

[0018] Electronic devices use integrated circuits (ICs) that include memory to store data. A common type of memory used in electronic circuits is DRAM. DRAM stores individual bits of data in individual capacitors within the IC. The capacitors can be charged or discharged to represent two states of a bit. Because the charge in the capacitors slowly leaks, data is gradually lost unless the charge is regularly refreshed. In contrast to non-volatile memory, DRAM is volatile because data is lost when power is removed.

[0019] Unlike conventional RAM chip technology, data in MRAM is not stored as charge or current, but rather through a magnetic storage element. The magnetic storage element can be formed by two ferromagnetic plates, each of which can maintain magnetization and separated by a thin non-magnetic insulating layer. One of the two ferromagnetic plates can be a permanent magnet set to a specific polarity, while the other of the two ferromagnetic plates can be changed to match the specific polarity of the external magnetic field to store memory. This configuration involving two ferromagnetic plates and a thin non-magnetic insulating layer is called a magnetic tunnel junction. MRAM is a non-volatile memory because it has the ability to maintain stored data even if the power is removed.

[0020] Figure 1is a schematic cross-sectional view of an exemplary MRAM stack on a substrate according to some implementations. The MRAM stack 100 is disposed on a dielectric layer 110, such as SiO2, which is disposed on a silicon or glass substrate (not shown). In the case of embedded MRAM, since the embedded MRAM may be MRAM embedded in non-memory circuits (such as metallization layers), there are various structures (not shown) between the substrate and the MRAM stack 100, including transistor levels of logic circuits and 3 to 5 metallization layers. These structures are all covered by or inserted into the dielectric layer 110. The MRAM stack 100 may include a top electrode layer 120 and a bottom electrode layer 130. The bottom electrode layer 130 is disposed on the dielectric layer 110 and may include a single layer of metal or a multilayer stack including multiple metal layers and other material layers (e.g., dielectric materials). The top electrode layer 120 is disposed above the bottom electrode layer 130 and can include a single metal layer or a multilayer stack comprising multiple metal layers and other material layers (e.g., dielectric materials). The MRAM stack 100 can be arranged into an array of MRAM cells connected by metal word lines and bit lines. In some implementations, the bottom electrode layer 130 is connected to the word lines, while the top electrode layer 120 is connected to the bit lines.

[0021] The MRAM stack 100 may include a memory element or a magnetoresistive effect element, wherein the memory element or the magnetoresistive effect element may be disposed between a top electrode layer 120 and a bottom electrode layer 130. The memory element or the magnetoresistive effect element may be a multilayer film or a magnetic tunnel junction (MTJ) stack 140. The MTJ stack 140 may include magnetic layers 150, 160, and a barrier layer 170 between the magnetic layers 150, 160. In addition, the MTJ stack 140 may include a plurality of MTJ stacks and a plurality of barrier layers, each barrier layer being positioned between a pair of magnetic layers. It should be understood that the MTJ stack 140 is illustrative and not restrictive, and may include other layers not shown. Figure 1The first magnetic layer 150 is designed to function as a free magnetic layer, while the second magnetic layer 160 has a fixed magnetization direction. In some implementations, each of the first magnetic layer 150 and the second magnetic layer 160 includes a magnetic material such as cobalt (Co), nickel (Ni), iron (Fe), or a combination thereof (e.g., CoNi, CoFe, NiFe, CoNiFe). Each of the first magnetic layer 150 and the second magnetic layer 160 may also include a non-magnetic material such as boron (B), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), aluminum (Al), silicon (Si), germanium (Ge), gallium (Ga), oxygen (O), nitrogen (N), carbon (C), platinum (Pt), palladium (Pd), ruthenium (Ru), or phosphorus (P) to form a magnetic compound (e.g., CoFeB). It should be understood that each of the first magnetic layer 150 and the second magnetic layer 160 may include one or more sublayers. In some implementations, the second magnetic layer 160 may be coupled to and disposed on an antiferromagnetic layer (not shown). The MTJ stack 140 further includes a tunnel barrier layer, or barrier layer 170, located between the first magnetic layer 150 and the second magnetic layer 160. The barrier layer 170 may include a non-magnetic insulating material such as magnesium oxide (MgO). Thus, the MTJ stack 140 may include a pair of ferromagnetic layers (i.e., the first magnetic layer 150 and the second magnetic layer 160) that collectively produce a magnetoresistive effect, and a non-magnetic intermediate layer (i.e., the barrier layer 170) therebetween. When the magnetization of the first magnetic layer 150 changes direction relative to the magnetization of the second magnetic layer 160, the resistivity of the MTJ stack 140 changes, exhibiting a low-resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially parallel, and a high-resistance state when the magnetization orientations of the pair of ferromagnetic layers are substantially anti-parallel. Therefore, the MRAM stack 100 can have two stable states, allowing the MRAM stack 100 to be used as a volatile memory.

[0022] In some implementations, the top electrode layer 120 can serve as a hard mask layer. During processing, the top electrode layer 120 can be deposited on the first magnetic layer 150 to pattern the MTJ stack 140 below. However, it should be understood that the positions of the first magnetic layer 150 and the second magnetic layer 160 can be reversed, so that the top electrode layer 120 is deposited on the second magnetic layer 160. In some implementations, the top electrode layer 120 includes tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), or other refractory metals. The MTJ stack 140 can be formed on the bottom electrode layer 130, wherein the bottom electrode layer 130 includes a conductive material such as Ta, Ti, W, TiN, TaN, Pt, Ru, etc.

[0023] It should be understood that the MRAM stack 100 may include components not necessarily shown in FIG. Figure 1 The layers in the MRAM stack 100 are not necessarily limited to metal or conductive materials, but may also include one or more layers of dielectric materials.

[0024] Etching the MRAM stack (including Figure 1 Materials in the MRAM stack 100 in FIG. 1 may present many challenges. Hard materials are typically etched using chemical etching processes, such as reactive ion etching (RIE). However, reactive ion etching of materials such as cobalt, iron, nickel, and other magnetic elements is difficult because these materials do not readily form volatiles when exposed to typical etchant chemistries. Consequently, many materials in the MRAM stack require more aggressive etchant chemistries. On the other hand, some materials in the MRAM stack cannot withstand such aggressive etchant chemistries. For example, a tunnel barrier layer such as MgO cannot withstand reactive chemistries, which may include radicals, ions, and neutral species containing fluorine, chlorine, iodine, oxygen, or hydrogen. These chemicals may react with the tunnel barrier layer, thereby damaging the tunnel barrier layer and adversely affecting the electrical and magnetic properties of the MRAM stack. In some cases, this can impair the tunnel magnetoresistance (TMR) effect in the MRAM stack.

[0025] Ion beam etching (IBE) has been widely used in various industries to pattern thin films. Ion beam etching (also known as ion milling) provides a highly directed beam of charged particles to etch features on a substrate. For purely physical etching processes, ion beam etching can be applied using an inert gas; however, in some cases, ion beam etching can be applied using a reactive species to enhance material etching using a chemical / reactive component. Generally speaking, ion beam etching can physically etch through hard materials by using individual particles to abrade an exposed target, dislodging atoms and molecules. Ion beam etching can be used to etch materials in an MRAM stack while avoiding reactive chemicals that could degrade sensitive layers (e.g., tunnel barriers).

[0026] Features in the MRAM stack can be patterned using ion beam etching. Ion beam etching is generally chemically non-reactive and physically etches the layers and materials exposed by the hard mask. This can cause atoms and molecules to be sputtered from the target. The sputtered atoms and molecules can be directed toward the exposed sidewalls of the MRAM stack and cause redeposition on the exposed sidewalls. Therefore, etching and redeposition can occur simultaneously. By performing ion beam etching at lower energy and a different impact angle than the ion beam etching used to pattern the MRAM stack, the redeposited material is cleaned from the sidewalls of the MRAM stack.

[0027] Figure 2 2 is a schematic cross-sectional view of an MRAM layer subjected to ion beam etching and sidewall redeposition. MRAM stacks 220a, 220b are formed on substrate 210. Each of the MRAM stacks 220a, 220b may include a pair of magnetic layers, wherein a tunnel barrier layer (e.g., MgO) may be sandwiched between the magnetic layers. It should be understood that in some implementations, each of the MRAM stacks 220a, 220b may include multiple tunnel barrier layers, each sandwiched between a pair of magnetic layers. Examples of layers and materials in the MRAM stacks 220a, 220b are described above with respect to FIG. Figure 1 The MRAM stack 100 in FIG. is described. The patterning process of conventional MRAM includes hard mask patterning, top electrode patterning, MTJ patterning, and bottom electrode patterning. It should be understood that ion beam etching can be used for some or all of the aforementioned patterning processes, wherein ion beam etching can be used for MTJ patterning. Reactive ion etching or ion beam etching can be used for patterning of the top electrode and patterning of the bottom electrode. In order to pattern the MRAM stack 220a, 220b, an ion beam 225 can be applied to the substrate 210 to physically etch the layers and materials exposed by the hard mask. The ion beam 225 sputters atoms and molecules from the surface exposed to the ion beam 225. As Figure 2As shown, sputtered atoms and molecules 275 may be directed toward and redeposited on the sidewalls of the MRAM stacks 220a, 220b. Some layers on the substrate 210 (e.g., layers of the MTJ stack) may include metal atoms such as Fe, Co, and Ni atoms. As the ion beam etches through the MTJ stack, these metal atoms may be displaced and redeposited on the sidewalls of the MRAM stacks 220a, 220b. When conductive material redeposits on the sidewalls of the tunnel barrier layer (which may be only a few nanometers thick), the magnetic layers may short-circuit in the MRAM stacks 220a, 220b.

[0028] The ion beam 225 applied to the substrate 210 can be directed at an angle. The angle of incidence of the ion beam 225 can be adjusted to control parameters such as etch rate, uniformity, shape, surface topography, and target surface composition. In some cases, the angle of incidence of the ion beam 225 is adjusted to clean the sidewalls of redeposited material. A lower angle of incidence of the ion beam 225 (i.e., more perpendicular) may cause more redeposition of material, while a higher angle of incidence optimized for the ion beam 225 (i.e., less perpendicular) can remove redeposited material to form a cleaner sidewall surface. Furthermore, as device density increases and aspect ratios increase, the feasibility of using higher angles of incidence when cleaning sidewall surfaces becomes more limited. Ion beam etching equipment

[0029] Figure 3 is a schematic diagram of an exemplary ion beam etching apparatus according to some implementations. The ion beam etching apparatus 310 includes a processing chamber 312 having a substrate holder 314 for supporting a substrate 316. The substrate 316 may be a semiconductor wafer. The multiple MRAM layers described earlier may be formed on the substrate 316. The multiple MRAM layers may include one or more magnetic layers and a tunnel barrier layer or multiple tunnel barrier layers. The multiple MRAM layers may also include an upper electrode layer and a lower electrode layer. The substrate 316 may be attached to the substrate holder 314 using any suitable technique. For example, the substrate 316 may be mechanically or electrostatically connected to the substrate holder 314. In some implementations, the substrate holder 314 provides for precise tilting and rotation and may include an electrostatic chuck (ESC) to engage the substrate 316.

[0030] The ion beam etching apparatus 310 further includes an ion beam source chamber 322, wherein the processing chamber 312 can be located outside of the ion beam source chamber 322 and coupled to the ion beam source chamber 322. The ion beam source chamber 322 can be separated from the processing chamber 312 by an ion extractor 340 and / or a mechanical shutter 348. An induction coil 332 can be arranged around an outer wall of the ion beam source chamber 322. A plasma generator 334 supplies RF power to the induction coil 332. The plasma generator 334 can include an RF source 336 and a matching network 338. In use, a gas mixture is introduced into the ion beam source chamber 322 and RF power is supplied to the induction coil 332 to generate a plasma within the ion beam source chamber 322, wherein the plasma generates ions.

[0031] The ion beam etching apparatus 310 further comprises a gas delivery system 350, which is fluidically connected to the ion beam source chamber 322. The gas delivery system 350 delivers one or more gas mixtures to the ion beam source chamber 322. The gas delivery system 350 can include one or more gas sources 352, valves 354, mass flow controllers (MFCs) 356, and a mixing manifold 358 that are fluidically connected to the ion beam source chamber 322. In some implementations, the gas delivery system 350 is configured to deliver an inert gas, such as helium (He), neon (Ne), argon (Ar), xenon (Xe), or krypton (Kr). In some implementations, the gas delivery system 350 delivers a gas mixture that also includes reactant chemicals and an inert gas.

[0032] The ion extractor 340 extracts positive ions from the plasma and accelerates the positive ions in the form of a beam toward the substrate 316. The ion extractor 340 may include a plurality of electrodes forming a grid or grid system. Figure 3 As shown, the ion extractor 340 includes three electrodes, with a first electrode 342, a second electrode 344, and a third electrode 346 being presented in order starting from the gas delivery system 350. A positive voltage is applied to the first electrode 342 and a negative voltage is applied to the second electrode 344, causing ions to be accelerated due to their potential difference. The third electrode 346 is grounded. The potential difference between the second electrode 344 and the third electrode 346 is controlled to control the energy and dispersion of the ion beam. A mechanical shutter 348 can be adjacent to the ion extractor 340. A neutralizer 360 can supply electrons into the processing chamber 312 to neutralize the charge of the ion beam passing through the ion extractor 340 and the mechanical shutter 348, wherein the neutralizer 360 can have its own gas delivery system using an inert gas (e.g., argon or xenon). In some implementations, the ion extractor 340 and / or the mechanical shutter 348 can be controlled so that the ion beam is delivered to the substrate 316 continuously or in a pulsed manner.

[0033] A position controller 366 can be used to control the position of the substrate holder 314. In particular, the position controller 366 can control the tilt angle and rotation of the substrate holder 314 relative to the tilt axis to position the substrate 316. In some implementations, an endpoint detector 368 can be used to sense the position of the ion beam relative to the substrate 316 and / or the substrate holder 314. A pump 370, such as a turbomolecular pump, can be used to control the pressure within the process chamber 312 and to exhaust reactants from the process chamber 312.

[0034] The ion beam etching apparatus 310 may also include a controller 390. The controller 390 (which may include one or more physical controllers or logic controllers) controls some or all of the operations of the ion beam etching apparatus 310. In some implementations, the controller 390 may be used to control the plasma generator 334, the gas delivery system 350, the neutralizer 360, the position controller 366, and the pump 370. The controller 390 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor controller board, and other similar components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller 390 and may be provided over a network. In some implementations, the controller 390 executes system control software. The system control software may include instructions for controlling the timing and / or amount of application of any one or more of the following chamber operating conditions: gas mixture and / or composition, gas flow rate, chamber pressure, chamber temperature, substrate / substrate holder temperature, substrate position, substrate holder tilt, substrate holder rotation, voltage applied to the grid, frequency and power applied to the coils or other plasma generating components, and other parameters for specific steps performed by the tool. The system control software may further control sweep operations and cleaning operations via the pump 370. The system control software may be configured in any suitable manner. For example, subroutines or control objects may be written for various process tool components to control the operation of the process tool components required to perform various process tool steps. The system control software may be encoded in any computer-readable programming language.

[0035] In some implementations, the system control software includes input / output control (IOC) sequencing instructions for controlling the aforementioned parameters. For example, each stage of the semiconductor manufacturing process may include one or more instructions executed by the controller 390. For example, instructions for setting process conditions for a stage may be included in a corresponding recipe stage. In some implementations, the recipe stages may be arranged in a sequence such that the steps in the ion beam etching process are performed in a specific order for that processing stage. For example, a recipe may be configured to perform a separate etch using ion beam etching at high energy and a trim etch using ion beam etching at low energy.

[0036] Other computer software and / or programs may be employed in some implementations. Examples of programs or portions of programs used for this purpose include substrate positioning programs, process gas composition control programs, pressure control programs, heater control programs, and RF power supply control programs.

[0037] The controller 390 can control these and other aspects based on sensor outputs (e.g., when power, potential, pressure, gas level, etc. reaches a certain threshold), operating time (e.g., opening a valve at certain times in the process), or based on instructions received from a user.

[0038] In general, the controller 390 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions communicated to the controller 390 in the form of various separate settings (or program files) that define operating parameters for performing a specific process on or for a semiconductor substrate or system. In some implementations, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during patterning of the MRAM stack on the substrate.

[0039] In some implementations, the controller 390 can be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller 390 can be in the "cloud" or all or part of a wafer fab host system that can allow remote access to substrate processing. The computer can enable remote access to the system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review trends or performance metrics across multiple manufacturing operations, change parameters of a current process, set processing steps to follow a current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system via a network (which can include a local network or the Internet). The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller 390 receives instructions in the form of data that specify parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool that the controller 390 is configured to interface with or control. Thus, as described above, the controller 390 can be distributed, for example, by including one or more discrete controllers networked together and working toward a common purpose (e.g., the processes and controls described herein). An example of a distributed controller 390 for such a purpose is one or more integrated circuits on a chamber communicating with one or more integrated circuits remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber.

[0040] As described above, depending on the one or more process steps to be performed by the tool, the controller 390 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the facility, a host computer, another controller, or a material transport tool used in transporting substrate containers to and from tool locations and / or load ports in a semiconductor fabrication facility. The aforementioned examples of tools with which the controller 390 may communicate are described in Figure 7-9 middle. Ion beam etching with sidewall cleaning

[0041] In the present disclosure, a dielectric gapfill material is deposited between an IBE separation etch process for patterning an MRAM stack and an IBE trim etch process for cleaning the sidewalls of the patterned MRAM stack. Generally, the IBE trim etch process for cleaning the sidewalls of the patterned MRAM stack results in sputtering of metal or conductive material that can redeposit onto the sidewalls. Sputtering of metal or conductive material can occur where the etch front of the IBE trim etch process includes the metal or conductive material. One approach to avoiding such sputtering is to provide a thick layer of dielectric material, such as silicon oxide (SiO2), as the etch front. The thick layer of dielectric material can be provided below the MRAM layer or below the magnetic layer in the MTJ stack. The thick layer of dielectric material can have a thickness of at least about 40 nm, at least about 50 nm, at least about 75 nm, or at least about 100 nm. In this way, any material redeposited onto the sidewalls during the ion beam etch is dielectric material, not conductive material. However, providing a thick layer of dielectric material beneath the magnetic layer in an MTJ stack can be impractical, increase overhead, complicate the manufacturing process, increase cost, and even reduce performance. For example, many MRAM devices are embedded memories located between metallization layers in an integrated circuit (IC), and the thickness of the dielectric layer in which the MRAM device resides may not be easily changed.

[0042] Figure 4A and 4B A schematic cross-sectional view of ion beam etching through multiple MRAM layers and underlying layers is shown. The MRAM stack 400 may include a first magnetic layer 450, a tunnel barrier layer 470, and a second magnetic layer 460, with the tunnel barrier layer 470 interposed between the first and second magnetic layers 450 and 460. The first magnetic layer 450 may also be referred to as a free layer and is designed to function as a free magnetic layer, and the second magnetic layer 460 may be referred to as a reference layer and is designed to have a fixed magnetization direction. In some implementations, the first and second magnetic layers 450 and 460 may comprise magnetic materials such as Co, Ni, Fe, Pt, or combinations thereof. The tunnel barrier layer 470 may comprise a non-magnetic insulating material such as MgO. The combination of the first magnetic layer 450, the tunnel barrier layer 470, and the second magnetic layer 460 generates a magnetoresistive effect. The MRAM stack 400 is disposed on a substrate 410, with the underlying layer 430 interposed between the substrate 410 and the MRAM stack 400. The lower layer 430 may include one or more layers of dielectric material, such as silicon oxide (SiO2). In some implementations, a hard mask layer or an electrode layer (not shown) may be disposed above the MRAM stack 400. In some implementations, the electrode layer (not shown) may be disposed between the lower layer 430 and the substrate 410. In some implementations, the MRAM stack 400 may include multiple tunnel barrier layers, each of which is sandwiched between a first magnetic layer and a second magnetic layer.

[0043] Ion beam etching can be performed to etch through the layers of the MRAM stack 400 to form a patterned MRAM stack, wherein the patterned MRAM stack can include lines, pillars, or other patterned features. The ion beam etching to form the patterned MRAM stack can be performed at high power and a relatively low angle of incidence. In addition, after forming the patterned MRAM stack, ion beam etching can be performed to clean the sidewalls of the patterned MRAM stack to remove undesirable material that has been redeposited on the sidewalls. The ion beam etching for cleaning the sidewalls of the patterned MRAM stack can be performed at relatively low power and a relatively high angle of incidence, with the angle of incidence being normal to the substrate surface.

[0044] exist Figure 4A In , the ion beam 425 can be directed at a certain angle to clean the sidewalls of the patterned MRAM stack. For example, the substrate 410 can be tilted or rotated to adjust the ion impact angle of the ion beam 425. The ion beam 425 impacts the sidewalls of the patterned MRAM stack to remove unwanted material. The ion beam 425 also impacts the lower surface of the MRAM stack 400 and causes sputtering of atoms and molecules at the lower surface. The sputtered atoms and molecules 475 can be directed toward the sidewalls of the patterned MRAM stack, which results in redeposition on the sidewalls of the patterned MRAM stack. When the etch front of the ion beam 425 has a conductive material (such as a metal), at least some of the conductive material may be redeposited onto the sidewalls of the patterned MRAM stack. In Figure 4A When the etching front of the ion beam 425 includes the second magnetic layer 460 , magnetic components having Co, Ni, Pt, or Fe may be redeposited on the walls of the patterned MRAM stack, thereby degrading the electrical and magnetic properties of the MRAM stack 400 .

[0045] Instead of an etch front having a conductive material, the etch front may comprise a dielectric material. Figure 4BDuring etching, ion beam 425 impacts the lower surface of MRAM stack 400, directing sputtered atoms and molecules 475 toward the exposed surface of the patterned MRAM stack. The etch front of ion beam 425 includes lower layer 430, where dielectric material, such as SiO2, may be redeposited on the sidewalls of the patterned MRAM stack. Atoms and molecules 475 sputtered from the dielectric material of lower layer 430 may not degrade the electrical and magnetic properties of MRAM stack 400. Thus, overetching can be performed to etch through lower layer 430 while ensuring that any back sputtering does not harm the patterned MRAM stack. The thickness of lower layer 430 may be sufficient to serve as an etch front for ion beam etching to adequately clean the sidewalls of the patterned MRAM stack. However, as described above, it may be undesirable to include a sufficiently thick lower layer 430 between substrate 410 and MRAM stack 400, particularly as having a thick lower layer 430 may be impractical in various devices.

[0046] In the present disclosure, the MRAM stack is not provided with an underlying layer of dielectric material of sufficient thickness as an etch front during cleaning. This underlying layer of dielectric material of sufficient thickness enables removal of redeposited sidewall material before the dielectric material is etched away. In the present disclosure, an IBE main etch process is performed to form a patterned MRAM stack, and then a gapfill dielectric material is deposited in the spaces between the patterned MRAM stack. The gapfill dielectric material can be etched back or otherwise formed to a sufficient depth so that the deposited gapfill dielectric material remains during all or a majority of a subsequent IBE trim etch cleaning step. In some implementations, the thickness of the deposited gapfill dielectric material extends above the depth of the tunnel barrier layer. After depositing the gapfill dielectric material, an IBE overetch or trim etch process is performed to clean the sidewalls of the patterned MRAM stack, wherein the etch front during the IBE trim etch process includes the gapfill dielectric material.

[0047] Figure 5 A flow chart of an exemplary ion beam etching method is shown according to some implementations. Figure 5 The operations of process 500 may include additional, fewer, or different operations. Figure 5 The description of processing 500 is Figures 6A-6F 5. A series of cross-sectional schematic diagrams are shown in FIG. 5, which illustrate the main etch, gap fill, planarization, etch back, IBE trim etch, and packaging operations. The operations of process 500 may be performed using an ion beam etch apparatus (e.g., Figure 3 The ion beam etching device 310 is used.

[0048] At block 510 of process 500, a plurality of MRAM layers disposed on a substrate are etched through to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer. Etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer. In some implementations, etching through the plurality of MRAM layers includes ion beam etching through the plurality of MRAM layers. In some implementations, etching through the plurality of MRAM layers includes reactive ion etching (RIE) through some of the plurality of MRAM layers and ion beam etching through at least the tunnel barrier layer. In some implementations, the plurality of MRAM layers include two or more tunnel barrier layers, wherein the ion beam etching is performed through the two or more tunnel barrier layers. A hard mask may be formed on the plurality of MRAM layers for patterning the MRAM stack. The hard mask may be formed, for example, of W, Ti, Ta, TiN, or other refractory metals. Etching through the plurality of MRAM layers at block 510 may also be referred to as a "main etch," "cut etch," "separation etch," "first etch," or "IBE separation etch."

[0049] Etching through the multiple MRAM layers may include etching through an MTJ stack comprising a first magnetic layer, a second magnetic layer, and a tunnel barrier layer between the first and second magnetic layers. The first magnetic layer may be positioned above the tunnel barrier layer, and the second magnetic layer may be positioned below the tunnel barrier layer. The tunnel barrier layer may comprise a non-magnetic insulating material, such as MgO. Each of the first and second magnetic layers may comprise a magnetic element, such as Co, Ni, Pt, Fe, or a combination thereof. In some implementations, etching through the MTJ stack may include ion beam etching through the MTJ stack. After etching through at least the second magnetic layer, the etching may stop at an underlying layer or dielectric layer. Etching through the multiple MRAM layers may include ion beam etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, but not through the underlying layer. Thus, the main etch or the split etch may proceed to an interface between the underlying layer and the multiple MRAM layers being etched, wherein the underlying layer may comprise a dielectric material, such as SiO2. The main etch may be performed on the upper surface of the underlying layer, and the main etch may be stopped on the underlying layer using optical emission spectroscopy or an endpoint detector.

[0050] When the ion beam etching etches through at least some of the MRAM layer, an ion beam of an inert gas can be generated from an ion beam source chamber. The ion beam source chamber can be coupled to a processing chamber where the substrate is located. The ion beam can be generated in the ion beam source chamber using a gas mixture containing an inert gas. The inert gas can include helium (He), neon (Ne), argon (Ar), xenon (Xe), krypton (Kr), or a combination thereof. In some implementations, the gas mixture can include one or more reactive gases to increase material etching using chemical / reactive components. In some implementations, the gas mixture does not have or substantially does not have reactive gases. RF power can be applied to a coil surrounding the ion beam source chamber to generate a plasma, and ions are extracted from the plasma to form an ion beam. A voltage is applied to an ion extractor (such as a grid) to extract ions to form an ion beam, and the ion beam can be accelerated toward the processing chamber. Controlling the voltage applied to the ion capture device can be used to control the etching rate when performing ion beam etching. The high voltage ion beam may be between about 400V and about 2000V for a "fast" etch with a high etch rate, and the low voltage ion beam may be between about 30V and about 400V for a "soft" etch with a low etch rate. The ion beam etch (main etch or separate etch) that etches through at least some of the multiple MRAM layers, including the tunnel barrier layer, to form a patterned MRAM stack may be performed at a relatively high voltage. Therefore, the main etch for etching through the multiple MRAM layers to form the patterned MRAM stack may be performed at a high voltage between about 400V and about 2000V. On the other hand, the trim etch or overetch for cleaning the sidewalls of the patterned MRAM stack may be performed at a low voltage between about 30V and about 400V.

[0051] In some implementations, etching through at least some of the plurality of MRAM layers may include applying an ion beam having an ion energy between about 200 eV and about 10,000 eV to the substrate. Compared to the trim etch, the main etch may be performed at a high ion energy to efficiently etch the material in the MRAM layer. In some implementations, the main etch or the separate etch may be performed for 10 minutes or less, 3 minutes or less, or 1 minute or less. In some implementations, the main etch may be performed in an ion beam etching apparatus having an ion beam source chamber coupled to a process chamber. Exemplary ion beam etching is described above. Figure 3 middle.

[0052] In some implementations, reactive ion etching (RIE) may be used to etch some of the MRAM layers. Specifically, RIE may be applied to film layers other than the tunnel barrier layer, as reactive species from the RIE process can damage the tunnel barrier layer. Ion beam etching may be performed after the RIE process to etch through the tunnel barrier layer. In some implementations, RIE may be applied to a hard mask layer or electrode layer disposed above the tunnel barrier layer. In some implementations, RIE may be applied to a first magnetic layer disposed above the tunnel barrier layer. In some implementations, RIE may be applied to a second magnetic layer disposed below the tunnel barrier layer. In some implementations, RIE may be applied to an electrode layer disposed below the second magnetic layer. However, any of the aforementioned MRAM layers may be etched using ion beam etching rather than RIE. Therefore, the main etching sequence for etching through multiple MRAM layers may include RIE followed by IBE, RIE followed by IBE and then RIE, IBE followed by RIE, or IBE throughout.

[0053] The main etch may cause conductive material to be redeposited onto the sidewalls of the patterned MRAM stack. The redeposited conductive material may be from one or more magnetic layers in the plurality of MRAM layers. Typically, when etching one or more magnetic layers in the plurality of MRAM layers, etching byproducts are generated that can be redeposited onto the exposed surface. The etching byproducts may include atoms or molecules of a metal or conductive material. When an ion beam is applied to the plurality of MRAM layers, these etching byproducts are sputtered. The one or more magnetic layers may include a non-volatile material, wherein the non-volatile material may include a magnetic material such as Co, Ni, Pt, Fe, etc. When such etching byproducts are redeposited onto the side surfaces of the tunnel barrier layer, the MTJ stack is adversely affected and may cause a short circuit.

[0054] Etching through the plurality of MRAM layers forms a patterned MRAM stack, wherein the patterned MRAM stack is a line, pillar, or other patterned feature. The main etch forms spaces between the patterned MRAM stacks. In some implementations, the patterned MRAM stack is a plurality of pillars having a high aspect ratio, wherein the aspect ratio of the patterned MRAM stack is at least 5:1, at least 7:1, at least 10:1, or at least 20:1. In some implementations, the pitch between adjacent MRAM stacks can be equal to or less than approximately 300 nm, between approximately 10 nm and approximately 300 nm, or between approximately 30 nm and approximately 250 nm.

[0055] In some implementations, the substrate can be positioned in a processing chamber of an ion beam etching tool prior to block 510 of process 500. A plurality of MRAM layers can be disposed on the substrate, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer.

[0056] Figure 6A A schematic cross-sectional view of an exemplary main etch according to some implementations is shown. Multiple MRAM layers 650, 660, and 670 are positioned above a substrate 610, and a lower layer 630 is positioned between the multiple MRAM layers 650, 660, and 670 and the substrate 610. Aspects of the multiple MRAM layers 650, 660, and 670 and the lower layer 630 are shown in FIG. Figure 1 and Figure 2 As described in [ 15 ], the plurality of MRAM layers 1650, 660, and 670 include at least a first magnetic layer 650, a second magnetic layer 660, and a tunnel barrier layer 670 between the first and second magnetic layers 650, 660. As described above, the plurality of MRAM layers 650, 660, and 670 may include a plurality of tunnel barrier layers, each sandwiched between a first and second magnetic layer. A main etch is performed to form patterned MRAM stacks 620a, 620b. The main etch may stop on the upper surface of the lower layer 630. In some implementations, the main etch or the split etch is performed through at least the tunnel barrier layer 670 when forming the patterned MRAM stacks 620a, 620b. An ion beam for the main etch or the split etch may be provided at a relatively high ion energy and a relatively low incident angle, the incident angle being normal to the substrate surface. Residues 605 comprising metal or conductive material are formed on the sidewalls of the patterned MRAM stacks 620a, 620b as a result of the main etch. Sputtered atoms and / or molecules from ion beam etching of the plurality of MRAM layers 650, 660, and 670 may cause accumulation of residue 605. The residue 605 may form on the tunnel barrier layer 670 and degrade the performance of the tunnel barrier layer 670.

[0057] Back to Figure 5 At block 520 of process 500, a gapfill dielectric material is formed in the space between the patterned MRAM stacks. In some implementations, the gapfill dielectric material may be formed along the sidewalls and lower surface of the patterned MRAM stacks. In some implementations, the gapfill dielectric material may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or plasma enhanced chemical vapor deposition (PECVD). However, it should be understood that the gapfill dielectric material may be deposited using any other suitable deposition technique, such as atomic layer deposition (ALD). For example, the gapfill dielectric material may be deposited in the space between the patterned MRAM stacks using a deposition technique to achieve bottom-up filling.

[0058] In some implementations, the gapfill dielectric material comprises any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, germanium nitride, magnesium oxide, or a combination thereof. For example, the gapfill dielectric material comprises one or both of silicon nitride and silicon oxide. The gapfill dielectric material may comprise a silicon nitride layer and a silicon oxide layer, or may comprise only a silicon nitride layer. In some implementations, it is desirable to avoid direct contact of the silicon oxide with the patterned MRAM stack. The above-mentioned dielectric material may fill the space between the patterned MRAM stacks, or at least fill the space above the underlying layer. Forming the gapfill dielectric material in the space between the patterned MRAM stacks may also be referred to as a "gapfill" or "dielectric gapfill" process.

[0059] In some implementations, gap filling can be performed in a deposition chamber such as a CVD, PVD, or PECVD chamber. Gap filling can be performed after the main etch and before the IBE trim etch. In some implementations, the main etch and gap filling can be performed in an integrated tool or a multi-station processing tool. The main etch operation at block 510 and the gap filling at block 520 can be performed in a manner that does not result in a vacuum break between operations.

[0060] In some implementations, forming a gapfill dielectric material in the spaces between the patterned MRAM stacks includes depositing the gapfill dielectric material in the spaces between the patterned MRAM stacks and above the patterned MRAM stacks, and selectively etching the gapfill dielectric material to a sufficient depth above an underlying layer. In some implementations, the sufficient depth above the underlying layer can correspond to a sufficient thickness to leave at least some gapfill dielectric material after the subsequent trim etch at block 530. The gapfill dielectric material can be initially deposited above the patterned MRAM stacks to create an excess of material. The gapfill deposition process is typically somewhat conformal, resulting in material being deposited along the sidewalls, lower surface, and upper surface of the patterned MRAM stacks. The gapfill deposition process can result in a somewhat "loaf-of-bread shape" because the deposition rate varies between the upper surface of the patterned MRAM stack and the lower surface of the patterned MRAM stack. This often results in an uneven topography from the gapfill. Therefore, when filling the spaces between the patterned MRAM stacks, an excess amount of gapfill dielectric material may be deposited, wherein the excess amount of gapfill dielectric material may be non-uniform in thickness across the upper surface of the gapfill dielectric material. In other words, some portions of the gapfill dielectric material are thicker than other portions.

[0061] After depositing excess gapfill dielectric material over the patterned MRAM stack, the excess material may be removed. In some implementations, process 500 further includes planarizing the gapfill dielectric material deposited over the patterned MRAM stack. For example, the excess material may be removed using chemical mechanical polishing (CMP) or etching.

[0062] In addition to or as an alternative to planarizing the excess material, the deposited gapfill dielectric material can be selectively etched using a dry or wet etch technique, wherein the gapfill dielectric material is selectively etched to a depth above the underlying layer. In some implementations, the depth can be between the upper surface of the tunnel barrier layer and the upper surface of the first magnetic layer, between the lower surface of the tunnel barrier layer and the lower surface of the second magnetic layer, or between the lower surface of the second magnetic layer and the upper surface of the underlying layer. When the multiple MRAM layers include multiple tunnel barriers having multiple first / second magnetic layers, the depth can be measured relative to the lowest tunnel barrier layer and the lowest first / second magnetic layer. In some implementations, the selective etch is a plasma etch that selectively removes the gapfill dielectric material without removing or substantially removing any hardmask layer or MRAM layer. The etch can have an etch selectivity greater than approximately 10:1 between the gapfill dielectric material and the hardmask layer or MRAM layer, meaning that the etch rate of the gapfill dielectric etch is greater than ten times the etch rate of the hardmask layer or MRAM layer. For example, the gap-fill dielectric material can be etched with fluorine plasma in a reactive ion etch (RIE) or chemical downstream etch (CDE) chamber. If the dielectric material is silicon oxide, it can also be removed using hydrogen fluoride (HF) vapor. The sufficient depth above the underlying layer can be between about 1 nm and about 20 nm above the depth of the underlying layer, between about 2 nm and about 15 nm above the depth of the underlying layer, or between about 3 nm and about 10 nm above the depth of the underlying layer. In some implementations, selective etching can be performed to remove the gap-fill dielectric material without exposing any underlying layer. In some implementations, selective etching can be performed to remove the gap-fill dielectric material without significantly etching through the underlying layer. As used herein, "substantially etching" through the underlying layer can constitute etching through at least 3 nm or at least 5 nm of the underlying layer. In some implementations, the sufficient depth above the underlying layer can be above the tunnel barrier layer. As described above, exposing the tunnel barrier layer to the reactant chemicals may damage the tunnel barrier layer. The selective etch leaves a residual gap-fill dielectric material to serve as an etch front during the IBE trim etch used to clean the sidewalls of the patterned MRAM stack. In some implementations, the selective etch can be stopped at an etch depth just above the tunnel barrier layer or at a sufficient depth above the underlying layer using appropriate endpoint detection techniques, such as optical emission spectroscopy (OES) or interferometric endpoint detection (IEP). The selective etch may also be referred to as an "etch back" process or an "isotropic etch back" process.

[0063] Figure 6B Shows that some implementations are being Figure 6A Schematic diagram of a cross-section of an exemplary gap fill process after the main etch of . After the main etch, a gap fill dielectric material 680 is deposited in the space between the patterned MRAM stacks 620a, 620b using a suitable deposition technique (e.g., CVD, PVD, or PECVD). In some implementations, the gap fill dielectric material 680 is conformally deposited along the exposed surfaces (e.g., sidewalls) of the patterned MRAM stacks 620a, 620b to perform the gap fill. Thus, any recess, gap, trench, opening, or space is filled by the gap fill dielectric material 680. Excess material of the gap fill dielectric material 680 is deposited above the patterned MRAM stacks 620a, 620b. In some implementations, the gap fill dielectric material 680 comprises silicon nitride or a combination of silicon nitride and silicon oxide.

[0064] Figure 6C Shows that some implementations are being Figure 6B Schematic cross-sectional view of an exemplary planarization process following a gapfill process. After depositing excess gapfill dielectric material 680, the upper surface of the excess material may be uneven. For example, the uneven topography may result in more dielectric gapfill material 680 in the field than in the gapfill area, which may result in a loaf-like shape. A planarization process (e.g., CMP or etching) may be performed to smooth the topography and remove excess material.

[0065] Figure 6D Shows that some implementations are being Figure 6CSchematic cross-sectional view of an exemplary etch-back process after a planarization process. After the planarization process or the gap-fill process, an etch-back process is performed to selectively remove the gap-fill dielectric material 680 relative to the plurality of MRAM layers 650, 660, and 670, or at least relative to the first magnetic layer 650. In some implementations, the etch-back process selectively removes the gap-fill dielectric material 680 relative to the hard mask layer. The etch-back process can be a dry etch or a wet etch. The dry etch can be a plasma etch. The etch-back process can be performed to remove the gap-fill dielectric material 680 to an etch depth above the underlying layer 630. In some implementations, the etch-back process can be performed to remove the gap-fill dielectric material 680 to an etch depth slightly above the depth of the tunnel barrier layer 670. In particular, the etch-back process can be performed to an etch depth slightly above the interface between the tunnel barrier layer 670 and the first magnetic layer 650. For example, the remaining gap-fill dielectric material 680 can be located at an etch depth of several nanometers above the upper surface of the tunnel barrier layer 670. In this manner, the tunnel barrier layer 670 is not exposed to the etch-back process. However, it should be understood that some implementations involving conformal deposition processes may not require this etch-back or planarization process.

[0066] Back to Figure 5 At block 530 of process 500, ion beam etching is performed to remove at least some of the gapfill dielectric material and the conductive material deposited on the sidewalls of the patterned MRAM stack. The ion beam etching, after forming the gapfill dielectric material over the underlying layer, is used to clean the sidewalls of the patterned MRAM stack. The ion beam etching that cleans the sidewalls of the patterned MRAM stack may remove the gapfill dielectric material to an etch depth that is below the depth of the tunnel barrier layer. In some implementations, the etch depth below the depth of the tunnel barrier layer does not reach the depth of the underlying layer. The ion beam etching used to clean the sidewalls of the patterned MRAM stack may also be referred to as an "overetch," "trim etch," "IBE trim etch," "sidewall clean etch," or "low-power trim etch."

[0067] The material deposited on the sidewalls of the patterned MRAM stack may include a metal or a conductive material. The metal or conductive material may be sputtered during the main etch at block 510 and redeposited on the sidewalls of the patterned MRAM stack. In other words, after the main etch, the back-sputtered, potentially damaged material may be located on the sidewalls of the patterned MRAM stack. In some implementations, some of the metal may include W, Ta, Ti, or TiN from the hard mask layer or electrode layer, and some of the metal may include Co, Ni, Pt, or Fe from the first or second magnetic layer. The metal or conductive material forms undesirable residues on the sidewalls of the patterned MRAM stack and may degrade the electrical and magnetic properties of the MTJ stack. Ion beam etching is performed at block 530, where the ion beam etching is performed at low power and an optimized angle of incidence to remove the undesirable residues.

[0068] When ion beam etching is performed to remove redeposited material on the sidewalls of the patterned MRAM stack, the ion beam can be generated from an ion beam source chamber using a gas mixture comprising an inert gas. In some embodiments, the gas mixture can include one or more reactive gases to enhance material etching using chemical / reactive components. In some embodiments, the gas mixture contains no or substantially no reactive gases. Ion beam etching can be performed at a relatively low voltage to remove redeposited material on the sidewalls of the patterned MRAM stack. In some embodiments, etching to remove redeposited material on the sidewalls of the patterned MRAM stack can include applying an ion beam having an energy between approximately 20 eV and approximately 400 eV to the substrate. An IBE trim etch can be performed at a lower ion energy relative to the main etch to remove undesirable residue. In some embodiments, the IBE trim etch can be performed for approximately 1 minute or longer, 3 minutes or longer, 5 minutes or longer, or 10 minutes or longer. In some implementations, the IBE trim etch can be performed in alternating first and second directions with or without rotating the substrate. Low ion energy is desirable for trimming to reduce ion-induced mixing effects of the MTJ layer.

[0069] In some implementations, the IBE trim etch can be performed in an ion beam etching tool (e.g. Figure 3The IBE trim etch can be performed in an ion beam etching apparatus as described in

[0045] . The IBE trim etch can be performed after gapfill, after planarization, or after etchback. In some implementations, the IBE trim etch and gapfill can be performed in an integrated tool or a multi-station processing tool. The gapfill operation at block 520 and the IBE trim etch at block 530 can be performed without breaking vacuum between operations. In some implementations, the main etch at block 510, the gapfill at block 520, and the IBE trim etch at block 530 can be performed without breaking vacuum between operations.

[0070] During the IBE trim etch, metal or other conductive materials are preferably not exposed. The remaining gapfill dielectric material serves as an etch front during the IBE trim etch to significantly reduce any backsputtering of metal or conductive material. Instead, by utilizing the etch front of the gapfill dielectric material, any backsputtering of the dielectric material does not adversely affect the electrical and magnetic properties of the MTJ stack. The IBE trim etch can remove the gapfill dielectric material to an etch depth below the interface between the tunnel barrier layer and the second magnetic layer without etching into the underlying layers. This maintains the initial etch front from the main etch at block 510 and avoids recessing or significantly recessing into the underlying layers.

[0071] In some implementations, the IBE trim etch removes material deposited on the sidewalls of the patterned MRAM stack. The exposed sidewalls of the patterned MRAM stack are free, or substantially free, of metal or conductive material deposited on the sidewalls of the patterned MRAM stack. The threshold for when the sidewalls are considered sufficiently clean can be set by the shorting performance of the MRAM device, measured as the fraction of shorted devices among all devices. Typically, only one or fewer devices in a million will short. Therefore, any remaining residue is sufficiently thin to minimally impact the off-state impedance of the MRAM device. For example, "substantially free" with respect to redeposited conductive material can mean a deposition thickness of less than approximately 1.5 nm, less than approximately 1.0 nm, or less than approximately 0.5 nm. Thus, any redeposited conductive material on the tunnel barrier layer after the IBE trim etch is negligible or nonexistent. The IBE trim etch can be performed for a sufficient length of time to remove the undesirable material so that the exposed sidewalls of the patterned MRAM stack are free, or substantially free, of redeposited conductive material.

[0072] Figure 6E Shows that some implementations are being Figure 6DSchematic cross-sectional view of an exemplary IBE trim etch process following an etch-back process. The remaining gapfill dielectric material 680 serves as an etch front during the IBE trim etch process. During the IBE trim etch process, an ion beam 625 is provided at a relatively low ion energy and an optimized angle of incidence to clean the sidewalls of the patterned MRAM stacks 620a, 620b. As the IBE trim etch process proceeds, the ion beam 625 removes residue 605 from the sidewalls of the patterned MRAM stacks 620a, 620b. Sputtered atoms and / or molecules 675 from the ion beam 625 may be directed toward the sidewalls of the patterned MRAM stacks 620a, 620b. However, the sputtered atoms and / or molecules 675 include dielectric material from the remaining gapfill dielectric material 680, which does not adversely affect the characteristics of the patterned MRAM stacks 620a, 620b. The IBE trim etch process proceeds to an etch depth below the depth of the tunnel barrier layer 670 and above the underlying layer 630. In some implementations, the IBE trim etch process does not penetrate significantly into the underlying layer 630. The exposed sidewalls of the patterned MRAM stacks 620a, 620b are free of residues 605 comprising conductive or magnetic material.

[0073] In some implementations, process 500 further includes conformally depositing an encapsulation material on at least the exposed sidewalls of the patterned MRAM stack after performing the IBE trim etch at block 530. The encapsulation material may include a suitable dielectric material, such as silicon nitride. The encapsulation material may be deposited to avoid or minimize damage to the tunnel barrier layer that may be exposed to air.

[0074] Figure 6F Shows that some implementations are being Figure 6E Figure 6 is a cross-sectional diagram of an exemplary encapsulation process following an IBE trim etch process. Encapsulation layer 690 comprises a dielectric material (e.g., silicon nitride) and is conformally deposited on the exposed surfaces of the patterned MRAM stacks 620a, 620b. Encapsulation layer 690 is conformally deposited along the sidewalls of the patterned MRAM stacks 620a, 620b and serves to protect at least tunnel barrier layer 670 from exposure to the ambient environment.

[0075] Figure 7A block diagram of an exemplary processing system for performing deposition and ion beam etching processes according to some implementations is shown. The processing system 700 can be a multi-station processing tool having one or more processing stations. The processing system 700 can include an inbound load lock 702 and an outbound load lock 704, one or both of which can include a plasma generating source. A robot 706 at atmospheric pressure is configured to move a substrate from a cassette loaded through a cabin 708 into the inbound load lock 702 via an atmospheric interface 710. In the inbound load lock 702, the robot 706 places the substrate onto a platform 712, and then the atmospheric port 710 is closed and the load lock 702 is evacuated. The chamber transfer port 716 is opened, the processing chamber 714, and another substrate handling system 718, which acts as another robot, places the substrate into one of the processing stations 780, 782, or from the loading station to the processing station 790 for processing. Although Figure 7 The implementation depicted in FIG includes a load lock, but it will be appreciated that in some implementations direct access of substrates into the processing stations may be provided.

[0076] The processing chamber 714 shown includes three processing stations 780, 782 and 790. The processing station 790 can be a removable module and can be adapted to process more than one substrate at a time. In this example, the processing station 790 includes four substations, namely Figure 7 Implement numbers 1 to 4 as shown in the scheme.

[0077] Each processing station (780, 782, and each of 1, 2, 3, and 4) may have a heated susceptor and a gas line inlet. It should be understood that in some implementations, each processing station may have different or multiple purposes. For example, in some implementations, processing station 780 may be used to deposit a gapfill dielectric material on a substrate, where the deposition technique may be CVD, PECVD, or other suitable deposition techniques. In some implementations, processing station 782 may be used to perform a main etch using IBE, and processing station 790 may be used to perform an IBE trim etch. In certain other implementations, processing station 790 may be used to perform ion beam etching for both the main etch and the IBE trim etch. Processing station 782 may be used to perform other processes, such as CMP, selective etch back, or CVD / PECVD / PVD. In some implementations, processing station 790 may have multiple substations 1-4 for performing multiple IBE trim etch processes or other processes. The IBE trim etch may take longer than the main etch and deposition processes. Although the processing station 790 is shown as including four substations, it should be understood that a processing station according to the present disclosure may include any number of substations. Furthermore, although the processing system 700 includes three processing stations (780, 782, and 790), it should be understood that in some implementations, the apparatus may include more or less than three processing stations because each processing station may be a removable or modifiable module. For example, in some implementations, the processing system 700 may have four or more processing stations, but in some other implementations, the processing system 700 may have two or fewer processing stations. In some implementations, additional processing stations may be used for planarization processing, such as CMP. In some implementations, additional processing stations may be used for selective etch back to remove gap fill dielectric material.

[0078] In some implementations, the processing system 700 may be an integrated multi-station processing tool for performing IBE (main and trim etch) and CVD / PECVD / PVD. For example, processing stations 780, 782, and 790 may be used to perform main etch, gap fill, trim etch, and packaging operations. The main etch, gap fill, trim etch, and packaging operations may be performed in a manner that does not result in a vacuum break between operations. Additional operations of planarization (e.g., CMP) and / or selective etch back (e.g., plasma etch) may be performed in separate tools or in an integrated multi-station processing tool. It should be understood that since the tunnel barrier layer of the MTJ stack will not be exposed to air or the ambient environment during planarization or selective etch back, such operations may be performed in separate tools. The tunnel barrier layer is protected by the gap fill dielectric material during planarization or selective etch back.

[0079] Figure 7A substrate handling system 718 is shown for transporting substrates within the processing chamber 700. In some implementations, the substrate handling system 718 can transport substrates between various processing stations and / or between a processing station and a load lock. Furthermore, the processing station 790 can include a separate substrate handling system 760 for moving substrates from another loading station 762 to the processing station 790. It should be understood that any suitable substrate handling system can be used. Non-limiting examples include a substrate turntable and a substrate handling robot.

[0080] In various implementations, integration of various stations can address footprint reduction issues and can efficiently transfer substrates between operations without causing vacuum to be broken. Figure 7 Also shown is an implementation of a system controller 750 for controlling processing conditions and hardware states of the processing system 700. The system controller 750 may include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. Aspects of the system controller 750 are described above with reference to Figure 3 Depending on the process step or steps to be performed by the tool, the system controller 750 may communicate with one or more of: circuits or modules of one or more other tools, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located within a factory, a host computer, another controller, or tools used in material transport to transfer substrate containers to and from tool locations.

[0081] Figure 8 An alternative block diagram of an exemplary processing system for performing deposition and ion beam etching processes according to some implementations is shown. Processing system 800 includes a transport module 803. Transport module 803 provides a clean, pressurized environment to minimize the risk of contamination when the substrate being processed is moved between various reactor modules. Multiple station reactors 807, 808, and 809 mounted to transport module 803 are referred to in this context as reactors or tool modules or simply modules, each of which is capable of performing ion beam etching and / or deposition. Reactors 807, 808, and 809 may include multiple stations 811, 813, 815, and 817 that may operate sequentially or non-sequentially according to the disclosed implementations. Each of stations 811, 813, 815, and 817 may be a heated susceptor or substrate support, one or more gas inlets or showerheads, or a dispersion plate. One or more of modules 807, 808, and 809 may be capable of performing ion beam etching, wherein the ion beam etching may be used to perform a main etch and / or a trim etch. Thus, one or more of modules 807, 808, and 809 may include a Figure 3ion beam etching equipment of the ion beam source chamber and the process chamber shown in . Another one or more of modules 807, 808 and 809 may be capable of performing deposition operations such as CVD / PECVD / PVD. Thus, the main etch, gap fill, trim etch and packaging operations can be performed in a manner that does not cause vacuum to be broken between operations.

[0082] The processing system 800 may also include one or more substrate source modules 801, in which substrates are stored before and after processing. An atmospheric robot 804 and an atmospheric transfer chamber 819 may first remove substrates from the source module 801 and transfer them to a load lock 821. A second substrate transfer device (typically a robot arm unit) in the transfer module 803 moves substrates from the load lock 821 to a module on the transfer module 803 in a pressurized (e.g., vacuum) environment, or moves substrates between modules.

[0083] In various implementations, the system controller 829 is used to control processing conditions and activities during processing. The system controller 829 typically includes one or more memory devices and one or more processors. Aspects of the system controller 829 are described above with reference to Figure 3 Depending on the process step or steps to be performed by the tool, the system controller 829 may communicate with one or more of: circuits or modules of one or more other tools, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located within the factory, a host computer, another controller, or tools used in material transport to transfer substrate containers to and from tool locations.

[0084] Figure 9 A block diagram of an exemplary processing system for performing planarization and / or etching processes is shown according to some implementations. Processing systems 700 and 800 can be integrated multi-station processing tools for performing ion beam etching and deposition, and can transfer a substrate to processing system 900 for performing planarization and / or selective etching processes.

[0085] The processing system 900 may include a vacuum transfer module 938 (VTM). A configuration of multiple transfer modules for transferring substrates between multiple storage facilities and processing modules may be referred to as a "cluster tool architecture" system. An airlock 930 (also referred to as a load lock or transfer module) is shown within a vacuum transfer module 938 having four processing modules 920a, 920b, 920c, and 920d. Each of the processing modules 920a, 920b, 920c, and 920d may be individually optimized for various operations. For example, one or more of the processing modules 920a, 920b, 920c, and 920d may be used for selective etching. One or more of the processing modules 920a, 920b, 920c, and 920d may be used for planarization processes, such as CMP. In some implementations, one or more of the processing modules 920a, 920b, 920c, and 920d may be used for ion beam etching or deposition. The airlock 930 and process modules 920a, 920b, 920c, and 920d may be referred to as "stations." Each station has a facet 936 that interfaces with a vacuum transfer module 938. As the substrate moves between stations, sensors 1-18 are used within each facet 936 to detect the passage of the substrate 926.

[0086] A robot 922 can be used to transfer substrates 926 between stations. In one embodiment, the robot 922 can have a single arm; in another embodiment, the robot 922 has two arms, each of which has an end effector 924 for picking up a substrate (e.g., substrate 926) for transfer. A front-end robot 932 in an atmospheric transfer module (ATM) 940 is used to transfer substrates 926 from a wafer cassette or front-opening unpacking unit (FOUP) 934 in a load port module (LPM) 942 to an airlock 930. Module centers 928 within process modules 920a, 920b, 920c, and 920d are locations for placing substrates 926. An alignment device 944 in the ATM 940 is used to align the substrates.

[0087] In an exemplary processing method, a substrate is placed into one of the FOUPs 934 in the LPM 942. The front-end robot 932 transfers the substrate from the FOUP 934 to the alignment device 944, which properly centers the substrate 926 before etching or processing. After alignment, the front-end robot 932 moves the substrate 926 into the airlock 930. Because the airlock module has the ability to match the environments between the ATM and VTM, the substrate 926 can be moved between the two pressure environments without damage. The robot 922 moves the substrate 926 from the airlock 930 via the vacuum transfer module 938 to one of the processing modules 920a, 920b, 920c, or 920d. To accomplish this substrate movement, the robot 922 utilizes an end effector 924 on each of its arms. Once the substrate 926 has been processed, the robot 922 moves the substrate 926 from the processing modules 920a, 920b, 920c, and 920d into the airlock 930. From here, the front end robot 932 can move the substrate 926 to one of the FOUPs or to the aligner 944. Figure 9 The tools in the above are used to implement Figure 3 Depending on the one or more process steps to be performed by the tool, the controller may communicate with one or more of: circuitry or modules of one or more other tools, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located within a factory, a host computer, another controller, or tools used in material transport to transfer substrate containers to and from tool locations. in conclusion

[0088] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the embodiments presented. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to avoid obscuring the disclosed embodiments. Although the disclosed embodiments are described in conjunction with specific embodiments, it should be understood that this is not intended to limit the disclosed embodiments.

[0089] Although the foregoing embodiments have been described in detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be made within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the embodiments of the present invention. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

1. An ion beam etching method, comprising: etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer, wherein etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap-fill dielectric material in spaces between the patterned MRAM stacks, wherein the gap-fill dielectric material comprises silicon nitride, silicon oxide, silicon oxycarbide, germanium oxide, magnesium oxide, germanium nitride, or a combination thereof; as well as An IBE trim etch is performed to remove at least some of the gapfill dielectric material and conductive material deposited on sidewalls of the patterned MRAM stack.

2. The method of claim 1 , wherein the gap-fill dielectric material is formed to a sufficient depth above an underlying layer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not cause recessing in the underlying layer. 3 . The method of claim 2 , wherein the sufficient depth above the underlying layer is between about 1 nm and about 20 nm above an upper surface of the underlying layer.

4. The method of claim 1 , wherein forming the gap-fill dielectric material in the space between the patterned MRAM stacks comprises: The gap-fill dielectric material is deposited in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

5. The method of claim 4 , wherein forming the gap-fill dielectric material in the space between the patterned MRAM stacks further comprises: The gapfill dielectric material is selectively etched to an etch depth above a depth of the tunnel barrier layer.

6. The method according to claim 5, further comprising: The gap-fill dielectric material deposited over the patterned MRAM stack is planarized.

7. The method of claim 1, wherein the gap-fill dielectric material comprises one or both of silicon nitride and silicon oxide.

8. The method of any one of claims 1-7, wherein the operations of etching through the plurality of MRAM layers, forming the gap-fill dielectric material, and performing the IBE trim etch are performed in a manner that does not result in a vacuum break between operations.

9. The method of claim 1 , wherein the plurality of MRAM layers comprises a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, wherein the underlayer comprises a dielectric material, and wherein the tunnel barrier layer comprises a non-magnetic insulating material.

10. The method of claim 9, wherein etching through the plurality of MRAM layers comprises etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer but not through the underlying layer by the ion beam etching.

11. The method of claim 9, wherein etching through the plurality of MRAM layers comprises reactive ion etching (RIE) through the first magnetic layer and ion beam etching through the tunnel barrier layer. 12 . The method of claim 9 , wherein etching through the plurality of MRAM layers comprises etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, wherein etching through the plurality of MRAM layers stops on the underlying layer.

13. The method of any one of claims 1-7, wherein ion beam etching through at least the tunnel barrier layer comprises applying a first ion beam having an energy between about 200 eV and about 10,000 eV to the substrate, and wherein performing IBE trim etching comprises applying a second ion beam having an energy between about 20 eV and about 400 eV to the substrate.

14. The method according to any one of claims 1 to 7, wherein the IBE trim etching is performed in a manner not to etch through an underlying layer disposed below the plurality of MRAM layers.

15. The method according to any one of claims 1 to 7, further comprising: After performing the IBE trim etch, an encapsulation material is conformally deposited onto at least the sidewalls of the patterned MRAM stack.

16. An ion beam etching method, the method comprising: etching through a plurality of magnetoresistive random access memory (MRAM) layers disposed on a substrate to form a patterned MRAM stack, wherein the plurality of MRAM layers include one or more magnetic layers and a tunnel barrier layer, wherein etching through the plurality of MRAM layers includes ion beam etching (IBE) through at least the tunnel barrier layer; forming a gap-fill dielectric material in spaces between the patterned MRAM stacks; as well as An IBE trim etch is performed to remove at least some of the gapfill dielectric material and the conductive material deposited on sidewalls of the patterned MRAM stack, wherein the operations of etching through the plurality of MRAM layers, forming the gapfill dielectric material, and performing the IBE trim etch are performed in a manner that does not result in a vacuum breach between operations. 17 . The method of claim 16 , wherein the gap-fill dielectric material is formed to a sufficient depth above an underlying layer disposed between the substrate and the plurality of MRAM layers such that performing the IBE trim etch does not cause recessing in the underlying layer.

18. The method of claim 17, wherein the sufficient depth above the underlying layer is between about 1 nm and about 20 nm above an upper surface of the underlying layer.

19. The method of claim 16, wherein forming the gap-fill dielectric material in the space between the patterned MRAM stacks comprises: The gap-fill dielectric material is deposited in the spaces between the patterned MRAM stacks and over the patterned MRAM stacks.

20. The method of claim 19, wherein forming the gap-fill dielectric material in the space between the patterned MRAM stacks further comprises: The gapfill dielectric material is selectively etched to an etch depth above a depth of the tunnel barrier layer.

21. The method of claim 20, further comprising: The gap-fill dielectric material disposed over the patterned MRAM stack is planarized.

22. The method of any one of claims 16 to 21, wherein the plurality of MRAM layers comprises a first magnetic layer, a second magnetic layer, the tunnel barrier layer between the first magnetic layer and the second magnetic layer, and an underlayer disposed below the second magnetic layer, wherein the underlayer comprises a dielectric material, and wherein the tunnel barrier layer comprises a non-magnetic insulating material.

23. The method of claim 22, wherein etching through the plurality of MRAM layers comprises etching through the first magnetic layer, the tunnel barrier layer, and the second magnetic layer but not through the ion beam etching of the underlying layer.

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