Embedded power module with multiple chips connected in parallel

Abstract

An embedded power module with multiple chips connected in parallel comprises a first AMB board, a chip assembly, a second AMB board and a circuit board. The first AMB board comprises a first insulating layer, a first lower copper layer and a first upper copper layer. The first upper copper layer is provided with a plurality of embedding grooves, and the chip assembly comprises a chip and a copper bar. The second AMB board comprises a second insulating layer, a second lower copper layer and a second upper copper layer. The first insulating layer is welded with the first upper copper layer, the second lower copper layer is welded with the first upper copper layer, the second insulating layer and the second lower copper layer are provided with avoiding holes, and the chip assembly is located in the avoiding holes and the embedding groove, so that double paths with double-sided heat dissipation are formed, and the heat dissipation efficiency is improved. The lower surface of the copper bar is connected to the chip, the upper surface of the copper bar is connected with the second upper copper layer, the laminated structure also shortens the vertical path of current input and output, the current loop area is reduced, and the stray inductance is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of power modules, and in particular to an embedded multi-chip parallel power module. Background Art

[0002] With the rapid development of electric vehicles and renewable energy generation, power semiconductor modules are evolving toward high power density, high frequency, and high-temperature operation. The widespread adoption of wide-bandgap semiconductor devices, such as silicon carbide (SiC), has placed increasingly stringent demands on packaging technology for heat dissipation, mechanical reliability, and electrical performance. Currently, using printed circuit boards (PCBs) to connect chips is a common solution. Traditional power modules often employ single-sided heat dissipation, with heat primarily dissipated outward through a single heat sink. In high-power density scenarios, heat easily accumulates within the module, leading to excessively high chip junction temperatures. This not only reduces module efficiency but can also cause thermal failure and shorten service life. Furthermore, to achieve high current output or redundant designs, power modules often require multiple chips to be connected in parallel. Traditional paralleling solutions often use planar interconnect wirebonds, but these solutions present several challenges: First, planar interconnects have long and dispersed paths, resulting in high parasitic inductance and resistance, leading to uneven current distribution between chips and an increased risk of local overcurrent. Second, the parasitic parameters of the bond wires increase significantly with increasing frequency, impacting the module's high-frequency characteristics. Summary of the Invention

[0003] In view of this, the present invention provides an embedded multi-chip parallel power module to solve the above technical problems.

[0004] A power module with embedded multi-chips in parallel includes a first AMB board, multiple chip assemblies arranged on the first AMB board, a second AMB board arranged on the first AMB board, and a circuit board arranged on the second AMB board. The first AMB board includes a first insulating layer, a first lower copper layer arranged on the first insulating layer, and a first upper copper layer arranged on the first insulating layer. The first insulating layer is located between the first lower copper layer and the first upper copper layer, and the first upper copper layer is provided with multiple embedded trenches. The chip assemblies include multiple chips arranged on the first AMB board and multiple copper bars arranged on the chips. The second AMB board includes a second insulating layer, a second lower copper layer arranged on the second insulating layer, and a second upper copper layer arranged on the second insulating layer. The second insulating layer is located between the second lower copper layer and the second upper copper layer. The second lower copper layer is disposed on the end surface of the second insulating layer facing the first AMB board, while the second upper copper layer is disposed on the end surface of the second insulating layer facing away from the first AMB board. The second lower copper layer is welded to the first upper copper layer. Avoidance holes are provided in the second insulating layer and the second lower copper layer corresponding to the position of the chip assembly. The chip assembly is located within the avoidance holes and the embedded groove. The lower surface of the copper busbar is connected to the chip, and the upper surface of the copper busbar is connected to the second upper copper layer of the second AMB board. The lower surface of the circuit board is welded to the upper surface of the second upper copper layer and a plurality of electrodes are correspondingly provided.

[0005] Furthermore, silver paste is provided in the embedded groove.

[0006] Furthermore, the first insulating layer and the second insulating layer are made of Si3N4, with a thermal conductivity of more than 80W / (m·K) and an overall thermal resistance of less than 0.01 K / W.

[0007] Furthermore, the embedded multi-chip parallel power module further includes a plastic package provided on the first AMB board and the second AMB board, a circuit board provided on the second AMB board, and two heat dissipation substrates provided on the first AMB board.

[0008] Furthermore, the plastic packaging body is formed by coating the first AMB board and the second AMB board with a sealing material and then solidifying the sealing material.

[0009] Furthermore, the lower surface of the first lower copper layer is exposed from the plastic package body and is flush with the bottom surface of the plastic package body, and the upper surface of the second upper copper layer is exposed from the plastic package body and is flush with the top surface of the plastic package body.

[0010] Furthermore, the lower surface of the circuit board is welded to the upper surface of the second upper copper layer and a plurality of electrodes are correspondingly provided. The electrodes and the copper busbars are connected through the second upper copper layer, so that two of the copper busbars of a chip are led out and connected to the control circuit on the circuit board.

[0011] Furthermore, the heat dissipation substrates are respectively arranged on the upper surface of the circuit board and the lower surface of the first lower copper layer, and a plurality of refrigerants are arranged in the heat dissipation substrates.

[0012] Compared with the prior art, the second AMB board of the embedded and multi-chip parallel power module provided by the present invention is welded to the first AMB board in a stacked manner, and the chip assembly is sandwiched between the two boards. The heat generated by the chip assembly can be simultaneously transferred downward to the heat dissipation substrate below through the first lower copper layer, and transferred upward to the heat dissipation substrate above through the second upper copper layer, forming a dual-path mode of double-sided heat dissipation, which greatly improves the heat dissipation efficiency. The stacked structure also shortens the vertical path of current input and output, reduces the current loop area, and effectively reduces stray inductance. The connection method of the copper busbar avoids the parasitic capacitance problem of traditional leads, and cooperates with the forced convection heat exchange of the refrigerant in the heat dissipation substrate to ultimately achieve the combined advantages of high reliability, low inductance and efficient heat dissipation. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A cross-sectional view of an embedded multi-chip parallel power module provided by the present invention.

[0014] Figure 2 for Figure 1 A cross-sectional view of a first AMB board and a chip assembly of an embedded multi-chip parallel power module.

[0015] Figure 3 for Figure 1 Current flow diagram of an embedded power module with multiple chips connected in parallel.

[0016] Figure 1: first AMB board 10, first insulating layer 11, first lower copper layer 12, first upper copper layer 13, embedded groove 14, chip assembly 20, chip 21, copper bus 22, second AMB board 30, second insulating layer 31, second lower copper layer 32, second upper copper layer 33, avoidance hole 34, plastic package 40, circuit board 50, electrode 51, heat dissipation substrate 60, refrigerant 61. DETAILED DESCRIPTION

[0017] The following is a further detailed description of specific embodiments of the present invention. It should be understood that the description of the embodiments of the present invention herein is not intended to limit the scope of protection of the present invention.

[0018] like Figures 1 to 3As shown, it is a schematic structural diagram of the embedded and multi-chip parallel power module provided by the present invention. The embedded and multi-chip parallel power module includes a first AMB board 10, a plurality of chip components 20 arranged on the first AMB board 10, a second AMB board 30 arranged on the first AMB board 10, a plastic package 40 arranged on the first AMB board 10 and the second AMB board 30, a circuit board 50 arranged on the second AMB board 30, and two heat dissipation substrates 60 arranged on the first AMB board 10. It is conceivable that the embedded and multi-chip parallel power module also includes other functional modules, such as connection components, and installation components, etc., which are technologies well known to those skilled in the art and will not be repeated here.

[0019] The first AMB board 10 includes a first insulating layer 11, a first lower copper layer 12 disposed on the first insulating layer 11, and a first upper copper layer 13 disposed on the first insulating layer 11. The first insulating layer 11 is located between the first lower copper layer 12 and the first upper copper layer 13. The first upper copper layer 13 is provided with a plurality of buried trenches 14 and channels formed by wet etching. The buried trenches 14 are used to accommodate the chip components 20 and are provided with silver paste on the bottom surface. The channels are used to separate the chip components 20 located in the upper bridge circuit or the lower bridge circuit, thereby forming the required circuit structure. The first lower copper layer 12, located away from the first insulating layer 11, is a complete copper layer and is used to contact the heat dissipation substrate 60, thereby better conducting heat to the heat dissipation substrate 60 for dissipation.

[0020] The chip assembly 20 includes a plurality of chips 21 disposed on the first AMB board 10 and a plurality of copper busbars 22 disposed on the chips 21 .

[0021] The chip 21 is attached to the embedded groove 14, which is filled with silver paste, through a die bonding process. The first AMB board 10 is then transferred to a sintering furnace. The silver paste sintering process involves evaporating the solvent in the silver paste at high temperatures, causing the silver particles within the paste to sinter and solidify, forming a dense sintered layer. This securely fixes the chip 21 within the embedded groove 14, providing an excellent electrical and thermal conduction path. To prevent oxidation during the subsequent heating process, the sintering furnace must first be evacuated to a vacuum level of less than 5 mbar. To facilitate interdiffusion and fusion between adjacent silver particles to form a dense sintered layer, the temperature must be heated to 200-300°C. Furthermore, to accelerate interdiffusion and fusion between the silver paste particles, a certain pressure, typically between 15 and 30 MPa, is applied to the surface of the chip 21. This pressure is maintained for a certain period of time to ensure sufficient interdiffusion and fusion between the silver paste particles, forming a dense sintered layer. Finally, the temperature is cooled to room temperature, securing the chip 21 within the embedded groove 14. The chip 21 is used to amplify and convert electrical signals to drive various load devices. The chip 21 itself should be existing technology, and its structure and working principle will not be described in detail here. As for the setting method of silver paste, a steel mesh that completely matches the position of the embedding groove 14 can be pre-made. Using an automatic printing machine to squeegee, the silver paste is accurately filled into the corresponding embedding groove 14. It is then baked in a nitrogen-filled oven to remove most of the solvent in an oxygen-free environment, so that the silver paste is pre-cured into a stable semi-dry state in preparation for subsequent chip mounting and sintering.

[0022] The lower surface of the copper busbar 22 is electrically connected to the chip 21, and the upper surface of the copper busbar 22 is point-connected to the second upper copper layer 33 of the second AMB board 30, thereby achieving circuit connectivity. Three copper busbars 22 are provided on each chip 21, two of which are used to connect to the electrodes 51 of the circuit board 50 through the circuits of the second upper copper layer 33 for signal transmission and control. The other copper busbar 22 is directly connected to the corresponding circuit of the second upper copper layer 33 to conduct current to the second upper copper layer 33 of the second AMB board 30.

[0023] The second AMB board 30 includes a second insulating layer 31, a second lower copper layer 32 disposed on the second insulating layer 31, and a second upper copper layer 33 disposed on the second insulating layer 31. The second insulating layer 31 is located between the second lower copper layer 32 and the second upper copper layer 33.

[0024] The first insulating layer 11 and the second insulating layer 31 can be made of Si3N4, a material with good thermal conductivity, with a thermal conductivity of up to 80 W / (m·K) and an overall thermal resistance of less than 0.01 K / W. The second lower copper layer 32 is provided on the end surface of the second insulating layer 31 facing the first AMB board 10, while the second upper copper layer 33 is provided on the end surface of the second insulating layer 31 facing away from the first AMB board 10.

[0025] The second lower copper layer 32 is welded to the first upper copper layer 13 to achieve the connection between the first AMB board 10 and the second AMB board 30. By setting a avoidance hole 34 at the position of the second insulating layer 31 and the second lower copper layer 32 corresponding to the chip assembly 20, the chip assembly 20 is located in the avoidance hole 34 and the embedded groove 14, and the second upper copper layer 33 is above the chip assembly 20 and the first lower copper layer 12 is below. Thus, the heat generated by the chip assembly 20 can not only be directly transferred downward through the first lower copper layer 12, but also be transferred upward through the second upper copper layer 33, forming a dual-path heat dissipation to avoid localized heat accumulation. The heat will be transferred to the two heat dissipation substrates 60 for double-sided heat dissipation, thereby having higher heat dissipation efficiency.

[0026] The second lower copper layer 32 is welded to the first upper copper layer 13, so that the second AMB board 30 is stacked on the first AMB board 10, which reduces the current loop and lowers the stray inductance. Specifically, a circuit structure is etched on the second upper copper layer 33, such as Figure 3 As shown, in this embodiment, taking the upper bridge of the half-bridge circuit as an example, when the upper bridge is turned on, current flows from the first upper copper layer 13 and enters the three chips 21. Subsequently, the current is connected to the second upper copper layer 33 through the copper bus 22 and output. In the stacked structure, the input path is from the first upper copper layer 13 to the chip 21, and the output path is from the chip 21 to the second upper copper layer 33. The input path and the output path are directly superimposed in the vertical direction to form a short and compact vertical current path. According to the basic characteristics of inductance, the inductance value is proportional to the area of the current loop, so the reduction of the loop area directly reduces the stray inductance. If the AMB board is an independent layered structure, the current path needs to be connected through external wiring or a longer horizontal copper layer, resulting in a longer horizontal extension distance of the current loop and a larger loop area.

[0027] The plastic package 40 can be formed by coating the sidewalls of the first AMB board 10 and the second AMB board 30 with a sealing material such as epoxy resin and then curing the coating to achieve sealing, enhance insulation, and inhibit environmental corrosion. The lower surface of the first lower copper layer 12 is exposed from the plastic package 40 and is flush with the bottom surface of the plastic package 40. The upper surface of the second upper copper layer 33 is exposed from the plastic package 40 and is flush with the top surface of the plastic package 40, facilitating connection with the heat dissipation substrate 60 and the circuit board 50.

[0028] The lower surface of the circuit board 50 is electrically welded to the upper surface of the second upper copper layer 33 and is correspondingly provided with a plurality of electrodes 51. The electrodes 51 and the copper busbars 22 are connected through the second upper copper layer 33, so that two of the copper busbars 22 of a chip 21 are directly connected to the control circuit on the circuit board 50, avoiding the parasitic capacitance caused by traditional leads and providing a stable signal transmission path.

[0029] The heat dissipation substrate 60 is respectively arranged on the upper surface of the circuit board 50 and the lower surface of the first lower copper layer 12. A plurality of refrigerants 61 are arranged in the heat dissipation substrate 60. The heat dissipation substrate 60 increases the contact area and forces convection heat exchange, and directly cools the double-sided heat source, namely the circuit board 50 and the lower surface of the first lower copper layer 12, so that the heat conduction path is short and the thermal resistance path is low. Combined with the double-flow heat conduction of the embedded chip, the heat on both sides is quickly discharged through the refrigerant 61, thereby improving the heat dissipation efficiency.

[0030] Compared with the prior art, the second AMB board 30 of the embedded and multi-chip parallel power module provided by the present invention is welded to the first AMB board 10 in a stacked manner, and the chip assembly 20 is sandwiched between the two boards. The heat generated by the chip assembly 20 can be simultaneously transferred downward to the heat dissipation substrate 60 below through the first lower copper layer 12, and upward to the heat dissipation substrate 60 above through the second upper copper layer 33, forming a dual-path mode for double-sided heat dissipation, which greatly improves the heat dissipation efficiency. The laminated structure also shortens the vertical path of current input and output, reduces the current loop area, and effectively reduces stray inductance. The connection method of the copper bus 22 avoids the parasitic capacitance problem of traditional leads, and cooperates with the forced convection heat exchange of the refrigerant 61 in the heat dissipation substrate 60, ultimately achieving the comprehensive advantages of high reliability, low inductance and efficient heat dissipation.

[0031] The above are only preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements or improvements within the spirit of the present invention are included in the scope of the claims of the present invention.

Claims

1. An embedded multi-chip parallel power module, characterized by: The embedded multi-chip parallel power module includes a first AMB board, a plurality of chip components arranged on the first AMB board, a second AMB board arranged on the first AMB board, and a circuit board arranged on the second AMB board, the first AMB board includes a first insulating layer, a first lower copper layer arranged on the first insulating layer, and a first upper copper layer arranged on the first insulating layer, the first insulating layer is located between the first lower copper layer and the first upper copper layer, the first upper copper layer is provided with a plurality of embedded grooves, the chip components include a plurality of chips arranged on the first AMB board, and a plurality of copper bars arranged on the chips, the second AMB board includes a second insulating layer, a second lower copper layer arranged on the second insulating layer A copper layer, and a second upper copper layer arranged on the second insulating layer, the second insulating layer is located between the second lower copper layer and the second upper copper layer, the second lower copper layer is arranged on the end surface of the second insulating layer facing the first AMB board, and the second upper copper layer is arranged on the end surface of the second insulating layer facing away from the first AMB board, the second lower copper layer is welded to the first upper copper layer, the second insulating layer and the second lower copper layer are provided with avoidance holes corresponding to the position of the chip component, the chip component is located in the avoidance hole and the embedded groove, the lower surface of the copper bus is electrically connected to the chip, the upper surface of the copper bus is electrically connected to the second upper copper layer of the second AMB board, the lower surface of the circuit board is electrically welded to the upper surface of the second upper copper layer and a plurality of electrodes are correspondingly provided.

2. The embedded multi-chip parallel power module according to claim 1, wherein: Silver paste is arranged in the embedded groove.

3. The embedded multi-chip parallel power module according to claim 1, wherein: The first insulating layer and the second insulating layer are made of Si3N4, have a thermal conductivity of more than 80W / (m·K), and an overall thermal resistance of less than 0.01K / W.

4. The embedded multi-chip parallel power module according to claim 1, wherein: The embedded multi-chip parallel power module further includes a plastic package provided on the first AMB board and the second AMB board, a circuit board provided on the second AMB board, and two heat dissipation substrates provided on the first AMB board.

5. The embedded multi-chip parallel power module according to claim 4, wherein: The plastic package body is formed by coating the first AMB board and the second AMB board with a sealing material and then solidifying the sealing material.

6. The embedded multi-chip parallel power module according to claim 4, wherein: The lower surface of the first lower copper layer is exposed from the plastic package body and is flush with the bottom surface of the plastic package body. The upper surface of the second upper copper layer is exposed from the plastic package body and is flush with the top surface of the plastic package body.

7. The embedded multi-chip parallel power module according to claim 4, wherein: The lower surface of the circuit board is welded to the upper surface of the second upper copper layer and is correspondingly provided with a plurality of electrodes. The electrodes and the copper busbars are connected through the second upper copper layer, so that two of the copper busbars of a chip are led out and connected to the control circuit on the circuit board.

8. The embedded multi-chip parallel power module according to claim 4, wherein: The heat dissipation substrates are respectively arranged on the upper surface of the circuit board and the lower surface of the first lower copper layer, and a plurality of refrigerants are arranged in the heat dissipation substrates.

Images