Resistive random access memory on buried bit lines

Abstract

A semiconductor structure is provided that includes a resistive random access memory on a surface of a bit line (28) embedded in a shallow trench isolation structure (12). The structure may also include a source line (SL) over the bit line (28) or embedded in the shallow trench isolation structure (12).

Description

Background Art

[0001] The present application relates to semiconductor technology, and more particularly, to a semiconductor structure including a resistive random access memory (ReRAM) on a buried bit line.

[0002] Non-volatile memory (NVM), or non-volatile storage devices, is a type of computer memory that retains stored information even after power is removed. In contrast, volatile memory requires a continuous power supply to retain data. NVMs such as ReRAM (sometimes abbreviated to RRAM), phase-change random access memory (PCRAM), and conductive bridge random access memory (CBRAM) have attracted renewed attention for their potential applications in neuromorphic computing with in-memory computing capabilities. They significantly reduce power consumption and eliminate the data transfer time between memory and the central processing unit (CPU) in traditional complementary metal oxide semiconductor (CMOS)-based neuromorphic computing. ReRAM is considered a promising technology for electronic synaptic devices, or memristors, for neuromorphic computing, as well as for high-density, high-speed NVM applications. In neuromorphic computing applications, resistive memory devices such as ReRAM devices can be used as the connection (i.e., synapse) between preceding and succeeding neurons, with the connection weight represented by the device's resistance. Summary of the Invention

[0003] A semiconductor structure is provided, which includes a resistive random access memory (ReRAM) located on a surface of a bit line embedded in a shallow trench isolation structure. The structure may also include a source line located above the bit line or embedded in the shallow trench isolation structure.

[0004] In one aspect of the present application, a semiconductor structure is provided. In one embodiment, the semiconductor structure includes a buried bit line embedded in a shallow trench isolation structure, and a resistive random access memory (ReRAM) located on a surface of the buried bit line, wherein the ReRAM is electrically connected to a source / drain region of at least one first transistor.

[0005] In this application, the ReRAM and buried bit lines are located at the same device level (i.e., the front-end-of-line (FEOL) level) as the transistors. Compared to conventional structures where the ReRAM is located at the back-end-of-line (BEOL) level, this semiconductor structure, incorporating buried bit lines and ReRAM at the same device level, significantly reduces resistance (approximately 5x to 20x). Another advantage of this structure is that it can improve the read and write operations of the bit lines. Yet another advantage of this structure is that it eliminates the need for a large number of metal stack write levels for the bit line connections. A further advantage is that a lower IR (current-resistance) voltage drop can be achieved, enabling the array in each block to contain a large number of unit cells. In such an embodiment, larger memory sizes can be achieved.

[0006] In an embodiment of the present application, the ReRAM and the buried bit lines are also embedded in an interlayer dielectric material structure located on the shallow trench isolation structure.

[0007] In an embodiment of the present application, at least one first transistor is a fin field-effect transistor (finFET). In the present application, a finFET includes a semiconductor fin serving as a device channel structure and a gate structure located above the semiconductor fin, wherein the lower portion of the semiconductor fin is located within a shallow trench isolation structure. The present application is not limited to the use of finFETs; therefore, other types of transistors, such as planar transistors, nanosheet transistors, or semiconductor nanowire transistors, may also be used.

[0008] In an embodiment of the present application, the structure may further include a source line located above the at least one first transistor, wherein the source line is electrically connected to the source / drain region of the at least one second transistor. In such an embodiment, the resistive random access memory (ReRAM) is electrically connected to the source / drain region of the at least one first transistor via a first source / drain contact structure, and the source line is electrically connected to the source / drain region of the at least one second transistor via a metal via structure and a second source / drain contact structure. In such an embodiment, the buried bit line is connected to the sense amplifier, and the source line is connected to a common ground reference.

[0009] In an embodiment of the present application, the structure may further include a buried source line embedded in the shallow trench isolation structure, wherein the buried source line is electrically connected to the source / drain region of the at least one second transistor. In such an embodiment, the resistive random access memory (ReRAM) is electrically connected to the source / drain region of the at least one first transistor via a first source / drain contact structure, and the buried source line is electrically connected to the source / drain region of the at least one second transistor via a metal via structure and a second source / drain contact structure. In such an embodiment, the buried bit line is connected to a sense amplifier, and the buried source line is connected to a common ground reference.

[0010] In any of the above embodiments, the at least one second transistor may be a fin field effect transistor (finFET), a planar transistor, a nanosheet transistor, a semiconductor nanowire transistor, or the like.

[0011] In an embodiment of the present application, a buried bit line extends below an uppermost surface of the semiconductor substrate.

[0012] In an embodiment of the present application, the aspect ratio of the buried bit line is 1:1 to 6:1. Such an aspect ratio can provide a low resistance bit line.

[0013] In an embodiment of the present application, the at least one first transistor includes a plurality of first transistors, and a resistive random access memory (ReRAM) is electrically connected to a source / drain region of each of the plurality of first transistors.

[0014] In an embodiment of the present application, the buried bit line is located in a region adjacent to a first device region including the at least one first transistor, and is located between the first device region and a second device region.

[0015] In an embodiment of the present application, the buried bit line is a buried metal track, the length of which is greater than the length of the resistive random access memory (ReRAM).

[0016] In another aspect of the present application, a memory array is provided. In one embodiment, the memory array includes: a plurality of buried bit lines embedded in a shallow trench isolation structure; a resistive random access memory (ReRAM) located on a surface of each of the plurality of buried bit lines, wherein the resistive random access memory (ReRAM) is electrically connected to a source / drain region of each of a plurality of first transistors; and a plurality of source lines electrically connected to a source / drain region of each of a plurality of second transistors, wherein the plurality of first transistors are adjacent to the plurality of second transistors.

[0017] In an embodiment of the present application, each of the plurality of source lines is located above the plurality of first transistors and the plurality of second transistors. In such an embodiment, each of the plurality of buried bit lines is connected to a sense amplifier, and each of the plurality of source lines is connected to a common ground reference.

[0018] In an embodiment of the present application, each of the plurality of source lines is a buried source line embedded in a shallow trench isolation structure. In such an embodiment, each of the plurality of buried bit lines is connected to a sense amplifier, and each of the plurality of source lines is connected to a common ground reference. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. 4 is a top view showing a device layout used in this application to describe the semiconductor structure of the present application.

[0020] Figure 2A 、 Figure 2B and Figure 2C are exemplary structures that can be used in this application. Figure 1A cross-sectional view taken along sections XX, Y1-Y1, and Y2-Y2 of the semiconductor substrate, the exemplary structure including a plurality of semiconductor fins extending upward from a surface of the semiconductor substrate, a shallow trench isolation structure positioned laterally adjacent to each semiconductor fin, a gate structure on a first portion of each semiconductor fin, a source / drain region on an opposite side of the gate structure and on a second portion of each semiconductor fin, and a first interlayer dielectric material layer embedding at least each source / drain region.

[0021] Figure 3A 、 3B and 3C are respectively after forming a buried bit line in at least a shallow trench isolation structure. Figure 2A 、 2B and cross-sectional views of exemplary structures shown in 2C.

[0022] Figure 4A 、 Figure 4B and Figure 4C After forming the ReRAM stack on each buried bit line, respectively Figure 3A 、 Figure 3B and Figure 3C A cross-sectional view of an exemplary structure is shown.

[0023] Figure 5A 、 Figure 5B and Figure 5C After patterning the ReRAM stack to provide ReRAM Figure 4A 、 Figure 4B and Figure 4C A cross-sectional view of an exemplary structure is shown.

[0024] Figure 6A 、 Figure 6B and Figure 6C After forming the ReRAM spacer to protect the sidewall of ReRAM Figure 5A 、 Figure 5B and Figure 5C A cross-sectional view of an exemplary structure is shown.

[0025] Figure 7A 、 Figure 7B and Figure 7C After forming the middle-of-line (MOL) contact structure and metal through-hole structure Figure 6A 、 Figure 6B and Figure 6C A cross-sectional view of an exemplary structure is shown.

[0026] Figure 8 is a cross-sectional view illustrating a ReRAM structure according to an embodiment of the present application.

[0027] Figure 9is a top view of a memory array according to an embodiment of the present application, the memory array including Figure 8 Multiple ReRAM structures shown.

[0028] Figure 10 is a top view of a plurality of resistive memory arrays according to an embodiment of the present application, wherein the plurality of resistive memory arrays include Figure 8 Multiple ReRAM structures shown.

[0029] Figure 11 yes Figure 10 Circuit diagram of multiple resistive memory arrays shown.

[0030] Figure 12 is a cross-sectional view illustrating a ReRAM structure according to an embodiment of the present application.

[0031] Figure 13 is a top view of a memory array according to an embodiment of the present application, the memory array including Figure 12 Multiple ReRAM structures shown.

[0032] Figure 14 is a top view of a plurality of resistive memory arrays according to an embodiment of the present application, wherein the plurality of resistive memory arrays include Figure 12 Multiple ReRAM structures shown.

[0033] Figure 15 yes Figure 14 Circuit diagram of multiple resistive memory arrays shown. DETAILED DESCRIPTION

[0034] The present application will now be described in more detail with reference to the following discussion and the accompanying drawings. It should be noted that the drawings are provided for illustration purposes only and, therefore, are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0035] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present application. However, one of ordinary skill in the art will appreciate that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0036] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under or beneath the other element or there may be intervening elements present. In contrast, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements present.

[0037] As described above, the present application provides a semiconductor structure comprising a buried bitline embedded in a shallow trench isolation structure, and a ReRAM located on a surface of the buried bitline, wherein the ReRAM is electrically connected to the source / drain regions of at least one first transistor. In the present application, both the buried bitline and the ReRAM are located at the same device level (i.e., the FEOL level) as the transistors. Compared to conventional structures in which the ReRAM is located in the BEOL, the semiconductor structure of the present invention exhibits a significant reduction in resistance (approximately 5 to 20 times). Another advantage of this structure is that it can achieve improved bitline read and write operations. Yet another advantage of this structure is that it eliminates the need to form a large number of metal stack write levels for bitline connections. A further advantage is that reduced IR drop can be achieved, enabling a larger number of unit cells per block in the array. In such an embodiment, larger memory sizes can be achieved. These and other aspects / advantages of the present application will now be described in more detail.

[0038] First reference Figure 1 , Figure 1 1 is a top view showing a device layout used in this application to describe the semiconductor structure of the present application. The device layout includes a plurality of semiconductor fins. Each semiconductor fin is Figure 1 The semiconductor fins are oriented parallel to each other. Figure 1 In the figure, the two semiconductor fins located in the upper portion are present in a first device region, while the two semiconductor fins located in the lower portion are present in a second device region. These different device regions are separated by a region containing ReRAM. In this application, this region between the two device regions will also include a buried bit line (not shown) located below the ReRAM. Figure 1 The section lines XX, Y1-Y1 and Y2-Y2 are also included. The section line XX is along the length direction and passes through one of the semiconductor fins, and the section line Y1-Y1 is along the length direction and passes through Figure 1 The middle gate structure GS is shown in FIG, and the cutting line Y2 - Y2 is in the region between a pair of adjacent gate structures; in the two device regions, this region will include the source / drain regions. Figure 1 Also included is a dotted circle that highlights the Figures 2A-6C The device layout area is shown in FIG.

[0039] It should be noted that Figure 2A 、 Figure 3A 、 Figure 4A 、 Figure 5A and Figure 6A Each of which represents an exemplary structure through the section line XX, Figure 2B 、 Figure 3B 、 Figure 4B 、 Figure 5B and Figure 6B Each of represents an exemplary structure through the section line Y1-Y1, and Figure 2C 、 Figure 3C 、 Figure 4C 、 Figure 5C and Figure 6C Each of them represents an exemplary structure through the section line Y2-Y2.

[0040] Now refer to Figure 2A 、 Figure 2B and Figure 2C , an exemplary structure that may be employed in the present application is illustrated through various cross-sectional views (i.e., XX-, Y1-Y1, and Y2-Y2, respectively). The exemplary structure includes a plurality of semiconductor fins 10F extending upward from a surface of a semiconductor substrate 10, a shallow trench isolation structure 12 located laterally adjacent to each semiconductor fin 10F, a gate structure 16 located on a first portion of each semiconductor fin 10F, source / drain regions 22 located on opposite sides of the gate structure 16 and on a second portion of each semiconductor fin 10F, and a first interlayer dielectric material layer 24 embedded in at least each source / drain region 22. Each gate structure 16 includes a gate dielectric material layer and a gate electrode. The gate dielectric material layer and the gate electrode are disposed on the gate structure 16. Figures 2A-2B 10F, but both are included in the gate structure 16. The exemplary structure also includes a gate spacer 18, a gate cap 20, and a dielectric material layer 15. The dielectric material layer 15 is composed of a dielectric material, such as SiO2, SiN, or SiON. The dielectric material layer 15 protects the semiconductor fin 10F and may therefore be referred to herein as a dielectric protection layer.

[0041] Figure 2A 、 Figure 2B and Figure 2C The semiconductor substrate 10 shown is composed of at least one semiconductor material having semiconducting properties. Examples of semiconductor materials that can be used as the semiconductor substrate 10 include, but are not limited to, silicon (Si), silicon-germanium (SiGe) alloys, silicon-germanium carbide (SiGeC) alloys, germanium (Ge), Group III / V compound semiconductors, or Group II / VI compound semiconductors.

[0042] Each semiconductor fin 10F is also composed of a semiconductor material, including those mentioned above for semiconductor substrate 10. The semiconductor material providing each semiconductor fin 10F can be compositionally the same as or different from the semiconductor material providing at least the upper portion of semiconductor substrate 10. In embodiments where the semiconductor material providing each semiconductor fin 10F is compositionally the same as the semiconductor material providing at least the upper portion of semiconductor substrate 10, no material interface exists between the semiconductor fin 10F and semiconductor substrate 10. In embodiments where the semiconductor material providing each semiconductor fin 10F is compositionally different from the semiconductor material providing at least the upper portion of semiconductor substrate 10, a material interface exists between the semiconductor fin 10F and semiconductor substrate 10. In the figures of this application, dashed lines are shown between the semiconductor fin 10F and semiconductor substrate 10 to illustrate possible material interfaces that may exist between these two elements. Each semiconductor fin 10F can have a width ranging from 5 nm to 25 nm, a height ranging from 10 nm to 50 nm, and a length ranging from 10 nm to 100 nm. The semiconductor fin 10F may be formed using a patterning process such as, for example, sidewall image transfer (SIT), photolithography, and etching, or a self-assembly process in which a self-assembling block copolymer is employed.

[0043] The shallow trench isolation structure 12 may include a trench dielectric material. The trench dielectric material may be composed of any trench dielectric, such as silicon oxide. The shallow trench isolation structure 12 has a height less than the height of each semiconductor fin 10F. The shallow trench isolation structure 12 may be formed by deposition (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD)) and etching. In some embodiments, the shallow trench isolation structure 12 may extend below the topmost surface of the semiconductor substrate 10.

[0044] As described above, gate structure 16 includes a gate dielectric material layer and a gate electrode, both of which are not shown separately in the figures but are intended to be located within the region defined by gate structure 16. Gate structure 16 is a component of a transistor; the transistor further includes source / drain regions 22 located on each side of gate structure 16. As known to those skilled in the art, the gate dielectric material layer directly contacts the physically exposed surface(s) of each semiconductor fin 10F, and the gate electrode is formed on the gate dielectric material layer. The gate dielectric material layer of gate structure 16 is composed of a gate dielectric material having a dielectric constant of 4.0 or greater. Unless otherwise specified, all dielectric constants mentioned herein are measured in a vacuum. Illustrative examples of gate dielectric materials include, but are not limited to, silicon dioxide, hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO4), zirconium silicon oxynitride (ZrSiO x N y ), tantalum oxide (TaO x ), titanium oxide (TiO), barium strontium titanium oxide (BaO6SrTi2), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), yttrium oxide (Yb2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (Pb(Sc,Ta)O3), and / or lead zinc niobate (Pb(Zn,Nb)O). The gate dielectric material may further include dopants such as La, Al, and / or Mg.

[0045] The gate electrode of gate structure 16 may include a conductive metal and an optional work function metal (WFM). The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to achieve an n-type threshold voltage shift. As used herein, "n-type threshold voltage shift" refers to a shift in the effective work function of the material containing the work function metal toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal is 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal is in the range of 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest achievable gate voltage that will turn on a semiconductor device (e.g., a transistor) by causing the device's channel to conduct. As used herein, the term "p-type threshold voltage shift" refers to a shift in the effective work function of the WFM-containing material toward the valence band of silicon in the silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. The conductive metal providing the gate electrode may include, but is not limited to, Al, W, or Co. Gate structure 16 may be formed using a gate-first process or a gate-last process (in a gate-last process, a sacrificial gate structure is formed first, and then, after further device processing, the sacrificial gate structure may be replaced with gate structure 16).

[0046] In the present application, the transistor is a fin field effect transistor (finFET), which includes a semiconductor fin 10F as a device channel structure, and a gate structure 16 is located on the upper portion of the semiconductor fin 10F, wherein the lower portion of the semiconductor fin 10F exists in a shallow trench isolation structure 12, as shown in FIG. Figure 2B Although this application describes finFETs being used, other types of transistors may be used, including, for example, planar transistors, nanosheet transistors, or semiconductor nanowire transistors.

[0047] The gate spacer 18 is made of any gate dielectric material, such as SiO x , SiN, SiBCN, SiOCN, SiON, or SiOC. Gate spacers 18 may be formed by deposition and etching. Each gate cap 20 may be composed of a dielectric hard mask material (e.g., SiN and / or SiON). Each gate cap 20 may be formed by deposition followed by chemical mechanical polishing (CMP).

[0048] The source / drain regions 22 include a semiconductor material and a dopant. As used herein, a "source / drain or S / D" region can be either a source region or a drain region, depending on subsequent wiring and applied voltage during transistor operation. The dopant can be an n-type dopant or a p-type dopant, both of which are defined below. The semiconductor material providing the source / drain regions 22 includes one of the semiconductor materials mentioned above when providing the semiconductor substrate 10. The semiconductor material providing the source / drain regions 22 can be compositionally the same as or different from the semiconductor material providing each semiconductor fin 10F. The term "n-type" refers to the addition of an impurity that contributes free electrons to the intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants (i.e., impurities) include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of an impurity to the intrinsic semiconductor that creates a valence electron deficiency. In silicon-containing semiconductor materials, examples of p-type dopants (i.e., impurities) include, but are not limited to, boron, aluminum, gallium, and indium. The concentration of n-type or p-type dopants in the source / drain regions 22 may be 1×10 18 atoms / cm 3 to 1×1021 atoms / cm 3 range, but also envisioned to be greater than 1×1021 atoms / cm 3 or less than 1×1018 atoms / cm 3 Note that the source / drain regions 22 are typically formed using an epitaxial growth process so that the source / drain regions 22 have the same crystal orientation as the growth surface of the semiconductor fin 10F on which they are formed.

[0049] First interlayer dielectric material layer 24 may be composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used herein refers to a dielectric material having a dielectric constant of less than 4.0. First interlayer dielectric material layer 24 may be formed by a deposition process such as CVD, PECVD, or spin-on coating.

[0050] Figure 2A 、 Figure 2B and Figure 2C The exemplary structure shown in FIG can be formed using any finFET processing technology known in the art. In order not to obscure the method of the present application, the details of the finFET processing are not described in more detail herein.

[0051] Now refer to Figure 3A 、 3B and 3C, respectively, showing the formation of buried bit lines 28 (two of which are in the shallow trench isolation structure 12) in at least Figure 3Cis shown by an example in Figure 2A 、 2B and the exemplary structure shown in 2C. The buried bit line 28 is formed on the upper side of the combined Figure 1 In some embodiments ( Figure 3C (not shown), the buried bit line 28 may be completely embedded in the shallow trench isolation structure 12, such that the topmost surface of the buried bit line 28 is coplanar with or below the topmost surface of the shallow trench isolation structure 12. In some embodiments (and as Figure 3C As shown in FIG. 1 ), the buried bit line 28 is embedded in both the shallow trench isolation structure 12 and the first interlayer dielectric material layer 24. In such an embodiment, the buried bit line 28 has a topmost surface located between the topmost surface and the bottommost surface of the first interlayer dielectric material layer 24. In some embodiments ( Figure 3A 、 3B 3C), the buried bit line 28 may extend below the topmost surface of the semiconductor substrate 10. This aspect of the present application is, for example, Figure 8 and Figure 12 Shown in.

[0052] Buried bit line 28 (which serves as a power rail in this application) is composed of any conductive metal-containing material, including but not limited to W, Co, Ru, Al, Cu, Pr, Rh, or Pb. A thin metal adhesion layer (e.g., TiN or TaN) may be present along the bottom and sidewalls of the conductive metal-containing material providing buried bit line 28. Buried bit line 28 can be formed by forming an opening 26 in the first interlayer dielectric material layer 24 and a portion of the shallow trench isolation structure 12. Opening 26 can be formed by photolithography and etching. At least one of the above-mentioned conductive metal-containing materials is then deposited into the opening, and recess etching may be performed after the deposition of the conductive metal-containing material. Deposition of the conductive metal-containing material may include CVD, PECVD, atomic layer deposition (ALD), sputtering, or electroplating.

[0053] In some embodiments of the present application, buried bit line 28 has an aspect ratio of 1:1 to 6:1. The term "aspect ratio" is used throughout this application to refer to the ratio of the height of buried bit line 28 to the width of buried bit line 28. The aspect ratios reported here are high aspect ratios that are advantageous for providing low resistance bit lines.

[0054] Now see Figure 4A 、 Figure 4B and Figure 4C , showing the respective Figure 3A 、 Figure 3B and Figure 3CThe exemplary structure shown in FIG. The ReRAM stack includes a first electrode 30, a filament-forming layer 32 (which may also be referred to herein as a dielectric conversion layer), and a second electrode 34. The first electrode 30 can be composed of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Cu, Co, CoWP, CoN, W, WN, or any combination thereof. The first electrode 30 can have a thickness of 2 nm to 80 nm; other thicknesses are possible and may be used as the thickness of the first electrode 30 in this application. The filament-forming layer 32 is composed of a dielectric material, such as a dielectric metal oxide having a dielectric constant of 4.0 or greater. The filament-forming layer 32 is electrically insulating at this point in the application, and during operational use, conductive filaments may form in the filament-forming layer 32. Examples of dielectric metal oxides that may be used as the filament-forming layer 32 include, but are not limited to, hafnium oxide, tantalum oxide, titanium oxide, aluminum oxide, silicon dioxide, or combinations thereof. In some embodiments, hydrogen may be present in the dielectric material providing the filament-forming layer 32. The filament-forming layer 32 may have a thickness of 1 nm to 50 nm; however, it is contemplated that other thicknesses may be used as the thickness of the filament-forming layer 32. The second electrode 34 may include one of the conductive materials mentioned above for the first electrode 30. The second electrode 34 may include a double-layer electrode stack, such as Figure 8 and Figure 12 , and a lower second electrode 34A and an upper second electrode 34B are shown. In some embodiments, the conductive material providing the second electrode 34 is compositionally the same as the conductive material providing the first electrode 30. In one example, the conductive material providing both the first electrode 30 and the second electrode 34 is composed of TiN. In other embodiments, the conductive material providing the second electrode 34 is compositionally different from the conductive material providing the first electrode 30. In one example, the conductive material providing the first electrode 30 is composed of TaN, and the conductive material providing the second electrode 34 is composed of TiN. A hard mask cap 36 is present on the second electrode 34. The hard mask cap 36 is composed of a hard mask material, such as SiN or SiON.

[0055] The ReRAM stack and hard mask cap 36 are formed by deposition (e.g., CVD, PECVD, or ALD) followed by a planarization process such as CMP. The planarization process removes any of the ReRAM stack and hard mask cap 36 formed outside the opening 26. At this point in the application, the first electrode 30, filament-forming layer 32, and second electrode 34 of the ReRAM stack are U-shaped and each have a topmost surface that is coplanar with each other. These coplanar topmost surfaces of the ReRAM stack are coplanar with the topmost surface of the hard mask cap 36.

[0056] Now refer to Figure 5A 、 Figure 5B and Figure 5C , respectively, after patterning the ReRAM stack to provide ReRAM Figure 4A 、 Figure 4B and Figure 4C The exemplary structure shown in FIG. The ReRAM includes the remaining (i.e., unetched) portion of the ReRAM stack, including the first electrode 30, the filament-forming layer 32, and the remaining (unetched) portion of the second electrode 34. These remaining (unetched) portions of the first electrode 30, the filament-forming layer 32, and the second electrode 34 are stacked one on top of the other to provide a pillar-shaped ReRAM, such as Figure 5C As shown. There may be some taper in the pillar ReRAM formed during this patterning step. The remaining (unetched) portion of the hard mask cap 36 is present at the top of the pillar ReRAM, as shown. Figure 5C As shown. The patterning of the ReRAM stack and hard mask cap 36 includes photolithography and etching. Note that the pillar ReRAM formed only exists on a portion of the underlying buried bit line 28; the remaining portion of the buried bit line 28 will extend into and out of the layer including Figure 5A 、 5B In an embodiment of the present application, the buried bit line 28 is a buried metal track whose length is greater than that of the pillar ReRAM.

[0057] Now refer to Figure 6A 、 Figure 6B and Figure 6C , respectively showing the ReRAM spacer 38 after forming the sidewall of the ReRAM Figure 5A 、 Figure 5B and Figure 5C The exemplary structure shown in . Figure 6C As shown, the ReRAM spacer 38 laterally surrounds the ReRAM and exists on the physically exposed portion of the buried bit line 28 and covers the entire sidewall of the ReRAM. Thus, the ReRAM spacer 38 has a topmost surface that is substantially parallel to the topmost surface of the ReRAM. Figure 6C The remaining (ie, unetched) portions of the top electrodes 34 of the pillar-shaped ReRAM are shown to be coplanar. The ReRAM spacer 38 is composed of any dielectric spacer material including, for example, silicon dioxide or silicon nitride, and can be formed by depositing the dielectric spacer material followed by a recess etch.

[0058] Now refer to Figure 7A 、 7B 7C and 7C respectively show the MOL contact structure and the metal through hole structure after formation. Figure 6A 、 6Band 6C. The MOL contact structure includes a source / drain contact structure 40 and a gate contact structure 42. The source / drain contact structure 40 is formed on the physically exposed surface of the source / drain region 22, as shown in FIG. Figure 7A As shown, the gate contact structure 42 is formed on the physically exposed surface of the gate structure, as shown Figure 7A As shown. Figure 7C As shown, the pillar-shaped ReRAM present on the buried bit line 28 is electrically connected to one of the source / drain regions of the transistor via one of the source / drain contact structures 40. During the formation of the MOL contact, the remaining (i.e., unetched) portion of the hard mask cap 36 is removed to expose the topmost surface of the ReRAM. Notably, the topmost surface of the second electrode 34 of the ReRAM is now physically exposed, and one of the source / drain contact structures 40 is in physical contact with the exposed topmost surface of the ReRAM; this one source / drain contact structure 40 is also in physical contact with the source / drain region, as shown in FIG. Figure 7C shown.

[0059] The metal via structure includes a first metal via structure 44 and a second metal via structure 45. The first metal via structure 44 contacts one of the gate contact structures 42, while the second metal via structure 45 contacts one of the source / drain contact structures 40. The metal via structure is embedded in an upper portion of an interlayer dielectric material structure 25, which includes a first interlayer dielectric material layer 24 and at least one additional interconnect dielectric material layer formed on the first interlayer dielectric material layer 24. The at least one additional interconnect dielectric material layer includes one of the dielectric materials mentioned above for the first interlayer dielectric material layer 24. The at least one additional interlayer dielectric material layer can be formed using a deposition process, such as CVD, PECVD, or spin coating.

[0060] The source / drain contact structures 40 and the gate contact structure 42 are composed of at least a contact conductor material. The contact conductor material may include, for example, a silicide substrate (such as Ni, Pt, NiPt), an adhesive metal substrate (such as TiN), and a conductive metal (such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof). The source / drain contact structures 40 and the gate contact structure 42 may also include one or more contact substrates (not shown). In one or more embodiments, the contact substrate (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In one or more embodiments in which a contact substrate is present, the contact substrate (not shown) may include a silicide substrate (such as Ti, Ni, NiPt, etc.) and a diffusion barrier material, as defined above. The source / drain contact structures 40 and the gate contact structure 42 can be formed by forming gate contact openings that physically expose the gate structure 16 and source / drain contact openings that physically expose the source / drain regions 22. These openings are then filled with at least a contact conductor material, as described above, and a planarization process is then performed to provide the source / drain contact structures 40 and the gate contact structure 42.

[0061] A metal via structure including first metal via structure 44 and second metal via structure 45 is then formed by first forming at least one additional interlayer dielectric material layer on first interlayer dielectric material layer 34 and a metallization process including via opening formation and filling the via opening with a conductive metal or metal alloy. Exemplary conductive metals that can be used to provide the metal via structure include, but are not limited to, Cu, W, Al, or Co, while exemplary conductive metal alloys that can be used to provide the metal via structure include Cu-Al alloys or Cu-W alloys.

[0062] It is worth noting that Figures 7A-7C FIG. 1 shows a semiconductor structure according to an embodiment of the present application. The semiconductor structure includes a buried bit line 28 embedded in a shallow trench isolation structure 12, and a ReRAM 30 / 32 / 34 located on a surface of the buried bit line 28, wherein the ReRAM 30 / 32 / 34 is electrically connected to one of the source / drain regions 22 of at least one first transistor. In the present application, the first transistor, the ReRAM 30 / 32 / 34, and the buried bit line 28 are located at the same device level (i.e., the FEOL level).

[0063] In the formation Figure 7A 、 Figure 7B and Figure 7CFollowing the exemplary semiconductor structure shown, a BEOL structure (not shown) and a carrier wafer (also not shown) can be formed. The BEOL structure includes various metal levels M1, M2, etc. The various metal levels include conductive structures (metal lines and vias) embedded in interconnecting dielectric material layers.

[0064] Now see Figure 8 , shows a ReRAM structure according to an embodiment of the present application. The ReRAM structure includes the above Figures 2A to 7C The various components mentioned. Notably, the ReRAM structure includes a buried bit line 28 embedded in the shallow trench isolation structure 12, and ReRAM 30 / 32 / 34A / 34B is located on the surface of the buried bit line 28, wherein the ReRAM 30 / 32 / 34A / 34B is electrically connected to one of the source / drain regions 22 of the at least one first transistor (here, the ReRAM is electrically connected to the source / drain region of each of the plurality of first transistors). The ReRAM structure also includes a source line SL located above the at least one first transistor, wherein the source line SL is electrically connected to the source / drain region 22 of the at least one second transistor. Here, the SL is at M1 and is therefore located in the back-end (BEOL) layer. The source line is electrically connected to the source / drain region 22 of the at least one second transistor via a metal via structure 46 and a second source / drain contact structure 41. The source line can be formed of a conductive metal or a conductive metal alloy. In one example, the source line is formed of Cu or W.

[0065] Now refer to Figure 9 , shows a top view of a memory array according to an embodiment of the present application, the memory array including Figure 8 Multiple ReRAM structures shown. It is worth noting that Figure 9 A continuous buried bit line 28 is shown, extending horizontally, with the ReRAM device located above it. In the area where the ReRAM device is formed, the memory cell extends to the adjacent SL. The gate structure 16 is oriented vertically relative to the BL / SL. The source / drain contact structure 40 is a mid-process connection. A key feature of this embodiment is that the buried bit line 28 is buried, while the source line is located in the M1 layer.

[0066] Now refer to Figure 10 , shows a top view of a plurality of resistive memory arrays according to an embodiment of the present application, the plurality of resistive memory arrays including Figure 8 Multiple ReRAM structures shown. It is worth noting that Figure 10 The buried bit line 28 containing the memory element and the M1 source line SL are shown, which run in the same direction. Here, the transistor source / drain is connected to the ReRAM device and the gate structure 16. In this embodiment, Figure 9Instead, two source lines are adjacent to each other, with each pair of source lines separated by a buried bit line 28 .

[0067] Now refer to Figure 11 , showing Figure 10 FIG1 is a circuit diagram of a plurality of resistive memory arrays shown in FIG1. In this figure, WL refers to word line, which is the gate electrode of each gate structure, and BL represents bit line, which is the buried bit line 28 in this application. In this figure, each WL is wired to word line decoder and driver 104, and each SL is wired to a common reference source 102. It is worth noting that Figure 11 A memory cell design with the notable feature that the BL and SL extend in the same direction, one of which is buried and the other at M1. Both the BL and SL are perpendicular to the WL, which can be located at a higher metal level than M1.

[0068] Now see Figure 12 , shows a ReRAM structure according to an embodiment of the present application. The ReRAM structure includes the above Figures 2A to 7C The various components mentioned above. Notably, the ReRAM structure includes a buried bit line 28 embedded in the shallow trench isolation structure 12, and ReRAM 30 / 32 / 34A / 34B is located on the surface of the buried bit line 28, wherein the ReRAM 30 / 32 / 34A / 34B is electrically connected to one of the source / drain regions 22 of at least one first transistor (here, the ReRAM is electrically connected to the source / drain region of each of the plurality of first transistors). The ReRAM structure also includes a source line (SL) located at the same level as the first transistor, wherein the SL is electrically connected to the source / drain region 22 of at least one second transistor. Here, the SL is equal to a buried line 29. The buried line 29 includes the materials mentioned above for the buried bit line 28 and is present in at least the shallow trench isolation structure 12. The source line SL is electrically connected to the source / drain region 22 of the at least one second transistor via a metal via (via) and a second source / drain contact structure 41.

[0069] Now refer to Figure 13 , shows a top view of a memory array according to an embodiment of the present application, the memory array including Figure 12 Multiple ReRAM structures shown. Figure 13 The memory array shown in is similar to Figure 9 The memory array shown in FIG, but in this figure both BL and SL are buried under the transistors, whereas in Figure 9 The middle BL is buried and the SL is at M1.

[0070] Now refer to Figure 14, shows a top view of a plurality of resistive memory arrays according to an embodiment of the present application, the plurality of resistive memory arrays including Figure 12 Multiple ReRAM structures shown. The memory array is similar to Figure 10 The memory array described in . Figure 14 The memory array shown in Figure 10 The difference between the memory arrays shown in Figure 14 In the example, the M1 track exists between the buried bit line 28 and the source line 29 connected to the device level, while in Figure 10 In the example, the M1 track is omitted.

[0071] Now refer to Figure 15 , showing Figure 14 A circuit diagram of a plurality of resistive memory arrays is shown. In this diagram, WL refers to word lines, which are the gate electrodes of each gate structure, and BL refers to bit lines, which are buried bit lines 28 in this application. In this diagram, each WL is wired to a word line decoder and driver 104, and each SL is wired to a common reference source 102. This circuit diagram is similar to the above Figure 11 The circuit diagram is shown in Figure 11 The main difference between the circuit diagrams depicted in Figure 15 In the BL and SL, both are buried, and in Figure 11 In the example, BL is buried and SL is at M1.

[0072] Although the present application has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the exact forms and details described and shown, but to fall within the scope of the appended claims.

Claims

1. A semiconductor structure comprising: a buried bit line embedded in a shallow trench isolation structure; as well as A resistive random access memory (ReRAM) is located on a surface of the buried bit line, wherein the ReRAM is electrically connected to a source / drain region of at least one first transistor.

2. The semiconductor structure according to claim 1, wherein The resistance random access memory and the buried bit line are further embedded in an interlayer dielectric material structure located on the shallow trench isolation structure.

3. The semiconductor structure according to claim 1, wherein The at least one first transistor is a fin field effect transistor (finFET), which includes a semiconductor fin as a device channel structure and a gate structure located on an upper portion of the semiconductor fin, wherein a lower portion of the semiconductor fin is located in a shallow trench isolation structure.

4. The semiconductor structure according to claim 1 , further comprising a source line located above the at least one first transistor, wherein The source line is electrically connected to the source / drain region of at least one second transistor.

5. The semiconductor structure according to claim 4, wherein The resistance random access memory is electrically connected to the source / drain region of the at least one first transistor through a first source / drain contact structure, and the source line is electrically connected to the source / drain region of the at least one second transistor through a metal through-hole structure and a second source / drain contact structure. The semiconductor structure according to claim 4 , wherein: The buried bit line is connected to a sense amplifier, and the source line is connected to a common ground reference.

7. The semiconductor structure according to claim 1 , further comprising a buried source line embedded in the shallow trench isolation structure, wherein The buried source line is electrically connected to a source / drain region of at least one second transistor.

8. The semiconductor structure according to claim 7, wherein: The resistance random access memory is electrically connected to the source / drain region of the at least one first transistor through a first source / drain contact structure, and the buried source line is electrically connected to the source / drain region of the at least one second transistor through a metal through-hole structure and a second source / drain contact structure.

9. The semiconductor structure according to claim 8, wherein The at least one second transistor is a fin field effect transistor.

10. The semiconductor structure according to claim 7, wherein: The buried bit line is connected to a sense amplifier, and the buried source line is connected to a common ground reference.

11. The semiconductor structure according to claim 1, wherein The buried bit line extends below an uppermost surface of the semiconductor substrate.

12. The semiconductor structure according to claim 1, wherein The aspect ratio of the buried bit line is 1:1 to 6:

1.

13. The semiconductor structure according to claim 1, wherein The at least one first transistor includes a plurality of first transistors, and the resistance random access memory is electrically connected to a source / drain region of each of the plurality of first transistors.

14. The semiconductor structure according to claim 1, wherein The buried bit line is located in a region adjacent to a first device region including the at least one first transistor and between the first device region and a second device region.

15. The semiconductor structure according to claim 1, wherein The buried bit line is a buried metal rail having a length greater than that of the RRAM.

16. A memory array comprising: a plurality of buried bit lines embedded in a shallow trench isolation structure; a resistive random access memory (ReRAM) located at a surface of each of the plurality of buried bit lines, wherein the ReRAM is electrically connected to a source / drain region of each of the plurality of first transistors; and A plurality of source lines electrically connected to the source / drain region of each of a plurality of second transistors, wherein the plurality of first transistors are adjacent to the plurality of second transistors.

17. The memory array of claim 16, wherein: Each of the plurality of source lines is located above the plurality of first transistors and the plurality of second transistors.

18. The memory array of claim 17, wherein: Each of the plurality of buried bit lines is connected to a sense amplifier, and each of the plurality of source lines is connected to a common ground reference.

19. The memory array of claim 16, wherein: Each source line of the plurality of source lines is a buried source line embedded in a shallow trench isolation structure.

20. The memory array of claim 19, wherein: Each of the plurality of buried bit lines is connected to a sense amplifier, and each of the plurality of source lines is connected to a common ground reference.

Images