Test case generation method, branch predictor verification method and related equipment

Abstract

The invention discloses a test case generation method, a branch predictor verification method and related equipment, and the test case generation method comprises the steps: obtaining a target global branch historical sequence which is generated by a TAGE branch predictor in a target application scene; according to the target global branch historical sequence, a corresponding target linear address sequence is obtained, and the target linear address sequence is obtained by arranging addresses of a plurality of target branch instructions in a target branch instruction stream in sequence; and according to the obtained multiple target linear address sequences, generating a target test case for testing the target branch instruction stream. According to the technical scheme provided by the embodiment of the invention, the verification coverage rate of the TAGE branch predictor can be improved, so that the verification efficiency and accuracy of the TAGE branch predictor are improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of branch prediction technology, and in particular to a test case generation method, a branch predictor verification method, and related equipment. Background Art

[0002] The branch predictor is a key component in the processor. It reduces pipeline stalls by predicting the path of upcoming branch instructions, thereby improving overall processing efficiency. As chip design complexity continues to increase, the accuracy of the branch predictor has an increasingly significant impact on processor performance, making branch predictor verification an indispensable part of chip verification.

[0003] The Tagged Geometric History Length (TAGE) branch predictor is widely used in processor architectures due to its accurate prediction performance. However, TAGE's complex history update mechanism, particularly the maintenance and update of the Global Branch History (GHist) that records the results of previous branch instruction executions, poses significant challenges to verification.

[0004] The global branch history (GHist) records the execution of previous branch instructions. Its complex update mechanism places higher demands on corner case verification. Therefore, how to effectively cover specific application scenarios of the TAGE branch predictor, such as corner cases, during verification, thereby improving the verification coverage and, consequently, the efficiency and accuracy of the TAGE branch predictor, has become a pressing issue. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a test case generation method, a branch predictor verification method and related equipment, which can improve the verification coverage of the TAGE branch predictor, thereby improving the verification efficiency and accuracy of the TAGE branch predictor.

[0006] To solve the above problems, an embodiment of the present invention provides a method for generating a test case, comprising:

[0007] Obtaining a target global branch history sequence, where the target global branch history sequence is generated by a labeled geometric history length branch predictor in a target application scenario;

[0008] According to the target global branch history sequence, a corresponding target linear address sequence is obtained, where the target linear address sequence is obtained by arranging addresses of multiple target branch instructions in the target branch instruction stream in sequence;

[0009] A target test case for testing a target branch instruction flow is generated according to the obtained multiple target linear address sequences.

[0010] Optionally, if values ​​of some bits of the target linear address sequence are known, obtaining the target linear address sequence according to the target global branch history sequence includes:

[0011] According to the target global branch history sequence and the values ​​of the known bits of the target linear address sequence, the values ​​of the unknown bits of the target linear address sequence are obtained by reverse deduction.

[0012] Optionally, obtaining the value of the unknown bit of the target linear address sequence by reverse deduction based on the target global branch history sequence and the value of the known bit of the target linear address sequence includes:

[0013]

[0014] Among them, LA[n][p n ] represents the pth target linear address in the nth target linear address sequence n The value of the unknown bit, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[k][p k ] represents the pth target linear address in the kth target linear address sequence k The value of a known bit.

[0015] Optionally, for each unknown bit in the target linear address sequence, after obtaining the value of the unknown bit of the target linear address sequence by reverse deduction based on the target global branch history sequence and the values ​​of the known bits of the target linear address sequence, obtaining the target linear address sequence based on the target global branch history sequence further includes:

[0016] For each unknown bit in the target linear address sequence, iteratively perform an operation of calculating an error value of a corresponding bit in the target historical branch sequence based on the value of the current iteration of the current unknown bit in the target linear address sequence, and correcting the value of the current iteration of the current unknown bit in the target linear address sequence based on the error value as the value of the next iteration of the current unknown bit in the target linear address sequence, until the error value of the corresponding bit in the target historical branch sequence meets the requirements.

[0017] Optionally, calculating the error value of a corresponding bit in the target historical branch sequence according to the current value of the current unknown bit in the target linear address sequence includes:

[0018]

[0019] Among them, ΔG i represents the error value of the i-th position of the target global branch history sequence, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[j][p j ] represents the pth target linear address in the jth target linear address sequence j The value of a known bit.

[0020] Optionally, the correcting a current value of a current unknown bit of the target linear address sequence according to the error value to use the current value as a value of a next iteration of the current unknown bit in the target linear address sequence includes:

[0021]

[0022] Among them, LA[n][p n ] (t+1) Indicates the pth target linear address in the nth target linear address sequence n The value of the unknown bit at the (t+1)th iteration, ΔG i represents the error value of the i-th position of the target global branch history sequence, Represents exclusive OR operation, LA[n][p n ] t Indicates the pth target linear address in the nth target linear address sequence n The value of the unknown bit at the tth iteration.

[0023] Optionally, the error value of the corresponding bit in the target historical branch sequence meets the requirement, including: the error value of the corresponding bit in the target historical branch sequence is zero.

[0024] Accordingly, an embodiment of the present invention further provides a branch predictor verification device, comprising:

[0025] A first acquisition unit is adapted to acquire a target global branch history sequence, wherein the target global branch history sequence is generated by a labeled geometric history length branch predictor in a target application scenario;

[0026] a second acquiring unit adapted to acquire a corresponding target linear address sequence according to the target global branch history sequence, wherein the target linear address sequence is obtained by sequentially arranging addresses of multiple target branch instructions in the target branch instruction stream;

[0027] The generating unit is adapted to generate a target test case for testing the target branch instruction flow according to the acquired target linear address sequence.

[0028] Accordingly, an embodiment of the present invention further provides a branch predictor verification method, comprising:

[0029] Obtaining a test case, wherein the test case includes a target test case generated by using any of the test case generation methods described above;

[0030] The obtained test case is used to verify the labeled geometric history length branch predictor to obtain the corresponding verification result.

[0031] Accordingly, an embodiment of the present invention further provides a branch predictor verification device, comprising:

[0032] a third acquiring unit, adapted to acquire a test case, wherein the test case includes a target test case generated by using any of the test case generation methods described above;

[0033] The verification unit is adapted to verify the labeled geometric history length branch predictor using the obtained test case and obtain the corresponding verification result.

[0034] Correspondingly, an embodiment of the present invention also provides a computer device, comprising: at least one memory and at least one processor; the memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the test case generation method or branch predictor verification method as described in any one of the above items.

[0035] Accordingly, an embodiment of the present invention further provides a computer program product, comprising a computer program / instruction, which, when executed by a processor, is used to implement the test case generation method or branch predictor verification method as described in any one of the above.

[0036] Correspondingly, an embodiment of the present invention further provides a storage medium storing one or more computer instructions, wherein the one or more computer instructions are used to implement the test case generation method or branch predictor verification method as described in any one of the above items.

[0037] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0038] The test case generation method provided by an embodiment of the present invention includes: obtaining a target global branch history sequence, where the target global branch history sequence is generated by a labeled geometric history length branch predictor in a target application scenario; obtaining a corresponding target linear address sequence based on the target global branch history sequence, where the target linear address sequence is obtained by arranging the addresses of multiple target branch instructions in a target branch instruction stream in sequence; and generating a target test case for testing the target branch instruction stream based on the obtained target linear address sequence.

[0039] In the test case generation method provided by an embodiment of the present invention, the target global branch history sequence is generated by the TAGE branch predictor in a target application scenario. Then, based on the target global branch history sequence, a corresponding target linear address sequence is obtained so that the target linear address sequence matches a specific historical condition. Then, based on the multiple target linear address sequences obtained, a target test case for testing the target branch instruction stream is generated. This method can efficiently reproduce the specific application scenarios of the marked geometric history length branch predictor under extreme conditions, boundary conditions or abnormal inputs such as extreme scenarios, which is beneficial to improving test coverage and further helps to improve the test accuracy of the marked geometric history length branch predictor. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a flow chart of an embodiment of a method for generating a test case provided by the technical solution of the present invention;

[0041] Figure 2 This is a schematic diagram of the framework structure of an embodiment of a test case generation device provided by the technical solution of the present invention;

[0042] Figure 3 It is a schematic diagram of an optional structure of an embodiment of a computer device provided by the technical solution of the present invention. DETAILED DESCRIPTION

[0043] As can be seen from the background art, the verification efficiency and accuracy of existing branch predictor verification methods still need to be improved.

[0044] In order to solve the above technical problems, an embodiment of the present invention provides a test case generation method, including: obtaining a target global branch history sequence, wherein the target global branch history sequence is generated by a marked geometric history length branch predictor in a target application scenario; according to the target global branch history sequence, obtaining a corresponding target linear address sequence, wherein the target linear address sequence is obtained by arranging the addresses of multiple target branch instructions in a target branch instruction stream in sequence; and according to the obtained target linear address sequence, generating a target test case for testing the target branch instruction stream.

[0045] In the test case generation method provided by an embodiment of the present invention, the target global branch history sequence is generated by a marked geometric history length branch predictor in a target application scenario. Then, based on the target global branch history sequence, a corresponding target linear address sequence is obtained so that the target linear address sequence matches a specific historical condition. Then, based on the multiple target linear address sequences obtained, a target test case for testing the target branch instruction stream is generated. This can efficiently reproduce the specific application scenarios of the marked geometric history length branch predictor under extreme conditions, boundary conditions or abnormal inputs such as extreme scenarios, which is beneficial to improving test coverage and thus helps to improve the test accuracy of the marked geometric history length branch predictor.

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0047] Figure 1 The following is a flow chart showing an embodiment of a method for generating a test case according to the technical solution of the present invention. Figure 1 A method for generating a test case may include the following steps:

[0048] Step S110: obtaining a target global branch history sequence, where the target global branch history sequence is generated by a TAGE branch predictor in a target application scenario;

[0049] Step S120: acquiring a corresponding target linear address sequence according to the target global branch history sequence, wherein the target linear address sequence is obtained by sequentially arranging addresses of multiple target branch instructions in the target branch instruction stream;

[0050] Step S130: generating a target test case for testing the target branch instruction flow according to the acquired target linear address sequence.

[0051] Please continue to refer to Figure 1 , execute step S110 to obtain a target global branch history sequence, where the target global branch history sequence is generated by a TAGE branch predictor in a target application scenario.

[0052] Obtain a target global branch history sequence, where the target global branch history sequence is generated by a TAGE branch predictor in a target application scenario, and provides a basis for subsequently obtaining a corresponding target linear address sequence based on the target global branch history sequence.

[0053] In an exemplary embodiment, the step of obtaining a target global branch history sequence includes: when the TAGE branch predictor is running and the target application scenario occurs, recording the corresponding global branch history sequence as the target global branch history sequence.

[0054] As an example, the target global branch history sequence is generated by the TAGE branch predictor under an extreme scenario of an extreme scenario, that is, the target application scenario is an extreme scenario in which the TAGE branch predictor operates. It is understood that the target application scenario of the TAGE branch predictor can also be other application scenarios besides extreme scenarios, and can be specifically set by those skilled in the art based on the verification requirements of the TAGE branch predictor, and is not limited here.

[0055] Please continue to refer to Figure 1 , execute step S120, obtain a corresponding target linear address sequence according to the target global branch history sequence, and the target linear address sequence is obtained by arranging the addresses of multiple target branch instructions in the target branch instruction stream in sequence.

[0056] According to the target global branch history sequence, a corresponding target linear address sequence is obtained. The target linear address sequence is obtained by arranging the addresses of multiple target branch instructions in the target branch instruction stream in sequence, providing a basis for subsequently generating a target test case for testing the target branch instruction stream based on the obtained target linear address sequence.

[0057] The inventors of this application have discovered through research that there is a preset relationship between the global branch history sequence and the linear address sequence of branch instructions. Therefore, if the target global branch history sequence is known, the target linear address sequence can be obtained based on the preset relationship between the target global branch history sequence and the target linear address sequence.

[0058] Specifically, the value of each bit in the target global branch sequence is affected by the values ​​of the corresponding multiple bits in the target linear address sequence. In other words, the value of each bit in the target global branch sequence is jointly determined by the values ​​of the corresponding multiple bits in the target linear address sequence.

[0059] Accordingly, when the global branch history sequence is known and the values ​​of some bits of the target linear address sequence are known, the step of obtaining the target linear address sequence according to the target global branch history sequence includes: obtaining the values ​​of the unknown bits of the target linear address sequence by reverse deduction based on the target global branch history sequence and the values ​​of the known bits of the target linear address sequence.

[0060] The target linear address sequence is obtained by arranging the linear addresses of multiple target branch instructions in the order in which the multiple target branch instructions are executed. Partially known bits of the target linear address sequence are the linear address of the last executed branch instruction when generating the target global branch history sequence. Accordingly, the unknown bits of the target linear address sequence are the linear addresses of branch instructions other than the last executed branch instruction.

[0061] In an exemplary embodiment, when the TAGE branch predictor is running and the target application scenario occurs, while recording the corresponding target global branch history sequence, the linear address of the last executed branch instruction is recorded as a known bit of the target linear address sequence.

[0062] Correspondingly, according to the values ​​of the known bits of the target global branch history sequence and the target linear address sequence, the values ​​of the unknown bits of the target linear address sequence are obtained by reverse deduction, which means: the linear address of the last executed branch instruction is used as the low bit of the target global branch history sequence, and according to the values ​​of the known low bits in the target global branch history sequence and the target linear address sequence, the values ​​of each unknown bit in the target linear address sequence are deduced in order from low to high.

[0063] In an exemplary embodiment, a preset relationship between the value of each bit in the target global branch sequence and the values ​​of the corresponding bits in the target linear address sequence satisfies:

[0064]

[0065] Among them, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[j][p i(j) ] represents the pth target linear address of the jth target linear address in the target linear address sequence n The value of the unknown bit, LA[k][p k ] represents the pth target linear address in the kth target linear address sequence i(j) The value of the units place.

[0066] It can be seen from the above formula (1) that the value of each bit in the target global branch history sequence is calculated by bitwise XORing the values ​​of the corresponding bits in the target linear address sequence. In particular, the longer the bit width (or length) of the target global branch history sequence is, the larger the value G of each bit in the target global branch history sequence is. i, then the values ​​of more bits in the target linear address sequence need to be calculated according to the bitwise XOR method, that is, the larger the value of N is.

[0067] As an example, when the bit width of the target global branch history sequence is 154 and the target linear address sequence includes the target linear addresses LA[0], LA[1], and LA[2] of three branch instructions, the value G0 of the 0th bit in the target global branch history sequence is calculated by the 2nd bit LA[0][2] of the target linear address LA[0], the 3rd bit LA[1][3] of the target linear address LA[1], and the 5th bit LA[2][5] of the target linear address LA[2] in a bitwise XOR manner; the value G1 of the 1st bit in the target global branch history sequence is calculated by the 5th bit LA[0][5] of the target linear address LA[0], the 8th bit LA[1][8] of the target linear address LA[1], and the 9th bit LA[2][9] of the target linear address LA[2] in a bitwise XOR manner, and so on.

[0068] As another example, when the bit width of the target global branch history sequence is 154 and the target linear address sequence includes only the target linear address LA[11:0] of one branch instruction, the update rule of the target global branch history sequence satisfies:

[0069]

[0070] Among them, new ghist[41:0] represents the 0th to 41st bits of the target global branch history sequence updated currently, new ghist[153:42] represents the 42nd to 153rd bits of the target global branch history sequence updated currently, LA[11:1] represents the 1st to 11th bits of the target linear address sequence LA[11:0], old ghist[153:42] represents the 42nd to 153rd bits of the target global branch history sequence updated last, old ghist[41:36] represents the 36th to 41st bits of the target global branch history sequence updated last, "3" represents a left shift of 3 bits, and "1" represents a left shift of 1 bit.

[0071] It should be pointed out that the above two situations are only examples. In practice, the number of bits in the target linear address sequence participating in the bitwise XOR operation may be more or less. The specific setting can be made by those skilled in the art according to actual needs and is not limited here.

[0072] Accordingly, when the target global branch history sequence is known and the values ​​of multiple low-order bits in the target linear address sequence are known, the following formula is used to reversely deduce the values ​​of each unknown bit in the target linear address sequence:

[0073]

[0074] Among them, LA[n][p n ] represents the pth target linear address in the nth target linear address sequence n The value of the unknown bit, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[k][p k ] represents the pth target linear address in the kth target linear address sequence k The value of a known bit.

[0075] In an exemplary embodiment, after the value of each unknown bit in the target linear address sequence is derived using the above formula (4) in order from low to high, the value of each unknown bit in the target linear address sequence derived is corrected using an iterative correction method.

[0076] Specifically, for each unknown bit in the target linear address sequence, after obtaining the value of the unknown bit of the target linear address sequence by reverse deduction based on the target global branch history sequence and the values ​​of the known bits of the target linear address sequence, the step of obtaining the target linear address sequence based on the target global branch history sequence also includes: for each unknown bit in the target linear address sequence, iteratively performing an operation of calculating the error value of the corresponding bit in the target historical branch sequence based on the value of the current iteration of the current unknown bit in the target linear address sequence, and correcting the value of the current iteration of the current unknown bit of the target linear address sequence based on the error value as the value of the next iteration of the current unknown bit in the target linear address sequence, until the error value of the corresponding bit in the target historical branch sequence meets the requirements.

[0077] By adopting the above-mentioned method, the value of each unknown bit in the target linear address sequence obtained by reverse deduction is iteratively corrected, which can gradually approach the final solution of the value of each unknown bit in the target linear address sequence and reduce the error, thereby helping to improve the accuracy of the obtained target linear address sequence, and further enabling the subsequently generated target test cases to cover the extreme scenarios of the operation of the TAGE branch predictor, which is helpful to improve the verification accuracy of the TAGE branch predictor.

[0078] In an exemplary embodiment, according to the current value of the currently unknown bit in the target linear address sequence, the error value of the corresponding bit in the target historical branch sequence is calculated using the following formula:

[0079]

[0080] Among them, ΔGi represents the error value of the i-th position of the target global branch history sequence, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[j][p j ] represents the pth target linear address in the jth target linear address sequence j The value of a known bit.

[0081] In an exemplary embodiment, based on the error value, the current value of the current unknown bit of the target linear address sequence is corrected using the following formula to serve as the value of the next iteration of the current unknown bit in the target linear address sequence:

[0082]

[0083] Among them, LA[n][p n ] (t+1) Indicates the pth target linear address in the nth target linear address sequence n The value of the unknown bit at the (t+1)th iteration, ΔG i represents the error value of the i-th position of the target global branch history sequence, Represents exclusive OR operation, LA[n][p n ] t Indicates the pth target linear address in the nth target linear address sequence n The value of the unknown bit at the tth iteration.

[0084] In an exemplary embodiment, the current value of the current unknown bit of the target linear address sequence is corrected according to the error value until the value ΔG of the i-th bit of the target global branch history sequence is equal to i is zero.

[0085] Please continue to refer to Figure 1 , executing step S130, generating a target test case for testing the target branch instruction flow according to the acquired target linear address sequence.

[0086] Based on the acquired target linear address sequence, a target test case is generated for testing the target branch instruction stream, providing a basis for subsequently using the target test case to verify the TAGE branch predictor and obtain the verification result of the TAGE branch predictor.

[0087] In an exemplary embodiment, the steps of generating a target test case for testing a target branch instruction stream based on multiple target linear address sequences obtained include: obtaining multiple target branch instructions corresponding to multiple target linear address sequences; arranging the multiple target branch instructions in sequence to obtain the target branch instruction stream; and generating a target test case for testing the target branch instruction stream.

[0088] The method for generating the target test case can be selected by those skilled in the art according to actual needs. For example, the target test case for testing the target branch instruction flow can be generated by manually writing or automatically generating, which is not limited here.

[0089] In the test case generation method provided by an embodiment of the present invention, the target global branch history sequence is generated by a TAGE branch predictor in a target application scenario. Based on the target global branch history sequence, a corresponding target linear address sequence is obtained so that the target linear address sequence matches a specific historical condition. Then, based on the multiple target linear address sequences obtained, a target test case for testing the target branch instruction stream is generated, and the TAGE branch predictor is verified. This method can efficiently reproduce specific application scenarios of the TAGE branch predictor under extreme conditions, boundary conditions or abnormal inputs such as extreme scenarios, thereby improving test coverage and thereby facilitating improving the test accuracy of the TAGE branch predictor.

[0090] Correspondingly, an embodiment of the present invention also provides a device for generating a test case.

[0091] Figure 2 The schematic diagram of the structure of the test case generation device provided by the technical solution of the present invention is shown. Figure 2 A test case generation device 20 may include: a first acquisition unit 201, adapted to acquire a target global branch history sequence, where the target global branch history sequence is generated by a TAGE branch predictor in a target application scenario; a second acquisition unit 202, adapted to acquire a corresponding target linear address sequence based on the target global branch history sequence; and a generation unit 203, adapted to generate a target test case for testing the target branch instruction stream based on the acquired target linear address sequence.

[0092] The test case generation device in the embodiment of the present invention can be used to execute the aforementioned test case generation method, or other functional modules can be used to execute the aforementioned test case generation method. For the test case generation method, please refer to the detailed description in the aforementioned section and will not be repeated here.

[0093] Accordingly, an embodiment of the present invention also provides a branch predictor verification method, including: obtaining a test case, the test case including a target test case generated by the test case generation method provided by an embodiment of the present invention; using the obtained test case to verify the marked geometric history length branch predictor, and obtaining the corresponding verification result.

[0094] The branch predictor verification method in the embodiment of the present invention uses the target test case generated by the test case generation method provided by the embodiment of the present invention to verify the TAGE branch predictor. It can efficiently reproduce the specific application scenarios of the TAGE branch predictor under extreme conditions, boundary conditions or abnormal inputs such as extreme scenarios, and can improve the test coverage, thereby helping to improve the test accuracy of the TAGE branch predictor.

[0095] Accordingly, an embodiment of the present invention also provides a branch predictor verification device, comprising: a third acquisition unit, suitable for acquiring test cases, wherein the test cases include target test cases generated using the test case generation method as described in any one of the above items; a verification unit, suitable for using the acquired test cases to verify the marked geometric history length branch predictor and obtain the corresponding verification results.

[0096] The branch predictor verification device in the embodiment of the present invention can be used to execute the aforementioned branch predictor verification method, or other functional modules can be used to execute the aforementioned branch predictor verification method. For details about the branch predictor verification method, please refer to the detailed description in the previous section and will not be repeated here.

[0097] Correspondingly, an embodiment of the present invention also provides a computer device, which can implement the test case generation method or branch predictor verification method provided by an embodiment of the present invention by loading the above-mentioned test case generation method or branch predictor verification method in program form.

[0098] refer to Figure 3 , which shows an optional hardware structure diagram of a computer device provided in an embodiment of the present invention. The computer device in the embodiment of the present invention includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0099] In this embodiment, the number of each of the processor 01 , the communication interface 02 , the memory 03 and the communication bus 04 is at least one, and the processor 01 , the communication interface 02 and the memory 03 communicate with each other via the communication bus 04 .

[0100] The communication interface 02 may be an interface of a communication module for network communication, such as an interface of a GSM module.

[0101] The processor 01 may be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the test case generation method or branch predictor verification method of this embodiment.

[0102] The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory. The memory 03 stores one or more computer instructions, which are executed by the processor 01 to implement the test case generation method or branch predictor verification method provided in the aforementioned embodiments.

[0103] It should be noted that the above-mentioned computer device may also include other devices (not shown) that may not be necessary for understanding the contents disclosed in the embodiments of the present invention; since these other devices may not be necessary for understanding the contents disclosed in the embodiments of the present invention, the embodiments of the present invention will not introduce them one by one.

[0104] Accordingly, an embodiment of the present invention further provides a computer program product, including a computer program / instruction, which, when executed by a processor, is used to implement the test case generation method or branch predictor verification method described in the embodiment of the present invention.

[0105] An embodiment of the present invention further provides a storage medium storing one or more computer instructions, wherein the one or more computer instructions are used to implement the test case generation method or branch predictor verification method provided in the aforementioned embodiment.

[0106] The embodiments of the present invention described above are combinations of elements and features of the present invention. Unless otherwise mentioned, elements or features may be considered as optional. Each element or feature may be put into practice without being combined with other elements or features. In addition, embodiments of the present invention may be constructed by combining some elements and / or features. The order of operations described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment and may be replaced by the corresponding configuration of another embodiment. It is obvious to those skilled in the art that claims that do not have a clear reference relationship to each other in the appended claims may be combined into embodiments of the present invention, or may be included as new claims in amendments after submitting this application.

[0107] The embodiments of the present invention may be implemented by various means such as hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiment of the present invention may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0108] In a firmware or software configuration, the embodiments of the present invention may be implemented in the form of modules, procedures, functions, and the like. Software codes may be stored in a memory unit and executed by a processor. The memory unit may be located inside or outside the processor and may send and receive data to and from the processor via various known means.

[0109] The above description of the disclosed embodiments will enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

[0110] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for generating a test case, characterized in that: include: Obtaining a target global branch history sequence, where the target global branch history sequence is generated by a labeled geometric history length branch predictor in a target application scenario; According to the target global branch history sequence, a corresponding target linear address sequence is obtained, where the target linear address sequence is obtained by arranging addresses of multiple target branch instructions in the target branch instruction stream in sequence; A target test case for testing the target branch instruction flow is generated according to the acquired target linear address sequence.

2. The test case generation method according to claim 1, wherein: If values ​​of some bits of the target linear address sequence are known, obtaining the target linear address sequence according to the target global branch history sequence includes: According to the target global branch history sequence and the values ​​of the known bits of the target linear address sequence, the values ​​of the unknown bits of the target linear address sequence are obtained by reverse deduction.

3. The test case generation method according to claim 2, wherein: The step of obtaining the unknown bit values ​​of the target linear address sequence by reverse deduction based on the target global branch history sequence and the known bit values ​​of the target linear address sequence includes: Among them, LA[n][p n ] represents the pth linear address in the nth linear address sequence of the target linear address n The value of the unknown bit, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[k][p k ] represents the pth linear address in the kth linear address sequence of the target linear address k The value of a known bit.

4. The test case generation method according to claim 2 or 3, wherein: For each unknown bit in the target linear address sequence, after obtaining the value of the unknown bit of the target linear address sequence by reverse deduction based on the target global branch history sequence and the value of the known bit of the target linear address sequence, obtaining the target linear address sequence based on the target global branch history sequence further includes: For each unknown bit in the target linear address sequence, iteratively perform an operation of calculating an error value of a corresponding bit in the target historical branch sequence based on the value of the current iteration of the current unknown bit in the target linear address sequence, and correcting the value of the current iteration of the current unknown bit in the target linear address sequence based on the error value as the value of the next iteration of the current unknown bit in the target linear address sequence, until the error value of the corresponding bit in the target historical branch sequence meets the requirements.

5. The test case generation method according to claim 4, wherein: The step of calculating the error value of the corresponding bit in the target historical branch sequence according to the current value of the current unknown bit in the target linear address sequence includes: Among them, ΔG i represents the error value of the i-th position of the target global branch history sequence, G i Represents the value of the i-th bit of the target global branch history sequence, Represents exclusive OR operation, LA[j][p j ] represents the pth linear address in the jth linear address sequence of the target linear address j The value of a known bit.

6. The test case generation method according to claim 4, wherein: Correcting the current value of the current unknown bit of the target linear address sequence according to the error value as the value of the next iteration of the current unknown bit in the target linear address sequence includes: Among them, LA[n][p n ] (t+1) Indicates the pth target linear address in the nth target linear address sequence n The value of the unknown bit at the (t+1)th iteration, ΔG i represents the error value of the i-th position of the target global branch history sequence, Represents exclusive OR operation, LA[n][p n ] t Indicates the pth target linear address in the nth target linear address sequence n The value of the unknown bit at the tth iteration.

7. The test case generation method according to claim 4, wherein: The error value of the corresponding bit in the target historical branch sequence meets the requirement, including: the error value of the corresponding bit in the target historical branch sequence is zero.

8. A test case generating device, characterized in that: include: A first acquisition unit is adapted to acquire a target global branch history sequence, where the target global branch history sequence is generated by a TAGE branch predictor in a target application scenario; a second acquiring unit adapted to acquire a corresponding target linear address sequence according to the target global branch history sequence, wherein the target linear address sequence is obtained by sequentially arranging addresses of multiple target branch instructions in the target branch instruction stream; The generating unit is adapted to generate a target test case for testing the target branch instruction flow according to the acquired target linear address sequence.

9. A branch predictor verification method, characterized in that: include: Obtaining a test case, wherein the test case includes a target test case generated by the test case generation method according to any one of claims 1 to 7; The obtained test case is used to verify the labeled geometric history length branch predictor to obtain the corresponding verification result.

10. A branch predictor verification device, characterized in that: include: a third acquiring unit, adapted to acquire a test case, wherein the test case includes a target test case generated by the test case generating method according to any one of claims 1 to 7; The verification unit is adapted to verify the labeled geometric history length branch predictor using the obtained test case and obtain the corresponding verification result.

11. A computer device, characterized in that: include: at least one memory and at least one processor; The memory stores one or more computer-executable instructions, and the processor calls the one or more computer-executable instructions to execute the test case generation method according to any one of claims 1 to 7 or the branch predictor verification method according to claim 9.

12. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, it is used to implement the test case generation method according to any one of claims 1 to 7 or the branch predictor verification method according to claim 9.

13. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the test case generation method according to any one of claims 1 to 7 or the branch predictor verification method according to claim 9.

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