Chip thermally induced warping prediction method, device and system and medium

Abstract

The invention provides a method, a device, a system and a medium for predicting thermally-induced warpage of a chip, and the method comprises the steps: according to an effective elastic modulus, an effective Poisson's ratio, an effective thermal expansion coefficient, a material volume fraction, a material elastic modulus, a material Poisson's ratio, a material thermal expansion coefficient and coordinates of all points of a to-be-predicted chip layout, carrying out the prediction of the thermally-induced warpage of the chip; calculating the initial thermally-induced warping displacement of the to-be-predicted chip layout under the current coordinate system; according to the minimum value point and the stationary value point of the initial thermally induced warping displacement, establishing a plurality of planes including the minimum value point and the stationary value point; respectively calculating cosine values of included angles between the plurality of planes and the coordinate axis of the current coordinate system; taking a plane with the minimum cosine value of the included angle as a correction plane; calculating a direction cosine value of the coordinate axis of the correction plane and the coordinate axis of the current coordinate system; and according to the initial thermally-induced warping displacement and the direction cosine value, calculating to obtain predicted thermally-induced warping displacement by using a coordinate axis translation and rotation formula. The thermally-induced warping distribution of the chip is calculated through a classical elastic mechanics theory, and rapid and accurate prediction is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method, device, system and medium for predicting thermally induced warpage of a chip. Background Art

[0002] As chip manufacturing process technology nodes continue to decrease, traditional feature size scaling becomes increasingly difficult and expensive. In order to break through this technical bottleneck, chiplet heterogeneous integration technology came into being.

[0003] The basic principle is to integrate "small chips" obtained through manufacturing processes at different technology nodes onto the same substrate to achieve more functions and performance improvements. However, the new manufacturing process also brings some new process difficulties. For example, during the integration of the "small chips", they need to be integrated into the substrate structure through solder joints, compound bonding, etc. The process involves large-scale heating and cooling processes. Due to the differences in the thermal properties of the materials, serious thermally induced warping and stress problems may occur, which in turn affects the product yield.

[0004] Therefore, how to quickly and accurately predict the thermal warpage during chip manufacturing so as to discover the thermal warpage hotspots that may appear during chip manufacturing during the design stage and facilitate designers to optimize the layout design of heterogeneous integrated chips is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] In view of this, this Summary of the Invention section is provided to briefly introduce the concepts that will be described in detail in the Detailed Description of the Invention section below. This Summary of the Invention section is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0006] The purpose of this application is to provide a chip thermal warpage prediction method, device, system and medium, which can quickly and accurately predict the thermal warpage during the chip manufacturing process, so as to find the thermal warpage hotspots that may appear in the chip manufacturing process during the design stage, and facilitate designers to optimize the layout design of heterogeneous integrated chips.

[0007] To achieve the above objectives, this application has the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a method for predicting thermally induced warpage of a chip, comprising:

[0009] Obtain the chip layout to be predicted;

[0010] Calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted;

[0011] Calculating a preliminary thermally induced warpage displacement of the chip layout to be predicted in a current coordinate system according to the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted;

[0012] According to the minimum point and the stationary point of the preliminary thermally induced warping displacement, a plurality of planes including the minimum point and the stationary point are established; and the cosine values ​​of the angles between the plurality of planes and the coordinate axes of the current coordinate system are calculated respectively;

[0013] Taking the plane with the smallest cosine value of the included angle as the correction plane; calculating the direction cosine values ​​of the coordinate axis of the correction plane and the coordinate axis of the current coordinate system;

[0014] The predicted thermally induced warping displacement is calculated based on the preliminary thermally induced warping displacement and the direction cosine value using a coordinate axis translation and rotation formula.

[0015] In a possible implementation, the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted are calculated based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted, and are specifically calculated by the following formula:

[0016]

[0017]

[0018]

[0019] Among them, E eff is the effective elastic modulus, v eff is the effective Poisson's ratio, α eff is the effective thermal expansion coefficient, n is the number of the various materials, c j is the volume fraction of the jth material, E j is the elastic modulus of the jth material, v j is the Poisson's ratio of the jth material, α j is the thermal expansion coefficient of the jth material.

[0020] In a possible implementation, the predicted thermally induced warping displacement is calculated based on the preliminary thermally induced warping displacement and the direction cosine value using a coordinate axis translation and rotation formula, specifically using the following formula:

[0021]

[0022] Wherein, w(x, y) is the preliminary thermally induced warping displacement, x is the abscissa of the preliminary thermally induced warping displacement, y is the ordinate of the preliminary thermally induced warping displacement, l1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis X of the current coordinate system, m1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Y of the current coordinate system, n1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Z of the current coordinate system, l2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system The direction cosine value of the coordinate axis X, m2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Y of the current coordinate system, n2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system, l3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis X of the current coordinate system, m3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Y of the current coordinate system, n3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Z of the current coordinate system, w 真 (x′, y′) is the predicted thermally induced warping displacement, x′ is the horizontal coordinate of the predicted thermally induced warping displacement, y′ is the vertical coordinate of the predicted thermally induced warping displacement, d1 is the translation distance of the coordinate axis X′ of the correction plane relative to the coordinate axis X of the current coordinate system, d2 is the translation distance of the coordinate axis Y′ of the correction plane relative to the coordinate axis Y of the current coordinate system, and d3 is the translation distance of the coordinate axis Z′ of the correction plane relative to the coordinate axis Z of the current coordinate system.

[0023] In a possible implementation, the preliminary thermally induced warpage displacement of the chip layout to be predicted in the current coordinate system is calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted, and is specifically calculated by the following formula:

[0024]

[0025]

[0026]

[0027] Among them, wai (ξ i ) is the thermally induced warping displacement of the symmetrical structure, B1, B2, B3, B4, B5, r1 and r2 are preset parameters calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio and the material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted, ξ i is the coordinate of each point of the chip layout to be predicted, w i (ξ i ) is the corrected thermally induced warping displacement, ξ iA is the coordinate of one end of the chip in the chip layout to be predicted, w′ i (ξ iA ) is the coordinate ξ iA The derivative of the corrected thermally induced warping displacement at i (ξ iA ) is the coordinate ξ iA The corrected thermally induced warping displacement, ξ iE is the coordinate of one end of the substrate in the chip layout to be predicted, ξ iB is the coordinate of the other end of the chip in the chip layout to be predicted, w′ i (ξ iB ) is the coordinate ξ iB The derivative of the corrected thermally induced warping displacement at i (ξ iB ) is the coordinate ξ iB The corrected thermally induced warping displacement, ξ iF is the coordinate of the other end of the substrate in the chip layout to be predicted, and m is the number of chips in the chip layout to be predicted.

[0028] In a second aspect, an embodiment of the present application provides a device for predicting thermally induced warpage of a chip, comprising:

[0029] An acquisition unit, used for acquiring the chip layout to be predicted;

[0030] A first calculation unit is used to calculate the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted;

[0031] a second calculation unit, configured to calculate a preliminary thermally induced warpage displacement of the chip layout to be predicted in a current coordinate system based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted;

[0032] a third calculation unit, configured to establish, based on the minimum point and the stationary point of the preliminary thermally induced warping displacement, a plurality of planes including the minimum point and the stationary point; and calculate the cosine values ​​of the angles between the plurality of planes and the coordinate axes of the current coordinate system respectively;

[0033] a fourth calculation unit, configured to take the plane with the smallest cosine value of the included angle as a correction plane; and calculate direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system;

[0034] A fifth calculation unit is configured to calculate, based on the preliminary thermally induced warping displacement and the direction cosine value, a predicted thermally induced warping displacement using a coordinate axis translation and rotation formula.

[0035] In a possible implementation, the first calculation unit is specifically configured to calculate the effective elastic modulus, effective Poisson's ratio, and effective thermal expansion coefficient of the chip layout to be predicted using the following formula:

[0036]

[0037]

[0038]

[0039] Among them, E eff is the effective elastic modulus, v eff is the effective Poisson's ratio, α eff is the effective thermal expansion coefficient, n is the number of the various materials, c j is the volume fraction of the jth material, E j is the elastic modulus of the jth material, v j is the Poisson's ratio of the jth material, α j is the thermal expansion coefficient of the jth material.

[0040] In a possible implementation, the fifth calculation unit is specifically configured to calculate the predicted thermally induced warping displacement using the following formula:

[0041]

[0042] Wherein, w(x, y) is the preliminary thermally induced warping displacement, x is the abscissa of the preliminary thermally induced warping displacement, y is the ordinate of the preliminary thermally induced warping displacement, l1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis X of the current coordinate system, m1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Y of the current coordinate system, n1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Z of the current coordinate system, l2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system The direction cosine value of the coordinate axis X, m2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Y of the current coordinate system, n2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system, l3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis X of the current coordinate system, m3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Y of the current coordinate system, n3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Z of the current coordinate system, w 真 (x′, y′) is the predicted thermally induced warping displacement, x′ is the horizontal coordinate of the predicted thermally induced warping displacement, y′ is the vertical coordinate of the predicted thermally induced warping displacement, d1 is the translation distance of the coordinate axis X′ of the correction plane relative to the coordinate axis X of the current coordinate system, d2 is the translation distance of the coordinate axis Y′ of the correction plane relative to the coordinate axis Y of the current coordinate system, and d3 is the translation distance of the coordinate axis Z′ of the correction plane relative to the coordinate axis Z of the current coordinate system.

[0043] In a possible implementation, the second calculation unit is specifically configured to calculate the preliminary thermally induced warping displacement using the following formula:

[0044]

[0045]

[0046]

[0047] Among them, wa i (ξ i ) is the thermally induced warping displacement of the symmetrical structure, B1, B2, B3, B4, B5, r1 and r2 are preset parameters calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio and the material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted, ξ i is the coordinate of each point of the chip layout to be predicted, w i (ξ i ) is the corrected thermally induced warping displacement, ξiA is the coordinate of one end of the chip in the chip layout to be predicted, w′ i (ξ iA ) is the coordinate ξ iA The derivative of the corrected thermally induced warping displacement at i (ξ iA ) is the coordinate ξ iA The corrected thermally induced warping displacement, ξ iE is the coordinate of one end of the substrate in the chip layout to be predicted, ξ iB is the coordinate of the other end of the chip in the chip layout to be predicted, w′ i (ξ iB ) is the coordinate ξ iB The derivative of the corrected thermally induced warping displacement at i (ξ iB ) is the coordinate ξ iB The corrected thermally induced warping displacement, ξ iF is the coordinate of the other end of the substrate in the chip layout to be predicted, and m is the number of chips in the chip layout to be predicted.

[0048] In a third aspect, an embodiment of the present application provides a chip thermal warpage prediction system, comprising:

[0049] memory for storing computer programs;

[0050] A processor is configured to implement the steps of the above-mentioned chip thermal warpage prediction method when executing the computer program.

[0051] In a fourth aspect, an embodiment of the present application provides a computer-readable medium having a computer program stored thereon, and when the computer program is processed and executed, the steps of the chip thermal warpage prediction method as described above are implemented.

[0052] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0053] The present application provides a method, device, system and medium for predicting thermal warpage of a chip, the method comprising: obtaining a chip layout to be predicted; calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted; and calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient, material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient and the various points of the chip layout to be predicted. The coordinates of the chip to be predicted are used to calculate the preliminary thermally induced warpage displacement in the current coordinate system of the chip layout to be predicted; based on the minimum point and stationary point of the preliminary thermally induced warpage displacement, multiple planes including the minimum point and stationary point are established; the cosine values ​​of the angles between the multiple planes and the coordinate axes of the current coordinate system are calculated respectively; the plane with the smallest cosine value of the angle is taken as the correction plane; the direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system are calculated; based on the preliminary thermally induced warpage displacement and the direction cosine values, the predicted thermally induced warpage displacement is calculated using the coordinate axis translation and rotation formulas. This application calculates the thermally induced warpage distribution of heterogeneous integrated chip arrays through the theory of classical elastic mechanics, achieving rapid and accurate prediction of thermally induced warpage during chip manufacturing, so as to discover thermally induced warpage hotspots that may occur during chip manufacturing during the design stage, and facilitate designers to optimize the layout design of heterogeneous integrated chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that the originals and elements are not necessarily drawn to scale.

[0056] Figure 1 A flowchart of a chip thermal warpage prediction method provided by an embodiment of the present application is shown;

[0057] Figure 2 A schematic diagram of a single-chip structure provided by an embodiment of the present application is shown;

[0058] Figure 3 A table diagram showing various preset parameter calculation formulas used in an embodiment of the present application is provided in an embodiment of the present application;

[0059] Figure 4 A schematic diagram of a full-chip stacking method provided in an embodiment of the present application is shown;

[0060] Figure 5 A schematic diagram of a chip thermal warpage prediction device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0061] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0062] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0063] As described in the background technology, the applicant has found through research that with the continuous reduction of chip manufacturing process technology nodes, traditional feature size scaling has become increasingly difficult and expensive. In order to break through this technical bottleneck, chiplet heterogeneous integration technology has emerged.

[0064] The basic principle is to integrate "small chips" obtained through manufacturing processes at different technology nodes onto the same substrate to achieve more functions and performance improvements. However, the new manufacturing process also brings some new process difficulties. For example, during the integration of the "small chips", they need to be integrated into the substrate structure through solder joints, compound bonding, etc. The process involves large-scale heating and cooling processes. Due to the differences in the thermal properties of the materials, serious thermally induced warping and stress problems may occur, which in turn affects the product yield.

[0065] Specifically, in order to integrate the "small chip" onto a substrate (such as a silicon adapter), a bonding process must be used. In this process, the "small chip" must first be soldered to the silicon adapter using flip-chip technology at a high temperature (such as 245°C), and then PI or other materials are filled between the small chip and the silicon adapter as a filling layer at a specific temperature (such as 150°C). After cooling, subsequent processes such as packaging are carried out. However, due to the multiple heating and cooling processes during the process, different material structures have different thermal expansion coefficients. For example, the thermal expansion coefficient of the silicon substrate is generally 2.6×10 -6 / ℃, the thermal expansion coefficient of silicon dioxide is 0.4×10 -6 / ℃, while the thermal expansion coefficient of the filling metal copper is 16.5×10 -6 / ℃, the thermal expansion coefficient of solid PI (polyimide film) is 29×10 -6 / ℃, the difference in thermal properties of materials will lead to thermally induced warping and stress problems. In severe cases, a series of problems such as device performance degradation, silicon adapter board breakage, and solder joint failure may occur, seriously affecting product yield.

[0066] While a large number of theoretical studies have been published in academia on the thermally induced warpage problem during the manufacturing of small-die heterogeneous integrated chips, most of these studies focus on warpage and stress analysis of ideally symmetrical structures and cannot be directly applied to predicting thermal warpage during the manufacturing of small-die heterogeneous integrated chips. In industry, thermal warpage analysis during the manufacturing of small-die heterogeneous integrated chips is primarily performed using commercial finite element analysis tools. However, the primary drawback of finite element calculations is the high computational resource consumption and unpredictable time costs. These drawbacks are exponentially magnified when heterogeneous integrated chips are scaled up.

[0067] Therefore, how to quickly and accurately predict the thermal warpage during chip manufacturing so as to discover the thermal warpage hotspots that may appear during chip manufacturing during the design stage and facilitate designers to optimize the layout design of heterogeneous integrated chips is a technical problem that needs to be solved in this field.

[0068] In order to solve the above technical problems, the embodiments of the present application provide a chip thermal warpage prediction method, device, system and medium, the method comprising: obtaining a chip layout to be predicted; calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted; calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient, material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient and the chip layout to be predicted; calculating ... and the chip layout to be predicted; calculating the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient and the chip layout to be predicted; calculating the effective elastic modulus, effective Poisson's ratio, The coordinates of each point in the graph are used to calculate the preliminary thermally induced warping displacement of the chip layout to be predicted in the current coordinate system; based on the minimum point and stationary point of the preliminary thermally induced warping displacement, multiple planes including the minimum point and stationary point are established; the cosine values ​​of the angles between the multiple planes and the coordinate axes of the current coordinate system are calculated respectively; the plane with the smallest cosine value of the angle is taken as the correction plane; the direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system are calculated; based on the preliminary thermally induced warping displacement and the direction cosine values, the predicted thermally induced warping displacement is calculated using the coordinate axis translation and rotation formula. This application calculates the thermally induced warping distribution of heterogeneous integrated chip arrays through the theory of classical elastic mechanics, and realizes the rapid and accurate prediction of thermally induced warping during chip manufacturing, so as to find thermally induced warping hotspots that may appear in the chip manufacturing process during the design stage, and facilitates designers to optimize the layout design of heterogeneous integrated chips.

[0069] Exemplary Methods

[0070] See also Figure 1FIG. 1 is a flow chart of a chip thermal warpage prediction method provided in an embodiment of the present application, including:

[0071] S101: Obtain the chip layout to be predicted.

[0072] S102: Calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted;

[0073] In the embodiment of the present application, in order to predict the thermally induced warpage of the chip, it is first necessary to read in the layout to obtain the internal structure information of the layout.

[0074] Then, the embodiment of the present application can calculate the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted.

[0075] Specifically, the extraction of characteristic parameters such as effective elastic modulus, effective Poisson's ratio, and effective thermal expansion coefficient is divided into isotropic extraction and transversely isotropic extraction. Generally, materials in the same layer are regarded as isotropic or transversely isotropic. The characteristic parameters of isotropic materials are extracted by the following formula:

[0076]

[0077]

[0078]

[0079] Among them, E eff is the effective elastic modulus, v eff is the effective Poisson's ratio, α eff is the effective thermal expansion coefficient, n is the number of various materials, c j is the volume fraction of the jth material, E j is the elastic modulus of the jth material, v j is the Poisson's ratio of the jth material, α j is the thermal expansion coefficient of the jth material.

[0080] Generally, the materials in the same layer are considered to be composed of binary materials, for example (the filling layer is composed of solder joints and PI), that is, n=2.

[0081] For the extraction of characteristic parameters of transversely isotropic materials, taking binary materials as an example, the following formula is used for calculation:

[0082]

[0083]

[0084]

[0085]

[0086]

[0087] Among them, for the same layer of material, x and y represent the two coordinate directions within the layer, and z represents the coordinate direction pointing outside the layer. is the effective elastic modulus along the xy direction, c1 is the volume fraction of the first material, c2 is the volume fraction of the second material, E1 is the elastic modulus of the first material, E2 is the elastic modulus of the second material, is the effective elastic modulus along the z direction, is the effective Poisson’s ratio along the xz direction, v1 is the Poisson’s ratio of the first material, v2 is the Poisson’s ratio of the second material, is the thermal expansion coefficient along the z direction, α1 is the thermal expansion coefficient of the first material, and α2 is the thermal expansion coefficient of the second material.

[0088] S103: Calculate the preliminary thermally induced warping displacement of the chip layout to be predicted in the current coordinate system based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio and the material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted.

[0089] In an embodiment of the present application, the preliminary thermally induced warping displacement of the chip layout to be predicted in the current coordinate system can be calculated based on the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient, material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted.

[0090] Specifically, in the embodiment of this application i The coordinates of each point of the chip layout to be predicted, see Figure 2 , which is a schematic diagram of a single-chip structure provided in an embodiment of the present application, wherein (a) is a symmetrical structure and (b) is an asymmetrical structure.

[0091] In the embodiment of the present application, a section passing through the center of the chip can be used as the i -z plane, the inside of the plane is ξ i The z-axis direction is the out-of-plane direction. The basic structure is considered to be a three-layer structure, including the substrate (silicon interposer layer), the filling layer, and the "chiplet" layer.

[0092] If the chip has a symmetrical structure, the warpage of the symmetrical structure can be calculated using the following formula:

[0093]

[0094] Among them, wai(ξi) is the thermally induced warping displacement of the symmetric structure, B1, B2, B3, r1 and r2 are preset parameters calculated based on the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient, material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted.

[0095] For details, see Figure 3 As shown in the table, it is a table of various preset parameter calculation formulas used in the embodiment of the present application, wherein B4, B5, B1, B2, B3, A 11 、A 12 、A 21 、A 22 ,γ,M1,M2,D,N1,N2,r1,r2,k1,k2,T1 0 、T2 0 ,λ 20 ,λ ij ,λ k 、E K * 、k k , L, G k , △T, △t, h1, h2, h3 and h k The parameters are all preset parameters, x1, x2, x3 and x4 are the horizontal coordinates of each point of the chip layout to be predicted, E is the abbreviation of the effective elastic modulus, v is the abbreviation of the effective Poisson's ratio, wa'(x2) is the derivative of the corrected thermally induced warpage displacement at the coordinate x2, wa(x2) is the corrected thermally induced warpage displacement at the coordinate x2, C 12 is the volume fraction of the 12th material, C 23 is the volume fraction of the 23rd material.

[0096] In most cases, the “chiplet” and the silicon adapter are arranged asymmetrically (e.g. Figure 2 (b)), so the above formula cannot be used directly to predict warpage, and a correction term needs to be added.

[0097]

[0098] w i (ξ i ) is the corrected thermally induced warping displacement, ξ iA is the coordinate of one end of the chip in the chip layout to be predicted, w′ i (ξ iA ) is the coordinate ξiA The derivative of the corrected thermally induced warping displacement at i (ξ iA ) is the coordinate ξ iA The corrected thermally induced warping displacement, ξ iE is the coordinate of one end of the substrate in the chip layout to be predicted, ξ iB is the coordinate of the other end of the chip in the chip layout to be predicted, w′ i (ξ iB ) is the coordinate ξ iB The derivative of the corrected thermally induced warping displacement at i (ξ iB ) is the coordinate ξ iB The corrected thermally induced warping displacement, ξ iF is the coordinate of the other end of the substrate in the chip layout to be predicted, and m is the number of chips in the chip layout to be predicted.

[0099] For example, see Figure 4 , which is a schematic diagram of a full-chip stacking method provided in an embodiment of the present application.

[0100] like Figure 4 As shown, the warpage at point D is the quantity to be determined, and (x, y, z) is the global coordinate system. First, connect point D with the centroid of the i-th chip (ignoring the z direction) and calculate the intersection point E with the edge of the silicon transfer surface. i 、F i ,if:

[0101] |C i E i |≥|C i F i |

[0102] Then Direction is relative coordinate ξ i The positive direction of the establishment (ξ i , z) relative coordinate system, otherwise Direction is relative coordinate ξ i The positive direction of the establishment (ξ i , z) relative coordinate system.

[0103] The warpage of multiple chips at D is superimposed to obtain the warpage distribution of the entire chip, that is:

[0104]

[0105] w(x,y) is the preliminary thermally induced warpage displacement, and m is the number of chips in the chip layout to be predicted.

[0106] S104: establishing multiple planes including the minimum point and the stationary point according to the preliminary thermally induced warping displacement; and calculating cosine values ​​of angles between the multiple planes and the coordinate axes of the current coordinate system respectively;

[0107] S105: taking the plane with the smallest cosine value of the included angle as the correction plane; calculating the direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system;

[0108] S106: Calculating a predicted thermally induced warping displacement based on the preliminary thermally induced warping displacement and the direction cosine values ​​using a coordinate axis translation and rotation formula.

[0109] In the embodiment of the present application, the above calculation boundary conditions are free boundary conditions, which are different from the actual process conditions. Therefore, the model parameters need to be corrected.

[0110] Specifically, based on the minimum point and stationary point of the warpage of the entire chip bottom surface, a plane can be determined for every three points (P1(x1,y1,z1), P2(x2,y2,z2), P3(x3,y3,z3)):

[0111] A(x-x1)+B(y-y1)+C(z-z1)=0;

[0112] A=(y3-y1)(z3-z1)-(y2-y1)(z2-z1);

[0113] B = (x3 - x1)(z2 - z1) - (x2 - x1)(z3 - z1);

[0114] C=(x2-x1)(y3-y1)-(x3-x1)(y2-y1);

[0115] That is, there are at most planes, select and determine the possible m planes that meet the condition: all points are located above the plane. That is, there is a real coordinate point (x0, y0, z0) on the bottom surface of the chip that meets the condition:

[0116]

[0117] The cosine values ​​of the angles between the plurality of planes and the coordinate axis of the current coordinate system are calculated respectively to determine the most likely stable plane.

[0118] Min(cos 2 α j +cos 2 β j +cos 2 γ j ),1≤j≤m

[0119] Among them, α j , β j , γ j are the angles between the jth face and the current coordinates X, Y, and Z axes respectively.

[0120] Based on the preliminary thermally induced warping displacement and direction cosine values, the predicted thermally induced warping displacement is calculated using the coordinate axis translation and rotation formulas. It is specifically calculated using the following formula:

[0121]

[0122] Wherein, w(x,y) is the preliminary thermally induced warping displacement, x is the abscissa of the preliminary thermally induced warping displacement, y is the ordinate of the preliminary thermally induced warping displacement, l1 is the direction cosine value between the coordinate axis X' of the correction plane and the coordinate axis X of the current coordinate system, m1 is the direction cosine value between the coordinate axis X' of the correction plane and the coordinate axis Y of the current coordinate system, n1 is the direction cosine value between the coordinate axis X' of the correction plane and the coordinate axis Z of the current coordinate system, l2 is the direction cosine value between the coordinate axis Y' of the correction plane and the coordinate axis The direction cosine value of axis X, m2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Y of the current coordinate system, n2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system, l3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis X of the current coordinate system, m3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Y of the current coordinate system, n3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Z of the current coordinate system, w 真 (x′, y′) is the predicted thermally induced warping displacement, x′ is the horizontal coordinate of the predicted thermally induced warping displacement, y′ is the vertical coordinate of the predicted thermally induced warping displacement, d1 is the translation distance of the coordinate axis X' of the correction plane relative to the coordinate axis X of the current coordinate system, d2 is the translation distance of the coordinate axis Y' of the correction plane relative to the coordinate axis Y of the current coordinate system, and d3 is the translation distance of the coordinate axis Z' of the correction plane relative to the coordinate axis Z of the current coordinate system.

[0123] Optionally, the embodiment of the present application may also set a hotspot threshold according to the process requirements of the chip foundry:

[0124] Max(w 真 (x′,y′))≤C1;

[0125]

[0126] Among them, C1 and C2 are set thresholds.

[0127] The embodiment of the present application can compare the warpage prediction result (ie, the predicted thermally induced warpage displacement) with the thresholds C1 and C2, and mark it as a hotspot if the threshold conditions are not met, so that the designer can prioritize the optimization of the hotspot.

[0128] An embodiment of the present application provides a chip thermal warpage prediction method, the method comprising: obtaining a chip layout to be predicted; calculating an effective elastic modulus, an effective Poisson's ratio, and an effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio, and material thermal expansion coefficient of various materials in the chip layout to be predicted; calculating a preliminary thermally induced warpage displacement of the chip layout to be predicted in a current coordinate system based on the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient, material volume fraction, material elastic modulus, material Poisson's ratio, material thermal expansion coefficient, and the coordinates of each point in the chip layout to be predicted; establishing multiple planes including the minimum point and the stationary point based on the minimum point and the stationary point of the preliminary thermally induced warpage displacement; respectively calculating the cosine values ​​of angles between the multiple planes and the coordinate axes of the current coordinate system; selecting the plane with the smallest cosine value of the angle as a correction plane; calculating the direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system; and calculating the predicted thermally induced warpage displacement based on the preliminary thermally induced warpage displacement and the direction cosine values ​​using coordinate axis translation and rotation formulas. This application uses classical elastic mechanics theory to calculate the thermally induced warpage distribution of heterogeneous integrated chip arrays, enabling rapid and accurate prediction of thermally induced warpage during chip manufacturing. This allows for the identification of potential thermally induced warpage hotspots during the design phase, facilitating optimization of heterogeneous integrated chip layouts. Furthermore, this method is a fast prediction method with far less computational overhead than existing finite element methods, thus shortening the design cycle.

[0129] Exemplary devices

[0130] See also Figure 5 FIG. 1 is a schematic diagram of a chip thermal warpage prediction device provided in an embodiment of the present application, comprising:

[0131] An acquisition unit, used for acquiring the chip layout to be predicted;

[0132] A first calculation unit is used to calculate the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted;

[0133] a second calculation unit, configured to calculate a preliminary thermally induced warpage displacement of the chip layout to be predicted in a current coordinate system based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted;

[0134] a third calculation unit, configured to establish, based on the minimum point and the stationary point of the preliminary thermally induced warping displacement, a plurality of planes including the minimum point and the stationary point; and calculate the cosine values ​​of the angles between the plurality of planes and the coordinate axes of the current coordinate system respectively;

[0135] a fourth calculation unit, configured to take the plane with the smallest cosine value of the included angle as a correction plane; and calculate direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system;

[0136] A fifth calculation unit is configured to calculate, based on the preliminary thermally induced warping displacement and the direction cosine value, a predicted thermally induced warping displacement using a coordinate axis translation and rotation formula.

[0137] In a possible implementation, the first calculation unit is specifically configured to calculate the effective elastic modulus, effective Poisson's ratio, and effective thermal expansion coefficient of the chip layout to be predicted using the following formula:

[0138]

[0139]

[0140]

[0141] Among them, E eff is the effective elastic modulus, v eff is the effective Poisson's ratio, α eff is the effective thermal expansion coefficient, n is the number of the various materials, c j is the volume fraction of the jth material, E j is the elastic modulus of the jth material, v j is the Poisson's ratio of the jth material, α j is the thermal expansion coefficient of the jth material.

[0142] In a possible implementation, the fifth calculation unit is specifically configured to calculate the predicted thermally induced warping displacement using the following formula:

[0143]

[0144] Wherein, w(x, y) is the preliminary thermally induced warping displacement, x is the abscissa of the preliminary thermally induced warping displacement, y is the ordinate of the preliminary thermally induced warping displacement, l1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis X of the current coordinate system, m1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Y of the current coordinate system, n1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Z of the current coordinate system, l2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system The direction cosine value of the coordinate axis X, m2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Y of the current coordinate system, n2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system, l3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis X of the current coordinate system, m3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Y of the current coordinate system, n3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Z of the current coordinate system, w 真 (x′, y′) is the predicted thermally induced warping displacement, x′ is the horizontal coordinate of the predicted thermally induced warping displacement, y′ is the vertical coordinate of the predicted thermally induced warping displacement, d1 is the translation distance of the coordinate axis X′ of the correction plane relative to the coordinate axis X of the current coordinate system, d2 is the translation distance of the coordinate axis Y′ of the correction plane relative to the coordinate axis Y of the current coordinate system, and d3 is the translation distance of the coordinate axis Z′ of the correction plane relative to the coordinate axis Z of the current coordinate system.

[0145] In a possible implementation, the second calculation unit is specifically configured to calculate the preliminary thermally induced warping displacement using the following formula:

[0146]

[0147]

[0148]

[0149] Among them, wa i (ξ i ) is the thermally induced warping displacement of the symmetrical structure, B1, B2, B3, B4, B5, r1 and r2 are preset parameters calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio and the material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted, ξ i is the coordinate of each point of the chip layout to be predicted, w i (ξ i ) is the corrected thermally induced warping displacement, ξiA is the coordinate of one end of the chip in the chip layout to be predicted, w′ i (ξ iA ) is the coordinate ξ iA The derivative of the corrected thermally induced warping displacement at i (ξ iA ) is the coordinate ξ iA The corrected thermally induced warping displacement, ξ iE is the coordinate of one end of the substrate in the chip layout to be predicted, ξ iB is the coordinate of the other end of the chip in the chip layout to be predicted, w′ i (ξ iB ) is the coordinate ξ iB The derivative of the corrected thermally induced warping displacement at i (ξ iB ) is the coordinate ξ iB The corrected thermally induced warping displacement, ξ iF is the coordinate of the other end of the substrate in the chip layout to be predicted, and m is the number of chips in the chip layout to be predicted.

[0150] The embodiment of the present application provides a device for predicting thermal warpage of a chip, and a method applied to the device includes: obtaining a chip layout to be predicted; calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted; and calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of each point in the chip layout to be predicted based on the effective elastic modulus, effective Poisson's ratio, effective thermal expansion coefficient, material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient and the coordinates of each point in the chip layout to be predicted. The preliminary thermally induced warping displacement of the chip layout to be predicted in the current coordinate system is calculated; based on the minimum point and stationary point of the preliminary thermally induced warping displacement, multiple planes including the minimum point and stationary point are established; the cosine values ​​of the angles between the multiple planes and the coordinate axes of the current coordinate system are calculated respectively; the plane with the smallest cosine value of the angle is taken as the correction plane; the direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system are calculated; based on the preliminary thermally induced warping displacement and the direction cosine values, the predicted thermally induced warping displacement is calculated using the coordinate axis translation and rotation formula. This application calculates the thermally induced warping distribution of heterogeneous integrated chip arrays through the classical elastic mechanics theory, and realizes a fast and accurate prediction of the thermally induced warping in the chip manufacturing process, so as to find the thermally induced warping hotspots that may appear in the chip manufacturing process during the design stage, so as to facilitate designers to optimize the layout design of heterogeneous integrated chips. At the same time, this method is a fast prediction method with much less computational consumption than the existing finite element method, which is conducive to shortening the design cycle.

[0151] Based on the above embodiments, the present invention provides a chip thermal warpage prediction system, including:

[0152] memory for storing computer programs;

[0153] A processor is configured to implement the steps of the above-mentioned chip thermal warpage prediction method when executing the computer program.

[0154] Based on the above embodiments, an embodiment of the present application further provides a computer-readable medium having a computer program stored thereon. When the computer program is processed and executed, the steps of the above-mentioned chip thermal warpage prediction method are implemented.

[0155] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0156] The computer-readable medium may be included in the system, or may exist independently without being incorporated into the system.

[0157] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for executing the methods shown in the flowcharts.

[0158] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from the other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0159] The above is only a preferred embodiment of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above-disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of protection of the technical solution of the present application.

Claims

1. A chip thermal warpage prediction method, characterized in that: include: Obtain the chip layout to be predicted; Calculating the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted; Calculating a preliminary thermally induced warpage displacement of the chip layout to be predicted in a current coordinate system according to the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted; According to the minimum point and the stationary point of the preliminary thermally induced warping displacement, a plurality of planes including the minimum point and the stationary point are established; and the cosine values ​​of the angles between the plurality of planes and the coordinate axes of the current coordinate system are calculated respectively; Taking the plane with the smallest cosine value of the included angle as the correction plane; Calculating direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system; The predicted thermally induced warping displacement is calculated based on the preliminary thermally induced warping displacement and the direction cosine value using a coordinate axis translation and rotation formula.

2. The method according to claim 1, characterized in that The effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted are calculated based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted, and are specifically calculated by the following formula: Among them, E eff is the effective elastic modulus, v eff is the effective Poisson's ratio, α eff is the effective thermal expansion coefficient, n is the number of the various materials, c j is the volume fraction of the jth material, E j is the elastic modulus of the jth material, v j is the Poisson's ratio of the jth material, α j is the thermal expansion coefficient of the jth material.

3. The method according to claim 1, characterized in that The predicted thermally induced warping displacement is calculated based on the preliminary thermally induced warping displacement and the direction cosine value using the coordinate axis translation and rotation formula, which is specifically calculated using the following formula: Wherein, w(x, y) is the preliminary thermally induced warping displacement, x is the abscissa of the preliminary thermally induced warping displacement, y is the ordinate of the preliminary thermally induced warping displacement, l1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis X of the current coordinate system, m1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Y of the current coordinate system, n1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Z of the current coordinate system, l2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system The direction cosine value of the coordinate axis X, m2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Y of the current coordinate system, n2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system, l3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis X of the current coordinate system, m3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Y of the current coordinate system, n3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Z of the current coordinate system, w 真 (x′, y′) is the predicted thermally induced warping displacement, x′ is the horizontal coordinate of the predicted thermally induced warping displacement, y′ is the vertical coordinate of the predicted thermally induced warping displacement, d1 is the translation distance of the coordinate axis X′ of the correction plane relative to the coordinate axis X of the current coordinate system, d2 is the translation distance of the coordinate axis Y′ of the correction plane relative to the coordinate axis Y of the current coordinate system, and d3 is the translation distance of the coordinate axis Z′ of the correction plane relative to the coordinate axis Z of the current coordinate system.

4. The method according to claim 1, wherein The preliminary thermally induced warpage displacement of the chip layout to be predicted in the current coordinate system is calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted, and is specifically calculated by the following formula: Among them, wa i (ξ i ) is the thermally induced warping displacement of the symmetrical structure, B1, B2, B3, B4, B5, r1 and r2 are preset parameters calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio and the material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted, ξ i is the coordinate of each point of the chip layout to be predicted, w i (ξ i ) is the corrected thermally induced warping displacement, ξ iA is the coordinate of one end of the chip in the chip layout to be predicted, w′ i (ξ iA ) is the coordinate ξ iA The derivative of the corrected thermally induced warping displacement at i (ξ iA ) is the coordinate ξ iA The corrected thermally induced warping displacement, ξ iE is the coordinate of one end of the substrate in the chip layout to be predicted, ξ iB is the coordinate of the other end of the chip in the chip layout to be predicted, w′ i (ξ iB ) is the coordinate ξ iB The derivative of the corrected thermally induced warping displacement at i (ξ iB ) is the coordinate ξ iB The corrected thermally induced warping displacement, ξ iF is the coordinate of the other end of the substrate in the chip layout to be predicted, and m is the number of chips in the chip layout to be predicted.

5. A chip thermal warpage prediction device, characterized in that: include: An acquisition unit, used for acquiring the chip layout to be predicted; A first calculation unit is used to calculate the effective elastic modulus, effective Poisson's ratio and effective thermal expansion coefficient of the chip layout to be predicted based on the material volume fraction, material elastic modulus, material Poisson's ratio and material thermal expansion coefficient of various materials in the chip layout to be predicted; a second calculation unit, configured to calculate a preliminary thermally induced warpage displacement of the chip layout to be predicted in a current coordinate system based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio, the material thermal expansion coefficient, and the coordinates of each point of the chip layout to be predicted; a third calculation unit, configured to establish, based on the minimum point and the stationary point of the preliminary thermally induced warping displacement, a plurality of planes including the minimum point and the stationary point; and calculate the cosine values ​​of the angles between the plurality of planes and the coordinate axes of the current coordinate system respectively; a fourth calculating unit, configured to take the plane with the smallest cosine value of the included angle as a correction plane; Calculating direction cosine values ​​of the coordinate axes of the correction plane and the coordinate axes of the current coordinate system; A fifth calculation unit is configured to calculate, based on the preliminary thermally induced warping displacement and the direction cosine value, a predicted thermally induced warping displacement using a coordinate axis translation and rotation formula.

6. The device according to claim 5, characterized in that The first calculation unit is specifically configured to calculate the effective elastic modulus, effective Poisson's ratio, and effective thermal expansion coefficient of the chip layout to be predicted using the following formula: Among them, E eff is the effective elastic modulus, v eff is the effective Poisson's ratio, α eff is the effective thermal expansion coefficient, n is the number of the various materials, c j is the volume fraction of the jth material, E j is the elastic modulus of the jth material, v j is the Poisson's ratio of the jth material, α j is the thermal expansion coefficient of the jth material.

7. The device according to claim 5, characterized in that The fifth calculation unit is specifically configured to calculate the predicted thermally induced warping displacement using the following formula: Wherein, w(x, y) is the preliminary thermally induced warping displacement, x is the abscissa of the preliminary thermally induced warping displacement, y is the ordinate of the preliminary thermally induced warping displacement, l1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis X of the current coordinate system, m1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Y of the current coordinate system, n1 is the direction cosine value of the coordinate axis X' of the correction plane and the coordinate axis Z of the current coordinate system, l2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system The direction cosine value of the coordinate axis X, m2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Y of the current coordinate system, n2 is the direction cosine value of the coordinate axis Y' of the correction plane and the coordinate axis Z of the current coordinate system, l3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis X of the current coordinate system, m3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Y of the current coordinate system, n3 is the direction cosine value of the coordinate axis Z' of the correction plane and the coordinate axis Z of the current coordinate system, w 真 (x′, y′) is the predicted thermally induced warping displacement, x′ is the horizontal coordinate of the predicted thermally induced warping displacement, y′ is the vertical coordinate of the predicted thermally induced warping displacement, d1 is the translation distance of the coordinate axis X′ of the correction plane relative to the coordinate axis X of the current coordinate system, d2 is the translation distance of the coordinate axis Y′ of the correction plane relative to the coordinate axis Y of the current coordinate system, and d3 is the translation distance of the coordinate axis Z′ of the correction plane relative to the coordinate axis Z of the current coordinate system.

8. The device according to claim 5, characterized in that The second calculation unit is specifically configured to calculate the preliminary thermally induced warping displacement using the following formula: Among them, wa i (ξ i ) is the thermally induced warping displacement of the symmetrical structure, B1, B2, B3, B4, B5, r1 and r2 are preset parameters calculated based on the effective elastic modulus, the effective Poisson's ratio, the effective thermal expansion coefficient, the material volume fraction, the material elastic modulus, the material Poisson's ratio and the material thermal expansion coefficient and the coordinates of each point of the chip layout to be predicted, ξ i is the coordinate of each point of the chip layout to be predicted, w i (ξ i ) is the corrected thermally induced warping displacement, ξ iA is the coordinate of one end of the chip in the chip layout to be predicted, w′ i (ξ iA ) is the coordinate ξ iA The derivative of the corrected thermally induced warping displacement at i (ξ iA ) is the coordinate ξ iA The corrected thermally induced warping displacement, ξ iE is the coordinate of one end of the substrate in the chip layout to be predicted, ξ iB is the coordinate of the other end of the chip in the chip layout to be predicted, w′ i (ξ iB ) is the coordinate ξ iB The derivative of the corrected thermally induced warping displacement at i (ξ iB ) is the coordinate ξ iB The corrected thermally induced warping displacement, ξ iF is the coordinate of the other end of the substrate in the chip layout to be predicted, and m is the number of chips in the chip layout to be predicted.

9. A chip thermal warpage prediction system, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the chip thermal warpage prediction method according to any one of claims 1 to 4 when executing the computer program.

10. A computer-readable medium, characterized in that The computer readable medium stores a computer program, which, when processed and executed, implements the steps of the chip thermal warpage prediction method according to any one of claims 1 to 4.

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