Circuit optimization method, system and device based on model predictive control and medium

Abstract

The invention provides a circuit optimization method, system and device based on model predictive control and a medium, and relates to the technical field of integrated circuit design, and the method comprises the steps: constructing a circuit knowledge graph and a simulation data lookup table according to a circuit design experience document and circuit simulation data; initializing a search feasible region of design points according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit; and according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, in combination with a model prediction control framework, executing a reinforcement learning method to obtain an optimal design point of the current circuit, and providing optimal configuration of the current circuit. According to the method, the consumption of simulation computing resources is effectively reduced, the optimization efficiency is improved, and meanwhile, the design is ensured to meet the multi-target performance requirements of gain, power consumption, bandwidth and the like.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to the field of optimized design of integrated circuits. Background Art

[0002] The automated optimization problem of robust analog integrated circuit design aims to achieve efficient, multi-objective optimization of circuit performance metrics (such as gain, power consumption, and bandwidth) within a complex and multi-dimensional design parameter space, thereby improving the stability, efficiency, and reliability of electronic devices under various operating environments. Existing optimization methods based on genetic algorithms draw on biological evolutionary theory to solve optimization problems by simulating the process of natural selection. However, they suffer from high computational costs when dealing with high-dimensional parameter spaces and struggle to find satisfactory solutions under complex constraints. Particle swarm optimization, a swarm intelligence-based technique suitable for solving complex optimization problems, is easy to implement and has good global search capabilities. However, when dealing with high-dimensional, multi-constrained analog circuit design problems, it can require long convergence times and is prone to getting stuck in local optima. Traditional Bayesian optimization methods, while powerful global optimization tools, are particularly well-suited for expensive function evaluations. However, when using Gaussian processes as surrogate models, they suffer from high computational overhead in high-dimensional, noisy design spaces. The complexity of training and inference increases dramatically with increasing data volume. Summary of the Invention

[0003] The present application provides a circuit optimization method, system, device and medium based on model predictive control to solve one or more technical problems existing in the prior art and at least provide a beneficial option or create conditions.

[0004] In one aspect, the present application provides a circuit optimization method based on model predictive control, comprising the following steps: Based on circuit design experience documents and circuit simulation data, a circuit knowledge graph and a simulation data lookup table are constructed; the circuit simulation data includes simulation data of the current circuit and simulation data of historical circuits; the circuit knowledge graph is used to define entities, relationships between entities, and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; Initializing the search feasible region of the design point according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a set of candidate design points for the current circuit; According to the simulation data lookup table, the circuit knowledge graph and the set of candidate design points, in combination with the model predictive control framework, a reinforcement learning method is executed to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

[0005] Furthermore, the search feasible region of the design point is initialized based on the circuit knowledge graph and the simulation data lookup table, and multi-point exploration Bayesian optimization is performed to obtain a set of candidate design points for the current circuit, including: Sampling data from the simulation data lookup table and training to obtain a proxy model; the proxy model fits the nonlinear simulation results of the analog circuit design by constructing an objective function; Initializing a search feasible region for the design point according to the circuit knowledge graph and the simulation data lookup table; By utilizing the multi-point acquisition function and combining the agent model, a multi-point exploration Bayesian optimization is performed in the search feasible domain to explore and screen out a set of candidate design points for the current circuit.

[0006] Furthermore, the multi-point acquisition function satisfies the following formula: ; in, represents the multi-point acquisition function, represents the number of design points in the candidate design point set, Indicates the design points; Indicates the The weighted multi-objective expectation improvement function corresponding to the design points satisfies the following formula: ; in, represents the number of objective functions of the surrogate model, Indicates the The objective function, Indicates the The design point corresponds to the The objective function value, express The corresponding weight coefficient is express The current optimal value, represents the mathematical expectation function.

[0007] Furthermore, the weighted multi-objective expected improvement function further includes a constraint penalty term, which is obtained according to the design experience rule; the weighted multi-objective expected improvement function satisfies the following formula: ; in, represents the number of constraints, Indicates the The design point for The penalty for violating the constraint, Indicates the The weight coefficient of each constraint condition.

[0008] Furthermore, the method of executing a reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph, and the set of candidate design points in combination with a model predictive control framework to obtain an optimal design point for the current circuit and provide an optimal configuration for the current circuit includes: Initializing the state space and action space of the reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph, and the set of candidate design points; the state space is used to describe the current state of the circuit, including the set of candidate design points and their corresponding performance indicators; the action space is used to describe the adjustable action range and its step size limit corresponding to the set of candidate design points, with its boundaries constrained by the simulation data lookup table and the circuit knowledge graph; Inputting the state space and the action space into the policy network of the reinforcement learning method, combining the state space and the action space with the reward function of the reinforcement learning method, and outputting an optimized parameter set; the optimized parameter set is a set of optimized circuit design parameters that are most likely to improve circuit performance; and using the optimized parameter set as an initial parameter search domain of the model predictive control framework; The model predictive control framework is used to construct a multi-step optimization problem model, and exploration and optimization are performed in the initial parameter search domain to obtain the optimal design point and provide the optimal configuration of the current circuit.

[0009] Furthermore, the multi-step optimization problem model satisfies the following formula: ; in, Indicates that from the current time step The beginning of the future The set of optimized parameters for time steps; Represents the multi-step optimization problem model, indicating that for the current time step The future The minimum cumulative cost of candidate actions in time steps; The time step in the state space is The state vector at time , , represents a state prediction model constructed based on the simulation data lookup table; The time step is The optimized parameter set when ; Indicates the current time step The objective function of represents the number of constraints, Used to indicate the time step is The state vector and the optimized parameter set at the time violate the The constraint penalty corresponding to the constraint condition is Indicates the The weight coefficient of each constraint condition.

[0010] Furthermore, the proxy model is a machine learning model.

[0011] On the other hand, the present application provides a circuit optimization system based on model predictive control, including a knowledge-driven module, a preliminary Bayesian optimization module, and an advanced collaborative optimization module; The knowledge-driven module is used to construct a circuit knowledge graph and a simulation data lookup table based on circuit design experience documents and circuit simulation data; the circuit simulation data includes simulation data of the current circuit and simulation data of historical circuits; the circuit knowledge graph is used to define entities, relationships between entities, and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; The preliminary Bayesian optimization module is used to initialize the search feasible domain of the design point according to the circuit knowledge graph and the simulation data lookup table, and perform multi-point exploration Bayesian optimization to obtain a set of candidate design points for the current circuit; The advanced collaborative optimization module is used to execute a reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph and the set of candidate design points, combined with a model predictive control framework, to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

[0012] On the other hand, the present application provides a circuit optimization device based on model predictive control, comprising: a processor and a memory; the memory is used to store a program; when the program is executed by the processor, the processor implements the aforementioned circuit optimization method based on model predictive control.

[0013] On the other hand, the present application provides a computer medium storing a program executable by a processor, wherein the program executable by the processor is used to implement the aforementioned circuit optimization method based on model predictive control when executed by the processor.

[0014] The beneficial effects of the present application are as follows: the present application provides a circuit optimization method based on model predictive control, including constructing a circuit knowledge graph and a simulation data lookup table based on circuit design experience documents and circuit simulation data; the circuit simulation data includes simulation data of the current circuit and simulation data of historical circuits; the circuit knowledge graph is used to define entities, associations between entities and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; based on the circuit knowledge graph and the simulation data lookup table, the search feasible domain of the design point is initialized, and multi-point exploration Bayesian optimization is performed to obtain a set of candidate design points for the current circuit; based on the simulation data lookup table, the circuit knowledge graph and the set of candidate design points, combined with the model predictive control framework, a reinforcement learning method is executed to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit. The present application effectively reduces the consumption of simulation computing resources and improves optimization efficiency, while ensuring that the design meets multi-objective performance requirements such as gain, power consumption, and bandwidth, overcomes the limitations of traditional methods in processing complex high-dimensional design spaces, and provides a more flexible, accurate and robust solution. This application also provides corresponding devices, systems and media. The beneficial effects of the devices, systems and media are similar to those of the methods and will not be described in detail here.

[0015] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be achieved and obtained through the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation to the technical solution of the present invention.

[0017] Figure 1 is a flow chart of a circuit optimization method based on model predictive control provided by this application; Figure 2 This is a flowchart of determining a set of candidate design points for a current circuit provided by the present application; Figure 3 This is a flow chart provided by the present application for determining the optimal design point of the current circuit; Figure 4 is a structural diagram of a circuit optimization system based on model predictive control provided by this application; Figure 5 This is a structural diagram of a circuit optimization device based on model predictive control provided in this application. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0019] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. The described embodiments should not be considered as limiting the present application. All other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0022] With the increasing complexity of electronic device functions and rising performance requirements, parameter optimization in analog circuit design has become a research hotspot. In analog circuit design, the parameter space is high-dimensional and complexly correlated. Traditional methods rely on engineers' experience or large-scale trial-and-error simulation processes, which are time-consuming and inefficient, making it difficult to quickly and efficiently explore the global optimal solution. This is especially true when optimizing multi-objective circuit performance (such as gain, power consumption, bandwidth, etc.), which requires balancing conflicting objectives. In addition, the cost of simulating device and circuit performance evaluation is high, especially in high-dimensional optimization parameter spaces, where multiple calls to simulation tools such as SPICE impose a significant computational burden. Analog circuit design also faces the challenges of insufficient human experience and data. Engineers' experience is difficult to systematize and embed into data-driven processes, while relying solely on experience is limited by the diversity of circuit performance models and nonlinear dynamic characteristics, resulting in inefficient knowledge transfer and a high reliance on historical data accumulation.

[0023] In the prior art, the patent with publication number CN117910410A discloses a large-scale multi-objective analog chip circuit evolutionary optimization design method, and proposes an optimization method that combines a differential grouping module and an adaptive cooperative co-evolution strategy. By intelligently grouping decision variables and iteratively adjusting each group of parameters using different optimization strategies, high-dimensional problems can be efficiently decomposed into low-dimensional sub-problems, and a confidence adaptive strategy is used to enhance the credibility and rigor of the grouping results.

[0024] Patent publication number CN118940705A discloses a circuit optimization method based on a pre- and post-simulation strategy and multi-objective optimization. First, in a pre-simulation process, a multi-objective heuristic strategy is used to adjust circuit component parameters, and the simulator is used to evaluate the objective function and constraint functions. Then, in a post-simulation process, an adaptive reference vector method is used to select elite solutions for layout and routing optimization, and the simulator is also used to calculate the objective and constraint values. If the constraints are not met, the optimization process is adaptively adjusted according to the specific situation until a satisfactory solution set is obtained.

[0025] Although the above two methods have achieved certain optimization effects, the former relies too much on the differential grouping module, which affects the co-evolution strategy, performs poorly in the real simulation environment and does not consider the design knowledge rules; the latter requires multiple calls to the simulator to calculate the index values ​​of a large number of solutions during the previous and subsequent simulation processes, resulting in long simulation time, high computing resource requirements, and limited task complexity.

[0026] Other common optimization methods such as genetic algorithms (GA), particle swarm optimization (PSO), traditional Bayesian optimization, and gradient-based methods also have their own limitations. For example, GA has high computational costs when processing high-dimensional parameter spaces, PSO may face problems such as long convergence time and local optimal solutions, traditional Bayesian optimization has high computational overhead in high-dimensional and noisy design spaces, and gradient-based methods are prone to falling into local optimal solutions and are not suitable for adjusting non-differentiable design parameters.

[0027] In response to the problems existing in the related art, the embodiments of the present application provide a circuit optimization method, system, device and medium based on model predictive control. The embodiments of the present application combine multi-point exploration Bayesian optimization, reinforcement learning and model predictive control, use simulation data lookup tables to reduce the number of simulation calls to reduce computing resource consumption, and dynamically adjust the optimization strategy to cope with changing design requirements. This method can not only explore the design space quickly and efficiently, avoid invalid exploration and fall into local optimal solutions, but also intelligently adjust the optimization direction according to multiple objectives and constraint requirements, greatly improving the optimization efficiency and accuracy, so that the circuit design can effectively reduce the design time and computing cost while meeting the performance indicators. Compared with the prior art, the embodiments of the present application introduce knowledge graphs to guide the selection of the initial design space, and combine historical data with design rules to enhance the optimization process, thereby ensuring design flexibility, robustness and adaptability to complex and changing design environments.

[0028] First, the circuit optimization method based on model predictive control provided by the embodiment of the present application will be described in detail with reference to the accompanying drawings.

[0029] Reference Figure 1 The implementation process of the circuit optimization method based on model predictive control provided in the embodiment of the present application includes but is not limited to the following steps.

[0030] Step 101: construct a circuit knowledge graph and simulation data lookup table based on circuit design experience documents and circuit simulation data.

[0031] The circuit knowledge graph is used to define entities, inter-entity relationships, and design experience rules in analog circuit design. Circuit simulation data includes simulation data for the current circuit and historical circuit simulation data. The simulation data lookup table stores circuit performance indicators corresponding to different design points. Each design point corresponds to a circuit design parameter combination.

[0032] Step 101 establishes a comprehensive knowledge base to support the subsequent circuit design optimization process. By integrating circuit design experience documents and circuit simulation data, this step constructs a circuit knowledge graph and simulation data lookup table (LUT). The circuit knowledge graph defines key entities in analog circuit design (such as transistors and resistors), the relationships between these entities, and the empirical rules accumulated during the design process. This not only helps understand the internal workings of the circuit but also provides valuable prior knowledge for optimization algorithms. The LUT, on the other hand, stores circuit performance indicators corresponding to different design points, allowing for quick query during the optimization process without having to perform time-consuming circuit simulations each time. Each design point corresponds to a specific combination of circuit design parameters, ensuring that the LUT data can be directly applied to actual design decisions.

[0033] The purpose of building a knowledge graph is to structure circuit design experience documents, including theoretical rules, engineering experience, and design constraints in the field, to provide a priori constraints and dynamic update capabilities for multi-objective optimization. First, entities and relationships are defined. Entity categories include circuit elements (such as transistors and resistors), circuit parameters (such as gain and power consumption), design specifications (such as the gain limit), and environmental factors (such as temperature). These entities are connected via triples (entity 1, relationship, entity 2), for example, "transistor affects gain." Next, the knowledge graph is constructed through four steps: collecting domain knowledge, establishing entities and relationships, integrating rules and constraints, and integrating dynamic data sources.

[0034] Specifically, this involves acquiring knowledge from circuit design experience documents, using a graph database to store entities and relationships, encoding physical rules and design constraints as edges in the graph, and integrating simulation tools to update performance data in real time. Technologies such as TransE and RotatE are then used to vectorize the entities and relationships in the knowledge graph, serving as input features for the optimization model. Furthermore, the rules in the knowledge graph are converted into optimization constraints or penalty terms in the objective function, allowing design specifications and performance limitations to be considered during the optimization process.

[0035] LUT generation aims to reduce real-time computing costs through pre-simulation by using SPICE tools to perform large-scale simulations of circuit performance under different process parameters and storing the results in tabular form for fast query.

[0036] Step 102 : Initialize the search feasible region of the design point based on the circuit knowledge graph and the simulation data lookup table, and perform multi-point exploration Bayesian optimization to obtain a set of candidate design points for the current circuit.

[0037] The goal of step 102 is to initialize the design space based on the circuit knowledge graph and the simulation data lookup table and identify an initial set of high-quality design points using Multi-Point Exploration Bayesian Optimization (MPE-BO). First, based on the information provided by the circuit knowledge graph, this step limits the feasible search domain, avoiding blindly searching unrealistic or unreasonable design parameter spaces. Then, multiple design points are evaluated in parallel using the MPE-BO method, which efficiently finds a set of design points close to the optimal solution in a complex, high-dimensional design space. Compared to traditional single-point exploration, this method increases the breadth of exploration, thereby accelerating the search for the global optimal solution while reducing the risk of falling into a local optimum. The result is a preliminarily selected set of candidate design points that represent potential excellent circuit configurations for the current circuit.

[0038] Step 103 , based on the simulation data lookup table, the circuit knowledge graph, and the candidate design point set, combined with the model predictive control framework, executes a reinforcement learning method to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

[0039] Step 103 utilizes a model predictive control (MPC) framework combined with reinforcement learning to further optimize the set of candidate design points obtained in step 102 to determine the final optimal design point. This process relies on immediate performance feedback provided by a simulation data lookup table, enabling the reinforcement learning algorithm to quickly evaluate the actual effect of each design point without requiring a full circuit simulation. Next, by integrating the design rules and constraints from the circuit knowledge graph into the MPC framework, it ensures that each adjustment meets the pre-set technical specifications and performance requirements. Reinforcement learning then iterates and optimizes based on this foundation, selecting the optimal action (i.e., adjusting the design parameters) based on the current state and gradually approaching the optimal design solution through a reward mechanism. Ultimately, this series of operations outputs a set of optimal circuit configuration parameters that meet all design objectives, achieving efficient, accurate, and robust circuit design optimization.

[0040] In some embodiments of the present application, in the process of constructing a circuit knowledge graph, the key entities in the circuit design are first defined. These entities include specific circuit elements such as operational amplifiers (Op-Amp), N-type transistors (NPN), P-type transistors (PNP), resistors (Resistor) and capacitors (Capacitor). In addition, circuit parameters such as transistor width (W), current (I), gain (Gain), bandwidth (Bandwidth) and power (Power) are also included. The design specifications cover specific design goals or constraints such as gain, phase margin, and power consumption. Environmental factors are also taken into consideration, such as temperature (Temperature), voltage (Voltage) and process variation (PVT), to reflect their impact on circuit performance.

[0041] Inter-entity associations describe interactions or dependencies between entities in the form of triples. For example, "transistor width affects gain" indicates that the physical size of a transistor has a direct impact on its gain; "gain and power consumption are inversely proportional" indicates that increasing gain generally leads to increased power consumption; and "voltage changes may affect current and power consumption" emphasizes the impact of voltage changes on circuit performance metrics. This definition of inter-entity associations provides a foundational framework for the subsequent construction of circuit knowledge graphs.

[0042] To construct design experience rules, design rules are first extracted from circuit design experience documents and encoded as edges in the knowledge graph, such as the inverse relationship between gain and power consumption or the impact of PVT variation on design objectives. Finally, by integrating data sources from simulation tools, circuit design parameters and performance can be compared and optimized against the rules in the knowledge graph, enabling dynamic adjustment based on feedback. This process ensures design accuracy and flexibility while supporting continuous knowledge updating and optimization.

[0043] In some embodiments of the present application, taking a two-stage operational amplifier as an example, the circuit knowledge graph corresponding to the two-stage operational amplifier includes entities such as circuit elements (e.g., operational amplifiers, transistors, resistors, capacitors), design parameters (transistor width, gain, power consumption, bandwidth), performance specifications (gain floor, power consumption ceiling, phase margin), and environmental factors (temperature, voltage, process variation (PVT). Physical rules and constraints between entities are defined using triples, such as "transistor width affects gain," "gain and power consumption are inversely proportional," and "temperature variation reduces bandwidth stability." Furthermore, the knowledge graph integrates circuit design experience (e.g., gain-bandwidth trade-off criteria), the impact of process variation on performance, and hard constraints (e.g., power consumption ≤ 5mW). A graph database (e.g., Neo4j) is used to manage and update relationships between entities, and a LUT (Low-Unit Test Set) is generated by integrating pre-calculated data generated by SPICE simulations. Dynamic feedback mechanisms for optimization results (e.g., expansion of successful cases and strengthening of out-of-limit parameter constraints) enable iterative updates of the knowledge graph. This provides solid prior knowledge support for Bayesian optimization and reinforcement learning, ensuring accuracy and efficiency in multi-objective parameter tuning.

[0044] In some embodiments of the present application, reference is made to Figure 2 In step 102, based on the circuit knowledge graph and the simulation data lookup table, the search feasible domain of the design point is initialized, and multi-point exploration Bayesian optimization is performed to obtain the set of candidate design points for the current circuit. The implementation process includes but is not limited to the following steps.

[0045] Step 201: Sample data from a simulation data lookup table and train to obtain a proxy model.

[0046] Among them, the surrogate model fits the nonlinear simulation results of the analog circuit design by constructing the objective function.

[0047] In step 201, data is sampled from the simulation data lookup table (LUT) to train a proxy model. This proxy model is designed to fit the nonlinear simulation results in analog circuit design by constructing an objective function. The key to this step is to effectively train the model using existing simulation data so that it can accurately predict circuit performance under different design parameter combinations. In this way, the number of actual simulations can be greatly reduced in the subsequent optimization process, thereby saving computing resources and time. The selection and training of the proxy model is crucial to improving the efficiency of the entire optimization process because it directly determines the accuracy of the performance prediction of the unexplored design space.

[0048] Step 202: Initialize the search feasible region of the design point based on the circuit knowledge graph and the simulation data lookup table.

[0049] In step 202, the search for the feasible domain of design points is initialized based on the circuit knowledge graph and the simulation data lookup table. This means not only considering existing simulation data but also incorporating domain expertise, rules, and experience to define the range of possible design parameters. The circuit knowledge graph provides important information about circuit components, design parameters, and their relationships, which helps determine which design parameter combinations are reasonable and worth exploring. This initialization of the search for the feasible domain ensures that the optimization algorithm does not waste time on unrealistic or invalid design points, improving the effectiveness and specificity of the search and laying the foundation for subsequent multi-point exploration.

[0050] Step 203 : Using the multi-point acquisition function and combining with the agent model, multi-point exploration Bayesian optimization is performed in the search feasible domain to explore and select a set of candidate design points for the current circuit.

[0051] In step 203, a multi-point acquisition function is used in combination with a previously trained proxy model to perform multi-point exploration Bayesian optimization within the search feasible domain, thereby screening out a set of candidate design points. The core of this step is to evaluate multiple design points simultaneously to accelerate the discovery of potential high-quality design solutions. The multi-point exploration method not only increases the chance of finding a better solution in each iteration, but also avoids the problem of traditional single-point exploration easily falling into local optimality. By intelligently selecting the next design point to be evaluated, the process can effectively narrow the range of optimal design points. Ultimately, the set of candidate design points screened out after this round of optimization represents the most promising circuit configuration after preliminary optimization, providing a solid foundation for further refined optimization.

[0052] In some embodiments of the present application, during each iteration of multi-point exploratory Bayesian optimization, a simulation data lookup table (LUT) is used to quickly evaluate the actual performance indicators of each round of optimization results (i.e., the set of candidate design points), avoiding the time-consuming circuit simulation process and ensuring the accuracy and efficiency of the evaluation results. Subsequently, the proxy model is updated based on these evaluation results, and the model parameters are readjusted or optimized by incorporating actual performance data into the training set to improve the accuracy of future design space predictions. This dynamic update mechanism not only enhances the proxy model's ability to predict the performance of unexplored areas, but also enables each round of optimization to make decisions based on the latest and most accurate information, thereby effectively improving the accuracy and efficiency of the overall optimization process. In this way, the entire process not only ensures the effectiveness of the initial screening, but also provides a solid foundation for subsequent optimization steps.

[0053] In the field of circuit optimization and design, traditional Bayesian optimization provides an efficient and systematic approach to exploring complex, high-dimensional parameter spaces. Its primary purpose is to reduce the number of expensive simulations while increasing the probability of finding the global optimal solution. Circuit design typically involves multiple interrelated design parameters (such as transistor size and bias current), which have complex and nonlinear relationships with circuit performance metrics (such as gain, power consumption, and bandwidth). Bayesian optimization constructs a surrogate model (typically a Gaussian process regression (GP)) to approximate the true objective function and uses an acquisition function (such as expected improvement (EI)) to intelligently select the next most promising point for evaluation.

[0054] Compared to traditional Bayesian optimization, the multi-point exploration Bayesian optimization (MPE-BO) proposed in the present embodiment accelerates the optimization process by simultaneously evaluating multiple design points, making it particularly suitable for complex, high-dimensional circuit design problems. This approach not only increases the chances of finding a better solution with each iteration, but also avoids the problem of traditional single-point exploration easily falling into local optimality. Furthermore, MPE-BO combines the prior information provided by the circuit knowledge graph with the pre-computed data in the simulation data lookup table (LUT), further improving optimization efficiency and accuracy, ensuring that the optimization results meet both design goals and the needs of practical applications.

[0055] In some embodiments of the present application, the multi-point acquisition function of the MPE-BO proposed in the embodiments of the present application satisfies the following formula (1): (1); In formula (1), represents the multi-point acquisition function, represents the number of design points in the candidate design point set, Indicates the A design point. Indicates the The weighted multi-objective expected improvement function corresponding to the design points.

[0056] The multi-point acquisition function MPEBO plays a core role in the MPE-BO method proposed in the embodiments of this application. Its main purpose is to accelerate the optimization process by simultaneously evaluating multiple design points, and is particularly suitable for complex and high-dimensional design spaces.

[0057] Different from the traditional Bayesian optimization which only selects one design point with the greatest potential for further exploration, the multi-point acquisition function is defined by formula (1) and selects all the points at once. This allows each iteration to explore multiple potential high-quality solutions simultaneously, effectively increasing the possibility of finding the global optimal solution and accelerating the convergence speed.

[0058] For each selected design point , It represents the expected improvement in meeting multiple optimization objectives at that point and reflects the possible differences in importance or priority between different objectives through a weighted approach, ensuring comprehensive consideration of each objective during the optimization process. By maximizing the sum of the MOEIs of all selected design points, MPEBO not only pursues the optimal value of a single objective, but also seeks to achieve the optimal balance between multiple objectives across the entire design space.

[0059] By considering the total expected improvement across multiple design points, MPE-BO is able to better balance exploring unknown areas with leveraging known good areas. This means it can delve deeper into under-explored areas that show promising performance, while also optimizing already good designs based on existing information.

[0060] Therefore, formula (1) not only provides an effective mechanism for MPE-BO to guide multi-point parallel exploration, but also ensures the effective search for the global optimal solution in multi-objective optimization scenarios by introducing MOEI, effectively improving the optimization efficiency and the quality of the results. This method is particularly suitable for solving complex circuit design problems, in which multiple conflicting objectives such as gain, power consumption, and bandwidth need to be optimized simultaneously.

[0061] In some embodiments of the present application, the weighted multi-objective expected improvement function satisfies the following formula (2): (2); In formula (2), represents the number of objective functions of the surrogate model, Indicates the The objective function, Indicates the The design point corresponds to the The objective function value, express The corresponding weight coefficient is express The current optimal value, represents the mathematical expectation function.

[0062] The weighted multi-objective expected improvement function (MOEI) plays a crucial role in the optimization framework proposed in the embodiments of this application. It is mainly used to evaluate and select design points with potential improvement value, especially when dealing with multi-objective optimization problems.

[0063] The core task of the MOEI function is to quantify the Design points Improvement potential in satisfying multiple objective functions. By calculating the expected improvement value of each design point relative to the current optimal solution, it is possible to effectively identify those design points that may bring effective performance improvements.

[0064] In practical applications, circuit design often needs to consider multiple conflicting objectives (such as gain, power consumption, bandwidth, etc.) at the same time. Represents the number of objective functions of the surrogate model, each objective function Reflects the requirements of the circuit in different aspects. By introducing the weight coefficient By performing weighted summation on each objective, MOEI can flexibly adjust the relative importance of each objective, thereby achieving balanced optimization among multiple objectives.

[0065] Mathematical expectation function , used to calculate a given design point Implement an improved probability weighted average. Specifically, the mathematical expectation function The calculation is the design point Relative to the current optimal solution If the improvement is negative, it is set to 0, ensuring that only those design points with the potential to bring positive improvement are focused. By maximizing this expected value, MOEI ensures that each iteration will move towards overall performance improvement.

[0066] By comprehensively considering the potential for improvement of each objective function, MOEI provides an effective mechanism to guide the search direction of the optimization algorithm. This not only helps to quickly find the global optimal solution, but also avoids falling into local optimal solutions, especially in complex, high-dimensional design spaces.

[0067] In summary, Equation (2) effectively explores the design space by quantifying the expected improvement of each design point relative to the current optimal solution and combining it with weight allocation among multiple objectives. This approach not only improves the efficiency and effectiveness of the optimization process but also ensures that the final design achieves an optimal balance between multiple key indicators, making it particularly suitable for solving complex circuit design problems.

[0068] In some embodiments of the present application, the weighted multi-objective expected improvement function further includes a constraint penalty term, which is obtained according to design experience rules. The weighted multi-objective expected improvement function satisfies the following formula (3): (3); In formula (3), represents the number of constraints, Indicates the The design point for The penalty for violating the constraint, Indicates the The weight coefficient of each constraint condition.

[0069] This embodiment of the application introduces a constraint penalty term into the weighted multi-objective expected improvement function (MOEI) to ensure that the design point not only brings performance improvements but also satisfies a series of preset design constraints. This mechanism is crucial for achieving circuit optimization design that is both efficient and meets practical application requirements.

[0070] The MOEI function first quantifies the potential value of each design point by calculating its expected improvement over the current optimal solution across multiple objective functions. This maintains a focus on balancing multiple objectives while encouraging the exploration of design points that offer the potential for significant performance improvements. A constraint penalty is then introduced to assess whether the design point satisfies all pre-defined design rules and restrictions.

[0071] Constraint penalty items are mainly used to deal with design points that do not meet the constraints. Indicates the The design point for The violation penalty of a constraint condition. If the design point satisfies a constraint condition, the corresponding If it is negative or zero, the penalty term will not work; otherwise, if the design point violates a constraint, a corresponding penalty will be imposed based on the degree of violation. Used to adjust the importance of different constraints to ensure that key constraints are given priority.

[0072] By introducing constraint penalties, the MOEI function effectively incorporates design experience rules into the optimization process, ensuring that the final design solution not only excels in performance metrics but also strictly adheres to various constraints in engineering practice (such as power consumption limits and physical dimensions). This helps avoid generating designs that have theoretically superior performance but are actually unfeasible.

[0073] By combining multi-objective improvements with constraint penalties, the optimization algorithm can more accurately identify high-quality design points that deliver breakthrough performance while meeting all design requirements. This approach improves the practical feasibility of the optimization results, making the final design more practical and capable of stable and reliable operation in real-world application environments.

[0074] In summary, the MOEI function further enhances the capabilities of the weighted multi-objective expected improvement function by introducing a constraint penalty term. This allows it to not only identify design points with high potential but also ensure that these design points strictly adhere to the preset design specifications. This is particularly important for solving complex circuit design problems, as it ensures that the optimization process pursues excellent performance while ensuring the practical feasibility and compliance of the design solution.

[0075] In some embodiments of the present application, during the entity extraction and rule encoding stage, relevant entities such as circuit elements, design parameters, and the like and their relationships, such as the inverse relationship between gain and power, are first extracted from the circuit knowledge graph. Through graph embedding technology (such as Graph Embeddings), these relationships and rules are converted into numerical information for easy subsequent processing and calculation. Next is the rule formatting process, which defines logical rules or formulas based on the extracted rules and expresses these rules in mathematical form. For example, the rule of "gain and power consumption are inversely proportional" is converted into the formula , and incorporate it into the objective function to achieve quantitative evaluation and optimization. This series of steps enables the professional knowledge in the knowledge graph to be effectively utilized in the automated design process, improving design efficiency and performance.

[0076] In some embodiments of the present application, the strategy of selecting the next design point in each iteration of the multi-point exploration Bayesian optimization MPE-BO satisfies the following formula (4): (4); In formula (4), It is Design points The next design point selected in each iteration.

[0077] This strategy enables MPE-BO to explore the design space more broadly by simultaneously selecting and evaluating multiple design points. This contrasts with traditional Bayesian optimization, which only selects a single, most promising design point for exploration. Multi-point exploration allows the algorithm to simultaneously search for potential high-quality solutions in different local regions, increasing the likelihood of discovering the global optimum.

[0078] In each iteration, the algorithm selects the design points with the largest expected sum of improvements. This approach ensures that each iteration makes the most informed choice based on the latest information, gradually guiding the search towards the optimal solution.

[0079] By maximizing the sum of expected improvements across all design points, MPE-BO not only considers the value of exploring unknown areas but also leverages existing simulation results and model predictions to guide the search direction, enabling the algorithm to quickly approach the optimal solution within a smaller number of iterations.

[0080] Because MPE-BO explores multiple design points simultaneously, it reduces the risk of getting stuck in a local optimum by prematurely concentrating on a particular region. Even if some regions appear to have high potential for improvement, through extensive parallel exploration, the algorithm still has the opportunity to discover other potentially better solutions.

[0081] In summary, by systematically selecting multiple high-potential design points for parallel evaluation, MPE-BO effectively combines the advantages of exploration and exploitation, not only accelerating the search for optimal solutions but also improving the quality of the final design. This approach is particularly well-suited for complex, high-dimensional circuit design problems with multiple local optima.

[0082] In some embodiments of the present application, the proxy model of MPE-BO is a machine learning model, including a support vector regression model (SVR).

[0083] By using machine learning models, particularly the SVR model, MPE-BO is able to efficiently approximate complex objective functions during analog circuit design optimization. Compared to traditional methods, this approach better handles nonlinear relationships and provides more accurate predictions of the objective function, thereby improving optimization efficiency and the accuracy of the results.

[0084] As a powerful nonparametric regression technique, SVR is particularly well-suited for handling nonlinear problems in high-dimensional spaces. Within the MPE-BO framework, SVR is used to fit an objective function model based on existing simulation data (such as circuit performance data under different process parameters). This enables the optimization algorithm to quickly evaluate different circuit design options without requiring time-consuming SPICE simulations, effectively reducing computational costs.

[0085] The SVR model uses kernel functions to handle nonlinear relationships in the input space. This means that even the most complex relationships between circuit design parameters and performance can be effectively modeled and predicted. This capability is crucial for accurate circuit optimization because it allows the algorithm to consider all possible combinations of design variables and their interactions, not just linear or simple relationships.

[0086] In each iteration of MPE-BO, the SVR model is trained using the currently available dataset to find the model parameters that minimize the loss function. This process involves adjusting the model's weights and biases to ensure that its output is as close as possible to the true target value. A well-trained SVR model provides a reliable foundation for the subsequent acquisition function optimization step, guiding the selection of the most promising design points for further exploration.

[0087] To further improve optimization efficiency, this paper also proposes incorporating domain knowledge from the knowledge graph into the initialization phase of the SVR model. This allows for faster convergence to the global optimal solution by setting a reasonable initial parameter range and avoiding searching unnecessary regions. The knowledge graph not only provides valuable information about the relationships between circuit components but also helps identify design parameter combinations that, based on historical data and engineering experience, are more likely to produce excellent results.

[0088] In some embodiments of the present application, the objective function of the SVR model is The following formula (5) is satisfied: (5); In formula (5), is the weight vector, represents the bias term, represents the number of slack variables, Indicates the slack variables; is a regularization parameter used to control the complexity of the model.

[0089] In some embodiments of the present application, the kernel function of the SVR model adopts a Gaussian radial basis function (RBF), and the RBF function satisfies the following formula (6): (6); In formula (6), is the width parameter of the kernel function; Is the output value of the kernel function, representing the input sample and The similarity between them. In high-dimensional space, it can be viewed as mapping the original input space to a higher-dimensional space and calculating the inner product of the two points there. The RBF kernel is able to map the original input space to a higher-dimensional space, making it easier to find a linear separation hyperplane in this new space, thereby effectively solving the nonlinear problem in the original space.

[0090] In some embodiments of the present application, reference is made to Figure 3 In step 103, based on the simulation data lookup table, the circuit knowledge graph and the candidate design point set, combined with the model predictive control framework, the reinforcement learning method is executed to obtain the optimal design point of the current circuit. The implementation process of providing the optimal configuration of the current circuit includes but is not limited to the following steps.

[0091] Step 301: Initialize the state space and action space of the reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph, and the candidate design point set.

[0092] The state space describes the current circuit state, including the set of candidate design points and their corresponding performance metrics. The action space describes the adjustable range of actions and their step size limits corresponding to the candidate design point set, with its boundaries constrained by the simulation data lookup table and the circuit knowledge graph.

[0093] Reinforcement learning methods can further fine-tune circuit design parameters based on multi-point exploration Bayesian optimization (MPE-BO). Through the dynamic interaction between state, action, and reward, reinforcement learning can continuously explore and optimize the design space, making it particularly suitable for tackling complex multi-objective optimization problems. In the field of circuit design, the state can represent the current design configuration and its performance indicators, the action involves changes in adjustable design parameters, and the reward evaluates the effectiveness of each action based on preset objectives (such as increasing gain, reducing power loss, etc.). This approach enables reinforcement learning to not only discover the optimal solution for a single performance indicator, but also effectively balance multiple conflicting design objectives to find the circuit design solution with the best overall performance. Therefore, the combination of MPE-BO and reinforcement learning provides a powerful new approach to solving complex circuit design problems.

[0094] In step 301, the state space and action space of the reinforcement learning method are initialized based on the simulation data lookup table, the circuit knowledge graph, and the set of candidate design points. The state space is designed to comprehensively describe the current design state of the circuit, including but not limited to the set of candidate design points under consideration and their corresponding performance metrics. This provides a basis for evaluating different design solutions. The action space, on the other hand, defines the range of actions that can be adjusted at these candidate design points and the step size limits, ensuring that the exploration process is both flexible and compliant with practical operational specifications. By combining the boundary conditions provided by the simulation data lookup table and the circuit knowledge graph, the scope of the action space can be effectively limited, ensuring the effectiveness and rationality of the search.

[0095] In step 302, the state space and action space are input into the policy network of the reinforcement learning method, and the optimized parameter set is output in combination with the reward function of the reinforcement learning method. The optimized parameter set is used as the initial parameter search domain of the model predictive control framework.

[0096] The optimized parameter set refers to a set of optimized circuit design parameters that are most likely to improve circuit performance; In step 302, the initialized state and action spaces are input into the reinforcement learning policy network, and a reward function is used to guide the output of an optimized parameter set. The core of this step is to identify the action combinations most likely to improve circuit performance. Based on the given state and action spaces, the policy network predicts the optimal course of action that will lead to improved performance. The output of this optimized parameter set serves as the initial parameter search domain for subsequent optimization phases. This process not only helps narrow the search scope and improve efficiency, but also ensures the directionality of the search, i.e., progress toward the goal of performance optimization.

[0097] Step 303 : Using the model predictive control framework, a multi-step optimization problem model is constructed, and exploration and optimization are performed in the initial parameter search domain to obtain the optimal design point and provide the optimal configuration of the current circuit.

[0098] In step 303, a multi-step optimization problem model is constructed using the Model Predictive Control (MPC) framework. Detailed exploration and optimization are performed within the initial parameter search domain. By predicting the circuit state for multiple future time steps, the system balances long-term performance against constraints, ensuring that the solution that maximizes long-term performance is found while satisfying system constraints. This results in an optimal set of design points and provides the optimal parameter combination for the current circuit configuration. This step emphasizes the importance of decision-making based on future predictions, allowing circuit design to focus not only on immediate performance improvements but also on maximizing overall stability and long-term benefits, providing strong support for achieving high-performance and stable circuit design.

[0099] The significance of model predictive control (MPC) in circuit optimization design lies in that it provides a powerful framework for handling dynamic optimization problems of complex, multivariable systems. By utilizing MPC, the circuit design process can make decisions based on predictions of multiple time steps into the future, which allows for finding solutions that maximize long-term performance while taking into account system constraints. Specifically, in circuit design, MPC can help engineers effectively balance different design objectives (such as gain, power consumption, bandwidth, etc.) while ensuring that various design constraints (such as voltage range, power consumption upper limit, etc.) are met. In addition, combined with simulation data and domain knowledge, MPC can quickly iterate and find the optimal or near-optimal design configuration while ensuring circuit stability and performance, thereby effectively improving design efficiency and quality. Therefore, MPC provides a flexible and efficient method for solving complex circuit design problems, especially for application scenarios that require precise control and optimization.

[0100] In some embodiments of the present application, the current time step in the state space The state vector can be expressed as ,in represents the circuit design parameters, Indicates its corresponding performance indicators, such as gain and power consumption.

[0101] In some embodiments of this application, design rules from the circuit knowledge graph are incorporated into a reward function, which is used to evaluate the quality of actions based on circuit performance. For multi-objective optimization, the reward function may be a weighted sum of multiple objectives (such as gain, power consumption, bandwidth, etc.). When the agent selects parameters that do not meet the design rules, its reward value can be reduced or severely penalized.

[0102] In some embodiments of the present application, the current time step The reward function The following formula (7) is satisfied: (7); In formula (7), Indicates the current time step The gain, Indicates the current time step Power consumption; yes The weight coefficient of yes Weight coefficient; Represents the constraint penalty term, which is used to measure the penalty for violating the design experience rules (such as power consumption limit, voltage range, etc.) to ensure that the circuit design meets all constraints. yes The weight coefficient of .

[0103] This reward function comprehensively considers the requirements of maximizing gain, minimizing power consumption, and adhering to design rules. By assigning different weights to different factors, the priorities among these objectives can be flexibly adjusted based on actual needs. This mechanism enables the reinforcement learning algorithm to effectively identify the optimal circuit configuration that both effectively improves performance and meets all design requirements during the exploration process. Furthermore, utilizing such a reward function encourages the algorithm to discover design solutions that, while slightly deficient in some aspects, are generally more balanced and practical, thereby improving the overall quality and applicability of the final circuit design.

[0104] In some embodiments of the present application, the policy network of the reinforcement learning method adopts a deep neural network (DNN). This measure effectively enhances the algorithm's ability to process complex, high-dimensional data, enabling the system to more accurately identify the optimal design parameters. By utilizing the powerful nonlinear fitting capabilities of DNN, the policy network can learn the complex mapping relationship between input features and output performance from a large amount of historical data and simulation results, thereby effectively guiding the exploration and optimization in the circuit design process. In addition, the hierarchical structure of DNN helps to automatically extract and understand key features in the data, reducing dependence on manual feature engineering, and further improving search efficiency and solution quality. Therefore, using DNN as a policy network not only improves the expressive power and generalization performance of the reinforcement learning model, but also provides strong support for solving complex multi-objective circuit design problems.

[0105] In some embodiments of the present application, the neural network structure of the policy network DNN is specifically as follows.

[0106] First, the input layer of the policy network DNN receives the current time step in the state space The state vector ,in Indicates the current time step The resistance, Indicates the current time step The capacitance, Indicates the current time step The gain, Indicates the current time step power consumption.

[0107] Secondly, the hidden layer of the policy network DNN consists of multiple fully connected layers, and each layer applies the ReLU activation function to introduce nonlinear transformations. Each hidden layer converts the output of the previous layer into the input of the next layer through the weight matrix and bias term. The calculation of the first hidden layer satisfies the following formula (8): (8); In formula (8), represents the output of the first hidden layer, is the weight matrix of the first hidden layer, is the corresponding bias term; the calculation of the second hidden layer satisfies the following formula (9): (9); In formula (9), represents the output of the second hidden layer, is the weight matrix of the second hidden layer, is the corresponding bias term.

[0108] Finally, the output layer of the policy network DNN is usually a linear layer that does not use an activation function or uses a problem-specific activation function (such as commonly used in regression tasks). The calculation of the output layer satisfies the following formula (10): (10); In formula (10), is the set of optimized parameters output by the policy network DNN. The goal of the policy network is to transform the state vector To the optimization parameter set 's mapping.

[0109] In some embodiments of the present application, the training of the policy network is to optimize the network parameters by maximizing the expected cumulative reward, so the deterministic policy gradient is used for training. In the deterministic policy gradient method, the policy gradient updates the parameters of the policy network by optimizing the expectation of the reward function. Given a policy and the reward function , the policy gradient update satisfies the following formula (11): (11); In formula (11), Represents the policy function Parameters The gradient, Indicates that the policy network is based on the current state The output action probability distribution, which means that for each possible action, the policy network will give a probability of performing the action, and the goal is to find the optimal probability distribution that maximizes the expected return; Represents the adoption strategy The expected total return under the target function is obtained by adjusting the parameters To maximize this indicator; Is a given state and actions The action-value function under , which measures the expected value of the long-term reward that can be obtained by taking an action in a specific state. By evaluating the value of different actions, we can understand which actions are more conducive to improving overall performance; For all possible states This emphasizes that the calculation of policy gradients needs to take into account all possible states of the environment. This approach ensures that the obtained gradients can effectively guide the improvement of the policy in various situations.

[0110] In summary, Equation (11) provides a systematic approach to directly optimize the parameters of a policy network in order to find the optimal behavior policy in an unknown environment. This approach avoids directly solving complex dynamic programming problems and instead learns the optimal policy through empirical data from interactions with the environment. It is particularly well-suited for complex and nonlinear decision-making processes, such as multi-objective optimization scenarios like circuit design optimization.

[0111] In some embodiments of the present application, the multi-step optimization problem model satisfies the following formula (12): (12); In formula (12), Indicates that from the current time step The beginning of the future The set of optimized parameters for time steps; Represents a multi-step optimization problem model, indicating that for the current time step The future The minimum cumulative cost of candidate actions in time steps; The time step in the state space is The state vector at time , , represents a state prediction model built based on a simulation data lookup table; The time step is The optimized parameter set when ; Indicates the current time step The objective function of represents the number of constraints, Used to represent the time step The state vector and optimization parameter set at this time violate the The constraint penalty corresponding to the constraint condition is Indicates the The weight coefficient of each constraint condition.

[0112] in, Indicates that from the current time step The beginning of the future The set of optimization parameters for each time step. By optimizing these parameters, we can approach or achieve the design goal as much as possible while satisfying all constraints. The optimization parameters here can be understood as different actions or adjustments taken at different time points.

[0113] also, The time step in the state space is The state vector at time , This means that MPC uses existing simulation data to predict future states, allowing each decision to take into account possible future conditions rather than simply reacting based on the current state. This makes the method well-suited for dealing with complex systems that require consideration of long-term impacts.

[0114] The core concept of MPC is "rolling optimization" or "moving window optimization". At each iteration, MPC recalculates the set of optimization parameters for a period of time in the future based on the current system state. , however, only the first bit in the sequence, i.e. Applied to actual systems, this mechanism allows MPC to make real-time adjustments based on the latest system information, thereby adapting to environmental changes and uncertainties.

[0115] In summary, the core goal of the multi-step optimization problem model is to minimize the future The optimal control strategy is found by accumulating the cost within the time step. The accumulative cost consists of two parts: one is the current time step The objective function , which is used to evaluate the performance after taking a specific action in a specific state. For example, in circuit design, it can be the difference between key performance indicators such as gain and power consumption and the expected target value. The other part is the constraint penalty , which is used to ensure that the solution satisfies all given design constraints.

[0116] In some embodiments of the present application, the objective function It is usually a weighted sum of circuit design objectives (such as gain, power consumption, etc.). For example, the objective function of maximizing gain and minimizing power consumption satisfies the following formula (13): (13); In formula (13), The time step is The gain when The time step is power consumption when .

[0117] In some embodiments of the present application, the constraint penalty amount Used to ensure that the design does not violate constraints. For example, the gain and When there are constraints, the constraint penalty Satisfies the following formula (14): (14); In formula (14), is the maximum limit of gain, This is the maximum limit for power consumption.

[0118] In some embodiments of the present application, after each iteration of the collaborative optimization process of reinforcement learning and MPC, the optimized parameters are verified by invoking a circuit simulation tool to ensure that the optimization objectives (such as gain, bandwidth, and power consumption) are met. If the results meet the expectations, the optimization process ends; if the results do not meet the design objectives, the optimization process continues until the preset maximum number of iterations is reached or the optimal solution is reached. Ultimately, when all optimization objectives are met, the optimized circuit design parameters are output, providing the optimal circuit configuration.

[0119] The reinforcement learning policy network selects actions based on the parameters and performance of the current circuit design, adjusting certain parameters to optimize circuit performance. Using real-time performance evaluation data provided by a simulation data lookup table (LUT), the policy network can more accurately predict the outcome of each action and refine its decision-making strategy through training. LUT data, as part of the input, helps the policy network identify which parameter adjustments will yield higher rewards. Meanwhile, model predictive control (MPC) aims to maximize or minimize specific design metrics, such as gain and power consumption, which typically requires multiple calculations using simulation tools. However, by utilizing the LUT, this technology avoids reliance on simulation calculations at each iteration and instead directly obtains partial circuit performance data from the LUT, accelerating the calculation of the objective function. Specifically, in each MPC optimization step, when evaluating the impact of a set of design parameters on circuit performance, the LUT provides pre-calculated performance data. This data can be used to directly obtain the objective function value (such as gain and power consumption) by looking up the corresponding circuit parameter combinations (e.g., resistor, capacitor, transistor size, etc.). This approach reduces the need for complex simulations and lowers computational costs. Especially when multiple objective function evaluations are required for each control step, the use of the LUT effectively improves the efficiency of the entire optimization process.

[0120] In some embodiments of the present application, the circuit knowledge graph is updated and adjusted according to the collaborative optimization results of reinforcement learning and MPC.

[0121] In summary, the embodiments of the present application provide a circuit optimization method based on model predictive control, which has the following technical effects.

[0122] The circuit optimization method based on model predictive control provided in the embodiments of this application achieves efficient and robust circuit design optimization through the deep integration of knowledge-driven and data-driven approaches. First, a knowledge graph containing circuit design experience documents and simulation data is constructed, defining entities and their associations and design experience rules. Combined with a simulation data lookup table (LUT), SPICE tools are used to pre-generate circuit performance data under different process parameters and store it in tabular form. This provides a priori constraints for the optimization process and avoids frequent calls to time-consuming simulation tools, effectively reducing computational costs.

[0123] During the efficient global exploration and preliminary optimization phase, multi-point exploration Bayesian optimization (MPE-BO) is employed to initialize the search for the feasible domain based on a knowledge graph, narrowing the range of unreasonable parameters. A support vector regression (SVR) surrogate model is used to fit the nonlinear objective function, combined with a multi-point acquisition function to evaluate multiple design points in parallel, breaking through the single-point limitation of traditional Bayesian optimization. Furthermore, a dynamically weighted multi-objective expected improvement function (MOEI) and constraint penalty terms are used to balance conflicts among multiple objectives, such as gain and power consumption, reducing the risk of local optimality and screening a set of candidate design points. Furthermore, leveraging the model predictive control (MPC) framework, a multi-step optimization model is constructed to predict circuit states for multiple future time steps, balancing long-term performance with constraints. A reinforcement learning policy network is then combined with a reward function to dynamically adjust parameters, achieving multi-objective collaborative optimization.

[0124] Finally, this method uses a dynamic update mechanism to iteratively update the knowledge graph, LUT, and SVR model based on the optimization results. This ensures that design rules and simulation data are iterated synchronously, adapting to complex process variations and dynamic environments, and ensuring that optimization decisions are based on the latest information. LUTs reduce the number of simulation calls, while MPE-BO accelerates convergence, improving overall optimization efficiency. The knowledge graph constraints combined with MPE-BO avoid local optimality traps, while the MOEI function quantifies the potential for multi-objective improvements. The MPC framework dynamically balances conflicting metrics such as gain, power consumption, and bandwidth. This approach is suitable for highly complex analog circuit design, rapidly generating optimal parameter combinations under strict constraints, and effectively improving design quality and robustness.

[0125] Secondly, refer to Figure 4 , an embodiment of the present application provides a circuit optimization system based on model predictive control, including a knowledge-driven module, a preliminary Bayesian optimization module and an advanced collaborative optimization module.

[0126] The knowledge-driven module is used to construct a circuit knowledge graph and simulation data lookup table based on circuit design experience documents and circuit simulation data; circuit simulation data includes simulation data of the current circuit and simulation data of historical circuits; the circuit knowledge graph is used to define entities, inter-entity relationships and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination.

[0127] The preliminary Bayesian optimization module is used to initialize the search feasible domain of the design point based on the circuit knowledge graph and simulation data lookup table, and perform multi-point exploration Bayesian optimization to obtain the set of candidate design points for the current circuit.

[0128] The advanced collaborative optimization module is used to execute reinforcement learning methods based on the simulation data lookup table, circuit knowledge graph and candidate design point set, combined with the model predictive control framework, to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

[0129] Secondly, refer to Figure 5 An embodiment of the present application provides a circuit optimization device based on model predictive control, comprising a processor and a memory. The memory is used to store a program. When the program is executed by the processor, the processor implements the aforementioned circuit optimization method based on model predictive control.

[0130] In addition, an embodiment of the present application provides a computer medium storing a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to implement the aforementioned circuit optimization method based on model predictive control.

[0131] Similarly, the contents of the above method embodiments are applicable to system embodiments, device embodiments and medium embodiments. The functions specifically implemented by the system embodiments, device embodiments and medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0132] In some optional embodiments, the functions / operations mentioned in the block diagram may not occur in the order mentioned in the operation schematic diagram. For example, depending on the functions / operations involved, the two boxes shown in succession may actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiments presented and described in the flow chart of the present application are provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operations and logical flows presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0133] In addition, although the present application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present application. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the routine skills of an engineer. Therefore, a person skilled in the art will be able to implement the present application as set forth in the claims using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present application, which is determined by the full scope of the appended claims and their equivalents.

[0134] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several programs that enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the various embodiments of the method of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0135] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable programs for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can retrieve and execute a program from a program execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, a program execution system, apparatus, or device.

[0136] More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting, or processing it in a suitable manner as necessary, and then storing it in a computer memory.

[0137] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application-specific integrated circuit having suitable combinational logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0138] In the above description of this specification, reference to the terms "one embodiment / implementation," "another embodiment / implementation," or "certain embodiments / implementations" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in the embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0139] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0140] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A circuit optimization method based on model predictive control, characterized in that: The steps include: Constructing a circuit knowledge graph and a simulation data lookup table based on circuit design experience documents and circuit simulation data; the circuit simulation data includes simulation data of the current circuit and simulation data of historical circuits; The circuit knowledge graph is used to define entities, relationships between entities, and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; Initializing the search feasible region of the design point according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a set of candidate design points for the current circuit; According to the simulation data lookup table, the circuit knowledge graph and the set of candidate design points, in combination with the model predictive control framework, a reinforcement learning method is executed to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

2. The circuit optimization method based on model predictive control according to claim 1, characterized in that: Initializing the search feasible region of the design point based on the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a set of candidate design points for the current circuit, including: Sampling data from the simulation data lookup table and training to obtain a proxy model; the proxy model fits the nonlinear simulation results of the analog circuit design by constructing an objective function; Initializing a search feasible region for the design point according to the circuit knowledge graph and the simulation data lookup table; By utilizing the multi-point acquisition function and combining the agent model, a multi-point exploration Bayesian optimization is performed in the search feasible domain to explore and screen out a set of candidate design points for the current circuit.

3. The circuit optimization method based on model predictive control according to claim 2, characterized in that: The multi-point acquisition function satisfies the following formula: ； in, represents the multi-point acquisition function, represents the number of design points in the candidate design point set, Indicates the design points; Indicates the The weighted multi-objective expectation improvement function corresponding to the design points satisfies the following formula: ； in, represents the number of objective functions of the surrogate model, Indicates the The objective function, Indicates the The design point corresponds to the The objective function value, express The corresponding weight coefficient is express The current optimal value, represents the mathematical expectation function.

4. The circuit optimization method based on model predictive control according to claim 3, characterized in that: The weighted multi-objective expectation improvement function further includes a constraint penalty term, which is obtained according to the design experience rule; the weighted multi-objective expectation improvement function satisfies the following formula: ； in, represents the number of constraints, Indicates the The design point for The penalty for violating the constraint, Indicates the The weight coefficient of each constraint condition.

5. The circuit optimization method based on model predictive control according to claim 1, characterized in that: The method of executing a reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph, and the set of candidate design points in combination with a model predictive control framework to obtain an optimal design point for the current circuit and provide an optimal configuration for the current circuit includes: Initializing the state space and action space of the reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph, and the set of candidate design points; the state space is used to describe the current state of the circuit, including the set of candidate design points and their corresponding performance indicators; the action space is used to describe the adjustable action range and its step size limit corresponding to the set of candidate design points, with its boundaries constrained by the simulation data lookup table and the circuit knowledge graph; Inputting the state space and the action space into the policy network of the reinforcement learning method, combining the state space and the action space with the reward function of the reinforcement learning method, and outputting an optimized parameter set; the optimized parameter set is a set of optimized circuit design parameters that are most likely to improve circuit performance; and using the optimized parameter set as an initial parameter search domain of the model predictive control framework; The model predictive control framework is used to construct a multi-step optimization problem model, and exploration and optimization are performed in the initial parameter search domain to obtain the optimal design point and provide the optimal configuration of the current circuit.

6. The circuit optimization method based on model predictive control according to claim 5, characterized in that: The multi-step optimization problem model satisfies the following formula: ； in, Indicates that from the current time step The beginning of the future The set of optimized parameters for time steps; Represents the multi-step optimization problem model, indicating that for the current time step The future The minimum cumulative cost of candidate actions in time steps; The time step in the state space is The state vector at time , , represents a state prediction model constructed based on the simulation data lookup table; The time step is The optimized parameter set when ; Indicates the current time step The objective function of represents the number of constraints, Used to indicate the time step is The state vector and the optimized parameter set at the time violate the The constraint penalty corresponding to the constraint condition is Indicates the The weight coefficient of each constraint condition.

7. The circuit optimization method based on model predictive control according to claim 3, characterized in that: The proxy model is a machine learning model.

8. A circuit optimization system based on model predictive control, characterized in that: It includes knowledge-driven module, preliminary Bayesian optimization module and advanced collaborative optimization module; The knowledge-driven module is used to construct a circuit knowledge graph and a simulation data lookup table based on circuit design experience documents and circuit simulation data; The circuit simulation data includes simulation data of the current circuit and simulation data of the historical circuit; The circuit knowledge graph is used to define entities, relationships between entities, and design experience rules in analog circuit design; the simulation data lookup table is used to store circuit performance indicators corresponding to different design points; each design point corresponds to a circuit design parameter combination; The preliminary Bayesian optimization module is used to initialize the search feasible domain of the design point according to the circuit knowledge graph and the simulation data lookup table, and perform multi-point exploration Bayesian optimization to obtain a set of candidate design points for the current circuit; The advanced collaborative optimization module is used to execute a reinforcement learning method based on the simulation data lookup table, the circuit knowledge graph and the set of candidate design points, combined with a model predictive control framework, to obtain the optimal design point of the current circuit and provide the optimal configuration of the current circuit.

9. A circuit optimization device based on model predictive control, characterized in that: include: processor and memory; The memory is used to store a program; when the program is executed by the processor, the processor implements the circuit optimization method based on model predictive control according to any one of claims 1 to 7.

10. A computer medium storing a program executable by a processor, characterized in that: The program executable by the processor is used to implement the circuit optimization method based on model predictive control according to any one of claims 1 to 7 when executed by the processor.

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