Radiation hardening numerical control oscillator, clock data recovery circuit and equipment

Abstract

The invention discloses an anti-radiation hardening digital controlled oscillator, a clock data recovery circuit and equipment, and the digital controlled oscillator is characterized in that an anti-radiation hardening circuit unit is connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), and comprises a voltage copying unit and a multiplexer; the voltage copying unit is used for copying a control voltage signal output by the digital-to-analog converter DAC, generating a copying voltage signal, sending the copying voltage signal to the multiplexer, and switching the output of the multiplexer from the control voltage signal to the copying voltage signal when the digital-to-analog converter DAC is subjected to single-particle bombardment. The DCO type clock data recovery circuit aims at solving the problem that a traditional DCO type clock data recovery circuit is prone to being affected by single particles when running in a radiation environment, single particle function interruption is generated, and consequently a space task fails, and the radiation hardening capacity of the DCO type clock data recovery circuit running in the radiation environment is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a radiation-hardened digitally controlled oscillator, a clock data recovery circuit and a device. Background Art

[0002] Clock and data recovery (CDR) circuits are core submodules in serial communication interfaces. A common type of CDR circuit is the DCO (Digital-Controlled Oscillator) circuit. A traditional DCO circuit consists of a digital-to-analog converter (DAC), a serial-to-parallel converter (S / P converter), a Bang-Bang phase detector (BBD), and a digitally controlled oscillator (DCO). The latter consists of a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The traditional DCO-based CDR circuit operates as follows: the DAC samples the data and edge information of a high-speed signal. The S / P converter parallelizes the sampled high-speed signal and reduces its rate. The BBD detects the data and edge information and determines whether the clock sampling point is ahead or behind. Finally, negative feedback is used to adjust the clock phase, aligning the clock sampling point with the optimal position in the center of the sampling window, thereby recovering the data and clock. However, traditional DCO-type clock data recovery circuits are easily affected by single-particle events when operating in a radiation environment, resulting in single-particle functional interruptions and causing space mission failures. The most sensitive module is the digital-to-analog converter in the digitally controlled oscillator. Summary of the Invention

[0003] Technical problem to be solved by the present invention: In response to the above-mentioned problems of the prior art, a radiation-hardened numerically controlled oscillator, a clock data recovery circuit and a device are provided. The present invention aims to solve the problem that traditional numerically controlled oscillators are easily affected by single particles when operating in a radiation environment, resulting in single particle function interruption and failure of space missions, and to improve the radiation-hardening capability of numerically controlled oscillators operating in a radiation environment.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: A radiation-hardened digitally controlled oscillator includes a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). A radiation-hardened circuit unit is connected between the DAC and the VCO. The radiation-hardened circuit unit includes a voltage replication unit and a multiplexer (MUX). A control voltage signal Vctr0 output by the DAC is fed into an input pin of the multiplexer (MUX) and an input end of the voltage replication unit. The voltage replication unit is configured to replicate the control voltage signal Vctrl0 and generate a replicated voltage signal Vctrl1, which is fed into another input pin of the multiplexer (MUX). When the DAC is struck by a single particle, the voltage replication unit switches the output of the multiplexer (MUX) from the control voltage signal Vctrl0 to the replicated voltage signal Vctrl1.

[0005] Optionally, the voltage replication unit includes a transmission gate TG, a capacitor C1, an operational amplifier AMP, two comparators COMP1 and COPM2, an exclusive OR gate and a delay module delay. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC is grounded through the transmission gate TG and the capacitor C1 in sequence. The intermediate node between the transmission gate TG and the capacitor C1 serves as the output end of the replicated voltage signal Vctrl1 and is connected to another input pin of the multiplexer MUX and the operational amplifier AMP. The high voltage VH and the low voltage VL are obtained through the operational amplifier AMP and its feedback circuit, and are compared with the control voltage signal Vctrl0 through the comparators COMP1 and COPM2 respectively. The two comparison results are input into the exclusive OR gate to obtain the selection signal S1 of the multiplexer MUX. The selection signal S1 is delayed by the delay module delay and connected to the control end of the transmission gate TG.

[0006] Optionally, the feedback circuit includes a switch and three resistors connected in series between a power supply and a ground, one end of the switch is connected to the power supply, and the other end is connected to the ground through three resistors in sequence, the control end of the switch is connected to the output end of the operational amplifier AMP, and the middle node between the first resistor of the three resistors and the switch serves as the output end of the high voltage VH, the middle node of the first two resistors serves as the negative feedback output end connected to the negative feedback input end of the operational amplifier AMP, and the middle node of the last two resistors serves as the output end of the low voltage VL.

[0007] Optionally, the resistance ratio of the three resistors is 1:1:79, and the resistor with a larger resistance value is located on the ground side, so that the voltage of the high voltage VH is 81 / 80×Vctrl1, and the voltage of the low voltage VL is 79 / 80×Vctrl1, where Vctrl1 is the replica voltage signal.

[0008] In addition, the present invention also provides a clock data recovery circuit, comprising a clock data recovery circuit unit with a digitally controlled oscillator, wherein the digitally controlled oscillator is the aforementioned radiation-hardened digitally controlled oscillator.

[0009] Optionally, the clock data recovery circuit unit includes a digital-to-analog converter, a serial-to-parallel module and a Bang-Bang phase detector. The output clock clock of the digitally controlled oscillator serves as the clock of the digital-to-analog converter, so that the digital-to-analog converter samples the data information data and edge information of the high-speed signal. The serial-to-parallel module is used to convert the serial high-sampling signal into a parallel analog signal to achieve signal speed reduction output. The Bang-Bang phase detector is used to perform phase detection on the data information and edge information in the output parallel analog signal to determine whether the sampling point of the clock at this time is ahead or behind, and output the phase detection code to the digitally controlled oscillator.

[0010] In addition, the present invention also provides an electronic device, comprising a device body and a circuit module arranged in the device body, wherein the circuit module comprises the clock data recovery circuit.

[0011] Compared with the prior art, the present invention primarily achieves the following beneficial effects: the present invention implements a radiation-hardened design for a digitally controlled oscillator through a radiation-hardened circuit unit composed of a voltage replicating unit and a multiplexer. The digitally controlled oscillator of the present invention has an radiation-hardened circuit unit connected between a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The radiation-hardened circuit unit includes a voltage replicating unit and a multiplexer. The voltage replicating unit is configured to replicate the control voltage signal output by the digital-to-analog converter (DAC) and generate a replicated voltage signal that is fed into the multiplexer. When the digital-to-analog converter (DAC) is struck by a single particle, the output of the multiplexer is switched from the control voltage signal to the replicated voltage signal to avoid being affected by a single-particle functional interruption. Furthermore, if the voltage replicating unit is struck by a single particle, no matter which voltage signal the multiplexer selects, the signal will not be affected by the single-particle functional interruption. This solves the problem that conventional digitally controlled oscillators are easily affected by single particles when operating in a radiation environment, resulting in single-particle functional interruptions and leading to space mission failures, and improves the radiation-hardened capability of digitally controlled oscillators operating in radiation environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a schematic diagram of the circuit principle of a traditional DCO type clock data recovery circuit.

[0013] Figure 2 Schematic diagram of the circuit principle of a radiation-hardened digitally controlled oscillator in an embodiment of the present invention. DETAILED DESCRIPTION

[0014] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings in the embodiments of the present invention.

[0015] like Figure 2 As shown, the radiation-hardened digitally controlled oscillator of this embodiment includes a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). A radiation-hardened circuit unit is connected between the DAC and the VCO. The radiation-hardened circuit unit includes a voltage replication unit and a multiplexer (MUX). The control voltage signal Vctrl0 output by the DAC is fed into one input pin of the multiplexer (MUX) and an input of the voltage replication unit. The voltage replication unit replicates the control voltage signal Vctrl0 to generate a replicated voltage signal Vctrl1, which is fed into another input pin of the multiplexer (MUX). When the DAC is struck by a single event, the voltage replication unit switches the output of the multiplexer (MUX) from the control voltage signal Vctrl0 to the replicated voltage signal Vctrl1. If the DAC is struck by a single event, the voltage replication unit switches the output of the multiplexer (MUX) from the control voltage signal Vctrl0 to the replicated voltage signal Vctrl1, thereby preventing single-event functional interruptions and providing the digitally controlled oscillator with single-event functional interruption resistance.

[0016] like Figure 2 As shown, the voltage replica unit of this embodiment includes a transmission gate TG, a capacitor C1, an operational amplifier AMP, two comparators COMP1 and COPM2, an XOR gate, and a delay module delay. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC passes through the transmission gate TG and the capacitor C1 in sequence and is grounded. The intermediate node between the transmission gate TG and the capacitor C1 serves as the replica voltage signal Vctr1 and is simultaneously connected to another input pin of the multiplexer MUX and the input end of the operational amplifier AMP. The high voltage VH and the low voltage VL are obtained through the operational amplifier AMP and its feedback circuit, and are compared with the control voltage signal Vctrl0 through the comparators COMP1 and COPM2, respectively. The two comparison results are input into the XOR gate to obtain the selection signal S1 of the multiplexer MUX. The selection signal S1 is delayed by the delay module and then connected to the control end of the transmission gate TG. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC is copied through the transmission gate TG to generate a replica voltage signal Vctrl1 and stored in the capacitor C1. After being fully charged, the transmission gate TG is used as an isolation to ensure that the replica voltage signal Vctrl1 is equal to the control voltage signal Vctrl0 in value, but they are not interconnected.

[0017] like Figure 2As shown, the feedback circuit of this embodiment includes a switch and three resistors connected in series between a power supply and a ground. One end of the switch is connected to the power supply, and the other end is connected to the ground through three resistors in sequence. The control end of the switch is connected to the output end of the operational amplifier AMP, and the middle node between the first resistor of the three resistors and the switch serves as the output end of the high voltage VH. The middle nodes of the first two resistors serve as the negative feedback output end and are connected to the negative feedback input end of the operational amplifier AMP. The middle nodes of the last two resistors serve as the output end of the low voltage VL.

[0018] like Figure 2 As shown, the three resistors in this embodiment have a resistance ratio of 1:1:79, with the larger resistor located on the ground side. This results in the voltage of the high voltage VH being 81 / 80 × Vctrl1, and the voltage of the low voltage VL being 79 / 80 × Vctrl1, where Vctrl1 is a replica voltage signal. The replica voltage signal Vctrl1 is passed through an operational amplifier AMP with unity gain negative feedback to generate comparison levels: the high voltage VH (81 / 80 × Vctrl1) and the low voltage VL (79 / 80 × Vctrl1).

[0019] The voltage replication unit of this embodiment operates as follows: The control voltage signal Vctrl0 output by the digital-to-analog converter (DAC) is replicated through a transmission gate (TG) to generate a replicated voltage signal (Vctrl1) stored in a capacitor (C1). The replicated voltage signal (Vctrl1) is then passed through a unity-gain negative feedback operational amplifier (AMP) to obtain comparison voltages: a high voltage (VH) (81 / 80 × Vctrl1) and a low voltage (VL) (79 / 80 × Vctrl1). High voltage (VH) and low voltage (VL) are compared with the control voltage signal (Vctrl0) by comparators (COMP1 and COPM2), respectively. If the control voltage signal (Vctrl0) is both less than high voltage (VH) and greater than low voltage (VL), both comparators (COMP1 and COPM2) output a logic "1" and a logic "0." If the control voltage signal (Vctrl0) is greater than high voltage (VH) or less than low voltage (VL), both comparators (COMP1 and COPM2) output a logic "1" and a logic "0." The outputs of the two comparators (COMP1 and COPM2) are connected to a two-input exclusive-OR gate. If the two inputs differ, the output selection signal (S1) is a logic "1." The output select signal S1 of the XOR gate is connected to the control port of the multiplexer MUX. When select signal S1 is logic "0," the control voltage signal Vctrl0 is selected for output to the voltage-controlled oscillator (VCO). When select signal S1 is logic "1," the replica voltage signal Vctrl1 is selected for output to the voltage-controlled oscillator (VCO). Simultaneously, select signal S1 is delayed by a delay module to obtain a signal delay select signal S1_delay to prevent compensation of the replica voltage signal Vctrl1 during a single-event effect (SEE) event. In a conventional DCO-type clock data recovery circuit, if the digital-to-analog converter (DAC) is struck by a single event in a radiation environment, the control signal Vctrl output to the high-gain VCO will change, causing a significant change in the clock frequency. After the SEE event ends, the clock frequency slowly recovers. However, due to the large deviation in the initial clock frequency, the clock data recovery circuit is highly likely to converge to an incorrect frequency during the recovery process, causing the clock data recovery circuit to interrupt its function. The radiation-hardened VCO in this embodiment does not prevent this. In the radiation-hardened digitally controlled oscillator of this embodiment, when the digital-to-analog converter (DAC) is struck by a single particle in a radiation environment, the control voltage signal Vctrl0 changes. This causes the voltage value of the control voltage signal Vctrl0 to be greater than VH (or less than VL), and comparators COPM1 and COMP2 output a logic "0" and a logic "1." At this point, the select control signal S1 of the multiplexer MUX changes to a logic "1," and the output voltage of the multiplexer MUX becomes a replica of the voltage signal Vctrl1.When other modules, such as the operational amplifier AMP, comparators COPM1 and COMP2, and logic gates, are bombarded, neither the control voltage signal Vctrl0 nor the replica control signal Vctrl1 is affected. Regardless of which output the multiplexer MUX selects, Vctrl remains unaffected. This shows that the radiation-hardened digitally controlled oscillator of this embodiment, through the radiation-hardened circuit unit composed of the voltage replicator and the multiplexer, implements a radiation-hardened design for the digitally controlled oscillator. This addresses the issue of traditional digitally controlled oscillators being susceptible to single-particle interference when operating in radiation environments, resulting in single-particle functional interruptions and space mission failures. This improves the radiation-hardened capability of digitally controlled oscillators operating in radiation environments.

[0020] In addition, this embodiment further provides a clock data recovery circuit, which includes a clock data recovery circuit unit with a digitally controlled oscillator, wherein the digitally controlled oscillator is a radiation-hardened digitally controlled oscillator. Figure 1 The clock data recovery circuit shown is the same as that shown in the figure. The clock data recovery circuit unit in this embodiment includes a digital-to-analog converter, a serial-to-parallel module and a Bang-Bang phase detector. The output clock clock of the digitally controlled oscillator serves as the clock of the digital-to-analog converter, so that the digital-to-analog converter samples the data information and edge information of the high-speed signal. The serial-to-parallel module is used to convert the serial high-speed sampling signal into a parallel low-speed signal to achieve signal speed reduction output. The Bang-Bang phase detector is used to perform phase detection on the data information and edge information in the output parallel low-speed signal to determine whether the clock sampling point at this time is ahead or behind, and output the phase detection code to the digitally controlled oscillator.

[0021] In addition, this embodiment further provides an electronic device, including a device body and a circuit module disposed in the device body, wherein the circuit module includes the clock data recovery circuit.

[0022] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A radiation-hardened digitally controlled oscillator, comprising a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO), characterized in that: An anti-radiation hardening circuit unit is connected between the digital-to-analog converter DAC and the voltage-controlled oscillator VCO. The anti-radiation hardening circuit unit includes a voltage replication unit and a multiplexer MUX. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC is respectively input to an input pin of the multiplexer MUX and an input end of the voltage replication unit. The voltage replication unit is used to replicate the control voltage signal Vctr0 and generate a replication voltage signal Vctr1, which is input to another input pin of the multiplexer MUX. When the digital-to-analog converter DAC is bombarded by a single particle, the multiplexer MUX switches the output from the control voltage signal Vctrl0 to the replication voltage signal Vctrl1.

2. The radiation hardened digitally controlled oscillator according to claim 1, wherein: The voltage replication unit includes a transmission gate TG, a capacitor C1, an operational amplifier AMP, two comparators COMP1 and COPM2, an XOR gate, and a delay module delay. The control voltage signal Vctrl0 output by the digital-to-analog converter DAC is sequentially connected to the transmission gate TG and the capacitor C1. The intermediate node between the transmission gate TG and the capacitor C1 serves as the replication voltage signal Vctrl1 and is simultaneously connected to another input pin of the multiplexer MUX and the input of the operational amplifier AMP. The high voltage VH and the low voltage VL are obtained through the operational amplifier AMP and its feedback circuit, and are compared with the control voltage signal Vctrl0 through the comparators COMP1 and COPM2, respectively. The two comparison results are input into the XOR gate to obtain the selection signal S1 of the multiplexer MUX. The selection signal S1 is delayed by the delay module and then connected to the control end of the transmission gate TG.

3. The radiation hardened digitally controlled oscillator according to claim 2, wherein: The feedback circuit includes a switch and three resistors connected in series between a power supply and a ground. One end of the switch is connected to the power supply, and the other end is connected to the ground through three resistors in sequence. The control end of the switch is connected to the output end of the operational amplifier AMP, and the middle node between the first resistor of the three resistors and the switch serves as the output end of the high voltage VH. The middle nodes of the first two resistors serve as the negative feedback output end and are connected to the negative feedback input end of the operational amplifier AMP. The middle nodes of the last two resistors serve as the output end of the low voltage VL.

4. The radiation hardened digitally controlled oscillator according to claim 3, wherein: The resistance ratio of the three resistors is 1:1:79, and the resistor with a larger resistance value is located on the ground side, so that the voltage of the high voltage VH is 81 / 80×Vctrl1, and the voltage of the low voltage VL is 79 / 80×Vctrl1, where Vctrl1 is a replica voltage signal.

5. A clock data recovery circuit, comprising a clock data recovery circuit unit with a digitally controlled oscillator, characterized in that: The digitally controlled oscillator is the radiation-hardened digitally controlled oscillator according to any one of claims 1 to 4.

6. The clock data recovery circuit according to claim 5, characterized in that: The clock data recovery circuit unit includes a digital-to-analog converter, a serial-to-parallel module and a Bang-Bang phase detector. The output clock clock of the digitally controlled oscillator serves as the clock of the digital-to-analog converter, allowing the digital-to-analog converter to sample the data information and edge information of the high-speed signal. The serial-to-parallel module is used to convert the serial high-sampling signal into a parallel analog signal to achieve signal speed reduction output. The Bang-Bang phase detector is used to perform phase detection on the data information and edge information in the output parallel analog signal to determine whether the clock sampling point at this time is ahead or behind, and output the phase detection code to the digitally controlled oscillator.

7. An electronic device comprising a device body and a circuit module disposed in the device body, characterized in that: The circuit module includes the clock data recovery circuit according to claim 6.

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