Ferroelectric domain wall memory array structure with gate tube and preparation method thereof
By etching the ferroelectric domain wall memory array structure of the electrical domain volatile interface layer on the surface of the ferroelectric single crystal thin film, the performance bottleneck caused by the separation of the memory cell and the computing cell is solved, and non-volatile storage with high density, low power consumption and high reliability is achieved.
Patent Information
- Application Number
- CN202510623631.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-15
- Publication Date
- 2025-08-22
AI Technical Summary
The performance bottlenecks caused by the physical separation of the storage units of existing ferroelectric memory and the calculation units, and the traditional 1T1C architecture limits the reduction of memory cell size and density improvement.
Using a ferroelectric domain wall memory array structure with its own gate tube, the electric domain volatile interface layer is etched on the surface of the ferroelectric single crystal thin film, and the formation and disappearance of the conductive domain wall are used to distinguish high and low resistance states, non-volatile storage is realized, and the data state is identified by reading the current magnitude.
Improves memory density and integration, reduces power consumption, enhances data reliability, and simplifies the preparation process of gate tubes, supporting three-dimensional integration and non-destructive reading.
Smart Images
Figure CN120529593A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of ferroelectric memory, and in particular relates to a ferroelectric domain wall memory array structure and a preparation method thereof. Background Art
[0002] As society becomes increasingly information-based and automated, massive amounts of data are being generated, placing higher demands on advanced storage technologies. The von Neumann architecture, while legendary in the digital age, has revealed structural flaws in the intelligent era. The physical separation of storage and computing units requires constant data movement between memory, the CPU, and storage, creating a performance-limiting storage barrier. In information storage, integrated storage and computing technologies are crucial for the continued miniaturization of memory.
[0003] Ferroelectric RAM (FeRAM) utilizes ferroelectric materials to generate two distinct polarization orientations under the influence of positive and negative electric fields. This polarization orientation is retained for a long time after power is removed, thereby achieving non-volatile storage of data "0" and "1." Ferroelectric RAM theoretically offers advantages such as nanosecond to picosecond read and write speeds, unlimited read and write cycles, low power consumption, and good compatibility with CMOS technology, making it an ideal storage technology. Currently, commercial ferroelectric memories typically utilize a ferroelectric capacitor and a transistor (1T1C) structure. This architecture utilizes a "charge integration" read mode to identify information, significantly limiting further reductions in memory cell size and preventing increases in device density. To increase device density, a new approach has been developed to utilize the conductivity of ferroelectric domain walls to store information. Unlike the traditional 1T1C architecture of ferroelectric memory, ferroelectric domain wall memory technology controls the high and low resistance states of ferroelectric memory cells by forming erasable conductive domain walls between antiparallel and parallel electrical domains. Data "0" and "1" states are distinguished by reading the current magnitude of the different resistance states, and the retention properties of the conductive domain walls enable non-volatile storage of information. In the data "1" state, a small voltage is applied to read the switching current of the ferroelectric memory cell without loss. Compared to the 1T1C structure, ferroelectric domain wall memory can significantly improve data storage density due to the domain wall width being in the range of a few nanometers. Summary of the Invention
[0004] The object of the present invention is to provide a ferroelectric domain wall memory array structure with a gate transistor having good device performance consistency and high storage capacity, and a preparation method thereof.
[0005] The ferroelectric domain wall memory array structure with a built-in gate transistor provided by the present invention comprises: a ferroelectric single crystal thin film as a basic memory cell; a domain-volatile interface layer prepared by plasma etching is provided on the surface of the ferroelectric single crystal thin film; a metal oxide electrode is provided below the ferroelectric single crystal thin film; and a perovskite substrate or silicon substrate epitaxial strontium titanate is provided below the metal oxide electrode; the ferroelectric single crystal thin film-metal oxide-substrate structure is covered by an inorganic nitrogen / oxide isolation layer; the single crystal thin film covered by the inorganic nitrogen / oxide isolation layer is provided with interconnecting metal through holes, and the inorganic nitrogen / oxide isolation layer is provided with interconnecting metal. The domain-volatile interface layer acts as a gate transistor, effectively preventing cross-interference between ferroelectric memory cells and greatly enhancing data reliability. The read current of the memory cell of the present invention has unidirectional conductivity, which can reduce leakage current and power consumption. No additional gate transistor is required on the memory cell, which can improve the storage density and integration of the memory array.
[0006] Further:
[0007] The ferroelectric domain wall memory array structure has a scale of M×N memory cells, and the numbers of M and N are determined according to needs.
[0008] The material of the ferroelectric single crystal thin film includes but is not limited to ferroelectric materials such as bismuth ferrite, lithium niobate, lithium carbonate, lead zirconate titanate, and hafnium oxide.
[0009] The metal oxide electrode materials include but are not limited to strontium ruthenate (SrRuO3) and its derivatives (such as BaRuO3,
[0010] (Ba, Sr)RuO3) and other electrode materials.
[0011] The perovskite substrate includes but is not limited to perovskite substrates with different crystal planes (100), (110), (111) or with beveled angles, such as strontium titanate and gadolinium scandate, which can be used for epitaxial growth of other oxide films.
[0012] The inorganic nitrogen / oxide isolation layer includes but is not limited to silicon dioxide and silicon nitride.
[0013] The interconnect metal is any one or more of metals such as gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, etc.
[0014] The method for preparing the ferroelectric domain wall memory array structure with a built-in gate transistor provided by the present invention comprises the following specific steps:
[0015] Step 1: Using pulsed laser deposition (PLD) technology, a layer of metal oxide strontium ruthenate is first grown on a perovskite substrate or a silicon substrate epitaxial strontium titanate. Strontium ruthenate serves as the bottom electrode. Then, a ferroelectric single crystal thin film of bismuth ferrite is grown on the strontium ruthenate. Bismuth ferrite serves as the memory cell.
[0016] Step 2: Using ultraviolet lithography to pattern the ferroelectric domain wall memory cell on the surface of the ferroelectric single crystal film, and making overlay marks;
[0017] Step 3: etching the ferroelectric domain wall memory cell using reactive ion etching technology, and then removing the photoresist mask;
[0018] Step 4: using reactive ion etching technology to etch out the domain volatile interface layer on the surface of the ferroelectric domain wall memory unit;
[0019] Step 5: Use ultraviolet lithography technology to photolithograph the bottom electrode interconnection pattern;
[0020] Step 6: Use reactive ion etching technology to complete the bottom electrode interconnection;
[0021] Step 7: Depositing an isolation layer using plasma enhanced chemical vapor deposition technology;
[0022] Step 8: Use ultraviolet lithography technology to photolithography the interconnection through-hole pattern;
[0023] Step nine: using reactive ion etching to form a through hole in the ferroelectric single crystal film and the isolation layer;
[0024] Step 10: Use ultraviolet lithography technology to photolithograph the interconnect metal pattern;
[0025] Step 11: Use physical vapor deposition to deposit interconnect metal to complete the preparation process.
[0026] Further:
[0027] In step 1, the step of growing strontium ruthenate and bismuth ferrite on a strontium titanate substrate by pulsed laser deposition includes:
[0028] (1) epitaxially growing a 5 nm to 50 nm thick strontium ruthenate film on the perovskite substrate or silicon substrate;
[0029] (2) growing a 100 nm to 1 μm thick bismuth ferrite film on the grown strontium ruthenate film;
[0030] (3) Cooling the growing film to room temperature at a rate of 5-30°C / min.
[0031] In step 2, the ultraviolet lithography technique is used to etch out ferroelectric domain wall memory cell patterns including but not limited to square, rectangle, and diamond, with a side length of 2μm-100μm; the overlay marks include but not limited to cross, strip, X, circle, and diamond.
[0032] In steps 3, 4, 6 and 9, the etching gas of the reactive ion etching technology includes but is not limited to NF3, C2F6, Cl2, HBr, O2, CF4, CHF3, and Ar2.
[0033] In steps five and ten, the bottom electrode interconnections and interconnection metal patterns photoetched using ultraviolet photolithography technology include but are not limited to long strips, long strips + square ends, and long strips + round ends.
[0034] In step five, the reactive ion etching technology is used to etch out the volatile interface layer of the ferroelectric domain wall memory unit, and the etching gas includes but is not limited to CF4, CHF3, and Ar2.
[0035] In step eight, the through hole pattern includes but is not limited to circle, square, and rectangle.
[0036] The present invention utilizes reactive ion etching technology to etch the interface layer of a ferroelectric memory cell into a volatile domain cell. After power is removed, the domains in the interface layer return to their initial orientation, disconnecting the conductive domain wall channels in the interface layer. Upon application of a small voltage, the domains in the interface layer flip under the action of a turn-on voltage, reconnecting the conductive domain wall channels in the interface layer. This is similar to the unidirectional conduction function of a diode, allowing the volatile domains in the interface layer to serve as natural selectors in a memory array. This eliminates the need for additional selectors, as is required in memory arrays such as PCRAM and MRAM. This significantly reduces the difficulty of preparing selectors, improves device performance consistency, and resolves compatibility issues between the electrical operations of the selector and the memory cell. Furthermore, it enables multi-layer array stacking, increasing storage capacity. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 This is a schematic structural diagram of the ferroelectric domain wall memory array with built-in gate transistor prepared in Example 1.
[0038] Figure 2 This is a schematic diagram of the ferroelectric domain wall memory with built-in gate transistor prepared in Example 1.
[0039] Figure 3 This is a SEM image of a single primitive ferroelectric domain wall memory in the ferroelectric domain wall memory array with a gate transistor prepared in Example 1.
[0040] Figure 4 This is the IV curve of a single primitive ferroelectric domain wall memory in the ferroelectric domain wall memory array with a gate transistor prepared in Example 1.
[0041] Figure 5 This is an equivalent circuit diagram of the ferroelectric domain wall memory array with built-in gate transistor prepared in Example 1.
[0042] The numbers in the figure are: 01 is the ferroelectric single crystal thin film, 02 is the interface layer with volatile electric domains, 03 is the metal oxide electrode, 04 is the substrate, 05 is the inorganic nitrogen / oxide isolation layer, 06 is the interconnection metal through hole, and 07 is the interconnection metal. DETAILED DESCRIPTION
[0043] The present invention is further described below by way of embodiments in conjunction with the accompanying drawings. The drawings provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention, and other embodiments and features in the embodiments below may be combined with each other without conflict.
[0044] Example 1, a ferroelectric domain wall memory array with a gate transistor, the specific structure is as follows Figure 1 As shown in the figure, from bottom to top, they are: ferroelectric single crystal thin film 01, interface layer with volatile domain 02, metal oxide electrode 03, substrate 04, inorganic nitrogen / oxide isolation layer 05, interconnection metal via 06, and interconnection metal 07. Among them, the interface layer with volatile domain 02 is of atomic level thickness. In order to make the interface layer more clearly represented, Figure 1 Its existence is exaggerated.
[0045] The method for preparing the ferroelectric domain wall memory array with a built-in gate transistor comprises the following specific steps:
[0046] (1) The substrate used for film growth is a SrTiO3 substrate with a 2° bevel angle in the (001) direction. On the substrate surface, a pulsed laser deposition system was used at a temperature of about 600°C and an oxygen pressure of 10Pa, using a 1J / cm 2 20nm strontium ruthenate film was grown at an energy density of 1.5J / cm 2 The energy density of 200nm was used to grow bismuth ferrite film on strontium ruthenate film;
[0047] (2) A square ferroelectric domain wall memory cell pattern is photoetched on the surface of a ferroelectric single crystal thin film using ultraviolet lithography. The memory cell pattern is a 40 μm × 40 μm square, and a cross-shaped overlay mark is made. The ferroelectric domain wall memory array consists of 16 × 16 memory cells.
[0048] (3) Reactive ion etching (RIE) was used to etch the ferroelectric domain wall memory cell, wherein the atmosphere for etching bismuth ferrite was CHF3, the flow rate was 30 sccm, the pressure was 3 Pa, and the power was 90 W;
[0049] (4) Reactive ion etching (RIE) was used to etch the volatile layer on the surface of the ferroelectric domain wall memory cell, wherein the etching atmosphere was CHF3, the flow rate was 40 sccm, the pressure was 5 Pa, and the power was 100 W;
[0050] (5) Using ultraviolet lithography technology to etch the strontium ruthenate bottom electrode interconnection pattern, the bottom electrode interconnection pattern is a long strip covered with bismuth ferrite, and the atmosphere for etching the strontium ruthenate is a mixed atmosphere of CHF3 and Ar2, with a CHF3 flow rate of 20 sccm, an Ar2 flow rate of 20 sccm, a gas pressure of 1 Pa, and a power of 100 W;
[0051] (6) using plasma enhanced chemical vapor deposition technology to deposit an isolation layer, wherein the isolation layer is silicon nitride with a thickness of 200 nm;
[0052] (7) Using ultraviolet lithography technology to etch the interconnection through-hole pattern, the pattern is a 16μm×16μm square;
[0053] (8) Reactive ion etching is used to form through holes in the ferroelectric single-element film and the isolation layer. The atmosphere for etching silicon nitride is CHF3, the flow rate is 30 sccm, the pressure is 1.3 Pa, and the power is 90 W;
[0054] (9) Using ultraviolet lithography technology to photolithograph interconnect metal patterns, the interconnect metal patterns are long strips with square ends;
[0055] (10) Physical vapor deposition is used to deposit interconnect metal, which is 10nm chromium + 100nm gold, to complete the preparation process.
[0056] Figure 2 This is a schematic diagram of the principle of a ferroelectric domain wall memory with its own gate tube. Figure 2 (a) The white arrows indicate the initial polarization direction of the ferroelectric memory cell and the interface layer 02. At this time, no conductive domain wall channel is formed and the entire device is in a high-resistance state. However, it should be noted that this is an example embodiment and the initial polarization direction is not limited to Figure 2 (a) Direction. Figure 2 (b) is to apply a voltage to the ferroelectric memory cell to flip its electric domain (defined as the coercive field voltage V c ), under the action of an external electric field, the electric domains of the volatile interface layer 02 and the ferroelectric single crystal film 01 are both oriented upward, and the conductive domain wall extends from the chromium / gold layer to the strontium ruthenate electrode. After the external electric field is removed, the electric domains of the interface layer are reversed to face downward due to its volatility, while the electric domain direction of the ferroelectric single crystal film 01 remains unchanged, and the conductive domain wall channel of the interface layer 02 is disconnected, as shown in FIG. Figure 2 (c) As shown. When the direction of the electric domain of the interface layer 02 is reversed to face upward (the voltage that causes the direction of the electric domain of the interface layer to reverse to face upward is defined as V on ), the channel of the conductive domain wall will be reconnected, and the entire device will be in a low resistance state and can be operated at a low voltage (defined as V read , where V on <V read <V c ) reads a large current, such as Figure 2 (d) Based on the above phenomenon, the logic state "0" or "1" is identified by the magnitude of the read current; read It is small and only plays the role of flipping the electric domain of the interface layer, and has no effect on the electric domain polarization state of the ferroelectric memory cell, thus realizing non-destructive reading of the current. Figure 3 This is a SEM image of a portion of a ferroelectric domain wall memory array device. The memory cell is 40μm×40μm. The bottom electrode is connected to the interconnect metal by a through hole. At the same time, the interconnect metal interconnects the memory cells on different bottom electrodes. 50 memory cells of the embodiment were randomly selected and subjected to IV testing with a sweep bias from -4V to 4V and then back to -4V. Figure 4 (a) As shown. When the voltage is in the negative direction, the device is not conducting, the device is in a high-resistance state, and the logic state is "0". Only when the voltage increases to between 2.5-4V, the current increases sharply, the device is in a low-resistance state, the memory cell forms a conductive domain wall channel, and the logic state is "1". Figure 4 (b) 50 memory cells randomly selected from the embodiment are subjected to IV test with the scan bias voltage ranging from 0V to 4V and then back to 0V. It can be found that V on The voltage is about 1V, which is due to the volatility of the interface layer domain, playing the role of a natural gate tube, which can effectively suppress the crosstalk current between storage units. read Between V on and V c The scanning process completes the information reading process of the storage unit, that is, non-destructive reading. Based on the above analysis, the volatile interface layer of the domain plays the role of a gate tube, and the formation and disappearance of the conductive domain wall channel can distinguish the high and low resistance states of the device. Its equivalent circuit diagram is shown as follows Figure 5 shown.
[0057] In summary, the present invention discloses a ferroelectric domain wall memory array with built-in gate transistors. This array primarily replaces the additional gate transistors in the array by etching a volatile interface layer of the domains. The formation and disappearance of the conductive domain wall channel distinguishes the high and low resistance states of the device, thereby identifying the logical state "0" or "1" by the magnitude of the read current. This ferroelectric domain wall memory array with built-in gate transistors achieves significant improvements in power consumption, density, and reliability by physically isolating unselected cells, supporting three-dimensional integration, and simplifying control logic.
[0058] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of the present invention. Those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solutions, and should all be included in the scope of the claims of the present invention.
Claims
1. A ferroelectric domain wall memory array structure with a built-in gate transistor, characterized in that: A ferroelectric single crystal film is used as a basic storage unit. The surface of the ferroelectric single crystal film is provided with a volatile interface layer of electric domains prepared by a plasma etching method. A metal oxide electrode is provided below the ferroelectric single crystal film, and a perovskite substrate or a silicon substrate epitaxial strontium titanate is provided below the metal oxide electrode. The ferroelectric single crystal film-metal oxide-substrate structure is covered by an inorganic nitrogen / oxide isolation layer. Interconnecting metal through holes are provided on the single crystal film covered by the inorganic nitrogen / oxide isolation layer, and interconnecting metal is provided on the inorganic nitrogen / oxide isolation layer.
2. The ferroelectric domain wall memory array structure according to claim 1, wherein: The structure scale of the ferroelectric domain wall memory array is M×N memory cells, and the numbers of M and N are determined according to needs.
3. The ferroelectric domain wall memory array structure according to claim 1, wherein: The material of the ferroelectric single crystal thin film is selected from bismuth ferrite, lithium niobate, lithium carbonate, lead zirconate titanate, and hafnium oxide; The metal oxide electrode material is selected from strontium ruthenate and its derivatives; The perovskite substrate is selected from strontium titanate, gadolinium scandate (100), (110), (111) different crystal planes or perovskite substrates with beveled angles that can be used for epitaxial growth of other oxide films; The inorganic nitrogen / oxide isolation layer is selected from silicon dioxide and silicon nitride; The interconnect metal is selected from gold, silver, aluminum, copper, chromium, platinum, titanium, and nickel.
4. The method for preparing a ferroelectric domain wall memory array structure according to claim 1, 2 or 3, wherein: The specific steps are: Step 1: Using pulsed laser deposition technology, a layer of metal oxide strontium ruthenate is first grown on a perovskite substrate or a silicon substrate epitaxial strontium titanate. Strontium ruthenate serves as the bottom electrode. Then, a ferroelectric single crystal thin film of bismuth ferrite is grown on the strontium ruthenate. Bismuth ferrite serves as the storage unit. Step 2: Using ultraviolet lithography to pattern the ferroelectric domain wall memory cell on the surface of the ferroelectric single crystal film, and making overlay marks; Step 3: etching the ferroelectric domain wall memory cell using reactive ion etching technology, and then removing the photoresist mask; Step 4: using reactive ion etching technology to etch out the domain volatile interface layer on the surface of the ferroelectric domain wall memory unit; Step 5: Use ultraviolet lithography technology to photolithograph the bottom electrode interconnection pattern; Step 6: Use reactive ion etching technology to complete the bottom electrode interconnection; Step 7: Depositing an isolation layer using plasma enhanced chemical vapor deposition technology; Step 8: Use ultraviolet lithography technology to photolithography the interconnection through-hole pattern; Step nine: using reactive ion etching to form a through hole in the ferroelectric single crystal film and the isolation layer; Step 10: Use ultraviolet lithography technology to photolithograph the interconnect metal pattern; Step 11: Use physical vapor deposition to deposit interconnect metal to complete the preparation.
5. The preparation method according to claim 4, characterized in that The pulsed laser deposition in step 1 grows strontium ruthenate and bismuth ferrite on a strontium titanate substrate, and the specific steps are: (1) growing a 5 nm to 50 nm thick strontium ruthenate film on a perovskite substrate or a silicon substrate epitaxially coated with strontium titanate; (2) growing a bismuth ferrite film with a thickness of 100 nm to 1 μm on the grown strontium ruthenate film; (3) Cooling the growing film to room temperature at a rate of 5-30°C / min.
6. The preparation method according to claim 4, characterized in that In step 2, the ultraviolet lithography technique is used to etch out the ferroelectric domain wall memory unit, which has a square, rectangle or diamond shape with a side length of 2μm-100μm; the overlay mark is a cross, strip, X, circle or diamond shape.
7. The preparation method according to claim 4, characterized in that In steps 3, 4, 6 and 9, the etching gas of the reactive ion etching technology is selected from NF3, C2F6, Cl2, HBr, O2, CF4, CHF3, and Ar2.
8. The preparation method according to claim 4, characterized in that The bottom electrode interconnection and interconnection metal etched by ultraviolet lithography in steps 5 and 10 are in the shape of a long strip, a long strip + a square end, or a long strip + a round end.
9. The preparation method according to claim 4, characterized in that In step five, the reactive ion etching technology is used to etch out the volatile interface layer of the ferroelectric domain wall memory unit, and the etching gas is selected from CF4, CHF3, and Ar2.
10. The preparation method according to claim 4, characterized in that The through hole pattern in step eight is circular, square or rectangular.