Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps that a substrate is provided, the substrate comprises an SGT device region and a BCD device region which are transversely arranged, and the conduction types of the SGT device region and the BCD device region are different; forming a plurality of deep grooves in the SGT device region and the BCD device region; gate material filling is carried out on the multiple deep grooves, a first voltage-withstanding gate structure and at least one gate filling structure of the SGT device area and a second voltage-withstanding gate structure of the BCD device area are formed, and the first voltage-withstanding gate structure is close to the BCD device area; forming a shield gate structure based on the at least one gate filling structure; and forming a plurality of shallow trench isolation structures arranged at intervals in the BCD device region, wherein the shallow trench isolation structures are located between the first voltage-withstanding gate structure and the second voltage-withstanding gate structure. According to the invention, the process cost of SGT and BCD device integration can be reduced, and the device connection is simplified.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Power transistors and BCD (Bipolar CMOS DMOS) devices are two common semiconductor power devices. The former is primarily used in power electronics to control and process high current, high voltage, and other electrical signals. For example, the new power semiconductor device, the SGT MOSFET (Shielded Gate Trench MOSFET), significantly reduces chip footprint through its vertical structure. Its vertical field oxide layer ensures voltage resistance while increasing the concentration of the drift region, thereby reducing device on-resistance. BCD devices integrate bipolar transistors, CMOS devices, and DMOS devices on a single chip. They combine the high transconductance and strong load driving capability of bipolar transistors, the high integration density and low power consumption of CMOS devices, and the high-voltage and high-current drive capabilities of DMOS devices, making them widely used in various fields.

[0003] In related technologies, power transistor devices and BCD devices are typically integrated on separate chips, connected and communicating via pins and other means. While this approach can achieve the functions of both devices, it has disadvantages such as a large number of pins, complex connections, and a large footprint. To reduce the number of pins and simplify connections, related technologies have attempted to integrate power transistor devices and BCD devices on the same chip. For example, by superimposing the manufacturing process of power transistor devices on a substrate that already has a BCD device, this allows for the integration of both power devices. However, this approach has a complex manufacturing process and is costly. Summary of the Invention

[0004] To solve the above technical problems, the present application discloses, in one aspect, a method for preparing a semiconductor structure, which comprises: Providing a substrate, the substrate comprising a SGT device area and a BCD device area arranged laterally, wherein the SGT device area and the BCD device area have different conductivity types; forming a plurality of deep trenches in the SGT device region and the BCD device region; Filling the plurality of deep trenches with a gate material to form a first voltage-resistant gate structure and at least one gate filling structure in the SGT device region, and a second voltage-resistant gate structure in the BCD device region, wherein the first voltage-resistant gate structure is adjacent to the BCD device region; forming a shield gate structure based on the at least one gate filling structure; A plurality of shallow trench isolation structures arranged at intervals are formed in the BCD device region, and the shallow trench isolation structure is located between the first voltage-resistant gate structure and the second voltage-resistant gate structure.

[0005] In a possible implementation, filling the multiple deep trenches with a gate material to form a first voltage-resistant gate structure and at least one gate filling structure in the SGT device area, and a second voltage-resistant gate structure in the BCD device area includes: forming a first oxide layer on the wall of the deep trench and the surface of the substrate; Depositing a gate material to form a first gate material layer filling the deep trench and covering the first oxide layer; The first gate material layer is thinned to expose the first oxide layer on the surface of the substrate, thereby obtaining the first voltage-resistant gate structure, the gate filling structure, and the second voltage-resistant gate structure isolated by the first oxide layer.

[0006] In a possible implementation manner, thinning the first gate material layer to expose the first oxide layer on the surface of the substrate includes: The first gate material layer is thinned to expose the first oxide layer on the surface of the substrate based on a chemical mechanical planarization process, and the first oxide layer on the surface of the substrate is further thinned to a first thickness.

[0007] In a possible implementation manner, forming a shield gate structure based on the at least one gate filling structure includes: shielding the first voltage-resistant gate structure and the second voltage-resistant gate structure; Performing an etch-back process on each of the gate filling structures to obtain a shielding gate, and forming an isolation oxide layer covering at least an exposed surface of the shielding gate, wherein the isolation oxide layer is continuous with the first oxide layer; A control gate is formed above the shielding gate based on a gate material backfill process, and the shielding gate and the control gate are isolated from each other by the isolation oxide layer and the first oxide layer.

[0008] In a possible embodiment, the shielding gate structure includes a first shielding gate structure and a second shielding gate structure; and performing an etch-back process on each of the gate filling structures to obtain a shielding gate, and forming an isolation oxide layer covering at least an exposed surface of the shielding gate includes: Carving back each of the gate filling structures to form a shielding gate of the first shielding gate structure and an initial shielding gate corresponding to the second shielding gate structure; shielding the shielding gate of the first shielding gate structure and removing the exposed portion of the first oxide layer to expose the unshielded substrate surface, a portion of the deep trench sidewall corresponding to the second shielding gate structure, and a portion of the initial shielding gate; The exposed portion of the initial shielding gate, the exposed deep trench wall and the exposed substrate surface are oxidized to form the isolation oxide layer and the shielding gate of the second shielding gate structure.

[0009] In a possible implementation manner, forming the control gate above the shielding gate based on the gate material backfill process includes: Depositing a gate material to form a second gate material layer that fills the etched-back deep trench and covers the surface of the substrate; thinning the second gate material layer to a second thickness; The thinned second gate material layer is etched to expose the first oxide layer and the isolation oxide layer on the surface of the substrate, thereby obtaining a control gate above the shielding gate.

[0010] In a possible implementation manner, forming a plurality of shallow trench isolation structures spaced apart in the BCD device region includes: forming a second oxide layer at least covering the shield gate structure; forming a plurality of shallow trenches spaced apart from each other in the BCD region based on a patterning process; The shallow trenches are filled with an isolation material to form the plurality of shallow trench isolation structures arranged at intervals.

[0011] In a possible implementation manner, forming a second oxide layer at least covering the shield gate structure includes: An oxide layer material is deposited to form a second oxide layer covering the shielding gate structure, the first voltage-resistant gate structure, the second voltage-resistant gate structure and the surface of the substrate.

[0012] In a possible implementation manner, forming a second oxide layer at least covering the shield gate structure includes: A second oxide layer at least covering the control gate of the shielding gate structure is formed by surface oxidation treatment, and the second oxide layer is continuous with the first oxide layer and the isolation oxide layer respectively.

[0013] In a possible implementation manner, after forming a plurality of shallow trench isolation structures spaced apart in the BCD device region, the preparation method further comprises: Doping structures are formed in the SGT device region and the BCD device region based on an ion implantation process. At least a portion of the doping structure in the SGT device region and at least a portion of the doping structure in the BCD device region are formed in the same ion implantation process.

[0014] In a possible implementation manner, before filling the plurality of deep trenches with a gate material, the preparation method further includes: performing thermal oxidation on the deep trench to form a sacrificial oxide layer on the wall of the deep trench; The sacrificial oxide layer is removed to expose the trench walls of the deep trenches, and the step of filling the multiple deep trenches with gate materials is performed.

[0015] In another aspect, the present application discloses a semiconductor structure, comprising: A substrate comprising a laterally arranged SGT device region and a BCD device region, wherein the SGT device region and the BCD device region have different conductivity types; A plurality of deep trenches are distributed in the SGT device area and the BCD device area; A first voltage-resistant gate structure is located in a deep trench of the SGT device region; at least one shield gate structure located in the deep trench of the SGT device region; A second voltage-resistant gate structure is located in the deep trench of the BCD device region; A plurality of shallow trench isolation structures are located in the BCD device region and arranged at intervals, wherein the shallow trench isolation structure is located between the first voltage-resistant gate structure and the second voltage-resistant gate structure.

[0016] In a possible embodiment, the shield gate structure includes a control gate and a shield gate, and the control gate and the shield gate are isolated by a continuous first oxide layer and an isolation oxide layer, the first oxide layer is located on a portion of the trench wall of the deep trench, and the isolation oxide layer is located on a portion of the trench wall of the deep trench, and is located between the control gate and the shield gate.

[0017] In a possible implementation manner, the semiconductor structure further includes: The second oxide layer at least covers the shielding gate structure; the second oxide layer is a deposition layer or an oxide layer formed by oxidizing the shielding gate structure.

[0018] In another aspect, the present application further discloses an integrated circuit, which includes the above-mentioned semiconductor structure.

[0019] In another aspect, the present application further discloses an electronic device, which includes the above-mentioned semiconductor structure.

[0020] Based on the above technical solution, this application has the following beneficial effects: The technical solution of the present application provides a laterally arranged SGT device area and a BCD device area of ​​different conductivity types in a substrate to facilitate modular integration of the SGT and BCD devices and provide a structural basis for internal communication connections between modules. This not only reduces the number of pins and simplifies connections, but also saves chip space and improves the integration, reliability, and stability of the integrated circuit. During the device integration and preparation process, multiple deep trenches are formed in the SGT and BCD device areas, and the multiple deep trenches are filled with gate material to form a first voltage-resistant gate structure and at least one gate filling structure in the SGT device area, and a second voltage-resistant gate structure in the BCD device area. A shielding gate structure is then formed based on the at least one gate filling structure. Based on the modularization of the SGT and BCD devices, the gate filling structures required in the two device areas can be formed through one-time trench etching and filling to facilitate subsequent gate preparation. Not only does this not add additional complex processes, but it also integrates the common processes of the two devices, further simplifying the process and reducing preparation costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in an exemplary embodiment of the present application; Figure 2-19 A schematic cross-sectional view of a semiconductor structure during a preparation process provided in an embodiment of the present application; Figure 20 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present application; Figure 21 A schematic cross-sectional view of another semiconductor structure provided in an embodiment of the present application; The following is a supplementary description of the accompanying drawings: 100-substrate, 101-SGT device area, 102-BCD device area, 103-epitaxial layer, 104-substrate layer, 201-first mask layer, 201a-pad oxide layer, 201b-hard mask layer, 202-deep trench, 203-sacrificial oxide layer, 204-first oxide layer, 205-first gate material layer, 206-first voltage-resistant gate structure, 207-gate filling structure, 208-second voltage-resistant gate structure, 209-shielding gate structure, 209a-first shielding gate structure, 209b-second shielding gate structure, 210-shielding gate, 211-control gate, 212-isolation oxide layer, 213-initial shielding gate, 214-second gate material layer, 215-second oxide layer, 216-photoresist layer, 217-annular spacer, 301-shallow trench, 302-shallow trench isolation structure, 303-second mask layer, 401-doping structure. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0024] References to "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of this application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0025] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between a minimum of 1 and a maximum of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0026] The term "layer" as used in this application refers to a portion of a material that includes an area with a certain thickness. A layer can extend over the entire underlying or superstructure, or can extend over a localized area of ​​the underlying or superstructure. In addition, a layer can be an area of ​​a homogeneous or heterogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a profiled surface. A layer can include multiple layers. For example, a substrate can include multiple sublayers, etc., and can be of the same or different materials.

[0027] It should be understood that the definitions of “consistent” and “vertical” used in this application refer to basic consistency or basic verticality that satisfies process errors, and do not refer to absolute consistency or absolute verticality in the physical sense.

[0028] It should be understood that the "plane" used in this application, such as "first plane", "second plane", etc., refers to the XY plane of the base or substrate structure, corresponding to the XY plane of the semiconductor structure, "in-plane direction", "lateral" refers to the direction parallel to the XY plane, "thickness direction", "trench depth direction" or "longitudinal" refers to the Z direction relative to the XY plane.

[0029] The following combination Figure 1-21 The following describes a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 1 It is a flow chart of a method for preparing a semiconductor structure. This specification provides method operation steps such as the embodiments or flow charts, but more or fewer operation steps may be included based on routine or non-creative work. The order of steps listed in the embodiments is only one way of executing the steps among many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order shown in the embodiments or the drawings or in parallel. The preparation method may include S11-S15: S11 : providing a substrate 100 , wherein the substrate 100 includes a SGT device region 101 and a BCD device region 102 arranged laterally, and the SGT device region 101 and the BCD device region 102 have different conductivity types.

[0030] Specifically, the substrate 100 is a semiconductor base capable of processing semiconductor devices. Exemplarily, the constituent material of the substrate 100 can be at least one of the following: silicon, a material containing silicon (such as a III-V compound semiconductor material of gallium arsenide (GaAs)), at least one of silicon on insulator (SOI), or other types of semiconductor materials capable of forming the substrate 100.

[0031] In possible embodiments, substrate 100 may be a continuous structure, such as a wafer substrate, or may include a substrate layer 104 and an epitaxial layer 103. The epitaxial layer 103 may be formed through an epitaxial growth process. It may be an epitaxial layer 103 homogeneous with the substrate layer 104, such as one that continues to grow along the lattice direction of the substrate layer 104 to form the epitaxial layer 103, or a heteroepitaxial layer 103. Specific process conditions, such as the growth temperature, may be the same as those of existing processes or may be adaptively adjusted. The epitaxial layer 103 may be formed through chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. Exemplary materials for the epitaxial layer 103 may include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), or other materials that can be epitaxially grown or deposited on the substrate layer 104 and that can be processed in the device region. In a possible implementation, reference Figure 2 , the SGT device region 101 and the BCD device region 102 may be formed in the epitaxial layer 103 .

[0032] Specifically, the SGT device region 101 is a substrate region for forming the SGT device and has a first conductivity type. The BCD device region 102 is a substrate region for forming the BCD device and has a second conductivity type. In a possible implementation, the SGT device region 101 and the BCD device region 102 are adjacent to each other to facilitate the fabrication of a communication structure between the two devices. In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. For example, the SGT device region 101 is an N-type deep well region, and the BCD device region 102 is a P-type deep well region.

[0033] S12 : forming a plurality of deep trenches 202 in the SGT device region 101 and the BCD device region 102 .

[0034] Specifically, refer to Figure 5 Multiple deep trenches 202 are laterally distributed across the SGT device region 101 and the BCD device region 102 and are formed based on a patterned etching process. In a possible embodiment, a first mask layer 201 is formed on the substrate 100, spanning the SGT device region 101 and the BCD device region 102. The first mask layer 201 is patterned to form etching windows to expose substrate regions corresponding to the deep trenches 202 in the SGT device region 101 and the BCD device region 102. Subsequently, the deep trenches 202 are etched using the first mask layer 201 as an etch barrier to form the multiple deep trenches 202.

[0035] Specifically, the first mask layer 201 covers at least the active area (AA) of the SGT device region 101 and the active area of ​​the BCD device region 102. Figure 3 The first mask layer 201 includes a pad oxide layer 201a located on the surface of the substrate and a hard mask layer 201b located on the pad oxide layer 201a. The pad oxide layer 201a is used to isolate and protect the substrate surface to avoid contamination of the substrate surface and reduce the stress of the hard mask layer 201b. The pad oxide can be formed on the substrate 100 by thermal oxidation or deposition process. Optionally, the material of the pad oxide layer 201a can include but is not limited to silicon dioxide. The hard mask layer 201b can be used for pattern transfer and to improve the accuracy of patterned etching. It can be formed by a deposition process. Optionally, the material of the hard mask layer 201b can include at least one of silicon nitride, titanium nitride, silicon dioxide, etc., or can also be other materials that can achieve pattern transfer. In one embodiment, the pad oxide layer 201a is a silicon oxide layer formed by thermal oxidation treatment, and the hard mask layer 201b is a deposited silicon dioxide layer.

[0036] Optionally, the deposition process can be implemented using a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPECVD), subatmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other types of chemical vapor deposition processes.

[0037] Specifically, the patterning process of the first mask layer 201 can specifically include: coating a photoresist on the first mask layer 201, performing a patterned exposure process on the photoresist, and etching the first mask layer 201 using the patterned photoresist as an etch barrier to form an etching window. Optionally, the deep trench 202 can be etched using a wet etching process, such as using phosphoric acid as the wet etching solution, or a dry etching process, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation, such as plasma etching using a mixture of C4F8 and O2.

[0038] It is understood that the multiple deep trenches 202 in the SGT device region 101 and the BCD device region 102 can be formed simultaneously in the same etching process, thereby integrating the trench etching steps of the two devices and reducing process costs. Alternatively, if the deep trenches 202 corresponding to the shield gate structure 209 and the deep trenches 202 corresponding to the surge gate structure (the first surge gate structure 206 and the second surge gate structure 208) are of different sizes, the deep trenches 202 of the shield gate structure 209 and the deep trenches 202 of the surge gate structure can be formed separately based on different patterned etching processes, such as first forming the deep trenches 202 of the shield gate structure 209 and then forming the deep trenches 202 of the surge gate structure.

[0039] In a possible implementation manner, the width of the deep trench 202 of the shield gate structure 209 is 0.4 μm-0.6 μm, preferably 0.5 μm.

[0040] S13 : Filling the multiple deep trenches 202 with gate material to form a first voltage-resistant gate structure 206 and at least one gate filling structure 207 in the SGT device area 101 , and a second voltage-resistant gate structure 208 in the BCD device area 102 . The first voltage-resistant gate structure 206 is adjacent to the BCD device area 102 .

[0041] Specifically, after forming a plurality of deep trenches 202, the first mask layer 201 is removed, and each deep trench 202 is filled with a gate material, and the gate materials in each deep trench 202 are isolated from each other. Figure 8 The first voltage-sustaining gate structure 206 is located between each gate filling structure 207 and the BCD device area 102, and is disposed adjacent to the BCD device area 102. The gate filling structure 207 is used to form a shielding gate structure 209. The second voltage-sustaining gate structure 208 is located in the BCD device area 102, and the active area of ​​the BCD device is disposed between the first voltage-sustaining gate structure 206 and the second voltage-sustaining gate structure 208.

[0042] In a possible implementation, reference Figure 4 , before S13, the preparation method further includes S21-S22: S21: performing thermal oxidation treatment on the deep trench 202 to form a sacrificial oxide layer 203 located on the wall of the deep trench; S22 : removing the sacrificial oxide layer 203 to expose the trench walls of the deep trenches 202 , and performing the step of filling the plurality of deep trenches 202 with gate materials in S13 .

[0043] Specifically, before removing the first mask layer 201, the exposed deep trench walls can be thermally oxidized to oxidize the base material into a sacrificial oxide layer 203 of a certain thickness. The sacrificial oxide layer 203 is then removed by wet or dry etching, allowing subsequent gate structure fabrication to proceed. The process steps of forming and removing the sacrificial oxide layer 203 can remove trench wall defects formed during the etching of the deep trench 202, flattening the trench walls and facilitating subsequent gate structure fabrication.

[0044] In a possible implementation, reference Figure 6-8 , S13 may specifically include S131-S133: S131: forming a first oxide layer 204 on the wall of the deep trench 202 and the surface of the substrate; S132: depositing a gate material to form a first gate material layer 205 filling the deep trench 202 and covering the first oxide layer 204; S133 : thinning the first gate material layer 205 to expose the first oxide layer 204 on the substrate surface, thereby obtaining a first voltage-resistant gate structure 206 , a gate filling structure 207 , and a second voltage-resistant gate structure 208 isolated by the first oxide layer 204 .

[0045] Specifically, the first oxide layer 204 may be formed based on a deposition process, referring to Figure 6 The first oxide layer 204 is a continuous film layer covering the deep trench wall, the substrate surface of the SGT device area 101 and the substrate surface of the BCD device area 102, and part of it can be used as the field oxide layer of the SGT device. The material of the first oxide layer 204 can be, but is not limited to, silicon dioxide. Then, refer to Figure 7 , a gate material is deposited to form a first gate material layer 205 , and the material of the first gate material layer 205 may include but is not limited to polysilicon.

[0046] Specifically, the first gate material layer 205 covering the substrate surface can be chemically mechanically planarized to remove the gate material covering the first oxide layer 204, thereby obtaining a first voltage-resistant gate structure 206, a gate filling structure 207 and a second voltage-resistant gate structure 208 that are isolated from each other and flush with the first oxide layer 204.

[0047] In some embodiments, reference Figure 8, the first gate material layer 205 is thinned with the first oxide layer 204 as a stop layer, that is, the thinning is stopped after the first oxide layer 204 is exposed. In other embodiments, referring to Figure 9 S133 may specifically include S1331: thinning the first gate material layer 205 to expose the first oxide layer 204 on the substrate surface using a chemical mechanical planarization process, and further thinning the first oxide layer 204 on the substrate surface to a first thickness to reduce the oxide layer thickness on the substrate surface, thereby reducing the step difference between the first voltage-resistant gate structure 206, the second voltage-resistant gate structure 208, and other device regions during subsequent fabrication, thereby planarizing the surface of the SGT device region 101 and the BCD device region 102. In one embodiment, the first oxide layer 204 may be thinned to half its original thickness. In one embodiment, the first thickness may be 900-1200 Å.

[0048] S14 : forming a shielding gate structure 209 based on the at least one gate filling structure 207 .

[0049] Specifically, refer to Figure 16 The shield gate structure 209 specifically includes a control gate 211 located at the top of the trench and a shield gate 210 located at the bottom of the trench. The control gate 211 is used to control the channel conduction and cutoff of the SGT device, and the shield gate 210 is used to adjust the electric field distribution in the channel.

[0050] In a possible implementation, reference Figure 10-16 , S14 may include S141-S143: S141: shielding the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208; S142: performing an etch-back process on each gate filling structure 207 to obtain a shielding gate 210, and forming an isolation oxide layer 212 covering at least the exposed surface of the shielding gate 210, wherein the isolation oxide layer 212 is continuous with the first oxide layer 204; S143 : forming a control gate 211 above the shielding gate 210 based on a gate material backfill process. The shielding gate 210 and the control gate 211 are isolated from each other by the isolation oxide layer 212 and the first oxide layer 204 .

[0051] Specifically, refer to Figure 10, the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208 are shielded by a photoresist layer 216, and a photoresist can be coated on the surface of the substrate to expose the photoresist area except for the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208 to expose each gate filling structure 207 and the substrate surface. Then, the gate filling structure 207 is etched back to remove part of the gate filling structure 207. The remaining part of the gate filling structure 207 serves as the shielding gate 210. The etching depth is determined based on the trench structure and electric field distribution requirements of the SGT device. Optionally, the etching back process can be implemented based on wet etching or dry etching. The wet etching can be carried out by acid etching, and the dry etching can be carried out by plasma etching.

[0052] Specifically, refer to Figure 16 The isolation oxide layer 212 is formed on the exposed surface of the shielding gate 210 to isolate the shielding gate 210 from the control gate 211. The isolation oxide layer 212 can be formed based on oxide layer deposition or thermal oxidation treatment. Figure 13 The shield gate 210 is thermally oxidized to in-situ form an isolation oxide layer 212 that is continuous with the first oxide layer 204, eliminating the need for additional patterning and masking. This also prevents the problem of excessive oxide thickness caused by oxide deposition. The isolation oxide layer 212 and the first oxide layer 204 form a continuous film layer to cover the shield gate 210, the deep trench walls, and the active area surface, thereby isolating the shield gate 210 and avoiding the adverse effects of film stress, thereby protecting the active area of ​​the substrate 100.

[0053] In a possible embodiment, after forming the shielding gate 210, refer to Figure 12 and Figure 13 , remove the photoresist layer 216 that shields the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208, and then perform oxide layer deposition and / or thermal oxidation treatment to form an isolation oxide layer 212 on the surface of the shielding gate 210, while the surface of the first voltage-resistant gate structure 206 and the surface of the second voltage-resistant gate structure 208 are also covered with an oxide layer to simplify the process.

[0054] Then, after forming the isolation oxide layer 212, the gate material is backfilled by a deposition process to obtain a control gate 211 that fills the deep trench 202 and is electrically isolated from the shielding gate 210. The backfilled gate material may include but is not limited to polysilicon. Figure 14-16 S143 may specifically include: depositing a gate material to form a second gate material layer 214 that fills the back-etched deep trench 202 and covers the surface of the substrate; thinning the second gate material layer 214 to a second thickness; etching the thinned second gate material layer 214 to expose the first oxide layer 204 and the isolation oxide layer 212 on the surface of the substrate to obtain a control gate 211 above the shielding gate 210.

[0055] Specifically, the deposition process of the gate material may include but is not limited to plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. The backfill depth exceeds the depth of the deep trench 202 to form a second gate material layer 214 covering the first oxide layer 204, and the thickness of the second gate material layer 214 is set based on process requirements. Then, based on the chemical mechanical polishing process, the second gate material layer 214 is thinned to a layer thickness reaching a second thickness to facilitate the back etching of the gate material. Then, based on wet etching or dry etching, the thinned second gate material layer 214 is backetched to remove the gate material on the surface of the substrate and expose the oxide layer on the surface of the substrate. The gate material remaining in the deep trench 202 forms the control gate 211 of the shield gate structure 209. Each control gate 211, the control gate 211 and the shield gate 210, and the control gate 211 and the substrate 100 are isolated by the first oxide layer 204 and the isolation oxide layer 212. Thus, by depositing a certain thickness of the second gate material layer 214 and then thinning it, the second gate material layer 214 is planarized before etching to facilitate etching precision control and ensure the control precision of the control gate 211. In one embodiment, the second thickness can be 800-1100 Å, preferably 1000 Å.

[0056] In some embodiments, the control gate 211 and shield gate 210 of each shield gate structure 209 have the same structure (not shown). The shield gate 210 of each shield gate structure 209 is formed simultaneously during the etching back process of the gate fill structure 207, and the isolation oxide layer 212 covers the surface of each shield gate 210. Accordingly, S142 may specifically include: etching back each gate fill structure 207 to form the shield gate 210 of each shield gate structure 209; removing the shielding layer on the first and second voltage-resistant gate structures 206 and 208, and oxidizing the surfaces of the shield gate 210, the first and second voltage-resistant gate structures 206, and 208 to form the isolation oxide layer 212. It is understood that the isolation oxide layer 212 formed in this embodiment serves as a gate oxide layer between the shield gate 210 and the control gate 211, and at least a portion of the first oxide layer 204 serves as a field oxide layer.

[0057] In other embodiments, reference Figure 16 The shielding gate structure 209 includes a first shielding gate structure 209a and a second shielding gate structure 209b. The control gate 211 and the shielding gate 210 of the first shielding gate structure 209a are different from the control gate 211 and the shielding gate 210 of the second shielding gate structure 209b. Accordingly, referring to Figure 11-16S142 may specifically include: etching back each gate filling structure 207 to form a shielding gate 210 of the first shielding gate structure 209a and an initial shielding gate 213 corresponding to the second shielding gate structure 209b; Figure 11-12 , shielding the shielding gate 210 of the first shielding gate structure 209a, and removing the exposed portion of the first oxide layer 204 to expose the unshielded substrate surface, a portion of the deep trench sidewall corresponding to the second shielding gate structure 209b, and a portion of the initial shielding gate 213; Figure 13 The exposed portion of the initial shield gate 213, the exposed deep trench walls, and the exposed substrate surface are oxidized to form an isolation oxide layer 212 and the shield gate 210 of the second shield gate structure 209b. It will be appreciated that in this embodiment, the region of the isolation oxide layer 212 covering the shield gate 210 and the deep trench walls serves as a gate oxide layer, while the region located on the substrate surface serves as a field oxide layer.

[0058] Specifically, the shielding gate 210 of the first shielding gate structure 209a is formed after the gate filling structure 207 is etched back, and then blocked by a photoresist layer 216 formed of a material such as a photoresist, thereby removing the first oxide layer 204 exposed on the surface of the substrate, and removing part of the first oxide layer 204 around the initial shielding gate 213, exposing the upper end of the initial shielding gate 213, as shown in FIG. Figure 12 As shown. Then, the photoresist layer 216 on the shielding gate surface of the first voltage-resistant gate structure 206, the second voltage-resistant gate structure 208, and the first shielding gate structure 209a is removed, and the exposed initial shielding gate 213, the deep trench wall, the substrate surface, the shielding gate 210, the surface of the first voltage-resistant gate structure 206, and the surface of the second voltage-resistant gate structure 208 are in-situ oxidized by thermal oxidation to form an isolation oxide layer 212 and a shielding gate 210 of the second shielding gate structure 209b formed after surface oxidation. In this way, the preparation of shielding gates 210 of different structures is achieved through simple back etching, masking, and in-situ oxidation processes. Combined with the thinning process of the first oxide layer 204 in the aforementioned S1331, the thickness of the first oxide layer 204 retained by masking is made close to the thickness of the isolation oxide layer 212 formed by in-situ oxidation on the substrate surface, while reducing the field oxygen thickness and avoiding the step difference on the substrate surface, thereby optimizing device performance.

[0059] Specifically, refer to Figure 13 and Figure 14 There is an annular spacer 217 between the isolation oxide layer 212 on the shielding gate 210 of the second shielding gate structure 209b and the isolation oxide layer 212 on the wall of the deep trench, and both are continuous with the first oxide layer 204 remaining in the deep trench 202. The control gate 211 fills the top of the shielding gate 210 and the annular spacer 217, forming a plug structure with the shielding gate 210.

[0060] S15 : forming a plurality of shallow trench isolation structures 302 arranged at intervals in the BCD device region 102 . The shallow trench isolation structures 302 are located between the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208 .

[0061] Specifically, after forming the first voltage-resistant gate structure 206 , the second voltage-resistant gate structure 208 and the shielding gate structure 209 based on the deep trench process, the BCD device region 102 is processed based on the shallow trench process to form a plurality of shallow trench isolation structures 302 .

[0062] In summary, by providing a laterally arranged SGT device area 101 and a BCD device area 102 with different conductivity types in the substrate 100, modular integration of SGT devices and BCD devices is facilitated, and a structural basis is provided for internal communication connections between modules. This not only reduces the number of pins and simplifies connections, but also saves chip space and improves the integration, reliability and stability of the integrated circuit. During the device integration preparation process, multiple deep trenches 202 are formed in the SGT device area 101 and the BCD device area 102, and the multiple deep trenches 202 are filled with gate materials to form a first voltage-resistant gate structure 206 and at least one gate filling structure 207 in the SGT device area 101, and a second voltage-resistant gate structure 208 in the BCD device area 102. Then, a shielding gate structure 209 is formed based on the at least one gate filling structure 207. On the basis of the modularization of SGT devices and BCD devices, the gate filling structures 207 required in the two device areas can be formed through one-time trench etching and filling to facilitate subsequent gate preparation. Not only does no additional complex process add, but the common processes of the two devices are integrated, further simplifying the process and reducing the preparation cost.

[0063] In a possible implementation, reference Figure 17-20 , S15 may specifically include S151-S153: S151: forming a second oxide layer 215 at least covering the shield gate structure 209; S152: forming a plurality of shallow trenches 301 spaced apart in the BCD region based on a patterning process; S153 : Filling the shallow trenches 301 with an isolation material to form a plurality of shallow trench isolation structures 302 arranged at intervals.

[0064] Specifically, the second oxide layer 215 covers the control gate 211 to prevent the control gate 211 from being damaged in subsequent processes. Figure 17, S151 may include S1511: depositing an oxide layer material to form a second oxide layer 215 covering the shielding gate structure 209, the first voltage-resistant gate structure 206, the second voltage-resistant gate structure 208 and the substrate surface. In this way, the second oxide layer 215 is formed by oxide layer deposition to achieve gate isolation and protection. Optionally, the deposition process includes but is not limited to plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. Exemplarily, HDPCVD can be used to form the second oxide layer 215, and the material of the second oxide layer 215 can include but is not limited to silicon dioxide.

[0065] In some other embodiments, S151 may include S1512: forming a second oxide layer 215 covering at least the control gate 211 of the shielding gate structure 209 by surface oxidation treatment, wherein the second oxide layer 215 is continuous with the first oxide layer 204 and the isolation oxide layer 212 .

[0066] Specifically, the exposed surface of the control gate 211 is thermally oxidized to form a second oxide layer 215 of a desired thickness, thereby preventing the oxide layer on the substrate from thickening, ensuring the effect of subsequent ion implantation in the active area, and preventing implantation damage to the control gate 211, thereby avoiding IGSS (Gate Reverse Current) leakage problems.

[0067] Specifically, due to the difference between the gate material and the substrate material, the thickness of the second oxide layer 215 formed by thermal oxidation is greater than the thickness of the isolation oxide layer 212 on the substrate surface, achieving better injection protection. The second oxide layer 215 formed by thermal oxidation of the gate material is an ellipsoid with a convex top and / or bottom surface.

[0068] In a possible embodiment, the thickness of the first oxide layer 204 and the isolation oxide layer 212 on the surface of the substrate 100 is not greater than a predetermined thickness, which is 70-130 Å, to improve the ion implantation effect while providing isolation protection. In a preferred embodiment, the thickness of the first oxide layer 204 and the isolation oxide layer 212 on the surface of the substrate is 70-130 Å.

[0069] In a possible implementation, the thickness of the isolation oxide layer 212 on the shielding gate 210 is greater than 100-130 Å, preferably greater than 130 Å, to provide effective isolation protection.

[0070] Specifically, the patterning process of the shallow trench 301 is similar to the patterning process of the deep trench 202. Figure 18A second mask layer 303 can be formed on the surface of the substrate, a photoresist is coated on the second mask layer 303, and the photoresist is patterned to expose a portion of the second mask layer 303. The patterned photoresist is used as an etching barrier layer to etch the second mask layer 303 to form an etching window of the shallow trench 301, such as Figure 19 As shown. Optionally, the shallow trench 301 can be etched using a wet etching process or a dry etching process. The material of the second mask layer 303 can include but is not limited to at least one of silicon nitride, titanium nitride, silicon dioxide, etc. In one example, the second mask layer 303 is a silicon nitride layer.

[0071] Specifically, the isolation material filling can be achieved by at least one deposition process, including but not limited to plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, subatmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, etc. The isolation material can include but is not limited to silicon oxide.

[0072] In a possible implementation, reference Figure 21 After S15, the preparation method further includes S16: forming a doping structure 401 in the SGT device area 101 and the BCD device area 102 based on an ion implantation process, and at least part of the doping structure 401 of the SGT device area 101 and at least part of the doping structure 401 of the BCD device area 102 are formed in the same ion implantation process.

[0073] Specifically, the same type of doping structure 401 in the SGT device region 101 and the BCD device region 102 can be formed in the same ion implantation process. This not only realizes the modular integration of the SGT device and the BCD device, but also integrates the similar process steps of the two devices to simplify the connection and improve the communication performance while simplifying the device manufacturing process and reducing the manufacturing cost. The doping structure 401 may include a well region and a source structure or a drain structure. For example, referring to Figure 21 The P-well region in the active area of ​​the SGT device and the P-well region in the active area of ​​the BCD device can be formed in the same ion implantation process, and the N+ well region in the active area of ​​the SGT device and the N+ well region in the active area of ​​the BCD device can be formed in the same ion implantation process. In one embodiment, the ion implantation process includes at least an ion implantation process and an annealing process. The second oxide layer 215 not only prevents ion implantation of the gate structure, but also reduces the risk of device damage during the annealing process.

[0074] In some embodiments, the SGT device formed in the SGT device region 101 is an SGT MOSFET, so as to further improve the performance of the semiconductor device, reduce the on-resistance, and improve the efficiency and reliability of the device circuit.

[0075] In summary, the above technical solution adopts a modular design, integrates SGT devices and BCD devices into the same chip, and performs a horizontal independent design of different module partitions. The modules can communicate with each other through internal connections, which not only reduces the number of pins and simplifies the connection, but also saves space, improves the integration, reliability and stability of integrated circuits, and is suitable for power electronics, communications, computers and other fields, and has broad application prospects. In addition, the integrated manufacturing process of the present application is relatively simple. Not only does it not require the addition of complex manufacturing steps, but it can also integrate common processes such as deep trench 202 etching, gate structure filling and ion implantation, reducing process complexity and thus reducing manufacturing costs. In addition, the semiconductor structure setting of the present application makes the circuit design flexible, can be designed and adjusted according to needs, and has good designability and scalability.

[0076] The present application also provides a semiconductor structure, which is prepared based on the above-mentioned preparation method. Figure 20 The semiconductor structure specifically includes: a substrate 100 , a plurality of deep trenches 202 , a first voltage-resistant gate structure 206 , at least one shielding gate structure 209 , a second voltage-resistant gate structure 208 and a plurality of shallow trench isolation structures 302 . The substrate 100 includes a laterally arranged SGT device area 101 and a BCD device area 102, and the SGT device area 101 and the BCD device area 102 have different conductivity types; multiple deep trenches 202 are distributed in the SGT device area 101 and the BCD device area 102; a first voltage-resistant gate structure 206 is located in the deep trench 202 of the SGT device area 101; at least one shielding gate structure 209 is located in the deep trench 202 of the SGT device area 101; a second voltage-resistant gate structure 208 is located in the deep trench 202 of the BCD device area 102; multiple shallow trench isolation structures 302 are located in the BCD device area 102 and are arranged at intervals, and the shallow trench isolation structure 302 is located between the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 208.

[0077] Specifically, the shielding gate structure 209 is formed based on the gate filling structure 207 , and the first voltage-resistant gate structure 206 , the second voltage-resistant gate structure 208 and the gate filling structure 207 are formed by filling the plurality of deep trenches 202 with gate materials.

[0078] In a possible embodiment, the shielding gate structure 209 includes a control gate 211 and a shielding gate 210, and the control gate 211 and the shielding gate 210 are isolated by a continuous first oxide layer 204 and an isolation oxide layer 212, the first oxide layer 204 is located on a portion of the trench wall of the deep trench 202, and the isolation oxide layer 212 is located on a portion of the trench wall of the deep trench 202, and is located between the control gate 211 and the shielding gate 210.

[0079] In some embodiments, the isolation oxide layer 212 is formed by a deposition process. In other embodiments, the isolation oxide layer 212 is formed by a thermal oxidation process.

[0080] In a possible embodiment, the shielding gate structure 209 includes a first shielding gate structure 209a and a second shielding gate structure 209b; the peripheral sides of the shielding gate 210 and the peripheral sides of the control gate 211 of the first shielding gate structure 209a are covered by the first oxide layer 204, and the top surface of the shielding gate 210 and the bottom surface of the control gate 211 are separated by an isolation oxide layer 212. The control gate 211 and the shielding gate 210 of the first shielding gate structure 209a are columnar structures arranged opposite to each other; the second shielding gate structure 209 The lower part of the deep trench wall where b is located is covered with the first oxide layer 204, and the upper part is covered with the isolation oxide layer 212. The upper end side of the shielding gate 210 is covered by the isolation oxide layer 212. There is an annular spacer 217 between the isolation oxide layer 212 on the shielding gate 210 and the isolation oxide layer 212 on the deep trench wall, and both are continuous with the first oxide layer 204 remaining in the deep trench 202. The control gate 211 fills the top of the shielding gate 210 and the annular spacer 217, forming a plug structure with the shielding gate 210.

[0081] In a possible implementation, the semiconductor structure further includes a second oxide layer 215 , which at least covers the shield gate structure 209 . The second oxide layer 215 is a deposited layer or an oxide layer formed by oxidizing the shield gate structure 209 .

[0082] Specifically, the thickness of the second oxide layer 215 formed by thermal oxidation is greater than the thickness of the isolation oxide layer 212 on the substrate surface. The second oxide layer 215 formed by thermal oxidation of the gate material is in the shape of an ellipsoid with a convex top and / or bottom surface.

[0083] In a possible embodiment, the semiconductor structure further includes a doping structure 401, referring to Figure 21 At least a portion of the doped structure 401 of the SGT device region 101 and at least a portion of the doped structure 401 of the BCD device region 102 are formed in the same ion implantation process.

[0084] It should be noted that the semiconductor structure embodiment of the present application is implemented based on the semiconductor structure preparation method embodiment, and the two are based on the same inventive concept.

[0085] The embodiment of the present application further provides an electronic device, which includes the semiconductor structure described above. Specifically, the electronic device includes the semiconductor structure and an electronic component connected to the semiconductor structure.

[0086] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product including an electronic device made of the above-mentioned semiconductor structure.

[0087] It should be noted that the order of the embodiments of the present application described above is for descriptive purposes only and does not represent the superiority or inferiority of the embodiments. The above description is of specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0088] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0089] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0090] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a SGT device area and a BCD device area arranged laterally, wherein the SGT device area and the BCD device area have different conductivity types; forming a plurality of deep trenches in the SGT device region and the BCD device region; Filling the plurality of deep trenches with a gate material to form a first voltage-resistant gate structure and at least one gate filling structure in the SGT device region, and a second voltage-resistant gate structure in the BCD device region, wherein the first voltage-resistant gate structure is adjacent to the BCD device region; forming a shield gate structure based on the at least one gate filling structure; A plurality of shallow trench isolation structures arranged at intervals are formed in the BCD device region, and the shallow trench isolation structure is located between the first voltage-resistant gate structure and the second voltage-resistant gate structure.

2. The preparation method according to claim 1, characterized in that Filling the plurality of deep trenches with gate materials to form a first voltage-resistant gate structure and at least one gate filling structure in the SGT device area, and a second voltage-resistant gate structure in the BCD device area includes: forming a first oxide layer on the wall of the deep trench and the surface of the substrate; Depositing a gate material to form a first gate material layer filling the deep trench and covering the first oxide layer; The first gate material layer is thinned to expose the first oxide layer on the surface of the substrate, thereby obtaining the first voltage-resistant gate structure, the gate filling structure, and the second voltage-resistant gate structure isolated by the first oxide layer.

3. The preparation method according to claim 2, characterized in that The thinning of the first gate material layer to expose the first oxide layer on the surface of the substrate comprises: The first gate material layer is thinned to expose the first oxide layer on the surface of the substrate based on a chemical mechanical planarization process, and the first oxide layer on the surface of the substrate is further thinned to a first thickness.

4. The preparation method according to claim 1, characterized in that The forming of the shielding gate structure based on the at least one gate filling structure comprises: shielding the first voltage-resistant gate structure and the second voltage-resistant gate structure; Performing an etch-back process on each of the gate filling structures based on an etch-back process to obtain a shielding gate, and forming an isolation oxide layer covering at least an exposed surface of the shielding gate, wherein the isolation oxide layer is continuous with the first oxide layer; A control gate is formed above the shielding gate based on a gate material backfill process, and the shielding gate and the control gate are isolated from each other by the isolation oxide layer and the first oxide layer.

5. The preparation method according to claim 4, characterized in that The shielding gate structure includes a first shielding gate structure and a second shielding gate structure; performing an etch-back process on each of the gate filling structures to obtain a shielding gate, and forming an isolation oxide layer covering at least an exposed surface of the shielding gate includes: Carving back each of the gate filling structures to form a shielding gate of the first shielding gate structure and an initial shielding gate corresponding to the second shielding gate structure; shielding the shielding gate of the first shielding gate structure and removing the exposed portion of the first oxide layer to expose the unshielded substrate surface, a portion of the deep trench sidewall corresponding to the second shielding gate structure, and a portion of the initial shielding gate; The exposed portion of the initial shielding gate, the exposed deep trench wall and the exposed substrate surface are oxidized to form the isolation oxide layer and the shielding gate of the second shielding gate structure.

6. The preparation method according to claim 4, characterized in that The forming of the control gate above the shielding gate based on the gate material backfill process includes: Depositing a gate material to form a second gate material layer that fills the etched-back deep trench and covers the surface of the substrate; thinning the second gate material layer to a second thickness; The thinned second gate material layer is etched to expose the first oxide layer and the isolation oxide layer on the surface of the substrate, thereby obtaining a control gate above the shielding gate.

7. The preparation method according to any one of claims 1 to 6, characterized in that The plurality of shallow trench isolation structures arranged at intervals in the BCD device region include: forming a second oxide layer at least covering the shield gate structure; forming a plurality of shallow trenches spaced apart from each other in the BCD region based on a patterning process; The shallow trenches are filled with an isolation material to form the plurality of shallow trench isolation structures arranged at intervals.

8. The preparation method according to claim 7, characterized in that The forming of a second oxide layer at least covering the shield gate structure comprises: An oxide layer material is deposited to form a second oxide layer covering the shielding gate structure, the first voltage-resistant gate structure, the second voltage-resistant gate structure and the surface of the substrate.

9. The preparation method according to claim 7, characterized in that The forming of a second oxide layer at least covering the shield gate structure comprises: A second oxide layer at least covering the control gate of the shielding gate structure is formed by surface oxidation treatment, and the second oxide layer is continuous with the first oxide layer and the isolation oxide layer.

10. The preparation method according to any one of claims 1 to 6, characterized in that After forming a plurality of shallow trench isolation structures spaced apart in the BCD device region, the preparation method further includes: Doping structures are formed in the SGT device region and the BCD device region based on an ion implantation process. At least a portion of the doping structure in the SGT device region and at least a portion of the doping structure in the BCD device region are formed in the same ion implantation process.

11. The preparation method according to any one of claims 1 to 6, characterized in that Before filling the plurality of deep trenches with gate material, the preparation method further comprises: performing thermal oxidation on the deep trench to form a sacrificial oxide layer on the wall of the deep trench; The sacrificial oxide layer is removed to expose the trench walls of the deep trenches, and the step of filling the multiple deep trenches with gate materials is performed.

12. A semiconductor structure, characterized in that include: A substrate comprising a laterally arranged SGT device region and a BCD device region, wherein the SGT device region and the BCD device region have different conductivity types; A plurality of deep trenches are distributed in the SGT device area and the BCD device area; A first voltage-resistant gate structure is located in a deep trench of the SGT device region; at least one shield gate structure located in the deep trench of the SGT device region; A second voltage-resistant gate structure is located in the deep trench of the BCD device region; A plurality of shallow trench isolation structures are located in the BCD device region and arranged at intervals, wherein the shallow trench isolation structure is located between the first voltage-resistant gate structure and the second voltage-resistant gate structure.

13. The semiconductor structure according to claim 12, wherein: The shielding gate structure includes a control gate and a shielding gate, wherein the control gate and the shielding gate are isolated by a continuous first oxide layer and an isolation oxide layer, wherein the first oxide layer is located on a portion of the trench wall of the deep trench, and the isolation oxide layer is located on a portion of the trench wall of the deep trench and between the control gate and the shielding gate.

14. The semiconductor structure according to claim 12, wherein: The semiconductor structure further comprises: The second oxide layer at least covers the shielding gate structure; the second oxide layer is a deposition layer or an oxide layer formed by oxidizing the shielding gate structure.

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