Variable composition ternary compound semiconductor alloys, structures and devices

Abstract

The invention discloses an In < x > Al < y > Ga < 1-x-y > N semiconductor structure with a photoelectric element. The photoelectric element is characterized by an epitaxial layer with different in-plane a-lattice parameters and different InN mole fractions. The active region is configured to emit radiation in different wavelength ranges, and is characterized by a strain state that differs from compressive strain by about 1% to 2%. The epitaxial layer is grown on a patterned In < x > Al < y > Ga < 1-x-y > N seed region on a single substrate, wherein the relaxed InGaN growth layer provides a (0001) In < x > Al < y > Ga < 1-x-y > N growth surface characterized by different in-plane a-lattice parameters and different InN molar fractions. The InxAlyGa1-x-yN semiconductor structure can be used in optoelectronic devices, such as in light sources for illumination and in display applications.

Description

[0001] Related applications

[0002] This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Application No. 63 / 436,309, filed on December 30, 2022, which is incorporated herein by reference in its entirety.

[0003] This application is related to U.S. application No. 16 / 689,064 filed on November 19, 2019 (issued as U.S. Patent No. 10,847,625) and PCT International Application No. PCT / US2020 / 061377 filed on November 19, 2020, each of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present invention relates to Indium-Aluminum-Gallium-Nitride (In x Al y Ga 1-x-y N) layer having substantially relaxed device-quality single-crystal relaxed (0001) In x Al y Ga 1-x-y N region, the region having a different in-plane a-lattice parameter; and relates to devices fabricated on a relaxed InGaN layer. Substantially relaxed wurtzite (0001)In x Al y Ga 1-x-y The N region has a value greater than or equal to The in-plane (or "a") lattice parameter of the substantially relaxed (0001)In x Al y Ga 1-x-y The N region is grown on multiple patterned III-nitride seed regions (such as GaN, In x Ga 1-x N, Al y Ga 1-y N、In x Al y Ga 1-x-y N, where x and y are not 0) or related alloy seed regions. During growth, In grown on the patterned seed region x Al y Ga 1-x-y The N relaxes and subsequently coalesces to provide a substantially relaxed (0001) In that can be used as a growth surface for other semiconductor materials and epitaxial layers. x Al y Ga 1-x-y N growth region. Basically relaxed (0001)Inx Al y Ga 1-x-y The N region can be used to fabricate optical and electronic devices used as light sources in systems used in lighting and display applications. Background Art

[0005] Micro light emitting diodes (LEDs) and micro laser based devices are expected to revolutionize the display and lighting industries. However, for displays, dense pixels per inch (PPI) and form factor limitations require multi-color emitters (such as red / green / blue (RGB) pixels) with sizes on the order of microns. This means that the size of each individual emitter must be on the order of a few microns or even submicrons. At this scale, mass transfer of sliced ​​emitters made using multiple wafers, where each wafer has a single color emitter, becomes challenging. Sequential deposition of multiple active regions is an alternative approach, but can lead to quality losses when multiple InGaN active regions with different InN contents grown on GaN are forced to lock to a single in-plane a-lattice parameter, resulting in different strain states. In order to produce high-density multi-wavelength emitters, it is desirable to implement variable composition InGaN with different in-plane a-lattice parameters on the same growth substrate. x Al y Ga 1-x-y N alloy.

[0006] Compound semiconductor materials are typically deposited or grown in a manner that matches the atomic lattice of the growth substrate to avoid the generation of growth defects (such as dislocations). In some cases, it is desirable to change the in-plane a-lattice parameter of the compound semiconductor material to provide materials and / or devices and / or systems with specific characteristics.

[0007] In x Ga 1-x N is currently targeted at GaN-based visible spectrum optoelectronic devices (including, for example, light-emitting diodes (LEDs) emitting blue or violet light, which currently underlie most LED-based lighting and display systems commercialized to date, as well as Blu-Ray TM InGaN is the preferred material for the active layer of violet-emitting laser diodes (LDs), the foundation of the violet-emitting laser diode industry. Today, such devices are manufactured using an InGaN active layer pseudomorphically grown on a gallium nitride (GaN) epitaxial layer. Unfortunately, the crystalline atomic lattice parameter of InGaN is greater than that of GaN, resulting in severe strain and increasingly poor material quality as the InN mole fraction or thickness of the InGaN grown on GaN (InGaN / GaN) increases. This limits the performance of optoelectronic devices based on InGaN / GaN, including, for example, LEDs and LDs.

[0008] To date, attempts to grow high-quality planar relaxed InGaN for device applications have not been commercially successful. Graded layer approaches used in some III-V material systems have attempted to use low-temperature molecular beam epitaxy (MBE) for InGaN. However, these growth conditions result in materials with high defect (e.g., point defect) densities that are difficult to mitigate and result in poor material quality. Similar approaches using the commercially preferred metal organic chemical vapor deposition (MOCVD) for c-plane InGaN are hampered by the lack of a slip system for (polar) c-plane growth, and past attempts to utilize non-polar and semi-polar growth planes have resulted in materials with high defect densities and / or devices requiring non-polar and semi-polar active regions. To reduce crystallographic defects, hydride vapor phase epitaxy (HVPE) has been used to grow thick InGaN layers, but this method is limited in the achievable InN mole fraction and is only applicable to N-polar surfaces, and is therefore not ideal for low-cost manufacturing. Attempts have been made to grow strained InGaN layers that can be exfoliated and bonded to compliant supports to facilitate relaxation, but this approach results in limited lattice expansion and non-planar grooved surfaces. The use of nanopillar or nanorod device structures designed to avoid the strain limitations of conventional heteroepitaxy results in non-planar device geometries that are less suitable for fabrication. Finally, techniques for generating porous GaN materials as compliant substrates for subsequent InGaN growth have been demonstrated, but result in limited lattice expansion and require regrowth after the porosification process, which complicates the process.

[0009] The use of patterning and regrowth has been used to grow high-quality lattice-mismatched heteroepitaxial growth of single-element (e.g., Ge on Si) and binary III-V (e.g., GaAs on Si) zinc-blende semiconductors. However, similar approaches for wurtzite semiconductors and / or ternary alloys (such as InGaN) have not been successful. Summary of the Invention

[0010] According to the present invention, a wurtzite III-nitride crystal semiconductor structure includes:

[0011] a substrate comprising a first substrate region and a second substrate region;

[0012] The first substrate region includes a first (0001) In x1 Al y1 Ga 1-x1-y1 The first In in the N growth zone x1 Al y1 Ga 1-x1-y1 N growth layer;

[0013] The second patterned In layer stacked on the second substrate region x2s Aly2s Ga 1-x2s-y2s GaN seed region;

[0014] A second patterned In stacked on x2s Al y2s Ga 1-x2s-y2s A second InGaAlN growth region including a second (0001) InGaAlN growth layer on the GaN seed region, wherein, x2 Al y2 Ga 1-x2-y2 A second InGaAlN growth region of the second InGaAlN growth layer x2 Al y2 Ga 1-x2-y2 N growth layer, where

[0015] The first (0001) InGaAlN growth region is characterized by a first in-plane a-lattice parameter; x1 Al y1 Ga 1-x1-y1 The second (0001) InGaAlN growth region is characterized by a second in-plane a-lattice parameter;

[0016] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter; x2 Al y2 Ga 1-x2-y2 N growth region is characterized by a second in-plane a-lattice parameter;

[0017] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter;

[0018] 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1

[0019] 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and

[0020] 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

[0021] According to the present invention, a wafer includes a semiconductor structure according to the present invention.

[0022] According to the present invention, an optoelectronic device includes a semiconductor structure according to the present invention.

[0023] According to the present invention, a multicolor optoelectronic device includes a semiconductor structure according to the present invention.

[0024] According to the present invention, a semiconductor device includes a semiconductor structure according to the present invention.

[0025] According to the present invention, a lighting system or a display system includes a semiconductor device according to the present invention.

[0026] According to the present invention, a method of manufacturing a wurtzite group III nitride crystal semiconductor structure includes:

[0027] (a) Depositing a first In stacked on a first substrate region of a substratex1 Aluminum y1 Gallium 1-x1-y1 N growth layer; and

[0028] (b) A second In x2 Al y2 Ga 1-x2-y2 N growth layer deposited on a second substrate region of a substrate, where the second In x2 Al y2 Ga 1-x2-y2 N growth layer is stacked on a second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region,

[0029] wherein,

[0030] The first In x1 Al y1 Ga 1-x1-y1 N growth layer includes a first (0001) In characterized by a first in-plane a-lattice parameter x1 Al y1 Ga 1-x1-y1 N growth region;

[0031] The second In x2 Al y2 Ga 1-x2-y2 N growth layer includes a second (0001) In characterized by a second in-plane a-lattice parameter x2 Al y2 Ga 1-x2-y2 N growth region; and

[0032] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter, wherein,

[0033] 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1

[0034] 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and

[0035] 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

[0036] According to the present invention, a semiconductor structure includes a semiconductor structure manufactured using the method according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Those skilled in the art will understand that the drawings described herein are for illustrative purposes only. The drawings are not intended to limit the scope of the present disclosure.

[0038] Figures 1A to 1EAn example of a process flow provided by the present disclosure for fabricating an InGaN layer with a relaxed InGaN region is shown.

[0039] Figures 2A to 2E An example of a process flow provided by the present disclosure for fabricating an InGaN layer with a relaxed InGaN region is shown.

[0040] Figures 3A to 3E An example of a process flow provided by the present disclosure for fabricating an InGaN layer with a relaxed InGaN region is shown.

[0041] Figures 4A to 4E An example of a process flow provided by the present disclosure for fabricating an InGaN layer with a relaxed InGaN region is shown.

[0042] Figure 5 Examples of positive etch masks having various shapes, sizes, and orientations relative to the (1-100) and (11-20) crystallographic directions of the Group III nitride wurtzite material are shown.

[0043] Figure 6 Shown are various shapes, sizes and relative to the III-nitride wurtzite material GaN or In x Al y Ga 1-x-y Examples of negative etch masks oriented in the (1-100) and (11-20) crystallographic directions of N.

[0044] Figure 7 Shown is the transition of an InGaN lattice characterized by a lattice parameter "a" similar to GaN (solid circles) to a larger relaxed InGaN lattice characterized by a lattice parameter "a'" (hatched circles).

[0045] Figure 8 Examples of LEDs incorporating Group III nitride semiconductor structures provided by the present disclosure are shown.

[0046] 9A to 9D Examples of LEDs incorporating Group III nitride semiconductor structures provided by the present disclosure are shown.

[0047] Figure 10 An example of a laser diode (LD) incorporating a Group III nitride semiconductor structure provided by the present disclosure is shown.

[0048] Figure 11 Examples of lighting devices and systems are shown in which LEDs provided by the present disclosure may be incorporated.

[0049] Figure 12Examples of display devices and systems into which LEDs provided by the present disclosure may be incorporated are shown.

[0050] Figure 13 A cross-sectional view of an example of a Group III nitride semiconductor structure provided by the present disclosure is shown.

[0051] FIG. 14A to FIG. 14B The ranges of the InN mole fraction and the a-lattice parameter of the relaxed (0001) InGaN region according to the peak emission wavelength are shown, respectively.

[0052] Figures 15A to 15F The method for preparing the (0001)In nanostructured carbon nanotubes with relaxed carbon nanotubes provided by the present disclosure is shown. x Al y Ga 1-x- y Relaxed In in the N region x Al y Ga 1-x-y Example of an N-tier process flow.

[0053] 16A to 16F The method for preparing the (0001)In nanostructured carbon nanotubes with relaxed carbon nanotubes provided by the present disclosure is shown. x Al y Ga 1-x- y Relaxed In in the N region x Al y Ga 1-x-y Example of an N-tier process flow.

[0054] Figure 17A and Figure 17B The relaxed (0001)In provided by the present disclosure is shown. x Al y Ga 1-x-y A cross-sectional view of an example of a Group III nitride semiconductor structure of an N region.

[0055] 18A to 18C Shown In x Al y Ga 1-x-y An example of nitrogen gradually growing on the (10-11) facet of a Group III nitride semiconductor to fill the “V-pit” structure.

[0056] Figure 19 Shown In x Al y Ga 1-x-y N gradually grows on the (10-11)GaN seed facet to provide relaxed (0001)In x Al y Ga 1-x-yArea N.

[0057] Figure 20 Shown In x Al y Ga 1-x-y N gradually grows on the (10-11)GaN seed facet to provide relaxed (0001)In x Al y Ga 1-x-y Example of N zone.

[0058] Figure 21 An example of an optoelectronic device provided by the present disclosure is shown, which includes a (0001) In grown on a substrate having different relaxed (0001) In layers stacked on the same growth layer. x Al y Ga 1-x-y Three optoelectronic elements on three different relaxed InGaN growth layers of the N region, the three optoelectronic elements being configured to emit at three different wavelength regions.

[0059] Figure 22 Shown is the relationship between the in-plane a-lattice parameter and the peak emission wavelength for different InGaN compositions deposited at different growth temperatures.

[0060] Figure 23 Epitaxial layers are shown during an intermediate step in the fabrication of a multi-wavelength optoelectronic device provided by the present disclosure.

[0061] Figure 24 An example of an optoelectronic device provided by the present disclosure is shown having three different relaxed In grown on a single growth layer. x Al y Ga 1-x-y Three isolated optoelectronic elements are formed on the N-growth layer, the three isolated optoelectronic elements being configured to emit radiation within different respective wavelength ranges.

[0062] Figure 25 An example of a stacked optoelectronic structure provided by the present disclosure is shown. DETAILED DESCRIPTION

[0063] "Substantially uniform lattice parameter" refers to a semiconductor layer characterized by a local lattice parameter of the semiconductor layer that varies less than 1% relative to an average lattice parameter, such as, for example, less than 0.5% relative to the average lattice parameter, or less than 0.1% relative to the average lattice parameter.

[0064] "Defect density" refers to the density of extended defects (such as dislocations) in a semiconductor layer in a planar view. Defect density can be determined using, for example, etching (and counting etch pit density (EPD)), cathode luminescence for observing and counting dark spots, or atomic force microscopy (AFM) for observing and counting small pits.

[0065] Lattice parameters can be determined using X-ray diffraction (XRD) and reciprocal space map (RSM) analysis. High angle or near-grazing incidence XRD techniques can be used to determine the lattice parameters of upper layers in structures where the lattice parameter may vary as a function of depth.

[0066] "Group III-V material" refers to a compound semiconductor material containing at least one element from column III and at least one element from column V of the periodic table. Group III-V materials can be In x Al y Ga 1-x-y N, such as GaN, AlN, InN, or InGaN, or (In)(Al)GaN, such as GaN, AlGaN, or InAlGaN.

[0067] "Growth plane" refers to a plane parallel to the plane of deposition of material onto a planar surface, such as the growth surface of a conventional substrate.

[0068] "Substantially perpendicular to the growth plane" refers to a surface that forms an angle of approximately 90 degrees relative to the growth plane, such as 88 to 92 degrees relative to the growth plane.

[0069] wurtzite GaN or GaN by having respectively about and The room temperature a-lattice parameter and c-lattice parameter of a wurtzite are characterized by the wurtzite crystal structure. The crystal plane orthogonal to the c-lattice parameter direction ("c-direction") is the c-plane with Ga-facets (0001) and N-facets (000-1). The plane containing the c-direction and perpendicular to the a-lattice parameter direction ("a-direction") is the {11-20} plane or "a-plane". The plane containing the c-direction and parallel to the a-lattice parameter direction is the {1-100} plane or "m-plane".

[0070] WurtziteIn x Al y Ga 1-x-y N、In x Ga 1-x N and Al y Ga 1-yN has the same crystal structure as wurtzite GaN, but may include a non-zero mole fraction x of InN to form a ternary compound in which the specified fraction of column III atoms is In and the remainder is essentially Ga. InN has and The room temperature a-lattice parameter and c-lattice parameter of In x Ga 1-x N has a room temperature a-lattice parameter and a c-lattice parameter that are between those of GaN and InN and depend on the mole fraction.

[0071] WurtziteIn x1 Al y1 Ga 1-x1-y1 N or InAlGaN has the same crystal structure as wurtzite GaN, but may include a non-zero mole fraction x of InN or a non-zero mole fraction y of AlN to form a ternary or quaternary compound in which the specified fraction of column III atoms is In and / or Al and the remainder is essentially Ga. AlN has approximately and The room temperature a-lattice parameter and c-lattice parameter of Al y Ga 1-y N has a room temperature a-lattice parameter and a c-lattice parameter that are between those of GaN and AlN and depend on the mole fraction.

[0072] Although this description focuses on growing (0001) InGaN on a GaN seed surface, the method is applicable to other wurtzite materials such as InGaN on AlN. x Al y Ga 1-x-y N, AlGaN on AlN, and AlGaN on GaN. When the seed comprises InGaN, the mole fraction of InN in the stacked InGaN layer may be different from the mole fraction of InN in the InGaN seed. For example, the mole fraction of InN in the stacked InGaN layer may be greater than the mole fraction of InN in the InGaN seed. In addition, the present invention is applicable to non-basal plane wurtzite structures, such as so-called non-polar and semi-polar GaN and related materials. The present invention is also applicable to other compound semiconductor systems (including zinc blende materials), such as InGaAs on GaAs, InGaAsP on InP, InGaSb on GaSb, and II-VI compound semiconductor systems.

[0073] "Relaxed InGaN" refers to an InGaN material that exhibits an in-plane a-lattice parameter that is equal to or nearly equal to that of a fully relaxed InGaN material. For example, wurtzite relaxed InGaN x Al y Ga1-x-y N has a value greater than (0% InN) and up to This is in contrast to strained InGaN materials such as InGaN that are grown pseudomorphically with GaN and therefore exhibit an in-plane a-lattice parameter equal to or nearly equal to that of GaN. Such strained or non-relaxed InGaN materials are referred to as InGaN / GaN.

[0074] "Pseudomorphic" refers to a layer that is grown on a base layer or substrate such that it is epitaxially aligned with the base layer even if the native (relaxed) lattice constant of the grown layer is different from that of the base layer or substrate. Thus, the pseudomorphic layer is essentially fully strained. For a wurtzite crystalline material characterized by a c-lattice parameter and an a-lattice parameter, the pseudomorphic layer will adjust to match the base layer or substrate, in which case the c / a ratio of the pseudomorphic layer will be different from that of the base layer or substrate, depending on the growth direction. For growth in the (0001) direction under compressive strain, the c / a ratio of the pseudomorphic layer will be greater than that of the base layer or substrate, while for tensile strain, the c / a ratio of the pseudomorphic layer will be less than that of the base layer or substrate. For growth in a non-polar direction (e.g., <10-10> or <11-20> direction) under compressive strain, the c / a ratio of the pseudomorphic layer will be less than that of the base layer or substrate, while for tensile strain, the c / a ratio of the pseudomorphic layer will be greater than that of the base layer or substrate. For a semi-polar growth direction, the strain will depend on whether the growth direction is within 45 degrees of the

[0001] direction (i.e., more vertical) or deviates from the

[0001] direction by more than 45 degrees (i.e., more lateral). For example, for growth in the semi-polar <10-11> direction under compressive strain, the c / a ratio of the pseudomorphic layer will be less than that of the base layer or substrate, while for tensile strain, the c / a ratio of the pseudomorphic layer will be greater than that of the base layer or substrate.

[0075] According to the present invention, the x Al y Ga 1-x-y In on the N seed region x Al y Ga 1-x-y N is not pseudomorphic relative to the seed region.

[0076] "In-plane lattice parameter" refers to the crystal lattice spacing within the growth plane. For (0001) materials such as InGaN, the in-plane lattice parameter is the a-lattice parameter.

[0077] "Lateral growth" refers to growth in a direction other than perpendicular to the growth plane (including growth parallel to the growth plane).

[0078] "Crystallographically equivalent" refers to planes of a semiconductor crystal that have the same atomic arrangement due to the symmetry of the crystal lattice. These crystal planes are equivalent because they can be transformed into one another by symmetry operations inherent in the semiconductor crystal structure, such as rotation or reflection. For wurtzite materials (such as Group III nitride semiconductors), an example of crystallographically equivalent planes is the set of m-planes {10-10}: (10-10), (01-10), (0-110), (0-1-10), (-1010), and (-1100). Another example of crystallographically equivalent planes is the set of a-planes {11-20}: (11-20), (1-120), (-2110), (-12-10), (2-110), and (21-10). Another example of crystallographically equivalent planes is the semipolar set {10-11}: (10-11), (01-11), (0-111), (0-1-11), (-1011), and (-1101). Of course, as will be appreciated by those skilled in the art, there are many more crystallographically equivalent plane sets.

[0079] "Critical thickness" refers to the maximum thickness of an epitaxial film that can be grown on a base layer or substrate without dislocations forming due to lattice mismatch between the film and the base layer or substrate. Beyond the critical thickness, the strain energy exceeds the energy required to form dislocations, resulting in the formation of dislocations to relieve the strain and, therefore, relaxation in the epitaxial film. This transition from a pseudomorphic film (below the critical thickness) to a (even partially) relaxed film via the formation of dislocations is called plastic deformation.

[0080] "Overlying" (such as an "overlying layer") refers to a layer (such as an epitaxial layer) that is positioned above an underlying layer. The overlying layer may contact the underlying layer. An overlying layer (such as an overlying InGaN layer) may have a uniform composition or may have a non-uniform composition parallel and / or perpendicular to the growth plane. One or more different epitaxial layers may be present between the overlying layer and the underlying layer.

[0081] "layer" (such as p-type In x Al y Ga 1-x-y N layer or active layer) refers to a layer including a single layer or including one or more sublayers (such as, for example, 1 to 100 sublayers). Each of the sublayers constituting the layer may have the same elemental composition, or at least one of the sublayers may have an elemental composition different from that of another sublayer. For example, p-type In x Al y Ga 1-x-yThe N layer may include In with different p-type dopant concentrations. x Al y Ga 1-x-y N Sublayer. Each of the sublayers forming the layer may be independently deposited under the same or different deposition conditions and may independently comprise the same or different elemental composition.

[0082] “In x Al y Ga 1-x-y N" refers to an alloy of gallium and nitrogen, aluminum and nitrogen, and optionally indium and / or aluminum. For example, In x Al y Ga 1-x-y N includes GaN, AlN, In x Ga 1-x N, Al y Ga 1-y N and In x Al y Ga 1-x-y N, where x and y are not 0.

[0083] “In x1s Al y1s Ga 1-x1s-y1s N" refers to the In associated with the first seed region x Al y Ga 1-x-y N alloy.

[0084] “In x2s Al y2s Ga 1-x2s-y2s N" refers to the In associated with the second seed region x Al y Ga 1-x-y N alloy.

[0085] “In x1 Al y1 Ga 1-x1-y1 N" refers to In associated with the first growth layer and the first (0001) growth region. x Al y Ga 1-x- y N alloy.

[0086] “In x2 Al y2 Ga 1-x2s-y2s N" refers to In associated with the second growth layer and the second (0001) growth region. x Al y Ga 1-x-y N alloy.

[0087] "Simultaneously depositing" means that the epitaxial layers are deposited or grown on different regions of the growth substrate at the same time and under the same reactor growth conditions (such as substrate temperature, gas temperature, reactants, flow rates, and pressure).

[0088] "Sequential deposition" means that the epitaxial layers are deposited or grown on different regions of the growth substrate at different times and under the same or different reactor growth conditions (such as substrate temperature, gas temperature, reactants, flow rates, and pressures).

[0089] Although much of this disclosure focuses on the growth of InGaN overlying a patterned (In)GaN seed region and the formation of a relaxed InGaN region, the present invention also encompasses the growth of InGaN overlying a patterned (In)GaN seed region. x1 Al y1 Ga 1-x1-y1 In on the N seed region x2 Al y2 Ga 1-x2-y2 The growth of N and the relaxed In x2 Al y2 Ga 1-x2-y2 The formation of an N region (where 0≤x1<1, 0≤y1<1, x1+y1≤1) and characterized by a wurtzite III-nitride crystal structure (and where 0≤x2<1, 0≤y2<1, x2+y2≤1 and x2>x1) and characterized by a wurtzite III-nitride crystal structure. For example, the seed region may comprise GaN, AlN, InGaN, AlGaN, or InAlGaN, and the overlying growth region may comprise InGaN, AlGaN, or InAlGaN, and the relaxed (0001) region may comprise InGaN, AlGaN, or InAlGaN, respectively.

[0090] Certain embodiments of materials, semiconductor structures, optoelectronic devices, and methods are now described in detail. The disclosed embodiments are not intended to limit the claims. On the contrary, the claims are intended to cover all alternatives, modifications, and equivalents.

[0091] The present invention teaches the formation of a wide-area planar, organized, at least partially but substantially uniformly relaxed layer of compound semiconductor material for use in optical and / or electronic devices. "Wide-area" refers to a size that is wider than the emission diameter of a single optoelectronic device (such as an LED or VCSEL). Consistent with micro-LEDs and micro-VCSELs, the wide-area is typically greater than 0.25 μm. 2 , but can be up to 1mm in some applications 2 or even larger than 1cm 2"Planar" refers to a semiconductor layer that exhibits at least one substantially flat surface and has substantially no significant thickness variation over a wide area. A planar semiconductor region can serve as a growth surface for an overlying epitaxial semiconductor layer. For example, a planar semiconductor layer can have an RMS roughness of less than 1 nm as determined using atomic force microscopy. A planar semiconductor layer can have a thickness that is, for example, within ±10% of the average thickness of the planar semiconductor layer. "Organized" refers to the property that a material is substantially crystalline rather than amorphous. "Relaxed" refers to the property that the in-plane lattice parameter of a material approximates the in-plane lattice parameter of an independent, organized, 100% relaxed version of the material having the same elemental composition. "Substantially relaxed" refers to a material wherein the in-plane lattice parameter of the material is within 30% of the in-plane lattice parameter of an independent, organized, 100% relaxed version of the material having the same elemental composition. "Uniform" refers to the property that the in-plane lattice parameter of the material has little or substantially no variation over a wide area over which optical and / or electronic device structures can be fabricated. Furthermore, the present invention is applicable to a wide range of semiconductor crystal systems (including the wurtzite crystal structure) and to higher order alloys (including ternary and quaternary alloys). Finally, the present invention is applicable to structures grown by a variety of growth methods (including, for example, molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD)).

[0092] In particular, the present invention teaches the formation of a large area planar organized layer of at least partially but substantially uniformly relaxed indium gallium nitride (InGaN) material for use as a base layer for optical and / or electronic devices. Various compositions (such as InN mole fractions) can be achieved. "Uniformly relaxed" refers to a layer having an in-plane lattice parameter that does not vary substantially over a large portion of a large area in a plane containing the growth plane. Such relaxed InGaN materials are referred to herein as relaxed InGaN, such as Native (OpnovixCorporation).

[0093] The present invention further teaches that based on the relaxed In x Al y Ga 1-x-y N (such as In x Ga 1-x N) (which may include additional InGaN layers pseudomorphically grown to the relaxed InGaN (ie, InGaN / InGaN), such as Native ) formation of optical and / or electrical devices and systems.

[0094] The present invention further includes a photovoltaic device having different corresponding In layers grown on a single growth layer. x Al y Ga 1-x-y Two or more optoelectronic elements are provided above the N-growth layer, the two or more optoelectronic elements being configured to emit at different respective wavelengths.

[0095] Other features and aspects of the present invention will be apparent from the following description and accompanying drawings. In particular, the teachings of the present invention are applicable to other compound semiconductor device materials, such as indium gallium nitride (InGaN). x Ga 1-x N), aluminum gallium nitride (Al y Ga 1-y N), aluminum gallium indium nitride (In x Al y Ga 1-x-y N), III-As materials, III-P materials, III-Sb materials, etc.

[0096] The present invention discloses the use of a semiconductor seed material deposited on a substrate for recording the crystalline growth of a compound semiconductor material. The seed material has a plurality of seed regions having edges that are planar seed surface portions, and each of the orthogonal directions to these planar seed surface portions has a crystallographically equivalent orientation that is not parallel to the normal of a large area of ​​the substrate. The crystallographically equivalent orientation of a limited number (preferably one) of exposed planar seed surfaces ensures uniform relaxation and composition control of the InGaN material grown thereon, thereby avoiding competing growth modes and problems associated with uncontrolled composition content (such as uneven InN incorporation, rough surfaces, etc.) when variable seed surface orientations are simultaneously presented for InGaN growth. The size of the seed surface portion is limited to a certain extent so that additional compound semiconductor material can be seeded and easily relaxes towards its relaxed in-plane lattice parameter during growth. The resulting "relaxed" compound semiconductor material subsequently grows out and coalesces to form a wide area (i.e., greater than 0.25 μm 2 Wide area relaxed compound semiconductor material films provide templates for the growth of improved optical and / or electronic device structures.

[0097] In particular, the present invention discloses a GaN seed region having a seed surface portion for recording In x Al y Ga 1-x-y N (such as, for example, InGaN, i.e., In x Ga 1-x N) of the crystal growth, wherein, in accordance with the use environment, Inx Ga 1-x N can be GaN and / or In x Ga 1-x N. Although aspects of this disclosure focus on InGaN, these aspects are also applicable to InGaN x Al y Ga 1-x- y N is related. The size of the GaN seed surface and the geometric structure associated with the seed surface are constrained to a certain extent, so that the InGaN material can be seeded and easily relax towards the relaxed in-plane lattice parameters of the InGaN material during growth. The crystallographic direction of the normal to the planar seed surface portion can be a non-polar direction (such as (11-20) or (1-100)) or a plane rotated between the non-polar direction or the semi-polar direction (such as (1-101)). The InGaN layer is then grown out and coalesced into a planar wide-area relaxed InGaN film. The relaxed InGaN film or layer is characterized by a planar relaxed (0001) region that can serve as a growth substrate for the superimposed epitaxial layer. The wide-area relaxed InGaN film provides a template for the growth of improved InGaN-based optical and / or electronic device structures.

[0098] An example of a method for growing a relaxed InGaN layer having a relaxed (0001) InGaN region is shown in Figures 1A to 1E middle.

[0099] like Figure 1A As shown, a main (0001) (i.e., c-plane) GaN (or AlN) layer 102 can be grown on a substrate 101 using any suitable semiconductor growth method. Examples of suitable substrates include sapphire, silicon carbide, silicon, aluminum nitride, and gallium nitride. Other useful substrate materials include engineered substrates such as silicon on insulator (SOI). The GaN layer 102 can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. The GaN layer 102 can be coated with a mask layer 103 of a material that rejects or slowly promotes the nucleation of group III nitride materials. Suitable mask materials include, for example, dielectrics (such as silicon nitride, silicon oxide, and aluminum oxide), but may also include other materials such as metals or semiconductors (single crystal or polycrystalline). The mask layer 103 and the underlying GaN layer 102 can be patterned and etched using photolithography (such as using nanolithography) and wet etching and / or dry etching methods to provide a mask layer 103 such as a semiconductor layer 102 having a thickness of less than 3 μm, less than 0.3 μm, or less than 0.03 μm. Figure 1B Suitable etching techniques include wet chemical etching, electrochemical etching, photochemical etching, photoelectrochemical etching, reactive ion etching (RIE), inductively coupled plasma RIE, chemically assisted ion beam etching (CAIBE), and the like.

[0100] The etched region 104 (where the mask and GaN material have been removed) exposes the GaN seed surface 102a. The seed surface 102a may be substantially perpendicular to the GaN (0001) c-plane. Figure 1C As shown, the GaN seed surface 102a can be used for the lateral growth of at least InGaN 105, thereby forming an InGaN / GaN heterojunction that is not coplanar with the substrate 101. Each exposed GaN seed surface 102a can have an equivalent crystallographic orientation. For example, the GaN seed surface 102a can be a main (1-100) (i.e., m-plane) or a main (11-20) (i.e., a-plane) or any plane rotated between the m-plane and the a-plane. In addition, the seed surface 102a can be intentionally misoriented with respect to the main GaN crystal plane, for example, to promote favorable and uniform growth characteristics. Figure 1D InGaN 106 is shown grown to fill the etch cavity and overlying a portion of the mask layer 103 . Figure 1E The InGaN layer 106 is shown to grow further until it coalesces and forms a relaxed InGaN layer 109 having a relaxed (0001) InGaN region 110 overlying the mask region 103 and the substrate 101 . Figure 1E Shown are plane 108a passing through relaxed InGaN region 109 and coplanar with (0001) InGaN surface 107, and plane 108b bisecting seed region 102 and the InGaN region between seed regions 102. The center of the seed region is indicated as 108c, and the center of the InGaN region between seed regions 102 is indicated as 108d.

[0101] Another technique for achieving seed region faceting is to achieve material redistribution to form preferred facets by mass transfer, which involves controlled thermal annealing in a specific gas environment. By heating the material to a high temperature in a controlled atmosphere (such as an inert or reducing gas, or a vapor containing a specific chemical element), the atoms on the surface become mobile, allowing mass transfer to occur. This process causes the formation and growth of certain crystal facets that are more energetically favorable, resulting in the exposure of a preferred set of planes. For example, when heated to a high temperature, GaN can undergo surface reconstruction, in which gallium and nitrogen atoms diffuse on the surface, resulting in the preferential formation and exposure of certain crystal facets determined by specific conditions, such as the gaseous environment (e.g., the ratio of nitrogen to ammonia and / or hydrogen).

[0102] The orientation of the GaN seed surface 102a can be determined by patterning and based on the growth orientation of the underlying GaN layer 101. The orientation of the seed surface 102a further depends on the surface angle of the etched GaN layer 102. For example, for a (0001) GaN layer and nearly vertical etching, the orientation of the GaN seed surface can vary from approximately (1-100) to (11-20) and any orientation rotated therebetween. This orientation can be selected to optimize InGaN growth conditions and InGaN material quality.

[0103] For InGaN grown on certain GaN seed surfaces (especially those that are substantially perpendicular to the major surface of the substrate), in order to facilitate the coalescence of the relaxed InGaN layer, it may be desirable to enhance lateral growth as compared to vertical growth by optimizing the growth conditions and / or by selecting a GaN seed surface orientation that promotes a fast growth rate.

[0104] The small size of the GaN seed surface promotes relaxation of the InGaN material deposited thereon and provides a planar crystallographic orientation for organized InGaN growth. During growth, the InGaN grows in an organized manner and relaxes toward its relaxed lattice parameter and eventually coalesces with a neighboring InGaN growth front originating in an adjacent etched region. Figure 1C , InGaN 105 grows from the opposite GaN seed surface 102a, and Figure 1D InGaN 106 grows to fill the etched cavity and overlie a portion of the mask layer 103. Continuing InGaN growth causes coalescence of InGaN grown on the surface of the GaN seed crystal in adjacent cavities. A relaxed InGaN layer then grows over the mask layer to form a continuous, planar, relaxed (0001) InGaN region 110 at the upper InGaN surface 107, which can serve as a relaxed (0001) InGaN growth surface or template.

[0105] In the InGaN growth method of the present invention, relaxation is allowed to proceed laterally, that is, by twisting rather than by tilting (which occurs when InGaN is grown directly on a (0001) GaN surface). Direct growth of InGaN on (0001) GaN introduces vertical InGaN strain gradients, which can cause problems during subsequent growth and coalescence of the InGaN. In contrast, the present invention provides reduced tilting, which allows the final coalesced film to be essentially free of strain and / or compositional inhomogeneities, thereby providing a high-quality, planar, relaxed (0001) InGaN wide-area surface for semiconductor growth. Furthermore, because relaxation occurs mostly uniformly at the GaN seed crystal surface, the vertical strain gradients generated when the strained layer is first grown pseudomorphically (and then etched and relaxed) can be avoided or minimized.

[0106] In the InGaN growth methods provided by the present disclosure, InGaN growth occurs primarily at the surface of the GaN seed material, and InGaN growth on other exposed surfaces is minimized or avoided entirely. Therefore, it can be beneficial to etch through the GaN seed material and into the underlying substrate to move the substrate growth surface away from the InGaN nucleation zone. Furthermore, the growth conditions for the InGaN layer can be selected to promote growth at one or more GaN seed crystal surfaces, rather than promoting InGaN nucleation and growth on the substrate, which would exhibit a competing growth mode. Figures 2A to 2E This method is illustrated in which both the GaN layer and a portion of the substrate are etched. By etching the substrate, the distance between the competing growth of GaN seed material (at the substrate surface) and the desired growth at the surface or surfaces is increased, with the goal of preventing InGaN growing on the substrate from competing. In addition, etching the substrate can be used to prevent the nucleation and growth of InGaN on the substrate, which further reduces the possibility of interfering with the competing growth mode.

[0107] Figure 2A A substrate 201, an overlying GaN layer 202, and an overlying mask layer 203 are shown. Figure 2B In FIG. 2 , the mask layer 203, the GaN layer 202, and a portion of the substrate 201 have been etched to provide a cavity 204 with an exposed GaN seed surface 202a. Figure 2C As shown, InGaN 205 grows on the GaN seed crystal surface 202a and laterally grows into the corresponding cavity 204 and above the substrate 201. Figure 2D As shown, continued InGaN growth 206 causes the lateral growth regions to coalesce and grow into a cavity 209 above the mask layer 203. A portion of the cavity 209 (i.e., a void) may be formed between the substrate 201 and the coalesced InGaN 206 within the cavity. In some embodiments, such a void may be used to assist in light extraction, such as in an LED device. Figure 2E As shown, continued InGaN growth causes InGaN grown from adjacent cavities to coalesce and form an InGaN layer 209 that can be used for the growth of an overlying semiconductor layer. The layer has a relaxed (0001) InGaN region 210 and a relaxed (0001) InGaN surface 207 . Figure 2E Shown are plane 208a passing through relaxed InGaN (0001) region 210 and coplanar with relaxed (0001) InGaN surface 207, and plane 208b bisecting seed region 202 and the InGaN region between seed regions 202. The center of the seed region is indicated as 208c, and the center of the InGaN region between seed regions 202 is indicated as 208d.

[0108] Figure 13 is Figures 2A to 2E Detailed cross-sectional view of the structure resulting from the process flow shown. A substrate 1301 (such as (0001) sapphire) includes optional etched regions 1306 extending into the substrate 1301. A GaN (or AlN) seed layer material 1302 characterized by an in-plane a-lattice parameter a1 overlies the substrate 1301 in the unetched regions and beneath a mask layer 1303. InGaN 1305 has nucleated at the edges of the seed layer material 1302 on the GaN seed surfaces, forming an InGaN / GaN heterojunction 1307 (i.e., the heterojunction is located at the interface between the InGaN region and the GaN seed region), which is orthogonal to those surfaces that share an equivalent crystallographic direction that is not parallel to the major surface of the substrate 1301. The InGaN material 1305 has at least partially grown laterally out of the InGaN region between the GaN seed surfaces 1307 to relax toward the relaxed InGaN in-plane a-lattice parameter a2. A plane 1308b, which is parallel to the major surface of substrate 1301 and bisects GaN seed surface 1307, is characterized by different in-plane a-lattice parameters at different locations within the cross section. For example, at the center point of the GaN seed region, the lattice parameter along plane 1308b is characterized by a lattice parameter a1 that is commensurate with the a-lattice parameter of GaN, and at the center point 1305 between GaN seed surfaces 1307, the lattice parameter along plane 1308b is approximately a2 that is commensurate with the lattice parameter of at least partially relaxed InGaN (based on the average mole fraction of InN in the InGaN layer). The average mole fraction of InN in the InGaN layer is determined, for example, by epitaxial growth conditions such as temperature and the relative flow rates of organometallic precursors, such as trimethylindium (TMI) and trimethylgallium (TMG) in MOCVD. In the region between the center points of a1 and a2, the lattice parameter along plane 1308b is characterized by an in-plane a-lattice parameter that is greater than a1 and less than a2 (because a2>a1). In a plan view (not shown), the variation in the in-plane a-lattice parameter within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figure 5 and Figure 6 ).

[0109] refer to Figure 13, the InGaN material 1305 coalesces over the mask layer 1303 to form a relaxed InGaN region 1304 having a planar (0001) InGaN surface 1305c. A plane 1308a parallel to the major surface of the initial growth substrate and positioned within the relaxed InGaN region 1304 is primarily characterized by an in-plane a-lattice parameter a2. In particular, at a center point 1305b between the GaN seed surfaces, the InGaN lattice parameter along plane 1308a is characterized by an in-plane lattice parameter a2, and at a center point above the GaN seed surface, the InGaN in-plane a-lattice parameter along plane 1308a is slightly less than a2. In a plan view (not shown), the variation in the in-plane a-lattice parameter within plane 1308a is characterized by a two-dimensional mask pattern applied to the GaN seed layer (see Figure 5 and Figure 6 Variations in the in-plane a-lattice parameter of InGaN can be detected, for example, using X-ray diffraction (XRD) and reciprocal space mapping (RSM), and can be resolved at the submicron scale using techniques known in the art, and in relaxed (0001) InGaN regions using grazing incidence techniques.

[0110] The midpoint of the plane 1308b within the seed region is indicated as 1308c, and the midpoint of the plane 1308b between the seed regions is indicated as 1308d.

[0111] The GaN seed region 1302 has an in-plane dimension of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed region 1302 may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1302 (e.g., the width of the GaN seed region 1302) may be less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask layer 1303 may be, for example, 0.01 μm to 1 μm, 0.02 μm to 0.8 μm, 0.05 μm to 0.5 μm, or 0.1 μm to 0.4 μm.

[0112] Figures 3A to 3E An example of a process flow for fabricating relaxed InGaN using a silicon-on-insulator (SOI) substrate is shown. In this embodiment, it is desirable to include a strain-controlling interlayer (such as a GaN, AlGaN, InGaN, or InAlGaN interlayer) within the semiconductor structure (not shown) to control wafer bowing, as is well known for GaN-on-Si growth.

[0113] Figure 3A A substrate 301 , an oxide layer 301 a , a silicon layer 301 b , a seed layer 302 , and a mask layer 303 are shown. Figure 3BCavity 304 is shown after etching down to silicon layer 301 b , which cavity forms the seed region and seed surface in seed layer 302 . Figure 3C The lateral growth of InGaN on the seed surface of the seed region in the seed layer 302 within the cavity 304 is shown. The InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. Figure 3D InGaN growth 306 from seed layer 302 has grown, and the InGaN growth front coalesces to fill the cavity and extend over a portion of mask layer 303. Figure 3E As shown, continued InGaN growth provides a planar relaxed InGaN layer 307 . Figure 3E Shown are plane 308a passing through the relaxed InGaN region and coplanar with the surface relaxed (0001) InGaN surface 307, and plane 308b bisecting the seed region 302 and the InGaN region between the seed regions 302. The center of the seed region is indicated as 308c, and the center of the InGaN region between the seed regions 302 is indicated as 308d.

[0114] Figures 4A to 4E Another example of a process flow for fabricating a relaxed InGaN layer using an SOI substrate is shown. Figures 3A to 3E Similar to the example of , additionally the top silicon layer and buried oxide layer 401a of the SOI substrate 401b are removed by etching (in region 404) to minimize the competing growth of InGaN on the silicon substrate and to favor InGaN growth on the seed surface.

[0115] Figure 4A A silicon-on-insulator (SOI) substrate 401 , an oxide layer 401 a , a silicon layer 401 b , a seed layer 402 , and an overlying mask layer 403 are shown. Figure 4B A cavity 404 is shown, caused by etching down to the substrate 401, which forms a seed region in the seed layer 402. Figure 4C In FIG, lateral InGaN growth 405 extends from the edge surface of the seed layer 402 into the cavity 404. The InGaN growth has a sufficiently high InN mole fraction to induce strain relaxation. Figure 4D As shown, the continued InGaN growth 406 causes the InGaN grown from the opposite seed surface to coalesce and then grow vertically to fill the upper portion of the cavity and extend above the mask layer 403. The preferential growth from the seed surface compared to the growth on the substrate forms a space 409 (i.e., a gap) between the substrate 401 and the InGaN layer 406. Figure 4E As shown, continued InGaN growth provides a planar relaxed (0001) InGaN surface 407 . Figure 4EShown are plane 408a passing through the relaxed InGaN region and coplanar with surface 407, and plane 408b bisecting seed region 402 and the InGaN region between seed regions 402. The center of the seed region is indicated as 408c, and the center of the InGaN region between seed regions 402 is indicated by 408d.

[0116] Figure 5 Example mask patterns for etching seed materials are shown, including stripes, rectangles, triangles, and hexagons. For wurtzite materials (such as group III nitride materials including InGaN), preferred pattern features are pattern features (such as hexagons or triangles) with edges that share equivalent crystallographic orientations. Other shapes and other relative sizes may also be used. The minimum dimension of the mask pattern may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The edges of the mask pattern may be aligned with certain crystal planes. For example, for a wurtzite material having a (0001) principal growth plane, the mask edges may be aligned with the (1-100) or (11-20) planes or any orientation therebetween to facilitate the growth of a high-quality relaxed InGaN layer.

[0117] Figure 6 An alternative set of mask patterns is shown, which are Figure 5 Reverse of the mask pattern shown, but otherwise similar.

[0118] Figure 7 A conceptual plan view cross section of a patterned GaN seed material having a lattice parameter a is shown, on the sides of which lateral heteroepitaxial growth is performed to grow an InGaN layer that is allowed to relax to the relaxed lattice parameter a via distortion. Figure 7 The transition of an InGaN lattice 701 / 701a (filled circles), characterized by a lattice parameter "a" similar to that of GaN, to a larger relaxed InGaN lattice 702 / 702a (hatched circles), characterized by a lattice parameter "a'", is shown. For sufficiently small sizes, the deformation is entirely elastic and no defects are formed. For larger sizes, some plastic deformation may occur but may be tolerable provided that the resulting defect density in the subsequently deposited overlying semiconductor layers is sufficiently low. For example, it is desirable for the extended defect density in the subsequently deposited semiconductor layers to be less than 5E9 cm 2 , such as less than 5E8cm 2 , or less than 5E7cm 2 , or less than 5E7cm 2 , or less than 5E6cm 2 or less than 5E5cm 2 The lateral InGaN growth and coalescence methods provided by the present disclosure can facilitate the annihilation of threading dislocations in Group III nitride materials.

[0119] Further control over the thickness and composition uniformity of the relaxed InGaN growth can be provided by growing a multilayer structure rather than by using a monolithic InGaN layer. For example, a 3 nm thick GaN with a 1 nm thick InN layer or a 2 nm thick GaN with a 2 nm thick InN layer can be used. 0.5 Ga 0.5 N to replace the 25% overall InGaN layer. The layer thickness of the individual layers can range from 0.5nm to 100nm, such as 1nm to 30nm, for example. The multilayer structure is not limited to the base layer and / or buffer layer, but can be used in the entire epitaxial stack (including semiconductor device layers, such as n-type InGaN, p-type InGaN and an active layer stacked on the relaxed InGaN layer) or in the layer between the relaxed InGaN layer and the stacked device layer. Such a multilayer structure is sometimes referred to as a superlattice layer. The multilayer structure is not limited to GaN and InGaN, but can include other alloys available for the III-nitride system. For example, the layer may include InAlGaN, InGaN, AlGaN and InAlN and other selected compositions. In addition to InGaN / GaN, layer pairs may also include InGaN / AlGaN, InGaN / InAlGaN, InAlGaN / InAlGaN, InGaN / InAlN and InAlN / GaN, etc.

[0120] Graded composition growth can also be used to transition from a seed region to a relaxed InGaN material. For example, the InN mole fraction in a layer grown on a GaN seed region can be slowly increased from about 0% to a target InN mole fraction so that stress and relaxation mechanisms (e.g., defects) are distributed in a uniform manner outside the seed region. In another example, a higher InN mole fraction can be used near the GaN seed region to quickly induce strain relaxation, and then the InN mole fraction can be gradually reduced as needed to achieve optimal growth conditions for the overlying relaxed InGaN layer.

[0121] The increased in-plane lattice parameter of the relaxed InGaN layer compared to that of InGaN / GaN allows the subsequently deposited semiconductor layers to be grown at temperatures much higher than those used for InGaN / GaN. InGaN with an in-plane a-lattice parameter of 1.5 has been shown to incorporate about 7% InN, compared to about 4% for InGaN / GaN. Because the mole fraction of InN incorporated into GaN is inversely proportional to the growth temperature using MOCVD, this means that about to The increase in the a-lattice parameter within the InGaN plane can increase the useful growth temperature by about 50°C. Further increases in the a-lattice parameter within the InGaN plane will allow the use of even higher temperatures for the same InN mole fraction. This effect can be used to achieve higher quality semiconductor layers grown on relaxed InGaN, not only by reducing point defect formation at higher temperatures, but also by reducing or eliminating pits that appear at the sites of threading dislocations in the surface of the InGaN film. Ideally, the growth temperature of the InGaN layer is kept high enough to eliminate pits or at least confine the pits to diameters much smaller than 1 μm, such as less than 200 nm or less than 50 nm. A thin layer of high temperature GaN or AlGaN grown on top of the pitted InGaN film can be used to "fill" the small pits.

[0122] The methods provided by the present disclosure may include recursion, which may help to obtain large lattice parameter changes. For example, a relaxed InGaN layer may be used as a seed layer to provide a seed surface for the growth of a relaxed InGaN layer of a higher InN mole fraction. The resulting new relaxed InGaN layer may then be used as a seed layer in another step of the process, and so on. This method may help to obtain a relaxed InGaN layer with a very high InN mole fraction, which may be suitable as a base layer for the growth of an active semiconductor layer configured to emit radiation at long wavelengths, such as ultra-red, to deep red, and even infrared wavelengths, such as, for example, wavelengths in the sub-range of 700 nm to 1.6 μm. Similarly, such methods may be used to form photosensitive materials optimized for solar photovoltaic applications.

[0123] The relaxed InGaN layer provided by the present disclosure can serve as a template and / or support structure for growing optical and / or electrical devices. Very large area wafers (including 150 mm, 200 mm or larger diameter wafers) can be achieved, which facilitates high-volume, low-cost manufacturing of these devices.

[0124] For example, Figure 8 An LED structure is shown, formed by growing an n-type layer 806 (e.g., doped with Si or Ge) over the relaxed (0001) InGaN surface of an InGaN layer 804, followed by an active region 807 containing InGaN, an optional p-type electron blocking layer 808 (comprising, for example, GaN, AlGaN, or InGaN (or multiple layers comprising alloys of these)), and then a stacking p-type layer 809 (such as a p-type GaN or InGaN layer). A highly doped (e.g., Mg-doped) p-type contact layer 810 (comprising, for example, GaN or InGaN) is stacked on the p-type layer 809 and provides an ohmic contact to the device on the p-side. Figure 8As shown, the semiconductor structure below the InGaN layer 804 includes a substrate 801, a GaN seed region 802, and a mask region 803. To the extent that there is a difference in refractive index between these various features, the presence of the refractive index difference can help improve light extraction from the device. In a related embodiment, a void is formed below region 805, and further light extraction benefits can be achieved. The resulting semiconductor wafer can be subjected to a series of process steps (such as photolithography, etching, and semiconductor deposition) to form isolated LED regions with suitable electrical contact materials to the n-type layer and the p-type layer. Such contact materials may include those with suitable optical characteristics (such as high optical reflectivity and / or transparency). Electrode metallizations 812a (e.g., NiAg, NiAu, TiAlCrNiAu, etc.) and 812b (e.g., TiAl, TiAlCrNiAu, etc.) can be deposited and patterned to provide electrical connections (e.g., using wire bonds). Various transparent conductive oxide (TCO) materials, such as indium-tin-oxide (ITO), can be used to fabricate the current spreading layer 811, particularly for resistive p-type layers. After fabrication of the semiconductor structure, the wafer can be sliced ​​to provide individual optoelectronic elements and devices that can be mounted into a suitable optoelectronic package by various means, including epoxy die attach, gold-gold bonding, or soldering. Electrical contact can be made to the p-type and n-type layers (e.g., using wire bonding) to form a working optoelectronic element or device to which power can ultimately be supplied. The device may further include luminescent down-conversion materials and / or encapsulating materials (such as silicone) to provide desirable light output characteristics, including white light for lighting applications. The device can be employed in systems for lighting and / or in display applications.

[0125] The barrier layer 808 may be placed directly above the active region 807, or may be formed by a spacer layer ( Figure 8 Typically, the spacer layer is nominally undoped and can be a layer to which a Cp2Mg source is turned on during MOCVD growth if the barrier layer or a layer above the barrier layer is to be p-doped.

[0126] like 9A to 9D As shown, various flip-chip (FC) LED architectures can be achieved, including: (a) standard; (b) thin-film flip-chip (TFFC), in which the initial growth substrate has been removed, but the mask and seed layer portions are retained; (c) TFFC in which the mask and seed layer portions are removed; and (d) TFFC in which the mask and seed layer portions are removed and the exposed InGaN layer is textured (for light extraction purposes) (such as by photolithography and / or chemical-based etching techniques).

[0127] 9A to 9DThe semiconductor structure shown includes a substrate 901, a seed region 902, a mask region 903, a relaxed InGaN layer 904 and an initial InGaN growth region 905, an n-type layer 906, an active region 907 containing InGaN, an optional p-type electron blocking layer structure 908, a p-type layer 909, a p-type contact layer 910, a p-side electrode metallization 911, and an n-side electrode metallization 912. Figure 9B In the Figure 9C In the , the growth and mask regions have been removed, and in Figure 9D In FIG. 9 , a portion of the relaxed InGaN region 904 has been removed and / or roughened 904a to enhance, for example, certain optical characteristics of the device.

[0128] Figure 10 Figure 2 shows a laser diode structure grown on a relaxed InGaN layer. Figure 10 As shown, a relaxed InGaN layer 1004 including an initial InGaN region 1005 is stacked on a mask region 1003, a seed region 1002, and a substrate 1001. A laser diode can be formed by growing an n-type optical confinement ("cladding") layer 1007 over the relaxed InGaN material 1004 and an n-type InGaN contact layer 1006, and then growing an InGaN-based active region 1009 including a waveguide region comprising waveguide layers 1008 and 1010 on either side of the InGaN-containing active layer 1009, and subsequently growing a p-type optical confinement ("cladding") layer 1011. Layers 1012 and 1013 are stacked on the p-type cladding layer 1011 and include a p-type AlGaN "electron blocking layer" and a p-type GaN layer, respectively. Wafer fabrication for laser diodes is similar to that for LEDs, except that the devices are formed into strips to form the laser cavity. After dicing or other separation techniques and forming the etched or cut mirror facets, highly reflective and anti-reflective dielectric coatings (not shown) can be deposited on the back and front sides of the facets, respectively. The laser diode can be mounted epitaxially face down or substrate face down into a suitable optoelectronic package, depending on the material selection and application details. Electrical contact can be made to the highly doped p-type contact layer 1014 and the n-type contact layer 1006 via electrode metallization 1015a and 1015b, respectively, to form a working optoelectronic element or device to which power can be supplied. Laser diodes are employed in systems for lighting and / or in display applications.

[0129] The relaxed InGaN layers provided by the present disclosure are suitable for influencing a wide range of system solutions for various applications, including lighting devices and systems ( Figure 11 ) and display device and system ( Figure 12The method can also be applied to solar photovoltaic applications.

[0130] The target composition of the relaxed InGaN layer can be selected based on the intended device, application, and performance requirements. For conventional InGaN light-emitting diodes that are lattice-matched to GaN, the best performing devices are those that emit in the ultraviolet wavelength range. At these wavelengths, the InGaN quantum wells are about 1% to 2% compressed relative to the strain state of the GaN base layer. The corresponding composition differences are large enough that bandgap engineering can provide very high quantum efficiency devices, while the strain state is low enough to allow relatively thick InGaN quantum well (QW) layers, which are used to reduce carrier density and mitigate non-radiative Auger recombination (also known as "attenuation"). Applying this acceptable range of strain states to other emission wavelengths, preferred composition ranges for the relaxed InGaN base layer provided by the present disclosure can be calculated for a wide range of emitters from blue light (about 450nm) to infrared light (about 1.3μm) wavelengths. The preferred ranges are listed in Tables 1 and 2.

[0131] Table 1. Preferred ranges of InN mole fraction of relaxed (0001) InGaN base layers for light emitting diodes and laser diodes according to emission color (PWL = peak wavelength in nm; Eg = band gap in eV; a_base = a-lattice parameter in the plane of the base layer at 300K in eV). a_QW = a-lattice parameter in the quantum well layer plane at 300K, in units of ).

[0132]

[0133] Table 2. Preferred ranges of InN mole fraction of relaxed InGaN (0001) base layers for light emitting diodes and laser diodes according to emission wavelength (PWL = peak wavelength in nm; Eg = band gap in eV; a_base = a-lattice parameter in the plane of the base layer at 300 K in eV). a_QW = a-lattice parameter in the quantum well layer plane at 300K, in units of ).

[0134]

[0135] Figure 14A and Figure 14BThe preferred ranges of InN mole fraction and a-lattice parameter for relaxed (0001) InGaN layers for use as templates for fabricating light-emitting diodes and laser diodes, consistent with the parameters presented in Tables 1 and 2, are illustrated graphically as a function of peak emission wavelength. Curve fitting of these data shows that the relaxed InN mole fraction and a-lattice parameter are consistent with the parameters presented in Tables 1 and 2 as a function of peak emission wavelength λ. x Ga 1-x The InN mole fraction x of the N base layer should satisfy the condition x min ≤x≤x max , where X min and X max Qualified by EQN.1 and EQN.2 respectively:

[0136] x min =-6.046E-07λ 2 +1.837E-03λ-6.917E-01(λ≥440nm)EQN.1

[0137] x max =-6.152E-07λ 2 +1.847E-03λ-6.142E-01(λ≥440nm)EQN.2

[0138] Similarly, as a function of the peak emission wavelength λ, the relaxed In x Ga 1-x The in-plane lattice parameter a of the N base layer should satisfy the condition a min ≤a≤a max , where a min and a max Qualified by EQN.3 and EQN.4 respectively:

[0139] a min =-2.067E-07λ 2 +6.366E-04λ-2.951(λ≥440nm)EQN.3

[0140] a max =-2.190E-07λ 2 +6.575E-04λ-2.970(λ≥440nm)EQN.4

[0141] The methods and semiconductor structures provided by the present disclosure can be suitable for fabricating vertical cavity surface emitting layers (VCSELs). The composition choices of the relaxed InGaN base layer for LDs or VCSELs are similar to those for LEDs and are shown in Tables 1 and 2.

[0142] Figures 15A to 15FAn example of steps in a method for producing a relaxed InGaN layer on a faceted GaN seed region edge surface is shown.In the method, a (0001) GaN or AlN seed layer 1502 on a substrate 1501 is provided. Figure 15A Shown are a substrate 1501, an overlying seed layer 1502, and an overlying mask layer 1503. The GaN seed layer can be, for example, less than 3 μm thick, less than 0.3 μm thick, or less than 0.03 μm thick. Figures 15A to 15F In the process flow shown, the seed layer 1502 can be coated with a mask layer 1503 containing a material that inhibits or slowly promotes GaN nucleation. The mask layer 1503 can be patterned and etched into various patterns as described herein using any suitable photolithography (including nanolithography) and etching methods (wet or dry or a combination thereof). The exposed GaN in the openings 1504 in the mask formed by etching can then be used to nucleate GaN seed material 1506, such as Figure 15C and Figure 15D As shown, it can be grown from the opening in the mask and, by appropriate selection of growth conditions, is allowed to form a seed region with a hexagonal base having edges (e.g., triangular facets). For example, the structure can be a hexagonal base with six sides and triangular facets that are {1-101} equivalent planes. After the facets are fully formed, as shown in FIG. Figure 15D As shown, the triangular facet surface 1507 can serve as a seed surface for at least lateral growth of InGaN, thereby forming a heterojunction that is not coplanar with the substrate surface. As the InGaN thickness increases, the small size of the GaN seed surface (facet) and the choice of the InGaN target composition promote relaxation of the overgrown InGaN while providing a flat, crystallographically equivalent orientation to ensure orderliness. The InGaN 1508 grows in an orderly manner and relaxes toward its relaxed lattice parameter to form a hexagonal structure with triangular facets as the relaxed InGaN, as shown in FIG. Figure 15E These InGaN facets can further grow out and eventually coalesce with the adjacent InGaN growth fronts of other planar seed facets. Figure 15FAs shown, the agglomerated InGaN is then grown over the mask layer and seed region, and the growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN layer or template 1509 having a relaxed (0001) InGaN surface as the upper region of the structure. This method has the advantage of providing a portion of the seed surface for InGaN nucleation without etching the GaN (or InGaN, AlGaN, or AlN) seed material. In addition, this method is very suitable when the growth substrate is a Group III nitride material (such as a GaN or AlN substrate). Therefore, this method facilitates the manufacture of LD devices in which low dislocation density (e.g., less than 5E7 cm for a GaN substrate) is required. -2 ) is preferred for long life operation (>10,000 hours).

[0143] 16A to 16F Another method for producing a relaxed InGaN layer on a faceted GaN surface is shown. Figures 15A to 15F The method shown is similar to that shown in FIG, except that the GaN seed material is nucleated directly on the substrate. In this method, a substrate 1601 suitable for GaN nucleation, such as sapphire, SiC, sapphire, AlN or GaN, may be provided. Figure 16A , the substrate 1601 may be coated with a mask layer 1602 of a material that slowly promotes GaN nucleation. Figure 16B As shown, the mask layer 1602 is patterned and etched into various patterns 1604 using photolithography (such as nanolithography) and etching techniques (wet or dry or a combination thereof). The exposed substrate 1603 in the openings in the mask formed by etching can then be used to nucleate GaN seed material 1605, as shown in FIG. Figure 16C As shown, it grows from an opening in the mask and, through appropriate selection of growth conditions, is allowed to form a GaN seed region having edges that are triangular facets and having a hexagonal base. For example, the seed region may have six sides and have triangular facets that are crystallographically equivalent to {1-101} planes. Figure 16D As shown, after the seed region is fully formed, the triangular facet surface 1607 is used as a seed surface for at least lateral growth of InGaN, thereby forming six heterojunctions in crystallographically equivalent planes that are not coplanar with the substrate. The small size of the GaN seed surface and the selection of the target composition of the grown InGaN material promote relaxation of the InGaN grown on the seed surface. In addition, each seed surface provides a flat crystallographically equivalent orientation to ensure orderliness throughout the grown InGaN material. The InGaN grows in an orderly manner and relaxes toward its relaxed lattice parameter to form facets 1608 as relaxed InGaN, as shown Figure 16EThese facets grow further and eventually coalesce with adjacent InGaN growth fronts growing from other seed regions. Figure 16F As shown, the agglomerated InGaN is then grown over the mask layer, and the growth conditions (e.g., growth temperature and TMI flow) are selected to form a continuous, planar, relaxed InGaN region 1609 having a relaxed (0001) InGaN surface or template across the substrate. This method has the advantage of providing a seed surface for InGaN nucleation without etching the GaN (or AlN) material. This method also has the advantage of providing the entire process in a single epitaxial growth process. In addition, this method is very suitable when the growth substrate is a Group III nitride material (such as a GaN or AlN substrate).

[0144] Figure 17A Provided by Figures 15A to 15F Detailed cross-sectional view of the structure resulting from the process flow shown. A substrate 1701 (such as (0001) sapphire) can serve as the primary growth substrate for a GaN (or InGaN, AlGaN, or AlN) seed layer 1702 characterized by an in-plane a-lattice parameter a1. The GaN seed layer 1702 has been grown between mask regions 1703 to form a GaN seed region 1702a having exposed edges of a crystallographically equivalent planar GaN seed surface. InGaN material has nucleated on the triangular GaN seed surface of the GaN seed region, forming a heterojunction 1707 that is not parallel to the major surface of the initial growth substrate 1701. The heterojunction 1707 can be formed on a stable, crystallographically equivalent facet of the GaN seed region, such as a {1-101} crystallographically equivalent facet. The InGaN material is at least partially grown laterally to relax towards a relaxed InGaN in-plane a-lattice parameter a2 in a region 1705 between the GaN seed surfaces. A plane 1708b that is parallel to the major surface of the initial growth substrate and that bisects the GaN seed material is characterized by different in-plane a-lattice parameters at different positions along the plane. In particular, at a center point within the GaN seed regions 1702a, the GaN material is characterized by an in-plane a-lattice parameter a1, and at a center point 1705 between the GaN seed regions 1702a, the in-plane a-lattice parameter is approximately a2. In the GaN region between these two center points, the in-plane a-lattice parameter is greater than a1 and less than a2 because a2>a1. In a plan view (not shown), the variation in the GaN in-plane a-lattice parameter within plane 1708b is characterized by a two-dimensional mask pattern that has been applied to the GaN seed layer material (see Figure 5 and Figure 6 ).

[0145] like Figure 17A and17B As shown, plane 1708b intersects the edge of seed region 1702a to position heterojunction 1709b at the interface between InGaN region 1704 and the seed region. The heterojunction is coplanar with a first crystal plane or first facet of the seed region. Any plane (such as plane 1708b) that is parallel to the primary growth surface and intersects both the InGaN region (such as at 1708c) and the seed region 1702a intersects the edge of seed region 1702a to position heterojunction 1709c at the interface between the InGaN region and the seed region, the heterojunction being coplanar with a second crystal plane or second facet of the seed region. Figure 17A and Figure 17B As shown, the first and second crystal planes are the same. The first and second crystal planes or facets may be crystallographically equivalent crystal planes or facets.

[0146] The InGaN material coalesces over the mask layer 1703 to form a relaxed InGaN region 1704 having a planar relaxed (0001) InGaN surface 1705c. A plane 1708a, parallel to the major surface of the initial growth substrate and located proximate to the surface 1705c within the InGaN layer 1704, is primarily characterized by the InGaN in-plane a-lattice parameter a2. At the center point 1705 between the GaN seed regions, the InGaNa-lattice parameter is a2, and at the center point within the GaN seed region, the in-plane a-lattice parameter may be slightly less than a2. In a plan view (not shown), any variation in the in-plane a-lattice parameter within plane 1708b is characterized by the two-dimensional mask pattern applied to the seed layer material (see Figure 5 and Figure 6 ). Changes in the in-plane a-lattice parameter can be detected by measurement techniques such as XRD and RSM and can be resolved at the sub-micron scale. The midpoint along plane 1708b within seed region 1702a is indicated as 1708c, and the midpoint between seed regions 1702a is indicated as 1708d.

[0147] The GaN seed regions 1702a may have an in-plane dimension of, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The height of the GaN seed regions 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The distance between adjacent GaN seed regions 1702a may be, for example, less than 3 μm, less than 0.3 μm, or less than 0.03 μm. The thickness of the mask material 1703 may be, for example, 0.01 μm to 1 μm.

[0148] Figure 17B Provided by 16A to 16F A detailed cross-sectional view of the structure resulting from the process flow shown. Figure 17AThe structures shown are similar, where the same elements are identified with the same numbers. However, in Figure 17B the structure, there is no planar starting GaN (or AlN) seed layer 1702. Instead, the GaN (or AlN) seed material directly nucleates on the substrate 1701 in the openings between the mask regions 1703. The substrate can be sapphire, GaN, AlN, silicon carbide, silicon, etc.

[0149] The wurtzite group III nitride crystal semiconductor structure can include, for example: a substrate including a first substrate region and a second substrate region; a first In x1 Al y1 Ga 1-x1-y1 N growth region of first In x1 Al y1 Ga 1-x1-y1 N growth layer stacked on the first substrate region; a second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region stacked on the second substrate region; a second In x2s Al y2s Ga 1-x2s-y2s N growth region of second (0001) In x2 Al y2 Ga 1-x2-y2 N growth layer stacked on the second patterned In x2 Al y2 Ga 1-x2-y2 N growth layer, where the first (0001) In x1 Al y1 Ga 1-x1-y1 N growth region is characterized by a first in-plane a-lattice parameter; the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth region is characterized by a second in-plane a-lattice parameter; the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter; 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1; 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

[0150] The substrate can include sapphire, silicon, silicon carbide, gallium nitride, silicon on insulator, gallium oxide or aluminum nitride.

[0151] The second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region contains GaN.

[0152] The first patterned Inx1s Al y1s Ga 1-x1s-y1s The N seed region may be stacked on the first substrate region, wherein 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; and the first In x1 Al y1 Ga 1-x1-y1 The N growth layer may be stacked on the first patterned In x1s Al y1s Ga 1-x1s-y1s On the N seed region. The first pattern In x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region may include GaN. The first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region may include the same composition. x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region may comprise different compositions.

[0153] A first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region can be characterized by: the intersection of the first plane and the first edge of the second patterned seed region locates the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction; and the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the first crystal plane of the seed region. x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction may include a compositional gradation from x1s and y1s to x1 and y1.

[0154] Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region positions the second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction, where the second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the second crystal plane of the seed region. Each of the first crystal plane and the second crystal plane is crystallographically equivalent.

[0155] A first plane parallel to the (0001) plane of the wurtzite III-nitride structure and intersecting the seed region is characterized by: the intersection of the first plane and the first edge of the first patterned seed region locates a first In x2s Al y2s Ga 1-x2s- y2s N / In x2 Al y2 Ga 1-x2-y2 N heterojunction; and the first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the first crystal plane of the seed region. x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction may include a compositional grading from x2s and y2s to x2 and y2.

[0156] Any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region positions the second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 N heterojunction, where the second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2The N heterojunction is coplanar with the second crystal plane of the seed region.

[0157] The group-III nitride semiconductor structure may include: (a) a seed region including In x Ga 1-x N (0 ≤ x ≤ 1) and having a wurtzite group-III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite group-III nitride structure and intersecting the seed region, wherein the intersection of the first plane with the first edge of the seed region positions an In x Ga 1-x N / In y Ga 1-y N heterojunction, where 0 < y ≤ 1 and y > x; and an In x Ga 1-x N / In y Ga 1-y N heterojunction is coplanar with the first crystal plane of the seed region; (c) any second plane parallel to the (0001) plane of the wurtzite group-III nitride crystal structure and intersecting the second edge of the seed region positions a group-III nitride heterojunction, where the group-III nitride heterojunction is coplanar with the second crystal plane of the seed region; and (d) a relaxed (0001) InGaN region stacked on the seed region, where the relaxed (0001) InGaN region is characterized by a in-plane a-lattice parameter greater than such that each of the first crystal plane and the second crystal plane is crystallographically equivalent.

[0158] The group-III nitride semiconductor structure may include: (a) a seed region including In x Ga 1-x N (0 ≤ x ≤ 1) and having a wurtzite group-III nitride crystal structure; (b) a first plane parallel to the (0001) plane of the wurtzite group-III nitride structure and intersecting the seed region, wherein the intersection of the first plane with the first edge of the seed region positions an In x Ga 1-x N / In y Ga 1-y N heterojunction, where 0 < y ≤ 1 and y > x; and an In x Ga 1-x N / In y Ga 1-y N heterojunction is coplanar with the first crystal plane of the seed region; (c) any second plane parallel to the (0001) plane of the wurtzite group-III nitride crystal structure and intersecting the second edge of the seed region positions a group-III nitride heterojunction, where the group-III nitride heterojunction is coplanar with the second crystal plane of the seed region; and (d) a relaxed (0001) InGaN region stacked on the seed region, where the relaxed (0001) InGaN region is characterized by a in-plane a-lattice parameter greater than characterized by the in-plane a-lattice parameter, where each of the first and second crystal planes is crystallographically equivalent.

[0159] The first parallel plane can intersect two facets of the seed region. Examples are Figure 17A and Figure 17B plane 1708b in x Ga 1-x N / In y Ga 1-y N, where 0 ≤ x < 1, 0 < y ≤ 1 and y > x, or where 0 ≤ x ≤ 1, 0 < y ≤ 1 and y > x.

[0160] Any second plane parallel to the (0001) plane of the wurtzite group-III nitride crystal structure and intersecting the seed region locates a group-III nitride heterojunction. Examples are Figure 17A and Figure 17B plane 1708c in

[0161] The InGaN region is located between the seed regions. The InGaN region (or at least a portion of the InGaN region between the seed regions) can be a partially relaxed InGaN region. The InGaN region can include more than one InGaN layer or region, where each of the InGaN layers or regions has a different elemental composition. The relaxed (0001) InGaN region can be stacked on the seed region. The relaxed (0001) InGaN region can be a fully relaxed (0001) InGaN region and can have an in-plane a-lattice parameter greater than (such as to ).

[0162] The seed region may have two or more facets, such as two, three, four, five, or six facets. The seed region may have six facets. The seed region may have, for example, a rectangular base, a triangular base, a square base, a pentagonal base, or a hexagonal base. The seed region may have a triangular base or a hexagonal base. The seed region may have a hexagonal base.

[0163] Each seed region may comprise, for example, (0001) GaN and may have, for example, approximately Each seed region may contain GaN, and the edge of each seed region may be positioned with In x Ga 1-x N / GaN heterojunction, where x>0, and the III-nitride heterojunction is a GaN-InGaN heterojunction.

[0164] Each seed region may comprise, for example, (0001) GaN and may have, for example, approximately Each seed region may contain GaN, and the edge of each seed region may be positioned with Al y Ga 1-y N / GaN heterojunction, where x>0, and the III-nitride heterojunction is a GaN-AlGaN heterojunction.

[0165] Each seed region may contain, for example, (0001)In x Ga 1-x N, and may have, for example, a value greater than Each seed region may contain In x Ga 1-x N, and the edge of each seed region can be positioned In x Ga 1-x N / In y Ga 1-y N heterojunction, where x>y, and the III-nitride heterojunction is an InGaN-InGaN heterojunction.

[0166] Each seed region may contain, for example, In x1 Al y1 Ga 1-x1-y1 N (0≤x1<1, 0≤y1<1, x1+y1≤1) and wurtzite III-nitride crystal structure. Each seed region may contain In x1 Al y1 Ga 1-x1-y1 N, and the edge of each seed region can be positioned In x1 Al y1 Ga 1-x1-y1 N / In x2 Al y2 Ga 1-x2-y2N heterojunction, where 0≤x2<1, 0≤y2<1, x2+y2≤1 and x2>x1, and is a (In)(Al)GaN / (In)(Al)GaN heterojunction.

[0167] Figure 18 to Figure 20 Aspects of the present invention are illustrated. Figure 18A 、 Figure 18B and Figure 18C A schematic plan view of a so-called "v-pit" structure that can form in III-nitride growth on a basal plane is shown. In particular, for III-nitride materials grown at low temperatures (e.g., GaN grown using MOCVD at temperatures below 800°C), the adatom dynamics are such that the semiconductor material tends not to fill in near the dislocation nucleus, causing the pit to form from a stable (10-11) plane with the dislocation nucleus at the center. As growth continues at low temperatures, the pit becomes larger ( Figure 18B ) and emits a collision ( Figure 18C As the pits become larger, the total surface area of ​​the exposed (10-11) facets becomes comparable to or even larger than that of the exposed (0001) surfaces. The presence of this large surface area of ​​(10-11) facets, where each facet is crystallographically equivalent, provides an opportunity to form high-quality relaxed InGaN on a (10-11) seed surface (e.g., GaN), as contemplated in the present invention.

[0168] For example, Figure 19 As shown, GaN can be nucleated at low temperatures onto a suitable substrate (such as GaN, sapphire, Si, SiC, AlN, etc.). After achieving a fairly high-quality GaN epitaxial film (e.g., by growing the GaN epitaxial film at an elevated temperature (e.g., above 900°C)), the growth conditions can be changed again so that v-pits are formed (e.g., by growing the GaN at a temperature below 800°C). The growth can then be terminated, the growth structure removed from the MOCVD reactor, and a suitable growth mask layer (such as SiO2 or SiN) can be selectively deposited on the (0001) GaN surface (but not on the (10-11) GaN surface). xThe dielectric layer). This can be achieved in various ways, such as by using high angle sputtering or deposition, or by selectively depositing a photoresist into the V-pits, followed by, for example, deposition and stripping. The GaN structure can then be returned to a reactor, such as an MOCVD or MBE reactor. InGaN can then be selectively grown on the exposed GaN seed region material on the (10-11) facet (optionally preceded by deposition of a thin layer of GaN). The InN mole fraction can be targeted to induce large strain, and therefore relaxation, as the thickness of the InGaN layer increases. The InGaN can be allowed to continue growing out over the mask region and coalesce with InGaN grown from the adjacent seed region, providing a planar, high quality, relaxed (0001) InGaN region and surface that can act as a template for device fabrication, as described in the present disclosure. InGaN layers can be grown at temperatures higher than typical temperatures for InGaN / GaN growth, such as at temperatures above 900°C. This is possible because relaxed InGaN material incorporates In much more easily than InGaN as a pseudomorphic form of GaN. The increased growth temperature allows for filling of v-pit defects and provides agglomerated planar films. Control of the morphology and composition uniformity of relaxed InGaN growth can be facilitated by growing a multilayer structure rather than by using a monolithic InGaN layer. For example, 3nm GaN can be grown with 1nm InN or 2nm GaN with 2nm In 0.5 Ga 0.5 The 25% overall InGaN layer is replaced by alternating layers of N. The layer thickness of the individual layers can range from 0.5 nm to 100 nm, such as 1 nm to 30 nm. Multiple periods of such a multilayer structure can be used, such as 2 to 10 layers, 2 to 100 layers, or more than 100 layers.

[0169] In another example, the masking step can be eliminated and the entire process can be done in situ in the growth chamber. Figure 20As shown, GaN can be nucleated onto a suitable substrate such as GaN, sapphire, Si, AlN, etc. After achieving a fairly high quality GaN epitaxial film (e.g., by growing at an elevated temperature (e.g., >900°C)), the growth conditions can be changed again so that v-pits are formed, for example, by growing the GaN at a temperature below 800°C. The v-pits can be grown so that the exposed surface area of ​​the {10-11} equivalent facets is greater than the exposed surface area of ​​the (0001) GaN. The exposed surface area of ​​the (10-11) facets can be more than twice the exposed surface area of ​​the (0001) GaN, for example, ten times the exposed surface area of ​​the (0001) GaN. InGaN can then be selectively grown on the (10-11) facets as seed regions. The InN composition can be targeted to induce large strain and therefore relaxation as the thickness of the InGaN layer increases, thereby exceeding the critical thickness. The InGaN growth may be allowed to continue to grow out and coalesce with InGaN grown from an adjacent seed region, providing a planar, high quality relaxed (0001) InGaN region that can serve as a template for device fabrication.

[0170] Because the (0001) GaN growth surface area is smaller than the (10-11) growth surface area, the latter growth mode dominates, allowing the InGaN to relax and become the dominant growth surface as the film thickness increases. It can be useful to grow InGaN layers at temperatures higher than the typical temperatures for InGaN / GaN growth. This is possible because the relaxed InGaN material can incorporate In much more easily than InGaN, which is a pseudomorphic form of GaN. The increased growth temperature allows the v-pit defects to be filled to provide agglomerated planar films. The morphology and composition uniformity of the relaxed InGaN growth can be controlled by growing a multilayer structure rather than by using a monolithic InGaN layer. For example, 3nm GaN can be grown with 1nm InN or 2nm GaN with 2nm In 0.5 Ga 0.5 The 25% overall InGaN layer is replaced by alternating layers of N. The layer thickness of the individual layers can range from 0.5 nm to 100 nm, such as 1 nm to 30 nm. Multiple periods of such a multilayer structure can be used, such as 2 to 10 layers, 2 to 100 layers, or more than 100 layers.

[0171] For example, a c-plane (0001) sapphire substrate can be loaded into an MOCVD reactor capable of supplying at least trimethylgallium, trimethylindium, and ammonia. A low-temperature GaN nucleation layer can be provided, followed by higher-temperature GaN growth (which may include three-dimensional island formation and then coalescence into a two-dimensional (0001) GaN film). This three-dimensional to two-dimensional transition helps to redirect threading dislocations laterally and helps reduce the total threading dislocation density at the growth surface, which can be reduced to less than 1E9 cm -2 Finally, 1E8cm can be achieved in a planar GaN layer. -2 Next, the growth temperature can be lowered (e.g., below 800°C) to form a v-pit structure characterized by tilted (10-11) planes at the dislocation cores. These planes can form an angle of about 63 degrees relative to the (0001) growth surface. The thickness of the low temperature layer controls the v-pit height and increases through growth so that the total surface area of ​​the exposed {10-11} facets is greater than the surface area of ​​the (0001) as shown in Table 3 for this particular example.

[0172] Table 3. Examples of growth structures.

[0173]

[0174] For example, at 1E8cm -2 In the case of a dislocation density of 0.1 μm, the target V-pit height can be 0.14 μm or greater.

[0175] This can be achieved through various mechanisms, such as starting with a lower dislocation density substrate (such as a “freestanding” GaN substrate) and by using various threading dislocation filtering methods (such as in situ SiN x By these means and other means known in the art, the dislocation density can be reduced to less than 1E7 cm -2 , less than 1E6cm -2 And even smaller than 1E5cm -2 Such lower dislocation densities are particularly beneficial for the performance and reliability of laser diodes.

[0176] After achieving the desired surface area ratio between the (10-11) and (0001) materials, trimethylindium (TMI) is flowed into the chamber to grow one or more InGaN layers on the (10-11) seed region and induce strain relaxation. The InGaN layers can be periodically alternating with the GaN layers. For example, each InGaN layer can be 0.5nm to 100nm thick (such as 1nm to 30nm thick) and can be sandwiched between GaN layers of similar thickness. In order to induce strain relaxation, the average composition of the strain-relaxed layer should be sufficiently high, for example, the average InN content can be greater than 5%. After or before strain relaxation begins, the growth temperature can be increased to help flatten the growth and achieve a planar, uniform, relaxed (0001) InGaN layer for device fabrication.

[0177] Planarization techniques are applicable not only to this embodiment but to all embodiments disclosed herein, including changing growth conditions (such as growth temperature, V / III ratio) and using dopants (e.g., Mg doping) to promote lateral growth compared to vertical growth. In addition, composition can also play a role, including using multilayer films (as described elsewhere in this specification) to promote planarization of epitaxial films.

[0178] While the above discussion focuses on V-pits that rely on dislocation nuclei for formation, other methods of forming semipolar facets throughout a III-nitride base material or substrate can also be employed, such as annealing and decomposition techniques designed to expose specific growth planes within the system. These techniques do not necessarily rely on dislocation nuclei and can provide techniques for providing the desired seed region facets without relying on dislocations.

[0179] It is important to note that while the above discussion refers to GaN seed regions, InGaN (or AlGaN) seed regions can also be utilized, provided that the material is a pseudomorphic form of any underlying GaN layers (e.g., GaN nucleation and / or buffer layers). The seed region is the region near the InGaN-GaN (or InGaN-InGaN) heterojunction where relaxation is ultimately induced. The seed material beneath these regions is referred to as the seed material rather than the seed region.

[0180] The relaxed InGaN layer provided by the present disclosure and the semiconductor structure including the relaxed InGaN layer can be used to manufacture electronic and optoelectronic devices, including InGaN-based optoelectronic devices such as LEDs, LDs and VCSELs. LEDs and LDs including the relaxed InGaN layer provided by the present disclosure can be used in lighting systems and display systems. In particular, for LEDs, the device can be formed on a relaxed InGaN base layer stacked on a substrate. The substrate can be thinned by techniques such as grinding, polishing or etching, and can be sliced ​​by methods known in the art (such as sawing, scribing and breaking or laser scribing and breaking) to provide individual LED chips or dies. More common LED chip or die sizes can be, for example, 100×100 μm 2 Up to 5×5mm 2 Micro LEDs can have dimensions below 100 × 100 μm. 2 to less than 0.5×0.5μm 2 device size. The individual LED chips can then be attached to a suitable packaging element that provides leads for making electrical contact to the device and dissipating heat. Die attachment can be achieved using any suitable method, such as epoxy or silicone attachment, solder-based attachment, or, in the case of small devices (such as, for example, micro-LEDs having a size of less than 30 μm), mass transfer techniques. Electrical connection for the chip to the package can be made using bonding wires (such as Au or Ag wires) to connect the anode and cathode leads in the package to the corresponding contact metallizations (i.e., electrodes) on the LED chip. In the case of a flip-chip device, the electrical connection can be made by an intermediary submount positioned between the LED chip and the package. The chip electrodes can be attached to the submount carrier by means such as solder attachment or Au bump attachment. The submount carrier can be sliced ​​and then mounted into the package by any suitable method.

[0181] The desired emission color from the packaged LED device is obtained by manufacturing and providing relaxed InGaN-based LEDs having the desired peak emission wavelength. Multiple such LED chips (optionally with different peak emission wavelengths) can be included in separate packages or combined together in a multi-chip package. For example, a single package can include red-emitting, green-emitting, and blue-emitting LED chips that can be arranged in a circuit and electrically coupled to a driver circuit inside or outside the package to operate the LED. The circuit details and drivers can be selected to allow the different colors of LEDs to be operated independently or together to provide a wide range of overall emission characteristics, including white light emission for use in lighting applications or for use as a backlight for liquid crystal display (LCD) devices (such as television displays, computer monitors, mobile phone displays, wearable display devices, etc.).

[0182] One or more LED chips can be combined with luminescence down conversion materials to provide a desired emission spectrum. Such luminescence down conversion materials may include phosphors, semiconductor nanoparticles (such as quantum dots) or perovskite materials. Multiple luminescence down conversion materials can be combined together in a single package. The LED chip emission wavelength can be selected to excite the luminescence down conversion material so that the emission from the package is a combination of direct emission from the LED chip and emission from the luminescence down conversion material, or the emission may be mainly just the emission of the luminescence down conversion material, wherein most of the LED chip light is completely absorbed by the luminescence down conversion material or is otherwise blocked or filtered and cannot be emitted from the package. Packaged LEDs using luminescence down conversion materials can be used to produce white light that is useful in lighting applications. Such devices can be electrically coupled to a drive circuit powered by an external power source (such as a mains power supply or battery power), thermally coupled to a heat sink, and optically coupled to various optical devices or lenses to provide a lighting device (such as an LED lamp or LED lamp).

[0183] The present invention can be used to manufacture LED chips with smaller sizes. In particular, LED chips with a size of 0.5×0.5 μm can be manufactured. 2 Up to 50×50μm 2 Devices of the size of a microLED (so-called "microLEDs"). For microLEDs, conventional slicing techniques are less applicable, and therefore other means for separating the devices may be employed. For example, separation may be achieved by forming LEDs of the desired size on a substrate, and then bonding the top surface of the LEDs to a carrier (such as blue tape or a submount carrier), and then removing the substrate. The individual devices may then be picked up and placed into a package component or into the backplane of a microLED-based display. Advanced die processing techniques as known in the art may be used to process microLED devices. In particular, red-emitting, green-emitting, and blue-emitting LEDs based on the present invention may be formed into microLEDs and arranged to provide microLED displays, and incorporated into systems such as televisions, computer monitors, tablets, mobile phones, wearable devices, and the like. Generally speaking, other separation techniques besides conventional slicing include laser cutting, stealth slicing, chemical etching, and plasma etching.

[0184] The LDs provided by the present disclosure that incorporate relaxed InGaN layers can also be incorporated into various systems. The LD packages are similar to the LED packages as described herein, except that a means is provided for managing the higher power density in the LD device from a thermal perspective, and a means is provided for optically accessing the laser facets. LDs of multiple emission colors can be provided in separate packages or combined into a single package. The LDs can be coupled to luminescent down-conversion materials to provide the desired emission spectrum. LDs are useful in applications where extremely high light density is required, such as in automotive headlight systems or projection displays that may include light modulation devices (such as grating optics, micromirror devices, and LCD modulators).

[0185] Figure 11 and Figure 12 Examples of lighting and display systems are shown separately.

[0186] Controlled crystal lattice engineering, such as that described in the preceding paragraph, can be utilized to achieve the deposition of high-quality, variable-composition III-V compound semiconductor alloys on the same growth substrate. "Controlled crystal lattice engineering" refers to the ability to fabricate high-quality relaxed III-V material layers using patterned growth layers that allow for the incorporation of varying InN contents determined by the configuration of the patterned growth layers to provide optoelectronic devices configured to emit radiation within a desired wavelength range.

[0187] In a method for fabricating a multicolor optoelectronic device, groups of optoelectronic elements can be fabricated sequentially on the same growth substrate (such as a GaN layer), wherein each optoelectronic element within the group is characterized by a similar in-plane a-lattice parameter and a similar InN content. For example, a first group of optoelectronic elements can be fabricated on a first portion of the growth substrate, a second group of optoelectronic elements can be fabricated on a second portion of the growth substrate, and a third group of optoelectronic elements can be fabricated on a third portion of the growth substrate. Each of the first, second, and third groups of optoelectronic elements can be characterized by a different in-plane a-lattice parameter and a different InN content, and can be configured to emit radiation within a different wavelength range.

[0188] For example, Figure 21 As shown, a first wavelength (λ1) optoelectronic element 2103a may be grown on a suitable substrate, which may include a conventional GaN buffer layer 2102 having an in-plane a-lattice parameter a0.

[0189] The substrate may be masked and etched to expose the first region 2102a of the GaN buffer layer 2102 .

[0190] An optional first relaxed InGaN growth layer (including pattern 1) 2104a can be deposited to overlie the first region 2102a of the GaN buffer layer 2102, such that the top (0001) InGaN growth region 2110a of the first relaxed InGaN growth layer 2104a has an in-plane a-lattice parameter a1 ≥ a0. The in-plane a-lattice parameter of the overlying InGaN layer will adopt an in-plane a-lattice parameter a1 ≥ a0. Epitaxial layers (such as an n-type InGaN layer 2105a, an active layer 2106a, and a p-type InGaN layer 2107a) can be deposited or overlie the first relaxed (0001) InGaN surface 2110a of the first relaxed InGaN growth layer 2104a to provide a first optoelectronic element 2103a.

[0191] Alternatively, the relaxed InGaN growth layer may not overlie the first region 2102a of the GaN buffer layer 2102, and the epitaxial layers of the optoelectronic element may be grown directly on the GaN buffer layer 2102 and will assume a pseudomorphic form of GaN with an in-plane a-lattice parameter a0.

[0192] After fabricating the first photovoltaic element 2103a, the wafer including the first photovoltaic element may be masked and etched to expose the second region 2102b of the GaN buffer layer 2102, thereby allowing for the growth of a second relaxed InGaN growth layer and a (0001) InGaN growth region under optimized conditions. A second relaxed InGaN growth layer (including pattern 2) 2104b may be deposited to overlie the second region 2102b of the GaN buffer layer 2102, allowing for a controlled degree of lattice relaxation, such that the in-plane a-lattice parameter of the layer is a2, which is greater than a1.

[0193] Epitaxial layers may be deposited on or above the second relaxed (0001) InGaN surface 2110b of the second relaxed (0001) InGaN growth region 2110b to provide a second optoelectronic element 2103b. The in-plane a-lattice parameter of the overlying InGaN layer will be a2, which is greater than a1. Epitaxial layers (such as an n-type InGaN layer 2105b, an active layer 2106b, and a p-type InGaN layer 2107b) may be deposited to overlying the second relaxed InGaN growth layer 2104b to provide a second optoelectronic element 2103b.

[0194] After fabricating the second optoelectronic element 2103b, the wafer may be masked and etched to expose the third region 2102c of the GaN buffer layer 2102, thereby enabling the growth of a third relaxed InGaN growth layer 2104c on the third region 2102c of the GaN buffer layer 2102 under optimized conditions.

[0195] A third relaxed InGaN growth layer (including pattern 3) 2104c can be deposited onto the third region 2102c of the GaN buffer layer 2102 to allow a controlled degree of further lattice relaxation so that the in-plane a-lattice parameter of the (0001) InGaN growth region 2110c of the third relaxed InGaN growth layer 2104c is a3 which is greater than a2.

[0196] Then, epitaxial layers can be deposited on or above third relaxed (0001) InGaN surface 2110c of third relaxed (0001) InGaN growth region 2110c to provide third optoelectronic element 2103c. The in-plane a-lattice parameter of the stacked layers will be a3, which is greater than a2. Epitaxial layers (such as n-type InGaN layer 2105c, active layer 2106c, and p-type InGaN layer 2107c) can be deposited to overlie third relaxed InGaN growth layer 2104c to provide third optoelectronic element 2103c.

[0197] Each of the relaxed InGaN growth layers 2104a / 2104b / 2104c can include different patterns configured such that the (0001) InGaN growth surface 2110a / 2110b / 2110c of each of the corresponding relaxed InGaN growth layers 2104a / 2104b / 2104c is characterized by a different in-plane a-lattice parameter and a different InN content. Additionally, at least one of the layers may not include patterning. The relaxed InGaN growth layers can be configured to impart different in-plane a-lattice parameters and different InN mole fractions to the overlying epitaxial layers (such as the InGaN layers). The different InN mole fractions of the active layer will result in an optoelectronic element capable of emitting radiation in different wavelength ranges.

[0198] Each of the relaxed InGaN growth regions 2104a / 2104b / 2104c includes a relaxed (0001) InGaN surface 2110a / 2110b / 2110c superposed on a relaxed (0001) InGaN region. The relaxed (0001) InGaN region superposes a partially relaxed InGaN region (superimposed on the seed region).

[0199] The structure, pattern, and / or elemental composition of each of the seed regions for each of the relaxed InGaN growth regions 2104a / 2104b / 2104c can independently be the same or different, depending on the selected emission wavelength. An optoelectronic device can include multiple optoelectronic elements capable of emitting radiation within a specific wavelength range.

[0200] For example, reference Figure 21, the multi-color optoelectronic device may include a plurality of optoelectronic elements 2103a, a plurality of optoelectronic elements 2103b, and a plurality of optoelectronic elements 2103c. The optoelectronic elements 2103a / 2103b / 2103c may be arranged to form pixels. The multi-color optoelectronic device may include, for example, 1 to 10 or 1 to 3 subgroups of optoelectronic elements having a relaxed (0001) InGaN region provided by the present disclosure, wherein each subgroup includes a plurality of optoelectronic elements capable of emitting radiation of different wavelengths. For example, the optoelectronic device may include 3 subgroups of optoelectronic elements having a relaxed (0001) InGaN region provided by the present disclosure, wherein each subgroup includes a plurality of optoelectronic elements capable of emitting radiation of different wavelengths. For example, the multi-color optoelectronic device may include 2 subgroups of optoelectronic elements having a relaxed (0001) InGaN region provided by the present disclosure, wherein each subgroup includes a plurality of optoelectronic elements capable of emitting radiation of different wavelengths.

[0201] In a multicolor optoelectronic device capable of emitting at multiple wavelengths, the composition of the relaxed (0001) InGaN surface overlying the relaxed (0001) InGaN region will be different for each wavelength.

[0202] In another method for fabricating a multicolor optoelectronic device, a relaxed InGaN growth layer overlying a GaN buffer layer may include groups of InGaN growth layers, wherein each group of relaxed InGaN growth layers is agglomerated and characterized by relaxed (0001) InGaN growth regions having different in-plane a-lattice parameters and different InN contents. An epitaxial layer may then be deposited overlying the relaxed InGaN growth layers to provide groups of optoelectronic elements overlying the respective groups of relaxed InGaN growth layers, wherein each group of optoelectronic elements is configured to emit radiation within a different wavelength range.

[0203] The first optoelectronic element may include a first InGaN active layer and a second InGaN active layer, wherein the first active layer is characterized by a first in-plane a-lattice parameter; the second InGaN active layer is characterized by a second in-plane a-lattice parameter; and wherein the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter. For example, the second in-plane a-lattice parameter may be greater than the first in-plane a-lattice parameter. big big or large For example, the a-lattice parameter in the second plane may be larger than the a-lattice parameter in the first plane. to For example, the a-lattice parameter in the second plane may be larger than the a-lattice parameter in the first plane. to or to

[0204] Figure 22 is a graph showing the relationship between the peak emission wavelength of a light emitting diode and the in-plane a-lattice parameter of the corresponding active layer. Figure 22 Typical MOCVD growth temperatures (T g )(Line 2201) at T g -20K (line 2202), at T g -40K (line 2203) and at T g At +20K (line 2204), the relationship between the in-plane a-lattice parameter of the active region and the peak emission wavelength of the light-emitting diode. For example, at T g, with about The active region with an in-plane a-lattice parameter of will have a peak emission wavelength of about 458 nm, with a wavelength of about The active region with an in-plane a-lattice parameter of will have a peak emission wavelength of about 528 nm and has a wavelength of about The active region of an LED having an in-plane a-lattice parameter of 100 nm will have a peak emission wavelength of approximately 635 nm. The InGaN alloy band edge is shown as line 2205. The data associated with lines 2206 and 2207 represent the peak emission wavelength of an LED having an in-plane a-lattice parameter of 100 nm (as presented by Even et al., Applied Physics Letters 110, 262-103, 2017) at T g At a temperature of -20K (line 2206) and at T g Experimental measurement results of the peak emission wavelength at (line 2207).

[0205] Controlled crystal lattice engineering allows the growth of light-emitting active regions with different emission wavelengths on a single wafer, such as light-emitting diodes (LEDs), superluminescent diodes, laser diodes (LDs), and vertical cavity surface-emitting lasers (VCSELs). Because the lattice engineering can be controlled at the submicron level within the selected growth region, monochromatic active regions can be fabricated at the micron or even submicron level on a single wafer.

[0206] Controlled crystal lattice engineering can also be used to achieve the simultaneous deposition of high-quality, variable-composition III-V compound semiconductor alloys. This allows the growth of light-emitting active regions with different emission wavelengths, such as light-emitting diodes (LEDs), superluminescent diodes, laser diodes (LDs), and vertical-cavity surface-emitting lasers (VCSELs), in a single epitaxial deposition process.

[0207] As described above, controlled crystal lattice engineering can be used to fabricate high-quality optoelectronic components and devices on large-area wafers, where each of the multiple optoelectronic components is configured to emit radiation within substantially the same wavelength range. In this method, the epitaxial layers comprising the optoelectronic components are grown on a patterned growth layer having a single pattern across the wafer surface.

[0208] Controlled crystal lattice engineering can be extended to the manufacture of optoelectronic elements configured to emit radiation in different wavelength ranges. In this manufacturing method, the relaxed InGaN growth layer may include multiple GaN seed regions with different pattern configurations (e.g., feature size, shape, and spacing). InGaN grows on the growth surface of the GaN seed region. Continued InGaN growth will cause InGaN grown from adjacent GaN seed regions and from relaxed InGaN regions between the GaN seed regions to coalesce. Further InGaN growth will cause relaxed InGaN regions superimposed on the GaN seed region and having a (0001) InGaN growth region characterized by an in-plane a-lattice parameter. Depending on the configuration of the GaN seed region, the coalesced relaxed InGaN growth layer will have different in-plane a-lattice parameters and incorporate different amounts of InN into the crystal lattice of the III-V semiconductor. Optoelectronic elements grown stacked on different relaxed InGaN growth layers can emit radiation in a wavelength range consistent with the incorporated InN content.

[0209] As described herein, dielectric materials such as SiO can be selectively formed using any suitable semiconductor deposition, lithography (including nanolithography), and etching techniques. x 、SiN x or AlO x ) to pattern the III-nitride epitaxial layers on the growth substrate or GaN buffer layer. The degree of patterning is intentionally selected to produce a desired in-plane strain state in the superimposed InGaN layer. For example, the growth of InGaN on an unpatterned (0001) GaN seed layer can result in an superimposed strained InGaN layer that is lattice matched to the GaN (i.e., a pseudomorphic form of GaN). The growth of InGaN on a densely patterned GaN seed region can result in a superimposed InGaN layer that is substantially relaxed and characterized by an in-plane a-lattice parameter that is close to the parameter of a fully relaxed InGaN layer of the same composition. Finally, a region with a pattern density between the pattern density of an unpatterned GaN seed region and that of a densely patterned GaN seed region can exhibit an in-plane a-lattice parameter of partially relaxed InGaN.

[0210] Control of the in-plane a-lattice parameter allows active regions of different compositions to have similar strain states that are optimal for device performance. For example, the optimal strain state for InGaN-based emitters is between about 1% and about 2% compressive strain, regardless of the emission wavelength. One way to make emitters exhibit similar beneficial strain states while allowing the InGaN composition of the corresponding active regions to differ and thus emit at different wavelengths (such as from the blue to green to red wavelength range) is to adjust the in-plane a-lattice parameter of the underlying material on which the InGaN-based emitter is grown.

[0211] The III-nitride epitaxial layer on the growth substrate can be selectively patterned with a dielectric material using known deposition, lithography (including nanolithography), and etching techniques to define GaN seed regions. The patterning can be intentionally selected to produce a desired strain state in the relaxed InGaN growth layer grown on the multiple GaN seed regions.

[0212] Because the in-plane a-lattice parameters of the relaxed InGaN growth layers overlying the various patterned GaN seed regions are different, even if the epitaxial TMI / III ratio and growth temperature used to deposit the InGaN layer overlying each of the corresponding relaxed InGaN growth layers are the same, the mole fraction of InN incorporated into each relaxed InGaN growth layer will be different. Using this method, multi-color active regions can be selectively grown simultaneously with micron or even submicron resolution on a single growth substrate in a single growth process.

[0213] Figure 23 The epitaxial layers of a multicolor optoelectronic structure are shown at an intermediate step in the fabrication process.

[0214] like Figure 23 As shown, three different relaxed InGaN growth layers 2304a / 2304b / 2304c can be grown stacked on a growth substrate such as a GaN buffer layer 2302. The three relaxed InGaN growth layers 2304a / 2304b / 2304c include GaN seed regions with different patterns (such as, for example, in terms of size, shape, and fill factor). The InGaN grown on the differently patterned GaN seed regions will coalesce to form relaxed InGaN regions having corresponding (0001) InGaN growth regions 2310a / 2310b / 2310c characterized by different in-plane a-lattice parameters and different InN mole fractions. Note that, as Figure 23 As shown, region 2304a may include GaN and have an in-plane a-lattice parameter of a1 = a0. Region 2304a may include a relaxed (0001) InGaN region having an in-plane a-lattice parameter of a1 > a0.

[0215] Because the in-plane a-lattice parameters of the two or three (0001) InGaN growth regions 2310a / 2310b / 2310c are different, the epitaxial InGaN layer including the active region grown to be superimposed on the three (0001) InGaN growth regions will be characterized by different in-plane a-lattice parameters and different InN mole fractions.

[0216] In a first step in an example of a fabrication process for preparing a multicolor optoelectronic structure, a GaN buffer layer 2302 characterized by an in-plane a-lattice parameter a0 may be deposited onto a substrate 2301 .

[0217] Separate relaxed InGaN growth layers 2304a / 2304b / 2304c can be independently deposited onto discrete portions of the GaN buffer layer 2301. Figure 23 As shown, the relaxed InGaN growth layer 2304 includes three relaxed InGaN growth layers 2304a / 2304b / 2304c. Examples of relaxed InGaN growth layers are shown in FIG. Figure 6 、 Figure 13 Figures 15 to 17 Figure 19 and Figure 20 Each relaxed InGaN growth layer may include a patterned GaN seed region, a patterned mask region, a relaxed InGaN region, and a partially or substantially relaxed (0001) InGaN region.

[0218] The configuration of the patterned GaN seed region and the patterned mask region can be different for each set of relaxed InGaN growth layers. The configuration of the patterned GaN seed region and the patterned mask region can be selected so that each set of relaxed InGaN growth layers 2304a / 2304b / 2304c is configured to emit radiation within a selected wavelength range.

[0219] For example, each relaxed InGaN growth layer in the first set of relaxed InGaN growth layers may include the same or similar GaN seed region pattern and may be configured to emit radiation in a first wavelength range, such as in the red wavelength range of 625 nm to 740 nm.

[0220] For example, each relaxed InGaN growth layer in the second set of relaxed InGaN growth layers may include the same or similar GaN seed region pattern and may be configured to emit radiation in a second wavelength range, such as in the green wavelength range of 515 nm to 570 nm.

[0221] For example, each relaxed InGaN growth layer in the third set of relaxed InGaN growth layers can include the same or similar GaN seed region pattern and can be configured to emit radiation in a third wavelength range, such as in the blue wavelength range of 400 nm to 495 nm.

[0222] Different groups of relaxed InGaN growth layers can be configured in a regular array and / or can be configured to form pixels stacked on a substrate. The configuration or arrangement can be Cartesian or can be triangular (i.e., triangular or hexagonal relationship). Multiple relaxed InGaN growth layers can be configured in an interwoven array.

[0223] The pattern of each set of relaxed InGaN growth layers can differ, for example, with respect to the pitch of the GaN seed structure, the height / depth of the GaN seed structure, the geometry of the GaN seed structure, the lateral dimensions of the GaN seed structure, and / or the growth facets of the GaN seed structure.

[0224] exist Figure 23 In the multi-color optoelectronic device shown, there are three different relaxed InGaN growth layers 2304a / 2304b / 2304c, each of which has a corresponding relaxed (0001) InGaN growth region 2310a / 2310b / 2310c, which have relaxed (0001) InGaN surfaces characterized by different in-plane a-lattice parameters and different InN mole fractions.

[0225] like Figure 23 As shown, the relaxed (0001) InGaN growth region 2310a and the relaxed (0001) InGaN surface of the relaxed InGaN growth layer 2304a may have an in-plane a-lattice parameter a1 that is greater than or equal to the in-plane a-lattice parameter of the GaN buffer layer 2302. The epitaxial layers (including, for example, an n-type InGaN layer 2305a, an active region 2306a, and a p-type InGaN layer 2307a) grown to overlie the (0001) InGaN growth region 2310a of the relaxed InGaN growth layer 2304a will have an in-plane a-lattice parameter a1 commensurate with the mole fraction of InN capable of emitting radiation within the first wavelength range.

[0226] like Figure 23As shown, the relaxed (0001) InGaN growth region 2310b and the relaxed (0001) InGaN surface of the relaxed InGaN growth layer 2304b may have an in-plane a-lattice parameter a2 that is greater than a1. Epitaxial layers (including, for example, n-type InGaN layer 2305b, active region 2306b, and p-type InGaN layer 2307b) grown to overlie the (0001) InGaN growth region 2310b of the relaxed InGaN growth layer 2304b will have an in-plane a-lattice parameter a2 that is commensurate with the mole fraction of InN capable of emitting radiation in the second wavelength range.

[0227] like Figure 23 As shown, the relaxed (0001) InGaN growth region 2310c and the relaxed (0001) InGaN surface of the relaxed InGaN growth layer 2304c may have an in-plane a-lattice parameter a3 that is greater than a2. The epitaxial layers (including the n-type InGaN layer 2305c, the active region 2306c, and the p-type InGaN layer 2307c) grown to overlie the (0001) InGaN growth region 2310c of the relaxed InGaN growth layer 2304c will have an in-plane a-lattice parameter a3 commensurate with the mole fraction of InN capable of emitting radiation in the third wavelength range.

[0228] The structure may include additional sets of relaxed InGaN growth layers configured to emit radiation in additional wavelength ranges.

[0229] The relaxed InGaN growth layer can be fabricated as described herein to provide a (0001) InGaN growth region having a desired InN mole fraction and in-plane a-lattice parameter.

[0230] For example, Figure 23 As shown, a first optoelectronic structure configured to emit radiation at a wavelength λ1 may be grown on a suitable substrate or a conventional GaN buffer layer having an in-plane a-lattice parameter a0.

[0231] An optional first mask (Pattern 1) can be deposited overlying the first region 2304a of the GaN buffer layer 2302 while different mask patterns (Pattern 2 and Pattern 3) are simultaneously deposited in regions 2304b and 2304c.

[0232] The wafer may then be etched to expose the GaN buffer layer 2302 in each patterned GaN seed region.

[0233] After exposing the GaN buffer layer in each region, epitaxial growth is performed to form a GaN seed region in each of the patterned regions. Once the GaN seed region is formed, growth switches to InGaN to coalesce on the patterned GaN seed region and form a (0001) InGaN growth region 2310a / 2310b / 2310c of each of the corresponding relaxed InGaN growth layers 2304a / 2304b / 2304c. Depending on the patterning of the GaN seed region, different (0001) InGaN growth regions will have different a-lattice parameters. Subsequently, and still in a single epitaxial deposition process, an n-type InGaN layer 2305 can be deposited to overlay each of the (0001) InGaN growth regions. The n-type InGaN layer 2305 includes three n-type InGaN regions 2305a / 2305b / 2305c, which are characterized by different in-plane a-lattice parameters and different InN mole fractions commensurate with the corresponding underlying (0001) InGaN growth regions 2310a / 2310b / 2310c of the relaxed InGaN growth layer 2304a / 2304b / 2304c.

[0234] The portion of the n-type InGaN layer 2305a stacked on the relaxed InGaN growth layer 2304a may have an in-plane a-lattice parameter a1, where a1>a0, the portion of the n-type InGaN layer 2305b stacked on the relaxed InGaN growth layer 2304b may have an in-plane a-lattice parameter a2, where a1>a2, and the portion of the n-type InGaN layer 2305c stacked on the relaxed InGaN growth layer 2304c may have an in-plane a-lattice parameter a3, where a3>a2.

[0235] After depositing the n-type InGaN layer 2305, an active layer 2306 can be deposited in the same single epitaxial deposition process to overly the n-type InGaN layer 2305. The active layer 2306 can include a single epitaxial layer or multiple epitaxial layers. The active layer 2306 can include active regions 2306a / 2306b / 2306c having an in-plane a-lattice parameter and InN mole fraction commensurate with corresponding portions of the underlying n-type InGaN layer 2205 and the growth surface 2310 of the relaxed InGaN growth layer 2304a / 2304b / 2304c.

[0236] After depositing the active layer 2306, a p-type InGaN layer 2307 can be deposited in a single epitaxial deposition process overlying the active layer 2306. Like the underlying layers, the p-type InGaN layer 2307 can include a p-type InGaN region (not labeled) having an in-plane a-lattice parameter and InN content commensurate with the underlying active layer, the n-type InGaN layer, and the growth surface 2310 of the relaxed InGaN growth layer 2304a / 2304b / 2304c.

[0237] Figure 23 The semiconductor structure shown may include additional epitaxial layers, such as cladding layers, electron blocking layers, reflective layers, and the like.

[0238] exist Figure 23 , three different optoelectronic elements corresponding to relaxed InGaN growth layers 2304a / 2304b / 2304c, n-type InGaN regions 2305a / 2305b / 2305c, active regions 2306a / 2306b / 2306c, and p-type InGaN regions 2307a / 2307b / 2307c characterized by different in-plane a-lattice parameters and InN mole fractions are shown. However, more than three different relaxed InGaN growth layers having different relaxed (0001) InGaN growth regions can be fabricated on a wafer. The relaxed InGaN growth layers can be configured to form pixels. Multiple relaxed InGaN growth layers can be configured in an interleaved array.

[0239] The InGaN growth layer may include a region that does not include a patterned GaN seed region, in which case the (0001) InGaN growth region and the overlying epitaxial layer are pseudomorphic forms of GaN. This is reflected in Figure 23 , where region 2304 can be an unpatterned GaN seed region, and the n-type InGaN region can be a pseudomorphic form of GaN and characterized by the same in-plane a-lattice parameter a0 as GaN without In.

[0240] Afterwards, you can Figure 23 The semiconductor structure shown is processed to isolate the individual photovoltaic elements and add electrodes.

[0241] The wafer may then be etched and metallized to provide electrical contacts.

[0242] Transparent conductive oxide (TCO) (eg, indium-tin-oxide (ITO)) electrical contacts may be used in an "epitaxial-up" configuration on the p-type InGaN layer 2307. Alternatively, reflective contacts, such as Ag-based contacts, may be used in an inverted configuration.

[0243] The cathodes may be connected in common or may be isolated by insulating the individual optoelectronic elements, such as by etching trenches between the individual elements until a mask layer or substrate (such as sapphire) is insulated. The cathode metallization to the n-type InGaN layer 2305 may be, for example, TiAl. The first wavelength (λ1), the second wavelength (λ2), and the third wavelength (λ3) may be, for example, blue, green, and red, respectively. However, the methods provided by the present disclosure may be used to fabricate optoelectronic elements configured to emit radiation in other wavelength ranges.

[0244] After growing the epitaxial layer (as compared to Figure 23 The wafer may be etched and metallized to provide contacts to the electrodes (e.g. Figure 24 shown).

[0245] Figure 24 Examples of optoelectronic devices configured to emit radiation in three different wavelength ranges are shown.

[0246] like Figure 24 As shown, the boundaries (possibly defective) between base layers with different strain states can be removed by etching down to the GaN buffer layer. Electrical contacts (such as transparent conductive oxide (TCO) contacts) can be deposited onto the p-type InGaN layer in an "epitaxial up" configuration. Alternatively, reflective contacts (such as Ag-based contacts) can be applied to the p-type InGaN layer in an inverse configuration. Figure 24 As shown, the cathodes may be common or may be isolated by insulating the individual photovoltaic elements, for example by etching trenches between the individual photovoltaic elements through an insulating mask layer or an insulating substrate, such as a sapphire substrate.

[0247] Individual photovoltaic elements may be isolated using known semiconductor manufacturing methods and a portion of the n-InGaN layer of each of the elements may be exposed.

[0248] Figure 24 A device with three optoelectronic elements is shown.

[0249] The cathode 2409a / 2409b / 2409c may be applied to overlap each of the n-type InGaN regions, and the anode 2408a / 2408b / 2408c may be applied to overlap each of the p-type InGaN regions.

[0250] like Figure 24 As shown, the optoelectronic device includes a growth substrate 2401 , a GaN buffer layer 2402 , and three optoelectronic elements stacked on the GaN buffer layer 2402 .

[0251] The optoelectronic elements 2403a / 2403b / 2403c include a relaxed InGaN growth layer 2409a / 2409b / 2409c, an n-type InGaN region stacked on the relaxed InGaN growth layer, an active region 2405a / 2405b / 2405c stacked on the n-type InGaN region, and a p-type InGaN region 2407a / 2407b / 2407c stacked on the respective active regions.

[0252] like Figure 24 As shown, each of the optoelectronic elements emits radiation within a different wavelength range λ1 , λ2 and λ3.

[0253] The growth can be selectively patterned and the overlying epitaxial layers can be deposited directly onto the selectively patterned substrate.By using a selectively patterned substrate, there is no need to use an intermediate GaN buffer layer between the growth substrate and the relaxed InGaN growth layer.

[0254] The emission apertures of various optoelectronic components can be independently adjusted in number, size, and shape to optimize overall performance, such as efficiency, contrast, and brightness uniformity. The emission apertures can also be independently adjusted to achieve the desired optical effect.

[0255] exist Figure 24 In the embodiment of the present invention, the optoelectronic elements are configured as LEDs. The structure can be configured as substantially coplanar strips to produce edge-emitting laser diodes that emit different colors.

[0256] The active region can also be integrated into a vertical cavity resonator (such as a distributed Bragg reflector stack) to provide multiple coplanar VCSELs emitting in different wavelength ranges and grown on the same substrate.

[0257] Figure 25 An example of a stacked optoelectronic device is shown. Figure 25 In the example shown, the stacked optoelectronic element is configured to emit radiation in three different wavelength ranges (λ1 , λ2 and λ3).

[0258] Figure 25 The stacked optoelectronic element shown includes a growth substrate 2501 and a stacked GaN layer 2502 having an in-plane a-lattice parameter a0.

[0259] The first optoelectronic element 2503a includes a first n-type GaN layer 2505a, an overlying first active region 2506a, and an overlying first p-type InGaN layer 2507a. Alternatively, the first optoelectronic element may include a first patterned region overlying the GaN layer 2502 and underlying the first n-type InGaN layer.

[0260] The second optoelectronic element 2503b includes: a first relaxed InGaN growth layer 2504b coalesced over a second patterned GaN seed region; and a stacked second n-type InGaN layer 2505b having an in-plane a-lattice parameter a2>a1; a stacked second active layer 2506b; and a second p-type InGaN layer 2507b stacked on the second active layer 2506b.

[0261] The third stacked optoelectronic element 2503c includes: a second relaxed InGaN growth layer 2504c deposited on the second patterned GaN seed region and stacked on the second p-type InGaN layer 2507b; an n-type InGaN layer having an in-plane a-lattice parameter a3>a2 stacked on the second relaxed InGaN growth layer 2540c; a third active layer 2506c stacked on the third n-type InGaN layer; and a third p-type InGaN layer 2507c stacked on the third active layer 2506c.

[0262] Transparent electrodes 2508a / 2508b / 2508c are stacked on the p-type InGaN layers 2507a / 2507b / 2507c, respectively, and are configured to pass radiation emitted by the underlying optoelectronic element.

[0263] Figure 25 The stacked optoelectronic device shown includes cathodes 2509a / 2509b / 2509c stacked on and electrically connected to n-type InGaN layers 2505a / 2505b / 2505c, respectively.

[0264] The first optoelectronic element is configured to emit radiation in a first wavelength range λ1 , the second optoelectronic element is configured to emit radiation in a second wavelength range λ2 , and the third optoelectronic element is configured to emit radiation in a third wavelength range λ3 .

[0265] It may be desirable that the material comprising each optoelectronic element is transparent to the radiation emitted by the active region of the underlying optoelectronic element. In other words, a "fully transparent" epitaxial stack is desired for all wavelengths of emission corresponding to emission from different active regions. To achieve this, the growth conditions and composition of the highest InN mole fraction base layer are selected to be transparent to emission from the active layer associated with the lowest InN mole fraction region. For example, in the case of an RGB emitter device, the composition of the base layer of the red emitting active region is selected to be substantially transparent to emission from the underlying blue emitting active region. This full epitaxial transparency can be achieved using the known band gap for InGaN compared to the alloy composition parameters, for example, for red, green, and blue emitters grown on an InGaN base layer having regions with different InGaN compositions and in-plane a-lattice parameters, where the stacked InGaN layers are deposited in a single epitaxial growth process.

[0266] In some aspects, the semiconductor structure includes a first optoelectronic element and a second optoelectronic element, wherein the first optoelectronic element includes a first active layer characterized by an a-lattice parameter in a first plane; the second optoelectronic element includes a second active layer characterized by an a-lattice parameter in a second plane; and the a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane.

[0267] The first optoelectronic element and the second optoelectronic element may or may not be stacked on a common substrate.The semiconductor structure may be incorporated into an optoelectronic device.

[0268] In certain aspects, a semiconductor structure can include an InGaN layer, such as a GaN buffer layer or a first relaxed InGaN growth layer and a second relaxed InGaN growth layer. The first relaxed InGaN growth layer can include a first relaxed (0001) InGaN region having a first in-plane a-lattice parameter, and the second relaxed InGaN growth layer can include a second relaxed (0001) InGaN region having a second in-plane a-lattice parameter, wherein the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter. For example, the first in-plane a-lattice parameter can differ, for example, by more than Greater than Greater than Greater than Greater than or greater than For example, the a-lattice parameters within the first plane may differ by, for example, greater than 0.2%, greater than 0.3%, greater than 0.5%, greater than 1%, or greater than 3%. The semiconductor structure may be stacked on a common substrate. The semiconductor structure may include stacked epitaxial layers to form a plurality of optoelectronic elements. The optoelectronic elements may or may not be stacked on a common substrate. The semiconductor structure may be stacked on a common GaN buffer layer.

[0269] Although the present disclosure describes detailed embodiments directed to an InGaN-GaN material system, the invention is not limited thereto and is similarly applicable to other systems, such as the AlGaN-AlN system of interest for ultraviolet light emitters and detectors.

[0270] Aspects of the Invention

[0271] The invention is further defined by one or more of the following aspects.

[0272] Aspect 1. A semiconductor structure, comprising:

[0273] a first relaxed (In)GaN growth layer including a first (0001) (In)GaN growth region;

[0274] a second relaxed InGaN growth layer, wherein the second relaxed InGaN growth layer comprises:

[0275] patterning a GaN seed region; and

[0276] a second (0001) InGaN growth region superimposed on the patterned GaN seed region; and

[0277] in,

[0278] The first (0001) (In)GaN growth region is characterized by a first in-plane a-lattice parameter;

[0279] The second (0001) InGaN growth region is characterized by a second in-plane a-lattice parameter; and

[0280] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0281] Aspect 2. The semiconductor structure according to aspect 1, wherein the first relaxed (In)GaN growth layer and the second relaxed InGaN growth layer are stacked on a common substrate, a common GaN buffer layer, or both a common substrate and a common GaN buffer layer.

[0282] Aspect 3. The semiconductor structure according to aspect 2, wherein:

[0283] The substrate includes a first substrate region and a second substrate region, wherein

[0284] The first relaxed (In)GaN growth layer is stacked on the first substrate region; and

[0285] The second relaxed InGaN growth layer is stacked on the second substrate region.

[0286] Aspect 4. The semiconductor structure of any one of aspects 2 to 3, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), or aluminum nitride.

[0287] Aspect 5. The semiconductor structure according to any one of aspects 2 to 4, wherein:

[0288] The GaN buffer layer includes a first GaN buffer zone and a second GaN buffer zone, wherein:

[0289] The first relaxed (In)GaN growth layer is stacked on the first GaN buffer region; and

[0290] The second relaxed InGaN growth layer is stacked on the second GaN buffer region.

[0291] Aspect 6. The semiconductor structure according to aspect 5, wherein the GaN buffer layer has The in-plane a-lattice parameter of .

[0292] Aspect 7. The semiconductor structure according to any one of aspects 1 to 6, wherein the semiconductor structure comprises:

[0293] a first optoelectronic element stacked on the first relaxed (In)GaN growth layer; and

[0294] A second optoelectronic element is stacked on the second relaxed InGaN growth layer.

[0295] Aspect 8. The semiconductor structure of aspect 7, wherein each of the first optoelectronic elements independently comprises:

[0296] an n-type (In)GaN layer stacked on the relaxed (In)GaN growth layer;

[0297] an active layer stacked on the n-type (In)GaN layer; and

[0298] A p-type (In) GaN layer is stacked on the active layer.

[0299] Aspect 9. The semiconductor structure of aspect 8, wherein the active layer is characterized by the in-plane a-lattice parameter of the underlying (0001) InGaN growth region.

[0300] Aspect 10. The semiconductor structure according to any one of aspects 1 to 9, wherein the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter, the difference being greater than

[0301] Aspect 11. The semiconductor structure of any one of aspects 1 to 9, wherein the second in-plane a-lattice parameter is larger than the first in-plane a-lattice parameter. to

[0302] Aspect 12. The semiconductor structure of any one of aspects 1 to 11, wherein the first relaxed (In)GaN growth layer does not include a patterned GaN seed region.

[0303] Aspect 13. The semiconductor structure of any one of aspects 1 to 11, wherein each of the first relaxed (In)GaN growth layer and the second relaxed InGaN growth layer independently comprises:

[0304] Multiple GaN seed regions;

[0305] Agglomerated InGaN regions between adjacent GaN seed regions;

[0306] a relaxed InGaN region stacked on the plurality of GaN seed regions and the coalesced InGaN region; and a (0001) InGaN growth region stacked on the relaxed InGaN region.

[0307] Aspect 14. The semiconductor structure of any one of aspects 1 to 13, wherein the first (0001) (In) GaN growth region is formed by The in-plane a-lattice parameter is used to characterize the

[0308] Aspect 15. A semiconductor structure according to any one of aspects 1 to 13, wherein the first (0001) (In) GaN growth region is formed by a process greater than The in-plane a-lattice parameter is used to characterize the

[0309] Aspect 16. A semiconductor structure according to any one of aspects 1 to 15, wherein the second (0001) grown InGaN region is formed by a process greater than The in-plane a-lattice parameter is used to characterize the

[0310] Aspect 17. A semiconductor structure according to any one of aspects 1 to 15, wherein the second (0001) grown InGaN region is formed by to The in-plane a-lattice parameter is used to characterize the

[0311] Aspect 18. The semiconductor structure according to any one of aspects 1 to 13, wherein:

[0312] The first (0001) (In) GaN growth region is formed by to characterized by the in-plane a-lattice parameters of

[0313] The second (0001) InGaN growth region is formed by to The in-plane a-lattice parameter is used to characterize the

[0314] Aspect 19. The semiconductor structure according to any one of aspects 1 to 18, wherein:

[0315] The (0001) (In)GaN first growth region includes a first InN mole fraction;

[0316] The second (0001) InGaN growth region comprises a second InN mole fraction; and

[0317] The second InN mole fraction is greater than the first InN mole fraction.

[0318] Aspect 20. The semiconductor structure of aspect 19, wherein the first InN mole fraction is 0 mol%.

[0319] Aspect 21. The semiconductor structure of aspect 19, wherein each of the first InN mole fraction and the second InN mole fraction is independently 0 mol % to 100 mol %.

[0320] Aspect 22. The semiconductor structure of any one of aspects 1 to 21, wherein the first (In)GaN growth layer comprises GaN.

[0321] Aspect 23. The semiconductor structure of any one of aspects 1 to 21, wherein the first (In)GaN growth layer comprises InGaN.

[0322] Aspect 24. The semiconductor structure of any one of aspects 1 to 21, wherein:

[0323] The first (In)GaN growth layer comprises a first InGaN, wherein the first (In)GaN growth layer includes a first plurality of GaN seed regions characterized by a first pattern;

[0324] The second InGaN growth layer includes a second plurality of GaN seed regions characterized by a second pattern; and

[0325] The first second pattern is different from the first pattern.

[0326] Aspect 25. A semiconductor structure according to Aspect 24, wherein the first pattern and the second pattern differ in the following aspects: the size of the GaN seed region, the shape of the GaN seed region, the filling factor of the GaN seed region, the spacing of the GaN seed region, the crystallographic orientation of the GaN seed region, the pattern of the seed region, or a combination of any of the above items.

[0327] Aspect 26. The semiconductor structure of any one of aspects 1 to 25, comprising a dielectric region proximate to each of the GaN seed regions.

[0328] Aspect 27. The semiconductor structure of aspect 26, wherein the dielectric region comprises SiOx, SiNx, or AlOx.

[0329] Aspect 28. The semiconductor structure of any one of aspects 1 to 27, wherein each of the GaN seed regions comprises a growth surface coplanar with a GaN crystal plane.

[0330] Aspect 29. The semiconductor structure according to aspect 1, wherein:

[0331] A first (0001) InGaN region is stacked on the first plurality of GaN seed regions, wherein the first (0001) InGaN region is stacked on the first plurality of GaN seed regions.

[0332] The InGaN growth region is characterized by a first in-plane a-lattice parameter and a first InN mole fraction; and

[0333] A second (0001) InGaN growth region overlies the second plurality of GaN seed regions, wherein the second (0001) InGaN region is characterized by a second in-plane a-lattice parameter and a second InN mole fraction.

[0334] Aspect 30. The semiconductor structure of aspect 29, wherein the (0001) InGaN growth region is formed by a process greater than The in-plane a-lattice parameter is used to characterize the

[0335] Aspect 31. The semiconductor structure of aspect 29, wherein the in-plane a-lattice parameter is to within the range.

[0336] Aspect 32. The semiconductor structure of any one of aspects 29 to 31, wherein each of the GaN seed regions comprises In x Ga 1-x N (0≤x<1) and wurtzite III-nitride crystal structure.

[0337] Aspect 33. The semiconductor structure of any one of aspects 29 to 32, wherein each of the GaN seed regions has 6 planar GaN seed facets.

[0338] Aspect 34. The semiconductor structure of any one of aspects 29 to 33, wherein each of the GaN seed regions is characterized by a hexagonal base.

[0339] Aspect 35. The semiconductor structure of any one of aspects 29 to 34, wherein each of the GaN seed regions comprises a seed surface that is coplanar with a crystal plane of GaN.

[0340] Aspect 36. The semiconductor structure of aspect 35, wherein each of the crystal planes is a crystallographically equivalent {10-11} plane.

[0341] Aspect 37. The semiconductor structure of aspect 35, wherein each of the crystal planes is a crystallographically equivalent {1-100} plane.

[0342] Aspect 38. The semiconductor structure of aspect 35, wherein each of the crystal planes is a crystallographically equivalent {11-20} plane.

[0343] Aspect 39. The semiconductor structure of aspect 35, wherein each of the crystal planes is a plane rotated about a {1-100} plane or a {11-20} plane.

[0344] Aspect 40. The semiconductor structure of aspect 35, wherein a region at a midpoint between the GaN seed regions is an agglomerated InGaN region.

[0345] Aspect 41. The semiconductor structure of any one of aspects 29 to 40, wherein the relaxed InGaN layer comprises more than one relaxed InGaN region, wherein each relaxed InGaN region has a different InN mole fraction.

[0346] Aspect 42. A semiconductor structure according to aspects 29 to 40, wherein each of the first relaxed InGaN growth layer and the second relaxed InGaN growth layer is independently configured to provide a (0001) InGaN growth region with a defined degree of in-plane a-lattice relaxation.

[0347] Aspect 43. The semiconductor structure of any one of aspects 29 to 42, wherein each of the first InGaN growth layer and the second InGaN growth layer is independently configured to have a (0001) InGaN growth region characterized by a different in-plane a-lattice parameter.

[0348] Aspect 44. The semiconductor structure of any one of aspects 29 to 43, wherein each of the first InGaN growth layer and the second InGaN growth layer is independently configured to have a (0001) InGaN growth region characterized by a different InN mole fraction.

[0349] Aspect 45. The semiconductor structure of any one of aspects 1 to 44, comprising:

[0350] a first n-type (In)GaN layer stacked on the first relaxed (In)GaN growth layer;

[0351] a first active layer stacked on the first n-type (In)GaN layer;

[0352] A first p-type (In) GaN layer is stacked on the first active layer.

[0353] a second n-type (In)GaN layer stacked on the second relaxed (In)GaN growth layer;

[0354] a second active layer stacked on the second n-type (In)GaN layer; and a second p-type (In)GaN layer stacked on the second active layer.

[0355] Aspect 46. The semiconductor structure of aspect 45, wherein the first n-type (In)GaN layer comprises GaN.

[0356] Aspect 47. The semiconductor structure of aspect 45, wherein the first n-type (In)GaN layer comprises InGaN.

[0357] Aspect 48. The semiconductor structure of aspect 47, wherein each of the first n-type InGaN layer and the second n-type InGaN layer independently has an in-plane a-lattice parameter equivalent to a corresponding underlying (0001) (In)GaN region.

[0358] Aspect 49. The semiconductor structure of any one of aspects 45 to 48, wherein:

[0359] The first n-type (In)GaN layer is characterized by a first in-plane a-lattice parameter;

[0360] The second n-type InGaN layer is characterized by a second in-plane a-lattice parameter; and

[0361] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0362] Aspect 50. A semiconductor structure according to any one of Aspects 45 to 49, wherein each of the first n-type InGaN layer and the second n-type InGaN layer is independently characterized by an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) (In)GaN region.

[0363] Aspect 51. The semiconductor structure of any one of aspects 45 to 50, wherein:

[0364] The first n-type (In)GaN layer includes a first InN mole fraction;

[0365] The second n-type InGaN layer comprises a second InN mole fraction; and

[0366] The second InN mole fraction is greater than the first InN mole fraction.

[0367] Aspect 52. The semiconductor structure of any one of aspects 45 to 51, wherein the first active layer comprises more than one first active layer.

[0368] Aspect 53. The semiconductor structure of any one of aspects 45 to 52, wherein the second active layer comprises more than one active layer.

[0369] Aspect 54. The semiconductor structure of any one of aspects 45 to 51, wherein each of the first active layer and the second active layer comprises more than one active layer.

[0370] Aspect 55. A semiconductor structure according to any one of Aspects 45 to 54, wherein the first active layer includes 1 to 40 active layers, the second active region includes 1 to 40 active layers, or each of the first active layer and the second active layer includes 1 to 40 active layers.

[0371] Aspect 56. The semiconductor structure of any one of aspects 45 to 55, wherein:

[0372] The first active layer includes a first InN mole fraction;

[0373] The second active layer comprises a second InN mole fraction; and

[0374] The second InN mole fraction is greater than the second InN mole fraction.

[0375] Aspect 57. The semiconductor structure according to any one of aspects 45 to 56, wherein:

[0376] The first active layer is characterized by a first in-plane strain value;

[0377] The second active layer is characterized by a second in-plane strain value; and

[0378] The first strain value is similar to the second strain value.

[0379] Aspect 58. The semiconductor structure of aspect 57, wherein the second in-plane strain value is within 10% of the first in-plane strain value.

[0380] Aspect 59. The semiconductor structure of aspect 57, wherein the second in-plane strain value is within 1% of the first in-plane strain value.

[0381] Aspect 60. The semiconductor structure of aspect 57, wherein each of the first strain value and the second strain value is independently within 1% to 2% of a compressive strain.

[0382] Aspect 61. The semiconductor structure of any one of aspects 45 to 60, wherein each of the first active layer and the second active layer comprises a multiple quantum well structure.

[0383] Aspect 62. The semiconductor structure of any one of aspects 45 to 61, wherein each of the first active layer and the second active layer comprises a light emitting diode structure.

[0384] Aspect 63. The semiconductor structure of any one of aspects 45 to 62, wherein each of the first active layer and the second active layer comprises a laser diode structure.

[0385] Aspect 64. The semiconductor structure of any one of aspects 45 to 63, wherein:

[0386] The first p-type (In)GaN layer is characterized by a first in-plane a-lattice parameter;

[0387] The second p-type InGaN layer is characterized by a second in-plane a-lattice parameter; and

[0388] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0389] Aspect 65. A semiconductor structure according to any one of Aspects 45 to 64, wherein each of the first p-type InGaN layer and the second p-type InGaN layer is independently characterized by an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) (In)GaN region.

[0390] Aspect 66. The semiconductor structure of any one of aspects 45 to 65, wherein:

[0391] The first p-type (In)GaN layer includes a first InN mole fraction;

[0392] The second p-type InGaN layer includes a second InN mole fraction; and

[0393] The second InN mole fraction is greater than the first InN mole fraction.

[0394] Aspect 67. A semiconductor structure according to any one of aspects 45 to 66, wherein each of the first p-type (In)GaN layer and the second p-type InGaN layer independently has to The in-plane a-lattice parameter is in the range of .

[0395] Aspect 68. The semiconductor structure of any one of Aspects 7 to 67, wherein the first optoelectronic element and the second optoelectronic element are configured to emit radiation within different wavelength ranges.

[0396] Aspect 69. The semiconductor structure of any one of aspects 7 to 68, wherein each of the first optoelectronic element and the second optoelectronic element independently comprises a light emitting diode, a laser diode, or a vertical cavity surface emitting laser.

[0397] Aspect 70. The semiconductor structure of any one of aspects 7 to 69, further comprising:

[0398] a cathode electrically connected to each of the first n-type (In)GaN layer and the second InGaN layer; and an anode electrically connected to each of the first p-type (In)GaN layer and the second p-type InGaN layer.

[0399] Aspect 71. The semiconductor structure of aspect 70, wherein the cathode comprises Ti and Al.

[0400] Aspect 72. The semiconductor structure of any one of aspects 70 to 71, wherein the cathode is commonly interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0401] Aspect 73. The semiconductor structure of any one of aspects 70 to 72, wherein the cathode is independently and commonly interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0402] Aspect 74. The semiconductor structure of any one of Aspects 73 to 73, wherein the anode comprises a transparent conductive oxide layer or a reflective contact.

[0403] Aspect 75. The semiconductor structure of any one of aspects 73 to 74, wherein the anode is commonly interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0404] Aspect 76. The semiconductor structure of any one of aspects 73 to 75, wherein the anode is independently commonly interconnected with each of the first n-type (In)GaN layer and the second InGaN layer.

[0405] Aspect 77. The semiconductor structure of any one of aspects 7 to 76, wherein each of the first optoelectronic element and the second optoelectronic element are electrically isolated from each other.

[0406] Aspect 78. A semiconductor device comprising the semiconductor structure according to any one of aspects 1 to 77.

[0407] Aspect 79. A lighting system or a display system, comprising the semiconductor device according to aspect 78.

[0408] Aspect 80. A method of manufacturing a semiconductor structure, the method comprising:

[0409] (a) depositing a first relaxed (In)GaN growth layer overlying a first substrate region of a substrate; and

[0410] (b) depositing a second relaxed InGaN growth layer overlying a second substrate region of the substrate, wherein the second relaxed InGaN growth layer includes a patterned GaN seed region,

[0411] in,

[0412] The first relaxed (In)GaN growth layer includes a first (0001) (In)GaN region characterized by a first in-plane a-lattice parameter;

[0413] The second relaxed InGaN growth layer includes a second (0001) InGaN region characterized by a second in-plane a-lattice parameter; and

[0414] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0415] Aspect 81. The method of aspect 80, wherein depositing the second relaxed InGaN growth layer comprises:

[0416] Fabricating a patterned GaN seed region;

[0417] growing InGaN on the GaN seed region so that InGaN grown on adjacent seed regions coalesces and forms a relaxed InGaN region; and

[0418] The relaxed InGaN region is grown to provide a (0001) InGaN growth region.

[0419] Aspect 82. The method according to Aspect 80 includes: after depositing the first relaxed (In)GaN growth layer and depositing the second relaxed InGaN growth layer, manufacturing a first photoelectric element stacked on the first relaxed InGaN growth layer, and manufacturing a second photoelectric element stacked on the second relaxed InGaN growth layer.

[0420] Aspect 83. The method according to any one of aspects 80 to 82, wherein

[0421] The first optoelectronic element includes an epitaxial layer stacked on the first relaxed (In)GaN growth layer; and

[0422] and

[0423] The second optoelectronic element includes an epitaxial layer stacked on the second relaxed InGaN growth layer.

[0424] Aspect 84. The method according to any one of aspects 80 to 83, wherein the epitaxial layer comprises an n-type (In)GaN layer, an active layer, a p-type (In)GaN layer, or a combination of any of the foregoing.

[0425] Aspect 85. The method of any one of aspects 80 to 84, wherein the first relaxed (In)GaN growth layer comprises GaN.

[0426] Aspect 86. The method of any one of aspects 80 to 85, wherein the first relaxed (In)GaN growth layer comprises a first GaN seed region.

[0427] Aspect 87. The method according to any one of aspects 80 to 86, wherein the method comprises: manufacturing the first optoelectronic element and the second optoelectronic element simultaneously.

[0428] Aspect 88. The method according to any one of aspects 80 to 87, wherein the method comprises: manufacturing the first optoelectronic element and the second optoelectronic element sequentially.

[0429] Aspect 89. The method according to any one of aspects 80 to 88, wherein each of the first optoelectronic element and the second optoelectronic element is independently selected from a light emitting diode, a laser diode, and a vertical cavity surface emitting laser.

[0430] Aspect 90. The method according to any one of aspects 80 to 89, comprising: after depositing the first relaxed (In)GaN growth layer and depositing the second relaxed InGaN growth layer:

[0431] (c) depositing a first n-type (In)GaN layer stacked on the first relaxed (In)GaN growth layer, and depositing a second n-type InGaN layer stacked on the second relaxed InGaN growth layer;

[0432] (d) depositing a first active layer stacked on the first n-type (In)GaN layer, and depositing a second active layer stacked on the second n-type InGaN layer;

[0433] (e) depositing a first p-type (In)GaN layer stacked on the first active layer, and depositing a second p-type InGaN layer stacked on the second active layer,

[0434] in,

[0435] The first active layer is characterized by a first in-plane a-lattice parameter;

[0436] The second active layer is characterized by a second in-plane a-lattice parameter; and

[0437] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0438] Aspect 91. The method of aspect 90, wherein depositing the first n-type (In)GaN layer and depositing the second n-type InGaN layer comprise simultaneous deposition.

[0439] Aspect 92. The method of aspect 90, wherein depositing the first n-type (In)GaN layer and depositing the second n-type InGaN layer comprise independently depositing.

[0440] Aspect 93. The method according to any one of aspects 90 to 92, wherein depositing the first active layer and depositing the second active layer include simultaneous deposition.

[0441] Aspect 94. The method according to any one of aspects 90 to 92, wherein depositing the first active layer and depositing the second active layer include independently depositing.

[0442] Aspect 95. The method according to any one of aspects 90 to 94, wherein depositing the first p-type (In)GaN layer and depositing the second p-type InGaN layer include simultaneous deposition.

[0443] Aspect 96. The method according to any one of aspects 90 to 94, wherein depositing the first p-type (In)GaN layer and depositing the second p-type InGaN layer include independently depositing.

[0444] Aspect 97. The method according to any one of aspects 90 to 96, wherein simultaneously depositing comprises depositing using the same deposition conditions.

[0445] Aspect 98. The method according to any one of aspects 90 to 96, wherein independently depositing comprises depositing using different deposition conditions.

[0446] Aspect 99. The method of any one of aspects 80 to 98, comprising depositing an electrical contact overlying each of the n-type (In)GaN layers.

[0447] Aspect 100. The method of any one of aspects 80 to 99, comprising depositing an electrical contact overlying each of the p-type (In)GaN layers.

[0448] Aspect 101. A semiconductor structure manufactured using the method according to any one of aspects 80 to 100.

[0449] Aspect 102. A semiconductor device comprising the semiconductor structure according to aspect 101.

[0450] Aspect 103. The semiconductor device according to aspect 102, wherein the semiconductor device comprises a lighting system or a display system.

[0451] Aspect 1A. A wurtzite III-nitride crystal semiconductor structure, comprising:

[0452] a substrate comprising a first substrate region and a second substrate region;

[0453] The first substrate region includes a first (0001) In x1 Al y1 Ga 1-x1-y1 The first In in the N growth zone x1 Al y1 Ga 1-x1-y1 N growth layer;

[0454] The second patterned In layer stacked on the second substrate region x2s Al y2s Ga 1-x2s-y2s N seed area;

[0455] Overlay on the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region includes a second (0001) In x2 Al y2 Ga 1-x2-y2 The second In growth zone x2 Al y2 Ga 1-x2-y2 N growth layer, where

[0456] First (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by the a-lattice parameter in the first plane;

[0457] Second (0001)In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by the a-lattice parameter in the second plane;

[0458] The a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane;

[0459] 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1

[0460] 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and

[0461] 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

[0462] Aspect 2A. The semiconductor structure according to Aspect 1A, wherein the first Inx1Aly1Ga1 - x1 - y1N growth layer is a GaN layer including a first (0001) GaN growth region.

[0463] Aspect 3A. The semiconductor structure according to Aspect 1A, wherein the first Inx1Aly1Ga1 - x1 - y1N growth layer is an In x1 Ga 1-x1 N growth region of In x1 Ga 1-x1 N layer.

[0464] Aspect 4A. The semiconductor structure according to Aspect 1A, wherein the first Inx1Aly1Ga1 - x1 - y1N growth layer is an In x1 Al y1 Ga 1-x1-y1 N growth region of In x1 Al y1 Ga 1-x1-y1 N layer, where 0 ≤ x1 < 1, 0 < y1 < 1 and x1 + y1 ≤ 1.

[0465] Aspect 5A. The semiconductor structure according to any one of Aspects 1A to 4A, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region includes a patterned GaN seed region.

[0466] Aspect 6A. The semiconductor structure according to any one of Aspects 1A to 4A, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region includes a patterned In x2s Ga 1-x2s N seed region.

[0467] Aspect 7A. The semiconductor structure according to any one of Aspects 1A to 4A, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region includes a patterned In x2s Aly2s Ga 1-x2s-y2s a GaN seed region, where 0 ≤ x2s < 1, 0 < y2s < 1 and x2s + y2s ≤ 1.

[0468] Aspect 8A. The semiconductor structure according to any one of Aspects 1A to 7A, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth region includes a second (0001) In x2 Ga 1-x2 N growth region.

[0469] Aspect 9A. The semiconductor structure according to any one of Aspects 1A to 7A, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region includes a patterned AlN seed region.

[0470] Aspect 10A. The semiconductor structure according to Aspects 1A to 9A, the semiconductor structure includes a first patterned In x1 Al y1 Ga 1-x1-y1 N growth region below the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region, where,

[0471] 0 ≤ x1s ≤ 1, 0 ≤ y1s ≤ 1 and x1s + y1s ≤ 1; and

[0472] the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s- y2s Each of the N seed regions includes the same composition. [[ID=6l]]

[0473] Aspect 11A. The semiconductor structure according to any one of Aspects 1A to 9A, the semiconductor structure includes a first patterned In x1 Al y1 Ga 1-x1-y1 N growth region below the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region, where,

[0474] 0 ≤ x1s ≤ 1, 0 ≤ y1s ≤ 1 and x1s + y1s ≤ 1; and

[0475] The first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s- y2s Each of the N seed regions includes a different composition.

[0476] Aspect 12A. The semiconductor structure of any one of Aspects 1A to 1A1, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers includes a different composition.

[0477] Aspect 13A. A semiconductor structure according to any one of aspects 1A to 12A, wherein the (0001) plane of the wurtzite III-nitride structure is parallel to the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed regions, 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1, the first plane of intersection is characterized by:

[0478] The intersection of the first plane and the first edge of the first patterned seed region positions the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction; and

[0479] The first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the first crystal face of the seed region, a facet of the seed region, or a combination thereof.

[0480] Aspect 14A. The semiconductor structure of aspect 13A, wherein the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction includes a compositional gradation from x1s and y1s to x1 and y1.

[0481] Aspect 15A. A semiconductor structure according to any one of aspects 13A to 14A, wherein any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region positions a second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction, wherein the second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the second crystal plane of the seed region.

[0482] Aspect 16A. The semiconductor structure of Aspect 15A, wherein each of the first crystal plane and the second crystal plane are crystallographically equivalent.

[0483] Aspect 17A. A semiconductor structure according to any one of aspects 1A to 12A, wherein the (0001) plane of the wurtzite III-nitride structure is parallel to the second patterned In x2s Al y2s Ga 1-x2s-y2s The first plane intersected by the N seed regions is characterized by:

[0484] The intersection of the first plane and the first edge of the first patterned seed region positions the first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 N heterojunction; and

[0485] The first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the first crystal plane of the seed region.

[0486] Aspect 18A. The semiconductor structure of aspect 17A, wherein the first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2The N heterojunction includes a compositional gradation from x2s and y2s to x2 and y2.

[0487] Aspect 19A. A semiconductor structure according to any one of aspects 17A to 18A, wherein any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region positions a second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 N heterojunction, wherein the second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the second crystal plane of the seed region.

[0488] Aspect 20A. The semiconductor structure of aspect 19A, wherein each of the first crystal plane and the second crystal plane are crystallographically equivalent.

[0489] Aspect 21A. The semiconductor structure of any one of aspects 1A to 20A, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 N growth zone through about The in-plane a-lattice parameter is used to characterize the

[0490] Aspect 22A. The semiconductor structure of any one of aspects 1A to 20A, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone through greater than The in-plane a-lattice parameter is used to characterize the

[0491] Aspect 23A. The semiconductor structure of any one of aspects 1A to 20A, wherein:

[0492] The first (0001)In x1 Al y1 Ga 1-x1-y1 N growth zone through greater than The first plane a-lattice parameter is used to characterize it;

[0493] The second (0001)In x2 Al y2 Ga 1-x2-y2 N growth zone through greater than characterized by a second in-plane a-lattice parameter; and

[0494] The difference between the a-lattice parameter in the first plane and the a-lattice parameter in the second plane exceeds 0.2%.

[0495] Aspect 24A. The semiconductor structure of any one of Aspects 1A to 23A, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), gallium oxide, or aluminum nitride.

[0496] Aspect 25A. The semiconductor structure of any one of aspects 1A to 24A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on a common GaN buffer layer, wherein the common GaN buffer layer is stacked on the substrate.

[0497] Aspect 26A. The semiconductor structure of aspect 25A, wherein:

[0498] The GaN buffer layer includes a first GaN buffer zone and a second GaN buffer zone;

[0499] The first In x1 Al y1 Ga 1-x1-y1 An N growth layer is stacked on the first GaN buffer region; and

[0500] The second x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on the second GaN buffer region.

[0501] Aspect 27A. The semiconductor structure of aspect 25A, wherein the GaN buffer layer has a thickness of about The in-plane a-lattice parameter of .

[0502] Aspect 28A. The semiconductor structure of any one of Aspects 1A to 27A, wherein the semiconductor structure comprises:

[0503] (a) superimposed on the first In x1 Al y1 Ga 1-x1-y1 A first photoelectric element on the N growth layer; and

[0504] (b) superimposed on the second In x2 Al y2 Ga 1-x2-y2A second photoelectric element is formed on the N growth layer.

[0505] Aspect 29A. The semiconductor structure of any one of aspects 1A to 24A, wherein the semiconductor structure comprises:

[0506] (a) superimposed on the first (0001)In x1 Al y1 Ga 1-x1-y1 A first photoelectric element on the N growth region; and

[0507] (b) superimposed on the second (0001)In x2 Al y2 Ga 1-x2-y2 A second photovoltaic element is formed on the N growth region.

[0508] Aspect 30A. The semiconductor structure of any one of aspects 28A to 29A, wherein:

[0509] The first photoelectric element comprises:

[0510] Overlaid on the first (0001)In x1 Al y1 Ga 1-x1-y1 n-type In on N growth layer x1 Al y1 Ga 1-x1-y1 N-layer;

[0511] Overlaid on the n-type In x1 Al y1 Ga 1-x1-y1 The first In on the N layer x1 Al y1 Ga 1-x1-y1 N active region; and

[0512] Overlaid on the first In x1 Al y1 Ga 1-x1-y1 p-type In on the N active region x1 Al y1 Ga 1-x1-y1 N layers; and

[0513] and

[0514] The second photoelectric element comprises:

[0515] Overlaid on the second (0001)In x2 Al y2 Ga 1-x2-y2 n-type In on N growth layer x2 Al y2 Ga 1-x2-y2 N-layer;

[0516] Overlaid on the n-type In x2 Al y2 Ga 1-x2-y2 The second In on the N layer x1 Al y1 Ga 1-x1-y1 N active region; and

[0517] Overlaid on the second In x1 Al y1 Ga 1-x1-y1 p-type In on the N active region x2 Al y2 Ga 1-x2-y2 N layers.

[0518] Aspect 31A. The semiconductor structure of aspect 30A, wherein each of the first active region and the second active region is characterized by an in-plane a-lattice parameter of an underlying (0001) growth region.

[0519] Aspect 32A. The semiconductor structure of any one of aspects 30A to 31A, wherein:

[0520] The first active region is characterized by a first in-plane a-lattice parameter;

[0521] The second active region is characterized by a second in-plane a-lattice parameter;

[0522] The a-lattice parameter in the second plane is larger than the a-lattice parameter in the first plane, and the difference is greater than

[0523] Aspect 33A. The semiconductor structure of aspect 32A, wherein the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter. to

[0524] Aspect 34A. A semiconductor structure according to any one of aspects 1A to 33A, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer is a GaN growth layer.

[0525] Aspect 35A. A semiconductor structure according to any one of aspects 1A to 33A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer is In x1 Ga 1-x1 N growth layer.

[0526] Aspect 36A. A semiconductor structure according to any one of aspects 1A to 33A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently superposed on the patterned GaN seed region and includes:

[0527] agglomeration regions between adjacent GaN seed regions; and

[0528] Superimposed on this region is a (0001) growth region.

[0529] Aspect 37A. A semiconductor structure according to any one of aspects 1A to 36A, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth zone is formed by about The (0001) GaN growth region is characterized by the in-plane a-lattice parameters.

[0530] Aspect 38A. A semiconductor structure according to any one of aspects 1A to 36A, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 N growth zone is formed by (0001)In is characterized by the in-plane a-lattice parameter x1 Ga 1- x1 N growth zone.

[0531] Aspect 39A. A semiconductor structure according to any one of aspects 1A to 38A, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone through greater than The in-plane a-lattice parameter is used to characterize the

[0532] Aspect 40A. A semiconductor structure according to any one of aspects 1A to 38A, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone is formed by (0001)In is characterized by the in-plane a-lattice parameter x2 Ga 1- x2 N growth zone.

[0533] Aspect 41A. A semiconductor structure according to any one of aspects 1A to 38A, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone through to The in-plane a-lattice parameter is used to characterize the

[0534] Aspect 42A. The semiconductor structure of any one of aspects 1A to 38A, wherein:

[0535] The first (0001)In x1 Al y1 Ga 1-x1-y1 N growth zone through to The first plane a-lattice parameter is used to characterize it;

[0536] The second (0001)In x2 Al y2 Ga 1-x2-y2 N growth zone through to characterized by a second in-plane a-lattice parameter; and

[0537] The a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane.

[0538] Aspect 43A. A semiconductor structure according to any one of aspects 1A to 42A, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 N growth region and the second (0001)In x2 Al y2 Ga 1-x2-y2 Each of the N growth zones is independently to The range of in-plane a-lattice parameters is used to characterize the lattice.

[0539] Aspect 44A. The semiconductor structure of any one of Aspects 1A to 43A, wherein:

[0540] The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region includes a first InN mole fraction;

[0541] The second (0001)In x2 Al y2 Ga 1-x2-y2 The N growth region comprises a second InN mole fraction; and

[0542] The second InN mole fraction is greater than the first InN mole fraction.

[0543] Aspect 45A. The semiconductor structure of Aspect 44A, wherein the first InN mole fraction is 0 mol%.

[0544] Aspect 46A. The semiconductor structure of Aspect 44A, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol%.

[0545] Aspect 47A. The semiconductor structure of aspect 44A, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol% and less than 100 mol%.

[0546] Aspect 48A. The semiconductor structure of aspect 1A, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer is a GaN growth layer.

[0547] Aspect 49A. The semiconductor structure of aspect 1A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer is In x1 Ga 1-x1 N growth layer.

[0548] Aspect 50A. The semiconductor structure of any one of aspects 1A to 49A, wherein:

[0549] The first In x1 Al y1 Ga 1-x1-y1 The N growth layer is stacked on a first patterned In layer characterized by a first pattern. x1s Al y1s Ga 1-x1s-y1s On the N seed region, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1;

[0550] The second x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region; and

[0551] The first second pattern is different from the first pattern.

[0552] Aspect 51A. The semiconductor structure of aspect 50A, wherein:

[0553] The first patterned In x1s Al y1s Ga 1-x1s-y1s The N seed region is a first patterned GaN region; and

[0554] The second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region is a second patterned GaN region.

[0555] Aspect 52A. A semiconductor structure according to any one of Aspects 50A to 51A, wherein the first pattern and the second pattern differ in the following aspects: the size of the seed region, the shape of the seed region, the fill factor of the seed region, the spacing of the seed region, the crystallographic orientation of the seed region, the base geometry of the seed region, the two-dimensional pattern of the seed region, or a combination of any of the above items.

[0556] Aspect 53A. The semiconductor structure of any of Aspects 1A to 52A, comprising a dielectric region adjacent to each of the seed regions.

[0557] Aspect 54A. The semiconductor structure of aspect 53A, wherein the dielectric region comprises SiO x 、SiN x 、AlO x or any combination of the above.

[0558] Aspect 55A. The semiconductor structure of any one of Aspects 1A to 54A, wherein:

[0559] The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region overlaps the first patterned In x1s Al y1s Ga 1-x1s-y1s On the N seed region, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; and

[0560] The first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region, the second patterned In x2s Al y2s Ga 1-x2s-y2s Each of the N seed regions includes a growth surface coplanar with a wurtzite Group Ill-nitride crystal plane.

[0561] Aspect 56A. The semiconductor structure of any one of Aspects 1A to 54A, wherein:

[0562] The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region overlaps the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region, wherein 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; and wherein the first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by a first in-plane a-lattice parameter and a first InN mole fraction;

[0563] The second (0001)In x2 Al y2 Ga 1-x2-y2 The N growth region is stacked on the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by the second in-plane a-lattice parameter and the second InN mole fraction;

[0564] The first in-plane a-lattice parameter is different from the second in-plane a-lattice parameter; and

[0565] The first InN mole fraction is different from the second InN mole fraction.

[0566] Aspect 57A. A semiconductor structure according to any one of aspects 54A to 55A, wherein each of the first in-plane a-lattice parameter and the second in-plane a-lattice parameter is independently greater than

[0567] Aspect 58A. A semiconductor structure according to any of Aspects 54A to 55A, wherein each of the first in-plane a-lattice parameter and the second in-plane a-lattice parameter is independently to within the range.

[0568] Aspect 59A. The semiconductor structure of any one of aspects 55A to 58A, wherein the first patterned seed region comprises In x1s Ga 1-x1sN and is characterized by a wurtzite group-III nitride crystal structure, where 0 ≤ x1s < 1; and the second patterned seed region contains In x2s Ga 1-x2s N and is characterized by a wurtzite group-III nitride crystal structure, where 0 ≤ x2s < 1.

[0569] Aspect 60A. The semiconductor structure according to any one of aspects 55A to 58A, wherein,

[0570] the first patterned seed region contains In x1s Ga 1-x1s N and is characterized by a wurtzite group-III nitride crystal structure, where 0 < x1s < 1; and

[0571] the second patterned seed region contains In x2s Ga 1-x2s N and is characterized by a wurtzite group-III nitride crystal structure, where 0 < x2s < 1.

[0572] Aspect 61A. The semiconductor structure according to any one of aspects 55A to 58A, wherein each of the first patterned seed region and the second patterned seed region contains GaN and is characterized by a wurtzite group-III nitride crystal structure.

[0573] Aspect 62A. The semiconductor structure according to aspect 61A, wherein each of the first patterned seed region and the second patterned seed region has six planar seed facets.

[0574] Aspect 63A. The semiconductor structure according to aspect 61A, wherein each of the first patterned seed region and the second patterned seed region is characterized by a hexagonal base.

[0575] Aspect 64A. The semiconductor structure according to any one of aspects 61A to 63A, wherein each of the first seed region and the second seed region includes a seed surface coplanar with a crystal plane of a wurtzite group-III nitride.

[0576] Aspect 65A. The semiconductor structure according to aspect 64A, wherein each of the crystal planes is a crystallographically equivalent {10-11} plane.

[0577] Aspect 66A. The semiconductor structure according to aspect 64A, wherein each of the crystal planes is a crystallographically equivalent {1-100} plane.

[0578] Aspect 67A. The semiconductor structure according to aspect 64A, wherein each of the crystal planes is a crystallographically equivalent {11-20} plane.

[0579] Aspect 68A. The semiconductor structure of aspect 64A, wherein each of the crystal planes is a plane rotated between a {1-100} plane and a {11-20} plane.

[0580] Aspect 69A. The semiconductor structure of Aspect 64, wherein a region at a midpoint between adjacent seed regions is a coalesced growth region.

[0581] Aspect 70A. The semiconductor structure of any of Aspects 61A to 65A, wherein each of the first seed region and the second seed region is substantially free of (0001) facets.

[0582] Aspect 71A. The semiconductor structure of any one of Aspects 1A to 70A, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer includes more than one In x1 Al y1 Ga 1-x1-y1 N growth zone, where each In x1 Al y1 Ga 1-x1-y1 The N growth regions have different InN mole fractions.

[0583] Aspect 72A. A semiconductor structure according to any one of aspects 1A to 71A, wherein the second In x2 Al y2 Ga 1-x2-y2 The N growth layer includes more than one In x2 Al y2 Ga 1-x2-y2 N growth zone, where each In x2 Al y2 Ga 1-x2-y2 The N growth regions have different InN mole fractions.

[0584] Aspect 73A. The semiconductor structure of aspects 1A to 72A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently configured to provide a (0001) growth region with a defined degree of in-plane a-lattice relaxation.

[0585] Aspect 74A. A semiconductor structure according to any one of aspects 1A to 72A, wherein the first In x1 Aly1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently configured to have a (0001) growth region characterized by a different in-plane a-lattice parameter.

[0586] Aspect 75A. A semiconductor structure according to any one of aspects 1A to 72A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently configured to have a (0001) growth region characterized by a different InN mole fraction.

[0587] Aspect 76A. The semiconductor structure of any one of aspects 1A to 75A, comprising:

[0588] Overlaid on the first (0001)In x1 Al y1 Ga 1-x1-y1 The first n-type In on the N growth region x1 Al y1 Ga 1-x1-y1 N-layer;

[0589] stacked on the first n-type In x1 Al y1 Ga 1-x1-y1 a first active region on the N layer;

[0590] A first p-type In stacked on the first active region x1 Al y1 Ga 1-x1-y1 N-layer;

[0591] Overlaid on the second (0001)In x2 Al y2 Ga 1-x2-y2 Second n-type In on the N growth region x2 Al y2 Ga 1-x2-y2 N-layer;

[0592] stacked on the second n-type In x2 Al y2 Ga 1-x2-y2 a second active region on the N layer; and

[0593] A second p-type In stacked on the second active regionx2 Al y2 Ga 1-x2-y2 N layers.

[0594] Aspect 77A. The semiconductor structure of aspect 76A, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 The N layer includes GaN.

[0595] Aspect 78A. The semiconductor structure of aspect 76A, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 N layer contains In x1 Ga 1-x1 N.

[0596] Aspect 79A. The semiconductor structure of aspect 76A, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second n-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers independently has an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) growth region.

[0597] Aspect 80A. The semiconductor structure of any one of aspects 76A to 79A, wherein:

[0598] The first n-type In x1 Al y1 Ga 1-x1-y1 The N growth layer is characterized by the a-lattice parameter in the first plane;

[0599] The second n-type In x2 Al y2 Ga 1-x2-y2 The N-grown layer is characterized by a second in-plane a-lattice parameter; and

[0600] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0601] Aspect 81A. The semiconductor structure of any one of aspects 76A to 79A, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second n-type In x2 Al y2 Ga 1-x2-y2Each of the N layers is independently characterized by an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) growth region.

[0602] Aspect 82A. The semiconductor structure of any one of aspects 76A to 79A, wherein:

[0603] The first n-type In x1 Al y1 Ga 1-x1-y1 The N layer includes a first InN mole fraction;

[0604] The second n-type In x2 Al y2 Ga 1-x2-y2 The N layer comprises a second InN mole fraction; and

[0605] The second InN mole fraction is greater than the first InN mole fraction.

[0606] Aspect 83A. The semiconductor structure of any of Aspects 76A to 82A, wherein the first active region comprises more than one first active layer.

[0607] Aspect 84A. The semiconductor structure of any of Aspects 76A to 83A, wherein the second active region comprises more than one active layer.

[0608] Aspect 85A. The semiconductor structure of any of Aspects 76A to 84A, wherein each of the first active region and the second active region independently comprises more than one active layer.

[0609] Aspect 86A. A semiconductor structure according to any one of Aspects 76A to 85A, wherein the first active region includes 1 to 40 active layers, the second active region includes 1 to 40 active layers, or each of the first active region and the second active region includes 1 to 40 active layers.

[0610] Aspect 87A. The semiconductor device of any one of aspects 76A to 86A, wherein each of the first active region and the second active region independently comprises one or more quantum wells or quantum dots comprising a Group III nitride material with In.

[0611] Aspect 88A. The semiconductor structure of any one of aspects 76A to 87A, wherein:

[0612] The first active region includes a first InN mole fraction;

[0613] The second active region comprises a second InN mole fraction; and

[0614] The second InN mole fraction is greater than the first InN mole fraction.

[0615] Aspect 89A. The semiconductor structure of any one of aspects 76A to 83A, wherein:

[0616] The first active region is characterized by a first in-plane strain value;

[0617] The second active region is characterized by a second in-plane strain value; and

[0618] The first strain value is similar to the second strain value.

[0619] Aspect 90A. The semiconductor structure of aspect 89A, wherein the second in-plane strain value is within 10% of the first in-plane strain value.

[0620] Aspect 91A. The semiconductor structure of Aspect 89A, wherein the second in-plane strain value is within 1% of the first in-plane strain value.

[0621] Aspect 92A. The semiconductor structure of aspect 89A, wherein each of the first strain value and the second strain value is independently within 1% to 2% of a compressive strain.

[0622] Aspect 93A. The semiconductor structure of any of aspects 76A to 92A, wherein each of the first active region and the second active region comprises a multiple quantum well structure.

[0623] Aspect 94A. The semiconductor structure of any of Aspects 76A to 92A, wherein each of the first active region and the second active region comprises a light emitting diode structure.

[0624] Aspect 95A. The semiconductor structure of any of Aspects 76A to 92A, wherein each of the first active region and the second active region comprises a laser diode structure.

[0625] Aspect 96A. The semiconductor structure of any one of aspects 76A to 92A, wherein:

[0626] The first p-type In x1 Al y1 Ga 1-x1-y1 The N layer is characterized by the first in-plane a-lattice parameter;

[0627] The second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is characterized by a second in-plane a-lattice parameter; and

[0628] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0629] Aspect 97A. The semiconductor structure of any one of aspects 76A to 96A, wherein the first p-type In x1 Al y1 Ga 1-x1-y1 N layer and the second p-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers is independently characterized by an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) growth region.

[0630] Aspect 98A. The semiconductor structure of any one of aspects 76A to 97A, wherein:

[0631] The first p-type In x1 Al y1 Ga 1-x1-y1 The N layer includes a first InN mole fraction;

[0632] The second p-type In x2 Al y2 Ga 1-x2-y2 The N layer comprises a second InN mole fraction; and

[0633] The second InN mole fraction is greater than the first InN mole fraction.

[0634] Aspect 99A. The semiconductor structure of any one of aspects 76A to 98A, wherein the first p-type In x1 Al y1 Ga 1-x1-y1 N layer and the second p-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers independently has to The in-plane a-lattice parameter is in the range of .

[0635] Aspect 100A. A semiconductor device according to any one of Aspects 76A to 99A, comprising a capping layer comprising a Group III nitride material with Al, wherein the capping layer is interposed between the active region and an overlying p-type Group III nitride layer.

[0636] Aspect 101A. The semiconductor structure of any of Aspects 22A to 100A, wherein each of the first optoelectronic element and the second optoelectronic element is configured to emit electromagnetic radiation within a different wavelength range.

[0637] Aspect 102A. The semiconductor structure of any of Aspects 28A to 33A, wherein each of the first optoelectronic element and the second optoelectronic element independently comprises a light emitting diode, a superluminescent diode, a laser diode, or a vertical cavity surface emitting laser.

[0638] Aspect 103A. The semiconductor structure of aspect 102A, further comprising:

[0639] electrically connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 a cathode of each of the N layers; and

[0640] electrically connected to the first p-type In x1 Al y1 Ga 1-x1-y1 N layer and the second p-type In x2 Al y2 Ga 1-x2-y2 an anode for each of the N layers.

[0641] Aspect 104A. The semiconductor structure of aspect 103A, wherein the cathode comprises Ti and Al.

[0642] Aspect 105A. The semiconductor structure of any one of aspects 103A to 104A, wherein the cathode and the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

[0643] Aspect 106A. A semiconductor structure according to any one of aspects 103A to 104A, wherein the cathode is independently connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

[0644] Aspect 107A. The semiconductor structure of any of Aspects 103A to 106A, wherein the anode comprises a transparent conductive oxide layer or a reflective contact.

[0645] Aspect 108A. The semiconductor structure of any one of aspects 103A to 107A, wherein the anode is adjacent to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

[0646] Aspect 109A. A semiconductor structure according to any one of aspects 103 to 107, wherein the anode is independently connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

[0647] Aspect 110A. The semiconductor structure of any of Aspects 103A to 109A, wherein the first optoelectronic element and the second optoelectronic element are electrically isolated from each other.

[0648] Aspect 111A. A wafer comprising the semiconductor structure according to any one of Aspects 1A to 108A.

[0649] Aspect 112A. An optoelectronic component comprising the semiconductor structure according to any one of aspects 1A to 108A.

[0650] Aspect 113A. A multicolor optoelectronic device comprising the semiconductor structure of any one of Aspects 1A to 108A.

[0651] Aspect 114A. A semiconductor device comprising the semiconductor structure of any one of Aspects 1A to 108A.

[0652] Aspect 115A. A lighting system or a display system, comprising the semiconductor device according to Aspect 114A.

[0653] Aspect 116A. A method of fabricating a wurtzite Group III nitride crystal semiconductor structure, the method comprising:

[0654] (a) Depositing a first In layer stacked on a first substrate region of the substrate x1 Al y1 Ga 1-x1-y1 N growth layer; and

[0655] (b) depositing a second In layer stacked on the second substrate region of the substratex2 Al y2 Ga 1-x2-y2 N growth layer, wherein the second In x2 Al y2 Ga 1-x2-y2 N growth layer is stacked on the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region,

[0656] wherein,

[0657] the first In x1 Al y1 Ga 1-x1-y1 N growth layer includes a first (0001) In characterized by a first in-plane a-lattice parameter x1 Al y1 Ga 1-x1-y1 N growth region;

[0658] the second In x2 Al y2 Ga 1-x2-y2 N growth layer includes a second (0001) In characterized by a second in-plane a-lattice parameter x2 Al y2 Ga 1-x2-y2 N growth region; and

[0659] the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter, wherein,

[0660] 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1

[0661] 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and

[0662] 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

[0663] Aspect 117A. The method according to aspect 116A, the method comprising: before step (a),

[0664] depositing a first patterned In stacked on the first substrate region x1s Al y1s Ga 1-x1s-y1s N seed region, wherein 0 ≤ x1s ≤ 1, 0 ≤ y1s ≤ 1 and x1s + y1s ≤ 1; and

[0665] depositing the first In stacked on the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed regionx1 Al y1 Ga 1-x1-y1 N growth layer.

[0666] Aspect 118A. The method according to aspect 117A, wherein the first patterned In x1s Al y1s Ga 1-x1s-y1s The N seed region includes a first GaN seed region.

[0667] Aspect 119A. The method according to any one of aspects 117A to 118A, wherein the second patterned In x1s Al y1s Ga 1-x1s-y1s The N seed region includes a second patterned GaN seed region.

[0668] Aspect 120A. The method according to any one of aspects 117A to 119A, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 The N growth layer has a different elemental composition.

[0669] Aspect 121A. The method according to any one of aspects 117 to 120, wherein

[0670] The first In x1 Al y1 Ga 1-x1-y1 The N growth layer includes a first In x1 Ga 1-x1 N growth layer;

[0671] The second x2 Al y2 Ga 1-x2-y2 The N growth layer includes a second In x2 Ga 1-x2 N growth layer; and

[0672] The first In x1 Ga 1-x1 N growth layer and the second In x2 Ga 1-x2 The N growth layer has a different elemental composition.

[0673] Aspect 122A. The method according to any one of aspects 117A to 121A, wherein the first In is deposited x1 Al y1 Ga 1-x1-y1The N growth layer includes growing a GaN growth layer to provide a (0001) GaN growth region.

[0674] Aspect 123A. The method according to any one of aspects 117A to 122A, wherein the first In is deposited x1 Al y1 Ga 1-x1-y1 The N growth layer includes:

[0675] Fabricate a first patterned In on a first substrate portion x1s Al y1s Ga 1-x1s-y1s N seed region, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1;

[0676] In x1 Al y1 Ga 1-x1-y1 N in the first patterning In x1s Al y1s Ga 1-x1s-y1s N seed region so that the growth is adjacent to the patterned In x1s Al y1s Ga 1-x1s-y1s In on the N seed region x1 Al y1 Ga 1-x1-y1 N aggregates and forms the first In x1 Al y1 Ga 1-x1-y1 N growth layer; and

[0677] Make the first In x1 Al y1 Ga 1-x1-y1 N growth layer is grown to provide (0001)In x1 Al y1 Ga 1-x1-y1 N growth zone.

[0678] Aspect 124A. The method according to any one of aspects 117A to 123A, wherein the second In x2 Al y2 Ga 1-x2-y2 The N growth layer includes:

[0679] Fabricate the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed area;

[0680] In x2 Al y2 Ga 1-x2-y2 N in the second patterning Inx2s Al y2s Ga 1-x2s-y2s grow on the N seed region so that the growth is on the adjacent In x2s Al y2s Ga 1-x2s-y2s In on the N seed region x2 Al y2 Ga 1-x2-y2 N aggregates and forms In x2 Al y2 Ga 1-x2- y2 N growth layer; and

[0681] Make the In x2 Al y2 Ga 1-x2-y2 N growth layer is grown to provide (0001)In x2 Al y2 Ga 1-x2-y2 N growth zone.

[0682] Aspect 125A. The method according to any one of aspects 117A to 124A, the method comprising: depositing the first In x1 Al y1 Ga 1-x1-y1 After the N growth layer and the second In x2 Al y2 Ga 1-x2-y2 After the N growth layer is formed, a layer stacked on the first (0001)In x1 Al y1 Ga 1-x1-y1 The first photoelectric element on the N growth region and the second (0001) In x2 Al y2 Ga 1-x2-y2 A second photovoltaic element is formed on the N growth region.

[0683] Aspect 126A. A method according to any aspect 125A, wherein

[0684] The first photoelectric element includes a first (0001)In x1 Al y1 Ga 1-x1-y1 an epitaxial layer on the N growth region; and

[0685] The second photoelectric element includes a layer stacked on the second (0001)In x2 Al y2 Ga 1-x2-y2 Epitaxial layer on the N growth region.

[0686] Aspect 127A. The method of aspect 126A, wherein the epitaxial layer comprises an n-type layer, an active region, a p-type layer, or a combination of any of the foregoing.

[0687] Aspect 128A. The method according to any one of aspects 126A to 127A, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer contains GaN.

[0688] Aspect 129A. The method according to any one of aspects 126A to 127A, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer contains In x1 Ga 1-x1 N.

[0689] Aspect 130A. The method according to any one of aspects 126A to 127A, wherein the second In x2 Al y2 Ga 1-x2-y2 The N growth layer contains In x2 Ga 1-x2 N.

[0690] Aspect 131A. The method according to any one of aspects 126A to 130A, wherein the method comprises: manufacturing the first optoelectronic element and the second optoelectronic element simultaneously.

[0691] Aspect 132A. The method according to any one of aspects 126A to 130A, wherein the method comprises: manufacturing the first optoelectronic element and the second optoelectronic element sequentially.

[0692] Aspect 133A. The method of any one of aspects 126A to 132A, wherein each of the first optoelectronic element and the second optoelectronic element is independently selected from a light emitting diode, a superluminescent diode, a laser diode, and a vertical cavity surface emitting laser.

[0693] Aspect 134A. The method according to any one of aspects 117A to 133A, the method comprising: depositing the first In x1 Al y1 Ga 1-x1-y1 After the N growth layer and the second In x2 Al y2 Ga 1-x2-y2 After the N growth layer:

[0694] (c) Deposition superimposed on the In x1 Al y1Ga 1-x1-y1 The first n-type In x1 Al y1 Ga 1-x1-y1 N layer, and deposited on top of the second In x2 Al y2 Ga 1-x2-y2 The second n-type In x2 Al y2 Ga 1-x2-y2 N-layer;

[0695] (d) depositing a layer stacked on the first n-type In x1 Al y1 Ga 1-x1-y1 The first active region on the N layer and the second n-type In layer are deposited on top of the second n-type In layer. x2 Al y2 Ga 1-x2-y2 a second active region on the N layer;

[0696] (e) depositing a first p-type In layer stacked on the first active region x1 Al y1 Ga 1-x1-y1 N layer, and a second p-type In layer deposited on the second active region x2 Al y2 Ga 1-x2-y2 N layers,

[0697] in,

[0698] The first active region is characterized by a first in-plane a-lattice parameter;

[0699] The second active region is characterized by a second in-plane a-lattice parameter; and

[0700] The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

[0701] Aspect 135A. The method of aspect 134A, wherein the first n-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second n-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited simultaneously.

[0702] Aspect 136A. The method of aspect 134A, wherein the first n-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second n-type In x2 Aly2 Ga 1-x2-y2 The N layer is deposited separately.

[0703] Aspect 137A. The method of any one of aspects 134A to 136A, wherein depositing the first active region and depositing the second active region comprise simultaneous deposition.

[0704] Aspect 138A. The method of any one of aspects 134A to 136A, wherein depositing the first active region and depositing the second active region comprise independently depositing.

[0705] Aspect 139A. The method of any one of aspects 134A to 138A, wherein the first p-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited simultaneously.

[0706] Aspect 140. The method according to any one of aspects 134A to 138A, wherein the first p-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited separately.

[0707] Aspect 141A. The method of any one of aspects 134A to 140A, wherein simultaneously depositing comprises depositing using the same deposition conditions.

[0708] Aspect 142A. The method of any one of aspects 134A to 140A, wherein independently depositing comprises depositing using different deposition conditions.

[0709] Aspect 143A. The method of any of aspects 134A to 142A, comprising depositing an electrical contact overlying each of the n-type layers.

[0710] Aspect 144A. The method of any of aspects 134A to 143A, comprising depositing an electrical contact overlying each of the p-type layers.

[0711] Aspect 145A. A semiconductor structure manufactured using the method of any one of Aspects 116A to 144A.

[0712] Aspect 146. A semiconductor wafer comprising the semiconductor structure according to any one of aspects 1A to 110A.

[0713] Aspect 147A. A multi-wavelength optoelectronic element comprising the semiconductor structure according to any one of aspects 1A to 110A.

[0714] Aspect 148A. A semiconductor device comprising the optoelectronic element according to aspect 147A.

[0715] Aspect 149A. A lighting system or a display system comprising the semiconductor device according to Aspect 148A.

[0716] Finally, it should be noted that there are alternative ways of implementing the embodiments disclosed herein. Therefore, the present embodiments are to be considered as illustrative and not restrictive, and the claims are not to be limited to the details given herein, but may be modified within the scope and equivalents of the claims.

Claims

1. A wurtzite group-III nitride crystal semiconductor structure, the semiconductor structure comprising: A substrate, the substrate comprising a first substrate region and a second substrate region; The first substrate region includes a first (0001) In x1 Al y1 Ga 1-x1-y1 The first In in the N growth zone x1 Al y1 Ga 1-x1-y1 N growth layer; A second patterned In layer stacked on the second substrate region x2s Al y2s Ga 1-x2s-y2s N seed area; Overlaid on the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region includes a second (0001) In x2 Al y2 Ga 1-x2-y2 The second In growth zone x2 Al y2 Ga 1-x2-y2 N growth layer, where The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by the a-lattice parameter in the first plane; The second (0001)In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by the a-lattice parameter in the second plane; The a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane; 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

2. The semiconductor structure according to claim 1, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer is a GaN layer including a first (0001) GaN growth region.

3. The semiconductor structure according to claim 1, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer includes the first (0001) In x1 Ga 1-x1 In in the N growth zone x1 Ga 1-x1 N layers.

4. The semiconductor structure according to claim 1, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer is an In x1 Al y1 Ga 1-x1-y1 N growth region including a first (0001) In x1 Al y1 Ga 1-x1-y1 N layer, where 0 ≤ x1 < 1, 0 < y1 < 1 and x1 + y1 ≤ 1.

5. The semiconductor structure according to any one of claims 1 to 4, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region includes a patterned GaN seed region.

6. The semiconductor structure according to any one of claims 1 to 4, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region includes a patterned In x2s Ga 1-x2s N seed region.

7. The semiconductor structure according to any one of claims 1 to 4, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region includes patterned In x2s Al y2s Ga 1-x2s-y2s N seed region, where 0 ≤ x2s < 1, 0 < y2s < 1 and x2s + y2s ≤ 1.

8. The semiconductor structure according to any one of claims 1 to 7, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region includes the second (0001)In x2 Ga 1-x2 N growth zone.

9. The semiconductor structure according to any one of claims 1 to 7, wherein the second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region includes a patterned AlN seed region.

10. The semiconductor structure according to claim 1 , comprising: x1 Al y1 Ga 1-x1-y1 The first patterned In below the N growth region x1s Al y1s Ga 1-x1s-y1s N seed region, where 0 ≤ x1s ≤ 1, 0 ≤ y1s ≤ 1 and x1s + y1s ≤ 1; and The first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s-y2s Each of the N seed regions includes the same composition.

11. The semiconductor structure according to any one of claims 1 to 9, comprising: x1 Al y1 Ga 1-x1-y1 The first patterned In below the N growth region x1s Al y1s Ga 1-x1s-y1s N seed region, where 0 ≤ x1s ≤ 1, 0 ≤ y1s ≤ 1 and x1s + y1s ≤ 1; and The first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region and the second patterned In x2s Al y2s Ga 1-x2s-y2s Each of the N seed regions includes a different composition.

12. The semiconductor structure according to any one of claims 1 to 11, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers includes a different composition.

13. The semiconductor structure according to any one of claims 1 to 12, wherein the (0001) plane of the wurtzite III-nitride structure is parallel to the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed regions, 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1, the first plane of intersection is characterized by: The intersection of the first plane and the first edge of the first patterned seed region positions the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction; and The first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the first crystal plane of the seed region, a facet of the seed region, or a combination thereof.

14. The semiconductor structure according to claim 13, wherein the first In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction includes a compositional gradation from x1s and y1s to x1 and y1.

15. The semiconductor structure according to any one of claims 13 to 14, wherein any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region positions a second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 N heterojunction, wherein the second In x1s Al y1s Ga 1-x1s-y1s N / In x1 Al y1 Ga 1-x1-y1 The N heterojunction is coplanar with the second crystal plane of the seed region.

16. The semiconductor structure according to claim 15, wherein each of the first crystal plane and the second crystal plane is crystallographically equivalent.

17. The semiconductor structure according to any one of claims 1 to 12, wherein the (0001) plane of the wurtzite III-nitride structure is parallel to the second patterned In x2s Al y2s Ga 1-x2s-y2s The first plane intersected by the N seed regions is characterized by: The intersection of the first plane and the first edge of the first patterned seed region positions the first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 N heterojunction; and The first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the first crystal plane of the seed region.

18. The semiconductor structure according to claim 17, wherein the first In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction includes a compositional gradation from x2s and y2s to x2 and y2.

19. The semiconductor structure according to any one of claims 17 to 18, wherein any second plane parallel to the (0001) plane of the wurtzite III-nitride crystal structure and intersecting the second edge of the seed region positions a second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 N heterojunction, wherein the second In x2s Al y2s Ga 1-x2s-y2s N / In x2 Al y2 Ga 1-x2-y2 The N heterojunction is coplanar with the second crystal plane of the seed region.

20. The semiconductor structure according to claim 19, wherein each of the first crystal plane and the second crystal plane is crystallographically equivalent.

21. The semiconductor structure according to any one of claims 1 to 20, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 N growth zone through The in-plane a-lattice parameter is used to characterize the 22. The semiconductor structure according to any one of claims 1 to 20, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth zone is formed by a process greater than about The in-plane a-lattice parameter is used to characterize the 23. The semiconductor structure according to any one of claims 1 to 20, wherein, The first (0001)In x1 Al y1 Ga 1-x1-y1 N growth zone through greater than The first plane a-lattice parameter is used to characterize it; The second (0001)In x2 Al y2 Ga 1-x2-y2 N growth zone through greater than characterized by a second in-plane a-lattice parameter; and The difference between the a-lattice parameter in the first plane and the a-lattice parameter in the second plane exceeds 0.2%.

24. The semiconductor structure according to any one of claims 1 to 23, wherein the substrate comprises sapphire, silicon, silicon carbide, gallium nitride, silicon-on-insulator (SOI), gallium oxide or aluminum nitride.

25. The semiconductor structure according to any one of claims 1 to 24, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on a common GaN buffer layer, wherein the common GaN buffer layer is stacked on the substrate.

26. The semiconductor structure according to claim 25, wherein, The GaN buffer layer comprises a first GaN buffer region and a second GaN buffer region; The first In x1 Al y1 Ga 1-x1-y1 An N growth layer is stacked on the first GaN buffer region; and The second x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on the second GaN buffer region.

27. The semiconductor structure of claim 25, wherein the GaN buffer layer has a thickness of about The in-plane a-lattice parameter of .

28. The semiconductor structure according to any one of claims 1 to 27, wherein the semiconductor structure comprises: (a) superimposed on the first In x1 Al y1 Ga 1-x1-y1 a first photoelectric element on the N growth layer; And (b) superimposed on the second In x2 Al y2 Ga 1-x2-y2 A second photoelectric element is formed on the N growth layer.

29. The semiconductor structure according to any one of claims 1 to 24, wherein the semiconductor structure comprises: (a) superimposed on the first (0001)In x1 Al y1 Ga 1-x1-y1 a first photoelectric element on the N growth region; And (b) superimposed on the second (0001)In x2 Al y2 Ga 1-x2-y2 A second photovoltaic element is formed on the N growth region.

30. The semiconductor structure according to any one of claims 28 to 29, wherein, The first optoelectronic element comprises: Overlaid on the first (0001)In x1 Al y1 Ga 1-x1-y1 n-type In on N growth layer x1 Al y1 Ga 1-x1-y1 N-layer; Overlaid on the n-type In x1 Al y1 Ga 1-x1-y1 The first In on the N layer x1 Al y1 Ga 1-x1-y1 N active region; and Overlaid on the first In x1 Al y1 Ga 1-x1-y1 p-type In on the N active region x1 Al y1 Ga 1-x1-y1 N layers; and And The second optoelectronic element comprises: Overlaid on the second (0001)In x2 Al y2 Ga 1-x2-y2 n-type In on N growth layer x2 Al y2 Ga 1-x2-y2 N-layer; Overlaid on the n-type In x2 Al y2 Ga 1-x2-y2 The second In on the N layer x1 Al y1 Ga 1-x1-y1 N active region; and Overlaid on the second In x1 Al y1 Ga 1-x1-y1 p-type In on the N active region x2 Al y2 Ga 1-x2-y2 N layers.

31. The semiconductor structure according to claim 30, wherein each of the first active region and the second active region is characterized by the in-plane a-lattice parameter of the following (0001) growth region.

32. The semiconductor structure according to any one of claims 30 to 31, wherein, The first active region is characterized by a first in-plane a-lattice parameter; The second active region is characterized by a second in-plane a-lattice parameter; The a-lattice parameter in the second plane is larger than the a-lattice parameter in the first plane, and the difference is greater than 33. The semiconductor structure of claim 32, wherein the second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter. to 34. The semiconductor structure according to any one of claims 1 to 33, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer is a GaN growth layer.

35. The semiconductor structure according to any one of claims 1 to 33, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer is In x1 Ga 1-x1 N growth layer.

36. The semiconductor structure according to any one of claims 1 to 33, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently superposed on the patterned GaN seed region and includes: A coalescence region between adjacent GaN seed regions; And A (0001) growth region stacked on the region.

37. The semiconductor structure according to any one of claims 1 to 36, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth zone is formed by about The (0001) GaN growth region is characterized by the in-plane a-lattice parameters.

38. The semiconductor structure according to any one of claims 1 to 36, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 The N growth zone is formed by more than about (0001)In is characterized by the in-plane a-lattice parameter x1 Ga 1-x1 N growth zone.

39. The semiconductor structure according to any one of claims 1 to 38, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone through greater than The in-plane a-lattice parameter is used to characterize the 40. The semiconductor structure of any one of claims 1 to 38, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone is formed by (0001)In is characterized by the in-plane a-lattice parameter x2 Ga 1- x2 N growth zone.

41. The semiconductor structure according to any one of claims 1 to 38, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 N growth zone through to The in-plane a-lattice parameter is used to characterize the 42. The semiconductor structure according to any one of claims 1 to 38, wherein, The first (0001)In x1 Al y1 Ga 1-x1-y1 N growth zone through to The first plane a-lattice parameter is used to characterize it; The second (0001)In x2 Al y2 Ga 1-x2-y2 N growth zone through to characterized by a second in-plane a-lattice parameter; and Wherein the a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane.

43. The semiconductor structure according to any one of claims 1 to 42, wherein the first (0001) In x1 Al y1 Ga 1-x1-y1 N growth region and the second (0001)In x2 Al y2 Ga 1-x2-y2 Each of the N growth zones is independently to The range of in-plane a-lattice parameters is used to characterize the lattice.

44. The semiconductor structure according to any one of claims 1 to 43, wherein, The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region includes a first InN mole fraction; The second (0001)In x2 Al y2 Ga 1-x2-y2 The N growth region comprises a second InN mole fraction; and The second InN mole fraction is greater than the first InN mole fraction.

45. The semiconductor structure according to claim 44, wherein the first InN mole fraction is 0 mol%.

46. ​​The semiconductor structure of Claim 44, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol%.

47. The semiconductor structure of Claim 44, wherein each of the first InN mole fraction and the second InN mole fraction is independently greater than 0 mol% and less than 100 mol%.

48. The semiconductor structure of claim 1, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer is a GaN growth layer.

49. The semiconductor structure of claim 1, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer is In x1 Ga 1-x1 N growth layer.

50. The semiconductor structure of any one of claims 1 to 49, wherein The first In x1 Al y1 Ga 1-x1-y1 The N growth layer is stacked on a first patterned In layer characterized by a first pattern. x1s Al y1s Ga 1-x1s-y1s On the N seed region, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; The second x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region; and The first second pattern is different from the first pattern.

51. The semiconductor structure of claim 50, wherein The first patterned In x1s Al y1s Ga 1-x1s-y1s The N seed region is a first patterned GaN region; and The second patterned In x2s Al y2s Ga 1-x2s-y2s The N seed region is a second patterned GaN region.

52. A semiconductor structure according to any one of claims 50 to 51, wherein the first pattern and the second pattern differ in the following aspects: the size of the seed region, the shape of the seed region, the fill factor of the seed region, the spacing of the seed region, the crystallographic orientation of the seed region, the base geometry of the seed region, the two-dimensional pattern of the seed region, or a combination of any of the above items.

53. The semiconductor structure of any one of claims 1 to 52, comprising a dielectric region adjacent to each of the seed regions.

54. The semiconductor structure of claim 53, wherein the dielectric region comprises SiO x 、SiN x 、AlO x or any combination of the above.

55. The semiconductor structure of any one of claims 1 to 54, wherein: The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region overlaps the first patterned In x1s Al y1s Ga 1-x1s-y1s On the N seed region, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; and The first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region, the second patterned In x2s Al y2s Ga 1-x2s-y2s Each of the N seed regions includes a growth surface coplanar with a wurtzite Group Ill-nitride crystal plane.

56. The semiconductor structure of any one of claims 1 to 54, wherein: The first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region overlaps the first patterned In x1s Al y1s Ga 1-x1s-y1s N seed region, wherein 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; and wherein the first (0001)In x1 Al y1 Ga 1-x1-y1 The N growth region is characterized by a first in-plane a-lattice parameter and a first InN mole fraction; The second (0001)In x2 Al y2 Ga 1-x2-y2 The N growth region is stacked on the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed region, wherein the second (0001) In x2 Al y2 Ga 1-x2-y2 The N growth region is characterized by the second in-plane a-lattice parameter and the second InN mole fraction; The first in-plane a-lattice parameter is different from the second in-plane a-lattice parameter; and The first InN mole fraction is different from the second InN mole fraction.

57. The semiconductor structure of any one of claims 54 to 55, wherein each of the first in-plane a-lattice parameter and the second in-plane a-lattice parameter is independently greater than 58. The semiconductor structure of any one of claims 54 to 55, wherein each of the first in-plane a-lattice parameter and the second in-plane a-lattice parameter is independently to within the range.

59. The semiconductor structure of any one of claims 55 to 58, wherein The first patterned seed region comprises In x1s Ga 1-x1s N and is characterized by the wurtzite III-nitride crystal structure, where 0≤x1s<1; and The second patterned seed region comprises In x2s Ga 1-x2s N and is characterized by the wurtzite III-nitride crystal structure, where 0≤x2s<1.

60. The semiconductor structure of any one of claims 55 to 58, wherein The first patterned seed region contains In x1s Ga 1-x1s N and is characterized by a wurtzite group III nitride crystal structure, where 0 < x1s < 1; and The second patterned seed region comprises In x2s Ga 1-x2s N and is characterized by the wurtzite III-nitride crystal structure, where 0 <x2s<1。 61. The semiconductor structure of any one of Claims 55 to 58, wherein each of the first and second patterned seed regions comprises GaN and is characterized by a wurtzite Ill-nitride crystal structure.

62. The semiconductor structure of Claim 61, wherein each of the first and second patterned seed regions has six planar seed facets.

63. The semiconductor structure of Claim 61, wherein each of said first patterned seed region and said second patterned seed region is characterized by a hexagonal base.

64. The semiconductor structure of any one of Claims 61 to 63, wherein each of the first and second seed regions comprises a seed surface that is coplanar with a crystal plane of wurtzite Group Ill-nitride.

65. The semiconductor structure of Claim 64, wherein each of the crystal planes is a crystallographically equivalent {10-11} plane.

66. The semiconductor structure of Claim 64, wherein each of the crystal planes is a crystallographically equivalent {1-100} plane.

67. The semiconductor structure of Claim 64, wherein each of the crystal planes is a crystallographically equivalent {11-20} plane.

68. The semiconductor structure of Claim 64, wherein each of the crystal planes is a plane rotated between a {1-100} plane and a {11-20} plane.

69. The semiconductor structure of claim 64, wherein a region at a midpoint between adjacent seed regions is a coalesced growth region.

70. The semiconductor structure of any one of Claims 61 to 65, wherein each of the first seed region and the second seed region is substantially free of (0001) facets.

71. The semiconductor structure of any one of claims 1 to 70, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer includes more than one In x1 Al y1 Ga 1-x1-y1 N growth zone, where each In x1 Al y1 Ga 1-x1-y1 The N growth regions have different InN mole fractions.

72. The semiconductor structure of any one of claims 1 to 71, wherein the second In x2 Al y2 Ga 1-x2-y2 The N growth layer includes more than one In x2 Al y2 Ga 1-x2-y2 N growth zone, where each In x2 Al y2 Ga 1-x2-y2 The N growth regions have different InN mole fractions.

73. The semiconductor structure of claims 1 to 72, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently configured to provide a (0001) growth region with a defined degree of in-plane a-lattice relaxation.

74. The semiconductor structure of any one of claims 1 to 72, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently configured to have a (0001) growth region characterized by a different in-plane a-lattice parameter.

75. The semiconductor structure of any one of claims 1 to 72, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N growth layers is independently configured to have a (0001) growth region characterized by a different InN mole fraction.

76. The semiconductor structure of any one of claims 1 to 75, comprising: Overlaid on the first (0001)In x1 Al y1 Ga 1-x1-y1 The first n-type In on the N growth region x1 Al y1 Ga 1-x1-y1 N-layer; stacked on the first n-type In x1 Al y1 Ga 1-x1-y1 a first active region on the N layer; A first p-type In stacked on the first active region x1 Al y1 Ga 1-x1-y1 N-layer; Overlaid on the second (0001)In x2 Al y2 Ga 1-x2-y2 Second n-type In on the N growth region x2 Al y2 Ga 1-x2-y2 N-layer; stacked on the second n-type In x2 Al y2 Ga 1-x2-y2 a second active region on the N layer; as well as A second p-type In stacked on the second active region x2 Al y2 Ga 1-x2-y2 N layers.

77. The semiconductor structure of claim 76, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 The N layer includes GaN.

78. The semiconductor structure of claim 76, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 N layer contains In x1 Ga 1-x1 N.

79. The semiconductor structure of claim 76, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second n-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers independently has an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) growth region.

80. The semiconductor structure of any one of claims 76 to 79, wherein The first n-type In x1 Al y1 Ga 1-x1-y1 The N growth layer is characterized by the a-lattice parameter in the first plane; The second n-type In x2 Al y2 Ga 1-x2-y2 The N-grown layer is characterized by a second in-plane a-lattice parameter; and The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

81. The semiconductor structure of any one of claims 76 to 79, wherein the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second n-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers is independently characterized by an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) growth region.

82. The semiconductor structure of any one of claims 76 to 79, wherein The first n-type In x1 Al y1 Ga 1-x1-y1 The N layer includes a first InN mole fraction; The second n-type In x2 Al y2 Ga 1-x2-y2 The N layer comprises a second InN mole fraction; and The second InN mole fraction is greater than the first InN mole fraction.

83. The semiconductor structure of any one of claims 76 to 82, wherein the first active region comprises more than one first active layer.

84. The semiconductor structure of any one of claims 76 to 83, wherein the second active region comprises more than one active layer.

85. The semiconductor structure of any one of claims 76 to 84, wherein each of the first active region and the second active region independently comprises more than one active layer.

86. A semiconductor structure according to any one of claims 76 to 85, wherein the first active region includes 1 to 40 active layers, the second active region includes 1 to 40 active layers, or each of the first active region and the second active region includes 1 to 40 active layers.

87. The semiconductor device of any one of claims 76 to 86, wherein each of the first active region and the second active region independently comprises one or more quantum wells or quantum dots comprising a Group III nitride material with In.

88. The semiconductor structure of any one of claims 76 to 87, wherein The first active region includes a first InN mole fraction; The second active region comprises a second InN mole fraction; and The second InN mole fraction is greater than the first InN mole fraction.

89. The semiconductor structure of any one of claims 76 to 83, wherein The first active region is characterized by a first in-plane strain value; The second active region is characterized by a second in-plane strain value; and The first strain value is similar to the second strain value.

90. The semiconductor structure of Claim 89, wherein the second in-plane strain value is within 10% of the first in-plane strain value.

91. The semiconductor structure of Claim 89, wherein the second in-plane strain value is within 1% of the first in-plane strain value.

92. The semiconductor structure of Claim 89, wherein each of the first strain value and the second strain value is independently within 1% to 2% of a compressive strain.

93. The semiconductor structure of any one of claims 76 to 92, wherein each of the first active region and the second active region comprises a multiple quantum well structure.

94. The semiconductor structure of any one of claims 76 to 92, wherein each of the first active region and the second active region comprises a light emitting diode structure.

95. The semiconductor structure of any one of claims 76 to 92, wherein each of the first active region and the second active region comprises a laser diode structure.

96. The semiconductor structure of any one of claims 76 to 92, wherein The first p-type In x1 Al y1 Ga 1-x1-y1 The N layer is characterized by the first in-plane a-lattice parameter; The second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is characterized by a second in-plane a-lattice parameter; and The second in-plane a-lattice parameter is greater than the first in-plane a-lattice parameter.

97. The semiconductor structure of any one of claims 76 to 96, wherein the first p-type In x1 Al y1 Ga 1-x1-y1 N layer and the second p-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers is independently characterized by an in-plane a-lattice parameter equivalent to the corresponding underlying (0001) growth region.

98. The semiconductor structure of any one of claims 76 to 97, wherein The first p-type In x1 Al y1 Ga 1-x1-y1 The N layer includes a first InN mole fraction; The second p-type In x2 Al y2 Ga 1-x2-y2 The N layer comprises a second InN mole fraction; and The second InN mole fraction is greater than the first InN mole fraction.

99. The semiconductor structure of any one of claims 76 to 98, wherein the first p-type In x1 Al y1 Ga 1-x1-y1 N layer and the second p-type In x2 Al y2 Ga 1-x2-y2 Each of the N layers independently has to The in-plane a-lattice parameter is in the range of .

100. A semiconductor device according to any one of claims 76 to 99, comprising a capping layer comprising a Group III nitride material with Al, wherein the capping layer is interposed between the active region and an overlying p-type Group III nitride layer.

101. The semiconductor structure of any one of claims 22 to 100, wherein each of the first optoelectronic element and the second optoelectronic element is configured to emit electromagnetic radiation within a different wavelength range.

102. The semiconductor structure of any one of claims 28 to 33, wherein each of the first optoelectronic element and the second optoelectronic element independently comprises a light emitting diode, a superluminescent diode, a laser diode, or a vertical cavity surface emitting laser.

103. The semiconductor structure of claim 102, further comprising: electrically connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 a cathode of each of the N layers; as well as electrically connected to the first p-type In x1 Al y1 Ga 1-x1-y1 N layer and the second p-type In x2 Al y2 Ga 1-x2-y2 an anode for each of the N layers.

104. The semiconductor structure of claim 103, wherein the cathode comprises Ti and Al.

105. The semiconductor structure according to any one of claims 103 to 104, wherein the cathode and the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

106. The semiconductor structure of any one of claims 103 to 104, wherein the cathode is independently connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

107. The semiconductor structure of any one of claims 103 to 106, wherein the anode comprises a transparent conductive oxide layer or a reflective contact.

108. The semiconductor structure according to any one of claims 103 to 107, wherein the anode and the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

109. The semiconductor structure of any one of claims 103 to 107, wherein the anode is independently connected to the first n-type In x1 Al y1 Ga 1-x1-y1 N layer and the second In x2 Al y2 Ga 1-x2-y2 Each of the N layers is commonly interconnected.

110. The semiconductor structure of any one of claims 103 to 109, wherein the first optoelectronic element and the second optoelectronic element are electrically isolated from each other.

111. A wafer comprising the semiconductor structure according to any one of claims 1 to 108.

112. An optoelectronic device comprising the semiconductor structure according to any one of claims 1 to 108.

113. A multi-color optoelectronic device comprising the semiconductor structure according to any one of claims 1 to 108.

114. A semiconductor device comprising the semiconductor structure according to any one of claims 1 to 108.

115. A lighting system or a display system, the lighting system or the display system comprising a semiconductor device according to claim 114.

116. A method of manufacturing a wurtzite group III nitride crystal semiconductor structure, the method comprising: (a) Depositing a first In layer stacked on a first substrate region of the substrate x1 Al y1 Ga 1-x1-y1 N growth layer; and (b) depositing a second In layer stacked on the second substrate region of the substrate x2 Al y2 Ga 1-x2-y2 N growth layer, where The second x2 Al y2 Ga 1-x2-y2 The N growth layer is stacked on the second patterned In x2s Al y2s Ga 1-x2s-y2s On the N seed region, wherein, The first In x1 Al y1 Ga 1-x1-y1 The N-grown layer includes a first (0001) In x1 Al y1 Ga 1-x1-y1 N growth zone; The second x2 Al y2 Ga 1-x2-y2 The N-grown layer includes a second (0001) In- phase characterized by a second in-plane a-lattice parameter. x2 Al y2 Ga 1-x2-y2 N growth zone; and the a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane, wherein, 0 ≤ x2s ≤ 1, 0 ≤ y2s ≤ 1 and x2s + y2s ≤ 1 0 ≤ x1 ≤ 1, 0 ≤ y1 ≤ 1 and x1 + y1 ≤ 1; and 0 < x2 ≤ 1, 0 ≤ y2 ≤ 1, x2 + y2 ≤ 1 and x2 > x1.

117. The method of claim 116, comprising: Before step (a), Depositing a first patterned In layer stacked on the first substrate region x1s Al y1s Ga 1-x1s-y1s N seed regions, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; and Deposition overlaps the first patterned In x1s Al y1s Ga 1-x1s-y1s The first In x1 Al y1 Ga 1-x1-y1 N growth layer.

118. The method of claim 117, wherein the first patterned In x1s Al y1s Ga 1-x1s-y1s The N seed region includes a first GaN seed region.

119. The method of any one of claims 117 to 118, wherein the second patterned In x1s Al y1s Ga 1-x1s-y1s The N seed region includes a second patterned GaN seed region.

120. The method of any one of claims 117 to 119, wherein the first In x1 Al y1 Ga 1-x1-y1 N growth layer and the second In x2 Al y2 Ga 1-x2-y2 The N growth layer has a different elemental composition.

121. The method according to any one of claims 117 to 120, wherein, The first In x1 Al y1 Ga 1-x1-y1 The N growth layer includes a first In x1 Ga 1-x1 N growth layer; The second x2 Al y2 Ga 1-x2-y2 The N growth layer includes a second In x2 Ga 1-x2 N growth layer; and The first In x1 Ga 1-x1 N growth layer and the second In x2 Ga 1-x2 The N growth layer has a different elemental composition.

122. The method of any one of claims 117 to 121, wherein the first In is deposited x1 Al y1 Ga 1-x1-y1 The N growth layer includes: grow a GaN growth layer to provide a (0001) GaN growth region.

123. The method of any one of claims 117 to 122, wherein the first In is deposited x1 Al y1 Ga 1-x1-y1 The N growth layer includes: Fabricate a first patterned In on a first substrate portion x1s Al y1s Ga 1-x1s-y1s N seed region, where 0≤x1s≤1, 0≤y1s≤1 and x1s+y1s≤1; In x1 Al y1 Ga 1-x1-y1 N in the first patterning In x1s Al y1s Ga 1-x1s-y1s grow on the N seed region so that the growth is on the adjacent patterned In x1s Al y1s Ga 1-x1s-y1s In on the N seed region x1 Al y1 Ga 1-x1-y1 N aggregates and forms the first In x1 Al y1 Ga 1-x1-y1 N growth layer; and Make the first In x1 Al y1 Ga 1-x1-y1 N growth layer is grown to provide (0001)In x1 Al y1 Ga 1-x1-y1 N growth zone.

124. The method of any one of claims 117 to 123, wherein the second In is deposited x2 Al y2 Ga 1-x2-y2 The N growth layer includes: Fabricate the second patterned In x2s Al y2s Ga 1-x2s-y2s N seed area; In x2 Al y2 Ga 1-x2-y2 N in the second patterning In x2s Al y2s Ga 1-x2s-y2s grow on the N seed region so that the growth is adjacent to the In x2s Al y2s Ga 1-x2s-y2s In on the N seed region x2 Al y2 Ga 1-x2-y2 N aggregates and forms In x2 Al y2 Ga 1-x2-y2 N growth layer; and Make the In x2 Al y2 Ga 1-x2-y2 N growth layer is grown to provide (0001)In x2 Al y2 Ga 1-x2-y2 N growth zone.

125. The method of any one of claims 117 to 124, comprising: In depositing the first x1 Al y1 Ga 1-x1-y1 After the N growth layer and the second In x2 Al y2 Ga 1-x2-y2 After the N growth layer is formed, a layer stacked on the first (0001)In x1 Al y1 Ga 1-x1-y1 The first photoelectric element on the N growth region and the second (0001) In x2 Al y2 Ga 1-x2-y2 A second photovoltaic element is formed on the N growth region.

126. The method according to any one of claims 125, wherein, The first photoelectric element includes a first (0001)In x1 Al y1 Ga 1-x1-y1 an epitaxial layer on the N growth region; and The second photoelectric element includes a layer stacked on the second (0001)In x2 Al y2 Ga 1-x2-y2 Epitaxial layer on the N growth region.

127. The method according to claim 126, wherein the epitaxial layer comprises an n-type layer, an active region, a p-type layer or a combination of any of the foregoing items.

128. The method of any one of claims 126 to 127, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer contains GaN.

129. The method of any one of claims 126 to 127, wherein the first In x1 Al y1 Ga 1-x1-y1 The N growth layer contains In x1 Ga 1-x1 N.

130. The method of any one of claims 126 to 127, wherein the second In x2 Al y2 Ga 1-x2-y2 The N growth layer contains In x2 Ga 1-x2 N.

131. The method of any one of claims 126 to 130, wherein the method comprises: Manufacture the first optoelectronic element and the second optoelectronic element simultaneously.

132. The method of any one of claims 126 to 130, wherein the method comprises: Manufacture the first optoelectronic element and the second optoelectronic element successively.

133. The method according to any one of claims 126 to 132, wherein each of the first optoelectronic element and the second optoelectronic element is independently selected from a light emitting diode, a superluminescent light emitting diode, a laser diode, and a vertical cavity surface emitting laser.

134. The method of any one of claims 117 to 133, comprising: In depositing the first x1 Al y1 Ga 1-x1-y1 After the N growth layer and the second In x2 Al y2 Ga 1-x2-y2 After the N growth layer: (c) Deposition superimposed on the In x1 Al y1 Ga 1-x1-y1 The first n-type In x1 Al y1 Ga 1-x1-y1 N layer, and deposited on top of the second In x2 Al y2 Ga 1-x2-y2 The second n-type In x2 Al y2 Ga 1-x2-y2 N-layer; (d) depositing a layer stacked on the first n-type In x1 Al y1 Ga 1-x1-y1 The first active region on the N layer and the second n-type In layer are deposited on top of the second n-type In layer. x2 Al y2 Ga 1-x2-y2 a second active region on the N layer; (e) depositing a first p-type In layer stacked on the first active region x1 Al y1 Ga 1-x1-y1 N layer, and a second p-type In layer deposited on the second active region x2 Al y2 Ga 1-x2-y2 N layers, wherein, the first active region is characterized by an a-lattice parameter in a first plane; the second active region is characterized by an a-lattice parameter in a second plane; and the a-lattice parameter in the second plane is greater than the a-lattice parameter in the first plane.

135. The method of claim 134, wherein the first n-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second n-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited simultaneously.

136. The method of claim 134, wherein the first n-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second n-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited separately.

137. The method according to any one of claims 134 to 136, wherein depositing the first active region and depositing the second active region comprises simultaneous deposition.

138. The method according to any one of claims 134 to 136, wherein depositing the first active region and depositing the second active region comprises independent deposition.

139. The method of any one of claims 134 to 138, wherein the first p-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited simultaneously.

140. The method of any one of claims 134 to 138, wherein the first p-type In is deposited x1 Al y1 Ga 1-x1-y1 N layer and depositing the second p-type In x2 Al y2 Ga 1-x2-y2 The N layer is deposited separately.

141. The method according to any one of claims 134 to 140, wherein simultaneous deposition comprises performing deposition using the same deposition conditions.

142. The method according to any one of claims 134 to 140, wherein independent deposition comprises performing deposition using different deposition conditions.

143. The method of any one of claims 134 to 142, comprising: Deposit electrical contacts stacked on each of the n-type layers.

144. The method of any one of claims 134 to 143, comprising: Deposit electrical contacts stacked on each of the p-type layers.

145. A semiconductor structure manufactured using the method according to any one of claims 116 to 144.

146. A semiconductor wafer, the semiconductor wafer comprising a semiconductor structure according to any one of claims 1 to 110.

147. A multi-wavelength optoelectronic element, the multi-wavelength optoelectronic element comprising a semiconductor structure according to any one of claims 1 to 110. [[ID= 149. A lighting system or a display system, comprising the semiconductor device according to claim 148.

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