Intermittent operation phase-locked loop and implementation method thereof

Abstract

The invention discloses an intermittently operated phase-locked loop and an implementation method thereof. The phase-locked loop can be controlled to be switched between an open loop and a closed loop. The phase-locked loop is controlled to be switched between an open loop and a closed loop by judging whether the performance of a phase-locked loop circuit meets a preset standard of a system applying the phase-locked loop or not in real time; or, the phase-locked loop circuit is controlled to be switched between the open loop and the closed loop according to a preset period according to a time period preset period required by the system for the preset standard of the phase-locked loop circuit. Therefore, the open loop or the closed loop of the phase-locked loop can be controlled according to actual needs, and the influence of the phase-locked loop on the system can be reduced while the phase-locked performance of the phase-locked loop can be completed.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an intermittently operated phase-locked loop and an implementation method thereof. Background Art

[0002] Traditional charge pump phase-locked loop circuits such as Figure 1 As shown, it includes: prescaler ( / M), phase frequency detector (PFD), charge pump circuit (CP), loop filter (LPF), voltage controlled oscillator (VCO), loop divider ( / N), output divider ( / K) and ( / L). Figure 1 The loop filter (LPF) shown can be, for example, a second-order filter shown in the dotted box, including capacitor C1, which acts as an integrating path, typically tens to hundreds of pico-farads; resistor R1 acts as a proportional path, typically thousands to tens of kilo-ohms; and capacitor C2 acts as further filtering, typically several to tens of pico-farads.

[0003] As phase-locked loop (PLL) circuits are increasingly used in chips, a chip typically contains one or more PLL circuits to provide the required clock frequency. However, the voltage-controlled oscillator (VCO) in a traditional PLL plays a crucial role in the overall PLL output jitter. For a VCO, any fluctuation in the control voltage causes fluctuations in the PLL output frequency, resulting in jitter. Furthermore, the VCO is sensitive to its power supply, and power supply fluctuations can also cause fluctuations in the PLL output frequency, resulting in jitter. Generally speaking, fluctuations in the VCO control voltage primarily arise from mismatches in the charge pump (CP) charge and discharge currents, while fluctuations in the VCO power supply primarily arise from crosstalk from other modules on the chip.

[0004] With the advancement of semiconductor technology, chips are increasingly demanding higher speeds and output quality for phase-locked loops (PLLs). Designing a PLL that improves its target performance while also balancing other aspects of its performance has become a major challenge in integrated circuit design. For example, high-speed PLLs are often accompanied by significant output jitter, making achieving high-speed, low-jitter PLLs a challenging task in the industry. Summary of the Invention

[0005] Based on the problem described above, the present invention proposes an intermittently operated phase-locked loop and an implementation method thereof, which can be controlled to switch between an open loop and a closed loop. By judging in real time whether the performance of the phase-locked loop circuit meets the preset standard of the system to which the phase-locked loop is applied, the phase-locked loop is controlled to switch between an open loop and a closed loop; or, a preset period is set according to the time period required by the system's preset standard for the phase-locked loop circuit to control the phase-locked loop circuit to switch between an open loop and a closed loop according to the preset period. In this way, the phase-locked loop can be controlled to be open or closed according to actual needs, so that the phase-locked loop can achieve phase-locked performance while reducing the impact of the phase-locked loop on the system. The details are as follows: In a first aspect, an embodiment of the present invention provides a method for implementing an intermittent phase-locked loop, characterized in that the intermittent phase-locked loop is implemented by controlling the phase-locked loop to switch between an open loop and a closed loop.

[0006] In a preferred embodiment, the phase-locked loop is controlled to switch between open loop and closed loop by determining in real time whether the performance of the phase-locked loop circuit meets the preset standards of the system to which the phase-locked loop is applied; or, a preset period is set according to the time period required by the system's preset standards for the phase-locked loop circuit to control the phase-locked loop circuit to switch between open loop and closed loop according to the preset period.

[0007] In a preferred embodiment, the method comprises the following steps: S1: Controlling the phase-locked loop to be in a closed-loop state, wherein the phase frequency detector compares the divided output frequency of the voltage-controlled oscillator with the frequency of the reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; S2: After a preset first time period, determine whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop. If not, proceed to step S3; if so, continue with step S1. S3: controlling the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; S4: After a preset second time period, determine whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop. If not, maintain step S3; if so, enter step S1 again.

[0008] In a preferred embodiment, the method comprises the following steps: S1: Controlling the phase-locked loop to a closed-loop state, wherein a phase frequency detector compares the divided output frequency of a voltage-controlled oscillator with the frequency of a reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; after the phase-locked loop has locked for a preset first time period, proceeding to step S2; S2: Control the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; and after the phase-locked loop is opened for a preset second time period, enter step S1 again.

[0009] In a preferred embodiment, the voltage-controlled oscillator is controlled by the control voltage and the power supply voltage, or by the control current corresponding to the control voltage and one or more bias currents.

[0010] In a preferred embodiment, the preset standard includes that the system is negligibly affected by the output jitter of the phase-locked loop.

[0011] In a preferred embodiment, the system includes an image sensor circuit, and the preset standard includes a time period during which the image sensor circuit is not performing a read or write operation.

[0012] In a preferred embodiment, to determine whether the performance of the phase-locked loop circuit meets the preset standards of the system using the phase-locked loop, the first time period between two adjacent judgments is less than or equal to the ideal interval time period between any two adjacent read and write operations of the image sensor, and the second time period is less than or equal to the ideal execution time period of any read and write operation of the image sensor.

[0013] In a preferred embodiment, the preset period includes a first time period and a second time period, wherein the first time period is equal to a time period during which the system is non-negligibly affected by the performance of the phase-locked loop; and the second time period is equal to a time period during which the system is negligibly affected by the performance of the phase-locked loop.

[0014] In a preferred embodiment, the first time period is equal to the interval between any two adjacent read and write operations of the image sensor, and the second time period is equal to the time period during which any read and write operation of the image sensor is performed.

[0015] In a preferred embodiment, the row time of the image sensor includes five sub-time periods, the first sub-time period includes a time period for stabilizing the reference signal; the second sub-time period includes a time period for reading the reference signal; the third sub-time period includes a time period for stabilizing the image signal; the fourth time period includes a time period for reading the image signal; and the fifth sub-time period includes time periods other than the first to fourth sub-time periods.

[0016] In a preferred embodiment, after the fifth sub-time period begins, the phase-locked loop is controlled to be closed, and before the first sub-time period arrives, the phase-locked loop is controlled to be open.

[0017] In a second aspect, the present invention proposes a phase-locked loop with intermittent operation, which is implemented according to the method of any of the aforementioned embodiments, wherein the phase-locked loop includes an inner-loop circuit and an outer-loop circuit; the inner-loop circuit includes a first control unit for controlling one or more positions of the inner-loop circuit to achieve the open loop or closed loop of the phase-locked loop.

[0018] In a preferred embodiment, the intra-loop circuit further includes a phase frequency detector, a charge pump circuit, a loop filter, and a frequency divider; the first control unit includes a switch for controlling one or more of the phase frequency detector, the charge pump circuit, and the loop filter to be disconnected or connected; or the first control unit includes a switch located between any two adjacent ones of the phase frequency detector, the charge pump circuit, and the loop filter.

[0019] In a preferred embodiment, the outer loop circuit includes a voltage generating unit, and the voltage generating unit is configured to provide a power supply voltage or one or more bias currents to the voltage controlled oscillator.

[0020] In a preferred embodiment, the voltage generating unit includes a voltage-stabilizing source follower module, and the voltage-stabilizing source follower module includes a single-stage source follower or a multi-stage source follower.

[0021] In a preferred embodiment, each stage of the source follower further includes a second control unit. When the phase-locked loop is open, the second control unit is disconnected; and when the phase-locked loop is closed, the second control unit is connected.

[0022] In a preferred embodiment, at least one stage of the source follower further includes a diode, and the diode is connected in parallel with the second control unit.

[0023] In a preferred embodiment, the source follower also includes a transistor, a first capacitor unit, and a second capacitor unit. The control end of the transistor is connected to the first level through the second control unit, and the drain end is also connected to the first level. One end of the first capacitor unit is connected to the control end of the transistor, and one end of the second capacitor unit is connected to the source end of the transistor. The first capacitor unit and the second capacitor unit are both equivalent capacitor units to the ground.

[0024] In a preferred embodiment, the source terminal of the transistor of the last-stage source follower is connected to the voltage-controlled oscillator to provide a power supply voltage.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: the present invention proposes an intermittently operated phase-locked loop and an implementation method thereof, which can be controlled to switch between open loop and closed loop according to actual needs, so that the phase-locked loop can achieve phase-locked performance while reducing the impact of the phase-locked loop on the system, thereby reducing the requirements for the output quality of the phase-locked loop, and realizing a high-speed and low-jitter phase-locked loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings constitute a part of this specification and are used to further understand the present invention. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principle of the present invention.

[0027] Figure 1 This is an example of an existing phase-locked loop.

[0028] Figure 2 This is an example of an implementation method for an intermittent phase-locked loop.

[0029] Figure 3 This is another example of an intermittent phase-locked loop implementation method.

[0030] Figure 4 FIG. 1 is a structural diagram of an intermittent phase-locked loop according to an embodiment of the present invention.

[0031] Figure 5 FIG. 4 is a structural diagram of an intermittent phase-locked loop according to another embodiment of the present invention.

[0032] Figure 6 FIG. 4 is a structural diagram of an intermittent phase-locked loop according to another embodiment of the present invention.

[0033] Figures 7a-7c This is an example of a filter module according to an embodiment of the present invention.

[0034] Figures 8a-8c This is another example of the filter module according to the embodiment of the present invention.

[0035] Figure 9 This is another example of the filter module according to the embodiment of the present invention.

[0036] Figures 10a-10c This is an example of the second filtering module in an embodiment of the present invention.

[0037] Figure 11 FIG. 1 is a structural diagram of an intermittent phase-locked loop according to a specific embodiment of the present invention.

[0038] Figure 12 for Figure 11 The equivalent circuit structure of one state of the phase-locked loop structure.

[0039] Figures 13 and 14 This is another example of an implementation method of an intermittent phase-locked loop. DETAILED DESCRIPTION

[0040] The following detailed description is illustrative and is intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs.

[0041] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention.

[0042] First, the functions of the basic modules involved in the existing phase-locked loop are introduced as follows. Figure 1 For example: Prescaler ( / M): Receives the frequency f from outside the phase-locked loop ref The clock signal is outputted at a reduced frequency suitable for phase-locked loop applications. ref / M is the reference clock signal. It is usually implemented as a digital counter, and the size of M can be changed according to application requirements.

[0043] Phase Frequency Detector (PFD): Receives the reference clock signal from the prescaler ( / M) and the feedback clock signal from the loop divider ( / N), compares the phase difference between the two, and outputs corresponding up and down signals. If the phase difference between the reference clock and the feedback clock is negative, meaning the reference clock signal lags behind the feedback clock signal, the down signal is high and the up signal is low. If the phase difference between the reference clock and the feedback clock is positive, meaning the reference clock signal leads the feedback clock signal, the up signal is high and the down signal is low. If the reference clock and feedback clock arrive at the same time, the up and down signals are simultaneously high for a period of time before simultaneously turning low. This period of time is usually determined by the delay circuit in the PFD circuit.

[0044] The charge pump circuit (CP) receives the up and down signals from the phase frequency detector (PFD). If the up signal is high and the down signal is low, the charge pump circuit (CP) outputs a charging current to the loop filter (LPF), increasing the output voltage (Vc) of the LPF and the frequency of the voltage controlled oscillator (VCO). If the up signal is low and the down signal is high, the charge pump circuit (CP) draws a discharge current from the loop filter (LPF), decreasing the output voltage (Vc) of the LPF and the frequency of the voltage controlled oscillator (VCO). If both the up and down signals are high, the charge and discharge currents are simultaneously enabled. If there is no mismatch between the charge and discharge currents, the output voltage (Vc) of the LPF and the output frequency of the voltage controlled oscillator (VCO) remain unchanged. If both the up and down signals are low, the charge and discharge currents are simultaneously disabled, resulting in the output voltage (Vc) of the LPF and the output frequency of the voltage controlled oscillator (VCO) remaining unchanged.

[0045] Loop filter (LPF): Figure 1For example, the loop filter (LPF) shown in the figure consists of two capacitors C1 and C2 and a resistor R1. It receives the current signal output by the charge pump circuit (CP) and converts the current signal into a voltage signal Vc, which is output to the voltage-controlled oscillator (VCO). The voltage-controlled oscillator (VCO) changes its output frequency according to the size of Vc.

[0046] Voltage controlled oscillator (VCO): receives the output voltage Vc from the loop filter (LPF) and outputs the corresponding frequency f according to the size of Vc out clock signal.

[0047] Loop divider ( / N): Receives the clock signal from the voltage controlled oscillator (VCO) and outputs a downconverted frequency of f out The feedback clock signal of / N is usually implemented as a digital counter, and the size of N can be changed according to the application requirements.

[0048] Output frequency divider ( / K) and ( / L): Receive the clock signal from the voltage controlled oscillator (VCO) output and output the down-converted frequency to f clk1 =f out / K and f clk2 =f out The clock signal of / L is provided to the modules outside the phase-locked loop that need the clock signal. It is usually implemented in the form of a digital counter, and the values ​​of K and L can be changed according to the application requirements. Since the phase-locked loop is a negative feedback system, when the phase-locked loop is locked, there will be f out / N=f ref / M, get f clk1 =N×f ref / (K×M), and f clk1 =N×f ref / (L×M). By selecting appropriate values ​​of M, N, K, and L, the desired output frequency clock signal can be obtained.

[0049] The following describes in detail an intermittently operated phase-locked loop and an example of its implementation method provided by the present invention.

[0050] In a first aspect, the present invention provides a method for implementing an intermittent phase-locked loop, which implements the intermittent phase-locked loop by controlling the phase-locked loop to switch between an open loop and a closed loop.

[0051] Preferably, the phase-locked loop can be controlled to switch between open loop and closed loop by judging in real time whether the performance of the phase-locked loop circuit meets the preset standard of the system applying the phase-locked loop; or, a preset period is set according to the time period required by the system's preset standard for the phase-locked loop circuit to control the phase-locked loop circuit to switch between open loop and closed loop according to the preset period.

[0052] Preferably, the design of a certain time period can be used to determine in real time whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop, so as to match the different performance requirements of the system using the phase-locked loop in real time, for example, Figure 2 As shown, the method includes the following steps: S1: Controlling the phase-locked loop to be in a closed-loop state, wherein the phase frequency detector compares the divided output frequency of the voltage-controlled oscillator with the frequency of the reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; S2: After a preset first time period, determine whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop. If not, proceed to step S3; if so, continue with step S1. S3: controlling the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; S4: After a preset second time period, determine whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop. If not, maintain step S3; if so, enter step S1 again.

[0053] Preferably, the performance of the phase-locked loop circuit can be designed based on a preset period to match the different performance requirements of the system in which the phase-locked loop is applied, such as Figure 3 As shown, the method includes the following steps: S1: Controlling the phase-locked loop to a closed-loop state, wherein a phase frequency detector compares the divided output frequency of a voltage-controlled oscillator with the frequency of a reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; after the phase-locked loop has locked for a preset first time period, proceeding to step S2; S2: Control the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; and after the phase-locked loop is opened for a preset second time period, enter step S1 again.

[0054] In this way, the phase-locked loop can cycle between the state of step S1 and the state of step S2 to match different performance requirements of the system to which the phase-locked loop is applied.

[0055] The preset standards mentioned above can include any performance requirement for a phase-locked loop (PLL). For example, using output jitter, a key performance indicator of a PLL, as an example, the preset standard could be that the system is negligibly affected by the PLL's output jitter, meaning that the PLL's output jitter is low. For example, an image sensor circuit using a PLL has high requirements for output jitter when performing read and write operations. In this case, the preset standard could be the time period during which the image sensor circuit is not performing read and write operations. By setting the preset standards, the performance requirements of the PLL can be better matched to actual needs.

[0056] For the aforementioned real-time determination of whether the performance of the phase-locked loop circuit meets the preset standards of the system in which the phase-locked loop is used, preferably, the first time period between two adjacent determinations is set to be less than or equal to the ideal interval between any two adjacent read and write operations of the image sensor, and the second time period is set to be less than or equal to the ideal execution time period of any read and write operation of the image sensor. This setting can ensure accurate switching time while appropriately reducing the number of real-time determinations.

[0057] Preferably, a first time period required to maintain lock and a second time period required to maintain open loop can be used as a preset period, with the preset period including the first time period and the second time period. For example, based on actual needs, the first time period is equal to the time period during which the system is significantly affected by the performance of the phase-locked loop; the second time period is equal to the time period during which the system is negligibly affected by the performance of the phase-locked loop. This eliminates the need for a real-time judgment module, allowing for appropriate circuit simplification and system area or volume reduction while adapting to the varying performance requirements of the systems employing the phase-locked loop.

[0058] Preferably, in the application of the image sensor, the first time period can be set to be equal to the interval between any two adjacent read and write operations of the image sensor, and the second time period can be set to be equal to the execution time period of any read and write operation of the image sensor.

[0059] Preferably, the voltage-controlled oscillator is controlled by a control voltage generated by comparing the divided output frequency of the voltage-controlled oscillator with the frequency of the reference clock signal by a frequency and phase detector, and is also controlled by a power supply voltage. Alternatively, the voltage-controlled oscillator is controlled by a control current corresponding to the control voltage and by one or more additional bias currents.

[0060] Preferably, the image sensor uses a correlated double sampling method to sample the output signal at the start and end of photoelectric signal integration. Specifically, within a signal output cycle, two sampling pulses are generated: one for sampling the reference signal and the other for sampling the image signal. Since the interval between the two sampling times is significantly smaller than the time constant, the difference in noise voltage between the two samples is small, and the sampling times are correlated. Subtracting the two sample values ​​can eliminate the interference of reference signal noise to a certain extent, resulting in a value closer to the actual effective value of the image signal. In a preferred embodiment, the effect of noise from the phase-locked loop (PLL) output clock on the correlated double sampling is also reduced by controlling the intermittent operation of the PLL. Controlling the intermittent operation of the PLL can provide a precise clock for the correlated double sampling. Further preferably, a signal output cycle of the image sensor, i.e., a line time, is configured to include five sub-periods: a first sub-period for stabilizing the reference signal; a second sub-period for reading the reference signal; a third sub-period for stabilizing the image signal; a fourth sub-period for reading the image signal; and a fifth sub-period for all time periods other than the first through fourth sub-periods. After the fifth sub-time period begins, the phase-locked loop is controlled to be closed, and before the first sub-time period arrives, the phase-locked loop is controlled to be open.

[0061] In a second aspect, the present invention provides an intermittently operated phase-locked loop, which is implemented according to any of the above-mentioned methods, such as Figure 4 The phase-locked loop includes an inner-loop circuit and an outer-loop circuit; the inner-loop circuit includes a voltage-controlled oscillator (VCO), a phase frequency detector (PFD), a charge pump circuit (CP), a loop filter, and a frequency divider (N). The inner-loop circuit also includes a first control unit for controlling one or more positions of the inner-loop circuit to achieve an open-loop or closed-loop phase-locked loop. Specifically, the first control unit can be a switch that controls one or more of the phase frequency detector (PFD), the charge pump circuit (CP), and the filter to be disconnected or connected; or, the first control unit can also be a switch located between any two adjacent ones of the phase frequency detector (PFD), the charge pump circuit (CP), and the filter, for example Figure 4 Switch S1 is shown.

[0062] Preferably, the outer circuit of the phase-locked loop further includes a voltage generating unit, such as Figure 4 The power supply shown is used to provide a power supply voltage or one or more bias currents to a voltage controlled oscillator (VCO).

[0063] Preferably, Figure 5 As shown, the voltage generating unit includes a voltage stabilizing source follower module, and the voltage stabilizing source module may include a single-stage source follower or a multi-stage source follower. Figure 5 The first-level source follower is shown in FIG. The first-level source follower includes a second control unit, a transistor, a first capacitor unit C21 , and the second capacitor unit C 22 The control terminal of the transistor is connected to the first level VDD through the second control unit, the drain terminal is also connected to the first level VDD, and the first capacitor unit C 21 One end is connected to the control end of the transistor, and the second capacitor unit C 22 One end of the first capacitor unit C 21 , the second capacitor unit C 22 Each is an equivalent capacitance unit relative to ground. The second control unit included in each source follower stage can be any module capable of controlling the connection between the gate and drain terminals of the transistor, such as switch S2. For multi-stage source followers, the source terminal of the transistor in the last source follower stage is connected to a voltage-controlled oscillator (VCO) to provide a power supply voltage.

[0064] Preferably, when the phase-locked loop is open, the second control unit is controlled to be disconnected; and when the phase-locked loop is closed, the second control unit is controlled to be connected. This can improve the power supply suppression of the voltage regulator, thereby further reducing the output jitter of the phase-locked loop. Specifically, when the system is insensitive to the output jitter of the phase-locked loop, the switch S2 is closed, and the power is supplied to C through S2. 21 Charge to the power supply voltage. When the system is more sensitive to the output jitter of the phase-locked loop, the switch S2 is disconnected and the source follows the voltage V SF The value of capacitor C 21 Maintain, thereby significantly improving the power supply rejection of the regulated source.

[0065] For the capacitor C 21 MOS capacitors are preferably used to implement the capacitor C 21 Furthermore, to avoid the leakage of the MOS capacitor itself, the leakage of the switch S2 when it is turned off is designed to be greater than or equal to the capacitance C 21 Leakage, thus ensuring that the source follows the voltage V during the period of the phase-locked loop open loop SF constant.

[0066] Preferably, Figure 6 As shown, the voltage source follower module may further include at least one diode PD, wherein the newly added diode PD can further provide a voltage to the capacitor C 21 In practical applications, the source follower may include at least one diode PD, which is connected in parallel with the second control unit, with one end connected to the first voltage level VDD and the other end connected to the control end of the transistor.

[0067] For any of the aforementioned intermittent phase-locked loops or their implementation methods, the filter can be any loop filter, one end of which is connected to the output terminal Vc node of the charge pump circuit CP. For example, the filter can be Figure 7a The first-order low-pass filter shown in Figure 7b The second-order low-pass filter shown in Figure 7c The third-order low-pass filter shown, or a higher-order low-pass filter, can also be other types of filters. Figure 7a As shown, it includes an RC series circuit with one end connected to the node Vc and the other end grounded. Specifically, the first-order low-pass filter may include a resistor unit R 11 and capacitor unit C 11 ; The filter can also be a second-order low-pass filter, such as Figure 7b As shown, relative to the first-order low-pass filter, it further includes a capacitor unit C with one end connected to the node Vc and the other end grounded. 21 ; The filter can also be a third-order low-pass filter, such as Figure 7c As shown, compared to the second-order low-pass filter, it further includes a resistor unit R 13 and capacitor unit C 13 , resistance unit R 13 One end is connected to the node Vc and the other end is connected to the charge pump current output. The low-pass filter can also be a higher-order low-pass filter, which will not be described here. It should be noted that R 11 、R 13 Represents the total equivalent resistance between the two nodes in the circuit, C 11 、C 21 They are the total equivalent capacitance between two nodes, and may be implemented in different ways depending on the semiconductor manufacturing process.

[0068] Preferably, the position of the first control unit for controlling the switching between the open loop and the closed loop of the phase-locked loop is arbitrary, as long as it can ensure that there is a capacitor to maintain the control voltage of the voltage-controlled oscillator VCO when the phase-locked loop is open. The first control unit for controlling the switching between the open loop and the closed loop of the phase-locked loop can preferably be located at the control switch of the filter. Figures 8a-8c As shown, the first control unit for controlling the phase-locked loop to switch between the open loop and the closed loop may be a switch S 11 When a first-order filter is used, such as Figure 8a As shown, the control voltage of the voltage controlled oscillator VCO in the open loop is determined by C 11 To maintain; when using a second-order filter, such as Figure 8b As shown, when the loop is disconnected, the control voltage of the voltage controlled oscillator VCO is determined by C 12 To maintain, when using a third-order filter, such as Figure 8c As shown, when the loop is disconnected, the control voltage of the voltage controlled oscillator VCO is determined by C 13 To maintain. Preferably, in order to save area, these capacitors of the filter are implemented using MOS capacitors, and in order to avoid slight fluctuations in the control voltage of the voltage-controlled oscillator VCO caused by leakage of the MOS capacitor itself, in a specific implementation, a switch S is set11 The leakage current during disconnection is consistent with the leakage current of the capacitors included in the filter, thereby ensuring that the control voltage of the voltage-controlled oscillator (VCO) remains unchanged during the period when the loop is disconnected.

[0069] Preferably, based on the intermittent phase-locked loop structure and its implementation method of any of the above embodiments, the filter can be further designed to improve the performance of the phase-locked loop. Figure 9 As shown, the filter 0 of the phase-locked loop circuit may include: a first filter module 1, a second filter module 2, and the phase-locked loop circuit further includes a lock detection module 7 and a control module 3. The first filter module 1 may be a first-order, second-order, or higher-order low-pass filter as described above, and the second filter module 2 is also connected to the output terminal Vc node of the charge pump circuit CP. Preferably, the second filter module 2 is as follows Figure 10a As shown, it includes a first capacitor unit C connected in parallel 31 and the first resistance unit R 31 , and a first capacitor unit C connected in parallel 31 and the first resistance unit R 31 The second capacitor unit C between the output terminal and the ground terminal 32 Preferably, the second filtering module 2 can also be as follows Figure 10b As shown, it also includes a second resistance unit R 32 , the second resistance unit R 32 With the first capacitor unit C 31 connected in series with the first resistance unit R 31 Preferably, the second filter module 2 can also be connected in parallel. Figure 10c As shown, it also includes a third resistance unit R 33 , the third resistance unit R 33 and the second capacitor unit C 32 Series connection.

[0070] It should be noted that the first resistance unit R 31 , the second resistance unit R 32 , the third resistance unit R 33 are the total equivalent resistance between the two nodes in the circuit, the first capacitor unit C 31 , the second capacitor unit C 32 They are respectively the total equivalent capacitance between two nodes. The capacitance or resistance may be realized in different forms according to the semiconductor manufacturing process.

[0071] Preferably, the switch used to implement control in any embodiment of the present invention may be, for example, an NMOS tube, a PMOS tube, or a parallel circuit of an NMOS tube and a PMOS tube, and may serve as a control unit as long as it can implement the functions of connection and disconnection.

[0072] Preferably, in a further implementation method of an intermittent phase-locked loop circuit based on the filter design, the control module 3 can also be controlled to bypass the second filter module 2 before the phase-locked loop circuit is locked to increase the locking speed; after the phase-locked loop circuit is locked, the control module 3 controls the second filter module 2 to connect to the phase-locked loop circuit to further reduce jitter or reduce the area of ​​the filter.

[0073] Preferably, the design of a certain time period can be used to determine in real time whether the performance of the phase-locked loop circuit meets the preset standards of the system using the phase-locked loop, so as to match the different performance requirements of the system using the phase-locked loop in real time, thereby further improving the performance of the phase-locked loop. Figure 13 As shown, the method includes the following steps: S1: Controlling the phase-locked loop to be in a closed-loop state, and controlling the bypass of the second filter module by the control module, and the phase frequency detector compares the output frequency of the voltage-controlled oscillator after frequency division with the frequency of the reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; S2: The control module controls the second filter module to connect to the phase-locked loop circuit; S3: After a preset first time period, determining whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop; if not, proceeding to step S4; if so, continuing with step S1; S4: controlling the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; S5: After a preset second time period, determine whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop. If not, maintain step S4; if so, enter step S1 again.

[0074] Preferably, the performance of the phase-locked loop circuit can be designed based on a preset period to match the different performance requirements of the system to which the phase-locked loop is applied, thereby further improving the performance of the phase-locked loop. Figure 14 As shown, the method includes the following steps: S1: Controlling the phase-locked loop to be in a closed-loop state, and controlling the bypass of the second filter module by the control module, and the phase frequency detector compares the output frequency of the voltage-controlled oscillator after frequency division with the frequency of the reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; S2: The control module controls the second filter module to connect to the phase-locked loop circuit, and after the phase-locked loop is locked for a preset first time period, the process proceeds to step S3; S3: Control the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; and after the phase-locked loop is opened for a preset second time period, enter step S1 again.

[0075] Preferably, Figure 11 As shown, the phase-locked loop circuit includes a lock detection module 7 for detecting the lock state of the phase-locked loop circuit and outputting a lock state signal to the control module 3. The control module 3 controls the second filter module 2 according to the lock state signal. The control module 3 can also control the bypass of the second filter module 2 by controlling the parallel partial bypass of the second filter module 2. The control module 3 can include a transmission gate PSG and an inverter INV. The input end and the output end of the transmission gate PSG are electrically connected to the first resistor unit R 31 The first end and the second end refer to the first resistance unit R 31 The first control end of the transmission gate PSG is directly electrically connected to the output end of the lock detection module 7, and the second control end of the transmission gate PSG is electrically connected to the output end of the lock detection module 7 through the inverter INV.

[0076] The control method based on the phase-locked loop circuit can be further designed to include: the control module 3 controls the second filter module 2 to be bypassed before the phase-locked loop circuit is locked according to the lock status signal output by the lock detection module 7 to achieve a fast locking effect; after the phase-locked loop circuit is locked, the second filter module 2 is controlled to be connected to the phase-locked loop circuit to reduce jitter or reduce the area of ​​the filter. Specifically, before locking, the second filter module is bypassed (for example, it can be short-circuited), at which time only the first filter module 1 is active, which can achieve a fast locking effect; after locking, the second filter module 2 is active to achieve a small equivalent Kvco (Gain of the voltage controlled oscillator). At this time, according to the application requirements, the small equivalent Kvco Achieve low area or low jitter effects.

[0077] Preferably, when the phase-locked loop is not locked, the output signal of the lock detection module 7 is low, at this time the transmission gate PSG is turned on, Vc and Vcont are short-circuited, that is, the circuit of the parallel part of the second filter module 2 is bypassed, at this time, the phase-locked loop circuit locking speed can be accelerated, at this time the equivalent circuit can be as follows Figure 12 As shown, the capacitance from Vc to ground is changed from C2 in the traditional phase-locked loop circuit to C 12 +C 32 .

[0078] By setting the first resistance unit R 31 The resistance value is designed to be several orders of magnitude higher than the R1 included in the traditional phase-locked loop filter, but the first capacitor unit C 31 and the second capacitor unit C 32The difference between the capacitors C1 and C2 in the traditional phase-locked loop filter is less than two orders of magnitude; therefore, the additional zeros and poles introduced by the second filter module circuit will be much smaller than the zeros and poles introduced by the traditional second-order filter (R1, C1, C2). Therefore, these newly added modules can make the open-loop transfer function of the phase-locked loop look first at the first resistor unit R 31 , the first capacitor unit C 31 and the second capacitor unit C 32 The introduced zero poles are followed by the resistance unit R of the low-pass loop filter of the first filtering module. 11 , capacitor unit C 11 , capacitor unit C 12 The low-frequency component of Vc can be introduced through the first resistor unit R 31 Directly reaches Vcont, and the high frequency component of Vc passes through the first capacitor unit C 31 The voltage is divided and reaches Vcont after attenuation, which eventually makes the loop equivalent to the traditional phase-locked loop. K VCO Decayed to α times of the original value, where α=C 31 ⁄(C 31 +C 32 ). Using equivalent K VCO Compared with the capacitors C1 and C2 of the traditional loop filter, the capacitor unit C involved in the first filtering module of this embodiment is α times the original one. 11 、C 12 It can be reduced to α times of the original value. In order to ensure that the loop bandwidth and phase margin remain unchanged, it is only necessary to enlarge the resistor R1 used in the traditional phase-locked loop to 1⁄α times of the original value, that is, to set the resistance unit R of the first filter module 11 The resistance value is 1 / α times that of R1. Since capacitors are one of the most area-consuming components in an integrated circuit, a large capacitor means a large size. Therefore, reducing the capacitance described above in this embodiment can significantly reduce the area of ​​the phase-locked loop filter, thereby reducing the area of ​​the phase-locked loop and its manufacturing cost.

[0079] It should be emphasized that the newly added first resistance unit R 31 A larger resistance value is set to reduce the effect of the large time constant introduced by the larger resistance value on the slow voltage buildup, that is, to reduce the newly added first resistance unit R 31 , the first capacitor unit C 31 and the second capacitor unit C 32The influence on the Vc node voltage and Vcont node voltage establishment speed of the phase-locked loop before locking. This embodiment adopts the lock detection module 7 to control the filter 0 so that before locking, although the topology of the phase-locked loop is consistent with the traditional one, due to the resistance unit R 11 It is 1⁄α times of the traditional resistor R1, and the capacitor unit C 11 The capacitance is α times that of the capacitor C1 of the traditional structure, which can make the loop bandwidth of the phase-locked loop in this stage higher than the loop bandwidth of the traditional structure, thereby achieving a faster locking effect compared with the traditional structure.

[0080] In addition, the phase-locked loop circuit can also be further designed into a phase-locked loop circuit with low output jitter, using the equivalent K VCO The characteristic of attenuation to α times of the original value only requires maintaining the resistance unit R of the first filter module compared to the traditional structure. 11 、C 11 、C 12 By keeping the values ​​of R1, C1, and C2 consistent with those of the traditional phase-locked loop circuit filter and increasing the phase-locked loop charge pump current to 1⁄α times that of the traditional structure, smaller output jitter can be achieved while maintaining the same loop bandwidth and phase margin compared to the traditional structure, while achieving faster locking.

[0081] While the basic concepts have been described above, it will be apparent to those skilled in the art that the detailed disclosure is merely illustrative and does not limit the present invention. Although not explicitly described herein, those skilled in the art may make various modifications, improvements, and revisions to the present invention. Such modifications, improvements, and revisions are suggested in the present invention and remain within the spirit and scope of the exemplary embodiments of the present invention.

[0082] It should be understood that the embodiments described herein are intended only to illustrate the principles of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly described and illustrated herein.

Claims

1. A method for implementing an intermittent phase-locked loop, characterized in that: The intermittent phase-locked loop is realized by controlling the phase-locked loop to switch between an open loop and a closed loop.

2. The method according to claim 1, characterized in that By determining in real time whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop, the phase-locked loop is controlled to switch between open loop and closed loop; or, A period is preset according to a time period required by a preset standard of the system for the phase-locked loop circuit to control the phase-locked loop circuit to switch between an open loop and a closed loop according to the preset period.

3. The method according to claim 2, characterized in that The method comprises the following steps, S1: Controlling the phase-locked loop to be in a closed-loop state, wherein the phase frequency detector compares the divided output frequency of the voltage-controlled oscillator with the frequency of the reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; S2: After a preset first time period, determine whether the performance of the phase-locked loop circuit meets the preset standard of the system using the phase-locked loop. If not, proceed to step S3; if so, continue with step S1. S3: controlling the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; S4: after a preset second time period, determining whether the performance of the phase-locked loop circuit meets a preset standard of the system in which the phase-locked loop is applied; if not, maintaining step S3; If satisfied, then go to step S1 again.

4. The method according to claim 2, characterized in that The method comprises the following steps, S1: Controlling the phase-locked loop to a closed-loop state, wherein a phase frequency detector compares the divided output frequency of a voltage-controlled oscillator with the frequency of a reference clock signal to generate a stable control voltage or control current to lock the phase-locked loop; after the phase-locked loop has locked for a preset first time period, proceeding to step S2; S2: Control the phase-locked loop circuit to open the loop to reduce the impact of the phase-locked loop on the system; and after the phase-locked loop is opened for a preset second time period, enter step S1 again.

5. The method according to any one of claims 3 to 4, characterized in that The voltage-controlled oscillator is controlled by the control voltage and the power supply voltage, or by the control current corresponding to the control voltage and one or more bias currents.

6. The method according to claim 2, characterized in that The preset standard includes that the system is negligibly affected by the output jitter of the phase-locked loop.

7. The method according to claim 2, characterized in that The system includes an image sensor circuit, and the preset standard includes a time period during which the image sensor circuit is not performing a read or write operation.

8. The method according to claim 3, characterized in that Whether the performance of the phase-locked loop circuit meets a preset standard of a system using the phase-locked loop is determined, wherein the first time period between two adjacent judgments is less than or equal to an ideal interval time period between any two adjacent read and write operations of the image sensor, and the second time period is less than or equal to an ideal execution time period of any read and write operation of the image sensor.

9. The method according to claim 2 or 4, characterized in that The preset period includes a first time period and a second time period, the first time period is equal to a time period in which the system is non-negligibly affected by the performance of the phase-locked loop; the second time period is equal to a time period in which the system is negligibly affected by the performance of the phase-locked loop.

10. The method according to claim 9, characterized in that The first time period is equal to the interval between any two adjacent read and write operations of the image sensor, and the second time period is equal to the time period during which any read and write operation of the image sensor is performed.

11. The method according to any one of claims 1 to 10, characterized in that The line time of the image sensor consists of five sub-time periods: The first sub-time period includes a time period of a stable reference signal; The second sub-time period includes a time period for reading a reference signal; The third sub-period includes a period of time for stabilizing the image signal; The fourth time period includes a time period for reading the image signal; The fifth sub-time period includes time periods other than the first to fourth sub-time periods.

12. The method according to claim 11, characterized in that After the fifth sub-time period begins, the phase-locked loop is controlled to be closed, and before the first sub-time period arrives, the phase-locked loop is controlled to be open.

13. A phase-locked loop (PLL) operating intermittently, implemented according to the method according to any one of claims 1 to 10, wherein the PLL comprises an inner loop circuit and an outer loop circuit; The in-loop circuit includes a first control unit, which is used to control one or more positions of the in-loop circuit to achieve the open loop or closed loop of the phase-locked loop.

14. The intermittently operated phase-locked loop according to claim 13, characterized in that: The loop circuit also includes a frequency detector, a charge pump circuit, a loop filter, and a frequency divider; The first control unit includes a switch for controlling one or more of the phase frequency detector, the charge pump circuit, and the loop filter to be disconnected or connected; or the first control unit includes a switch located between any two adjacent ones of the phase frequency detector, the charge pump circuit, and the loop filter. 15 . The intermittently operated phase-locked loop according to claim 13 , wherein the outer loop circuit comprises a voltage generating unit, and the voltage generating unit is configured to provide a power supply voltage or one or more bias currents to the voltage-controlled oscillator.

16. The intermittently operated phase-locked loop according to claim 15, characterized in that: The voltage generating unit includes a voltage-stabilizing source follower module, and the voltage-stabilizing source follower module includes a single-stage source follower or a multi-stage source follower.

17. The intermittently operated phase-locked loop according to claim 16, characterized in that: Each stage of the source follower further includes a second control unit. When the phase-locked loop is open, the second control unit is disconnected; and when the phase-locked loop is closed, the second control unit is connected.

18. The intermittently operated phase-locked loop according to claim 17, characterized in that: At least one level of the source follower further includes a diode, and the diode is connected in parallel with the second control unit.

19. The intermittently operated phase-locked loop according to claim 17 or 18, characterized in that: The source follower also includes a transistor, a first capacitor unit, and a second capacitor unit. The control end of the transistor is connected to the first level through the second control unit, and the drain end is also connected to the first level. One end of the first capacitor unit is connected to the control end of the transistor, and one end of the second capacitor unit is connected to the source end of the transistor. The first capacitor unit and the second capacitor unit are both equivalent capacitor units to the ground.

20. The intermittently operated phase-locked loop according to claim 19, characterized in that: The source terminal of the transistor of the last-stage source follower is connected to the voltage-controlled oscillator to provide a power supply voltage.

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