Overshoot and undershoot suppression circuit of low dropout regulator

Abstract

The invention provides an LDO overshoot and undershoot suppression circuit, and belongs to the field of integrated circuits. The LDO overshoot and undershoot suppression circuit comprises an LDO used for providing a stable output voltage; the overshoot suppression circuit is used for suppressing overshoot of the LDO; the undershoot suppression circuit is used for suppressing the undershoot of the LDO; the overshoot suppression circuit comprises a first comparator and a fifth transistor, the inverting input end of the first comparator is electrically connected with the output end of the LDO, the non-inverting input end of the first comparator is connected with a first reference voltage, and the output end of the first comparator is electrically connected with the grid electrode of the fifth transistor. The undershoot suppression circuit comprises a second comparator, a first transistor, a second transistor and a third transistor, the non-inverting input end of the second comparator is connected with a second reference voltage, the inverting input end of the second comparator is electrically connected with the output end of the LDO, and the output end of the second comparator is electrically connected with the grid electrode of the first transistor. According to the LDO overshoot and undershoot suppression circuit, LDO overshoot and undershoot can be suppressed.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an overshoot and undershoot suppression circuit for a low voltage difference linear regulator. Background Art

[0002] An LDO (Low Dropout Regulator) is a commonly used power management module. It provides a stable voltage output for the internal circuits of memory devices. However, during operation, the LDO's output voltage may overshoot or undershoot, which can negatively impact the entire circuit. Summary of the Invention

[0003] The present invention aims to provide an LDO overshoot and undershoot suppression circuit capable of suppressing LDO overshoot and undershoot, a memory with the LDO overshoot and undershoot suppression circuit, and a control method of the LDO overshoot and undershoot suppression circuit.

[0004] The present invention discloses an LDO overshoot and undershoot suppression circuit, which is characterized by comprising:

[0005] A low-dropout linear regulator for providing a stable output voltage;

[0006] an overshoot suppression circuit, configured to suppress overshoot of the low-dropout linear regulator;

[0007] an undershoot suppression circuit, configured to suppress the undershoot of the low-dropout linear regulator;

[0008] The overshoot suppression circuit includes: a first comparator and a fifth transistor, wherein the inverting input terminal of the first comparator is electrically connected to the output terminal of the low-voltage difference linear regulator, the non-inverting input terminal of the first comparator is connected to a first reference voltage, the output terminal of the first comparator is electrically connected to the gate of the fifth transistor, the source of the fifth transistor is electrically connected to the output terminal of the low-voltage difference linear regulator, and the drain of the fifth transistor is grounded;

[0009] The undershoot suppression circuit includes: a second comparator, a first transistor, a second transistor and a third transistor, the non-inverting input of the second comparator is connected to a second reference voltage, the inverting input of the second comparator is electrically connected to the output of the low-voltage difference linear regulator, the output of the second comparator is electrically connected to the gate of the first transistor, the source of the first transistor is grounded, the drain of the first transistor is electrically connected to the gate and drain of the second transistor, and the gate of the third transistor, the sources of the second transistor and the third transistor are connected to a power supply voltage, and the drain of the third transistor is electrically connected to the gate of the power tube of the low-voltage difference linear regulator.

[0010] The present invention also discloses a memory with a low voltage difference linear regulator overshoot and undershoot suppression circuit, which is characterized by comprising:

[0011] A low voltage dropout linear regulator overshoot and undershoot suppression circuit, comprising:

[0012] A low-dropout linear regulator for providing a stable output voltage;

[0013] an overshoot suppression circuit, configured to suppress overshoot of the low-dropout linear regulator;

[0014] an undershoot suppression circuit, configured to suppress the undershoot of the low-dropout linear regulator;

[0015] The overshoot suppression circuit includes: a first comparator and a fifth transistor, wherein the inverting input terminal of the first comparator is electrically connected to the output terminal of the low-voltage difference linear regulator, the non-inverting input terminal of the first comparator is connected to a first reference voltage, the output terminal of the first comparator is electrically connected to the gate of the fifth transistor, the source of the fifth transistor is electrically connected to the output terminal of the low-voltage difference linear regulator, and the drain of the fifth transistor is grounded;

[0016] The undershoot suppression circuit includes: a second comparator, a first transistor, a second transistor and a third transistor, the non-inverting input of the second comparator is connected to a second reference voltage, the inverting input of the second comparator is electrically connected to the output of the low-voltage difference linear regulator, the output of the second comparator is electrically connected to the gate of the first transistor, the source of the first transistor is grounded, the drain of the first transistor is electrically connected to the gate and drain of the second transistor, and the gate of the third transistor, the sources of the second transistor and the third transistor are connected to a power supply voltage, and the drain of the third transistor is electrically connected to the gate of the power tube of the low-voltage difference linear regulator.

[0017] The present invention also discloses a control method for an overshoot and undershoot suppression circuit of a low voltage difference linear regulator, which is characterized in that:

[0018] The low voltage difference linear regulator overshoot and undershoot suppression circuit comprises:

[0019] A low-dropout linear regulator for providing a stable output voltage;

[0020] an overshoot suppression circuit, configured to suppress overshoot of the low-dropout linear regulator;

[0021] an undershoot suppression circuit, configured to suppress the undershoot of the low-dropout linear regulator;

[0022] The overshoot suppression circuit includes: a first comparator and a fifth transistor, wherein the inverting input terminal of the first comparator is electrically connected to the output terminal of the low-voltage difference linear regulator, the non-inverting input terminal of the first comparator is connected to a first reference voltage, the output terminal of the first comparator is electrically connected to the gate of the fifth transistor, the source of the fifth transistor is electrically connected to the output terminal of the low-voltage difference linear regulator, and the drain of the fifth transistor is grounded;

[0023] The undershoot suppression circuit includes: a second comparator, a first transistor, a second transistor and a third transistor, a non-inverting input terminal of the second comparator is connected to a second reference voltage, an inverting input terminal of the second comparator is electrically connected to the output terminal of the low-voltage difference linear regulator, an output terminal of the second comparator is electrically connected to the gate of the first transistor, a source of the first transistor is grounded, a drain of the first transistor is electrically connected to the gate and drain of the second transistor, and the gate of the third transistor, sources of the second transistor and the third transistor are connected to a power supply voltage, and a drain of the third transistor is electrically connected to the gate of a power transistor of the low-voltage difference linear regulator;

[0024] The control method of the low voltage difference linear regulator overshoot and undershoot suppression circuit includes:

[0025] an overshoot suppression step, wherein when the output voltage overshoots, the voltage at the inverting output terminal of the first comparator is higher than the first reference voltage, the first comparator outputs a low level, and the fifth transistor is turned on to pull down the output voltage;

[0026] Undershoot suppression step: when the output voltage undershoots, the voltage at the inverting input terminal of the second comparator is lower than the second reference voltage, the second comparator outputs a high level, the first transistor is turned on, the gate voltage of the third transistor is pulled down, and the third transistor is turned on, pulling up the output voltage.

[0027] The LDO overshoot and undershoot suppression circuit, the memory with the LDO overshoot and undershoot suppression circuit, and the control method of the LDO overshoot and undershoot suppression circuit of the present invention can suppress LDO overshoot and undershoot, thereby making the output voltage of the LDO more stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic block diagram of a memory with an LDO overshoot and undershoot suppression circuit according to the present invention.

[0029] Figure 2 It is a schematic diagram of an LDO overshoot and undershoot suppression circuit of the present invention.

[0030] Figure 3The present invention is a flow chart of a method for controlling an LDO overshoot and undershoot suppression circuit.

[0031] Explanation of symbols

[0032] 100LDO overshoot and undershoot suppression circuit

[0033] 10LDO

[0034] 11Third comparator

[0035] 20 Overshoot suppression circuit

[0036] 21 First comparator

[0037] 30 Undershoot suppression circuit

[0038] 31 Second comparator

[0039] R1 first resistor

[0040] R2 second resistor

[0041] M power tube

[0042] M1 first transistor

[0043] M2 second transistor

[0044] M3 third transistor

[0045] M5 fifth transistor DETAILED DESCRIPTION

[0046] The LDO overshoot and undershoot suppression circuit, the memory with the LDO overshoot and undershoot suppression circuit, and the LDO overshoot and undershoot suppression method of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 Schematic block diagram of a memory with an LDO overshoot and undershoot suppression circuit according to the present invention. Figure 1 As shown, the memory with an LDO overshoot and undershoot suppression circuit of the present invention includes an LDO overshoot and undershoot suppression circuit 100, which includes: an LDO 10, which is used to provide a stable output voltage VOUT; an overshoot suppression circuit 20, which is used to suppress overshoot of the LDO 10; and an undershoot suppression circuit 30, which is used to suppress undershoot of the LDO 10.

[0047] Figure 2 : is a circuit structure diagram of the LDO overshoot and undershoot suppression circuit of the present invention. Figure 2As shown, the overshoot suppression circuit 20 includes: a first comparator 21 and a fifth transistor M5, wherein the inverting input terminal of the first comparator 21 is electrically connected to the output terminal of the LDO 10, the non-inverting input terminal of the first comparator 21 is connected to the first reference voltage VREFN, the output terminal of the first comparator 21 is electrically connected to the gate of the fifth transistor M5, the source of the fifth transistor M5 is electrically connected to the output terminal of the LDO 10, and the drain of the fifth transistor M5 is grounded.

[0048] In this embodiment, the fifth transistor M5 is a PMOS (P Metal Oxide Semiconductor Field Effect Transistor). The first reference voltage VREFN is a voltage where an overshoot occurs, for example, 1.3V.

[0049] The undershoot suppression circuit 30 includes: a second comparator 31, a first transistor M1, a second transistor M2, and a third transistor M3. The non-inverting input terminal of the second comparator 31 is connected to the second reference voltage VREFP, the inverting input terminal of the second comparator 31 is electrically connected to the output terminal of the LDO 10, the output terminal of the second comparator 31 is electrically connected to the gate of the first transistor M1, the source of the first transistor M1 is grounded, the drain of the first transistor M1 is electrically connected to the gate and drain of the second transistor M2, and the gate of the third transistor M3, the sources of the second transistor M2 and the third transistor M3 are connected to the power supply voltage VDD, and the drain of the third transistor M3 is electrically connected to the gate of the power transistor M of the LDO 10.

[0050] In this embodiment, the first transistor M1 is an NMOS (N Metal Oxide Semiconductor Field Effect Transistor), and the second transistor M2 and the third transistor M3 are both PMOS. The second reference voltage VREFP is an undershoot voltage, for example, 0.6V. The power supply voltage VDD is 3.3V.

[0051] The LDO 10 can be an LDO commonly used in the art. In this embodiment, the LDO 10 includes: a third comparator 11, a power tube M, a first resistor R1, and a second resistor R2. The power tube M is an N-type power tube, the drain of the power tube M is connected to the power supply voltage VDD, the gate is electrically connected to the output end of the third comparator 11, and the source is electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The non-inverting input end of the third comparator 11 is connected to the third reference voltage VREF, and the inverting input end of the third comparator 11 is electrically connected to the second end of the first resistor R1. The source of the power tube M is electrically connected to the output end of the LDO 10, and is used to output a stable output voltage VOUT to an external circuit.

[0052] In this embodiment, the power tube M is an N-type power tube, which is used in application scenarios where the voltage difference between the input voltage and the output voltage VOUT is relatively large.

[0053] Figure 3 FIG. 1 is a flow chart of a control method for an LDO overshoot and undershoot suppression circuit according to the present invention. Figure 3 As shown, the control method of the LDO overshoot and undershoot suppression circuit of the present invention includes:

[0054] In the overshoot suppression step S001, when the output voltage VOUT overshoots, the voltage at the inverting output terminal of the first comparator 21 will be higher than the first reference voltage VREFN. At this time, the output terminal of the first comparator 21 is at a low level, and the fifth transistor M5 is turned on, pulling down the output voltage VOUT, thereby suppressing the overshoot.

[0055] In this embodiment, the normal value of the output voltage VOUT is 1.1 V, and the first reference voltage VREFN is 1.3 V. That is, when the output voltage VOUT is greater than 1.3 V, the output terminal of the first comparator 21 is at a low level, and the fifth transistor M5 is turned on, pulling down the output voltage VOUT, thereby suppressing overshoot.

[0056] In addition, if Figure 2 As shown, the inverting input terminal of the first comparator 21 is electrically connected to the output terminal of the LDO 10, that is, the detection point A is set at the output terminal of the LDO 10. In this way, when the output voltage VOUT overshoots, it can be quickly detected in real time and the overshoot can be suppressed. Therefore, the speed of suppressing the overshoot can be accelerated.

[0057] In the undershoot suppression step S002, when the output voltage VOUT undershoots, the voltage at the inverting input terminal of the second comparator 31 will be lower than the second reference voltage VREFP. At this time, the output terminal of the second comparator 31 is at a high level, the first transistor M1 is turned on, and the gate voltage of the third transistor M3 is pulled down. The third transistor M3 is turned on, thereby increasing the gate current of the power tube M. In this way, the current flowing through the power tube M will also increase, so that the output voltage VOUT can be pulled up, thereby suppressing the undershoot.

[0058] In this embodiment, the second reference voltage VREFP is 0.9 V. That is, when the output voltage VOUT is less than 0.9 V, the output terminal of the second comparator 31 is high, the first transistor M1 and the third transistor M3 are turned on, and the output voltage VOUT is pulled up, thereby suppressing undershoot.

[0059] In addition, if Figure 2 As shown, the inverting input terminal of the second comparator 31 is electrically connected to the output terminal of the LDO 10. That is, the detection point A is set at the output terminal of the LDO 10. In this way, when the output voltage VOUT undershoots, feedback can be provided in a timely manner to suppress the undershoot. Therefore, the speed of suppressing the undershoot can be accelerated.

[0060] By means of the LDO overshoot and undershoot suppression circuit, the memory with the LDO overshoot and undershoot suppression circuit, and the control method of the LDO overshoot and undershoot suppression circuit of the present invention, the overshoot and undershoot of the LDO can be suppressed, thereby making the output voltage of the LDO more stable.

[0061] Although the present invention has been disclosed in the form of embodiments as described above, they are not intended to limit the present invention. Any professional and technical personnel in this field may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached claims.

Claims

1. A low-dropout linear regulator overshoot and undershoot suppression circuit, characterized in that: include: A low-dropout linear regulator (10) for providing a stable output voltage; an overshoot suppression circuit (20) for suppressing overshoot of the low-dropout linear regulator (10); An undershoot suppression circuit (30) for suppressing undershoot of the low-dropout linear regulator (10); The overshoot suppression circuit (20) comprises: a first comparator (21) and a fifth transistor (M5), wherein the inverting input terminal of the first comparator (21) is electrically connected to the output terminal of the low-voltage-difference linear regulator (10), the non-inverting input terminal of the first comparator (21) is connected to a first reference voltage, the output terminal of the first comparator (21) is electrically connected to the gate of the fifth transistor (M5), the source of the fifth transistor (M5) is electrically connected to the output terminal of the low-voltage-difference linear regulator (10), and the drain of the fifth transistor (M5) is grounded; The undershoot suppression circuit (30) comprises: a second comparator (31), a first transistor (M1), a second transistor (M2) and a third transistor (M3); a non-inverting input terminal of the second comparator (31) is connected to a second reference voltage; an inverting input terminal of the second comparator (31) is electrically connected to the output terminal of the low-voltage-difference linear regulator (10); an output terminal of the second comparator (31) is electrically connected to the gate of the first transistor (M1); a source terminal of the first transistor (M1) is grounded; a drain terminal of the first transistor (M1) is electrically connected to the gate and drain terminal of the second transistor (M2) and the gate terminal of the third transistor (M3); sources of the second transistor (M2) and the third transistor (M3) are connected to a power supply voltage; and a drain terminal of the third transistor (M3) is electrically connected to the gate terminal of the power transistor of the low-voltage-difference linear regulator (10).

Images