A data reading method of SRAM memory cell in FPGA

Abstract

The application discloses a data reading method of an SRAM storage unit in an FPGA, and relates to the field of FPGA. The method controls the word line of the selected SRAM storage unit to switch from a low level state to a high level state from t0 moment until t4 moment. The word line voltage value is boosted to a preset lower limit voltage value at t0 moment to realize the switching to the high level state, and is gradually increased from the preset lower limit voltage value according to a preset boosting mode until a preset upper limit voltage value is reached, and the boosting speed of the word line voltage value does not exceed a preset boosting speed. The word line voltage value is gradually boosted according to a smaller boosting speed, thereby effectively avoiding the problem of voltage overshoot caused when the word line voltage value is instantaneously switched to the high level state at the preset upper limit voltage value, avoiding the influence on the data in the SRAM storage unit, ensuring the accuracy of data reading, and ensuring that the data in the FPGA is not damaged.

Description

TECHNICAL FIELD

[0001] The application relates to the field of FPGA technology, and particularly relates to a data reading method for an SRAM storage unit in an FPGA. BACKGROUND

[0002] A static random access memory (SRAM) is a memory with a static access function, and can save data stored in the memory without a refresh circuit. An SRAM with a six-tube structure is widely used in an FPGA as a storage unit to form a storage array. A single SRAM storage unit with a six-tube structure is connected to a word line WL and bit lines BL and BLN in the FPGA, as shown in the figure. Figure 1

[0003] The working process of the SRAM storage unit in the FPGA storage array mainly includes three parts: writing data into the SRAM storage unit, keeping data in the SRAM storage unit, and reading data from the SRAM storage unit. In the stage of reading data from the SRAM storage unit, the voltage of the word line WL needs to be precharged to a high level to turn on the gate tubes M5 and M6, and then the data node in the SRAM storage unit charges / discharges to the bit lines BL and BLN, and a sensitive amplifier identifies the voltage difference between the two bit lines BL and BLN to amplify the level into qualified high and low levels, that is, the data is read out. However, when the voltage of the word line WL is switched from a low level state to a high level state, an overshoot phenomenon is likely to occur in practice, and when the voltage of the word line WL acting on the SRAM storage unit has the overshoot phenomenon, the data in the SRAM storage unit is likely to be damaged. SUMMARY

[0004] In view of the above problems and technical requirements, the present application provides a data reading method for an SRAM storage unit in an FPGA, and the technical scheme of the application is as follows.

[0005] The data reading method for the SRAM storage unit in the FPGA comprises the following steps.

[0006] The bit line of the selected SRAM storage unit is precharged, the word line of the selected SRAM storage unit is switched from a low level state to a high level state from t0 to t4, and then switched back to the low level state at t4; and the data of the selected SRAM storage unit is read through the bit line within the time range from t0 to t4.

[0007] ​The word line voltage value of the selected SRAM memory unit is boosted to a preset lower limit voltage value at t0 to switch to a high level state, and is gradually increased from the preset lower limit voltage value according to a preset boosting mode until a preset upper limit voltage value is reached, and the boosting speed of the word line voltage value does not exceed a preset boosting speed.

[0008] A further technical solution is that the method further comprises:

[0009] In the debugging stage of the FPGA, the boosting mode of the word line voltage value is adjusted, and data reading is performed on each SRAM memory unit through the bit lines respectively until the preset boosting mode is determined; when the word line voltage value is boosted according to the preset boosting mode, data reading operations of all SRAM memory units can be completed within the time range from t0 to t4.

[0010] A further technical solution is that the method further comprises:

[0011] The programmable fuse array is programmed according to the boosting control logic corresponding to the preset boosting mode, and the programmed programmable fuse array controls the word line voltage value to be boosted according to the preset boosting mode in the working stage of the FPGA.

[0012] A further technical solution is that the method further comprises:

[0013] When the word line voltage value is boosted to reach the preset upper limit voltage value, and the read enable signal of the effective level is detected, the voltage difference between the two bit lines connected to the selected SRAM memory unit is stored in the data holder.

[0014] A further technical solution is that the preset boosting mode is a stepped boosting mode composed of a plurality of gradient voltage values that increase sequentially, the voltage difference between adjacent two gradient voltage values does not exceed a voltage difference threshold, the smallest gradient voltage value is equal to the preset lower limit voltage value, and the largest gradient voltage value is equal to the preset upper limit voltage value; the programmable fuse array controls the word line voltage generation circuit to generate each gradient voltage value and apply it to the word line connected to the selected SRAM memory unit according to the boosting control logic.

[0015] A further technical solution is that the duration of each gradient voltage value is equal, or the duration of at least two gradient voltage values is not equal.

[0016] A further technical solution is that the word line voltage generation circuit comprises a voltage dividing circuit, a multiplexer and a configuration control circuit, the voltage dividing circuit leads out a plurality of voltage dividing ports connected to each input end of the multiplexer, and the programmable fuse array controls the voltage dividing ratio of the voltage dividing circuit according to the boosting control logic, so that the voltage dividing circuit outputs each corresponding gradient voltage value through each voltage dividing port.

[0017] The configuration control circuit is connected to a control end of the multiplexer and controls the multiplexer to output the gradient voltage values obtained by each input end in ascending order, and the gradient voltage value output by the multiplexer is applied to the word line connected to the selected SRAM storage unit as a word line voltage value.

[0018] The further technical solution is that the configuration control circuit comprises a configuration controller, an address decoder and an address outputter.

[0019] The configuration controller sends the SRAM address of the selected SRAM storage unit to the address decoder, the address decoder decodes the received SRAM address and outputs a word line enable signal, and when the address outputter obtains the valid level of the word line enable signal, the gradient voltage value output by the multiplexer is applied to the word line connected to the selected SRAM storage unit as a word line voltage value according to the corresponding word line address of the obtained SRAM address.

[0020] The further technical solution is that the address outputter comprises a NAND gate, an inverter and a level conversion unit connected in sequence, the NAND gate obtains the word line enable signal and the word line address at the input end, the NAND gate and the inverter are connected to the power supply voltage, the level conversion unit is connected to the word line voltage value output by the multiplexer, and the level conversion unit converts the power supply voltage into the word line voltage value.

[0021] The further technical solution is that the configuration controller also outputs a reset enable signal to the NAND gate.

[0022] The beneficial technical effects of the present application are:

[0023] The present application discloses a data reading method of an SRAM storage unit in an FPGA. When the word line of the selected SRAM storage unit is switched to a high level state, the data reading method controls the word line voltage value to gradually increase at a smaller voltage increasing speed, thereby effectively avoiding the problem of voltage overshoot when the word line voltage value is instantaneously switched to the preset upper limit voltage value in the high level state, avoiding the influence on the data in the SRAM storage unit, ensuring the accuracy of data reading, and ensuring that the data in the FPGA is not damaged. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a circuit structure of a conventional six-tube SRAM connected to a word line and a bit line in an FPGA.

[0025] Figure 2 It is a method flowchart of the data reading method of the SRAM storage unit in an embodiment.

[0026] Figure 3are the level state waveform diagrams of the pre-charge enable signals PRECHARGE_EN and PRECHARGE_B, the read enable signal READ_EN and the word line WL, and the voltage waveform diagram of the word line voltage value VWL.

[0027] Figure 4 is a circuit structure diagram of a word line voltage generation circuit in an embodiment.

[0028] Figure 5 is a circuit structure diagram of an address outputter in an embodiment. DETAILED DESCRIPTION

[0029] The specific embodiments of the present application will be further described below with reference to the accompanying drawings.

[0030] The present application discloses a data reading method of an SRAM storage unit in an FPGA, please refer to the flow chart shown in Figure 2 and the waveform diagram shown in Figure 3 , which comprises the following steps,

[0031] The selected bit line of the SRAM storage unit is pre-charged, and under the joint action of the pre-charge enable signals PRECHARGE_EN and PRECHARGE_B, the two groups of bit lines BL and BLN of the selected SRAM storage unit are pre-charged to high potential and maintained. The waveform diagram of the pre-charge enable signals PRECHARGE_EN and PRECHARGE_B is shown in Figure 3 .

[0032] According to the SRAM address of the selected SRAM storage unit, the word line WL of the selected SRAM storage unit is decoded and controlled to rise from the low potential state VL to the high potential state VH from the t0 time point until the t4 time point to return to the low potential state VL. Please refer to the waveform diagram of the level state of the word line WL shown in Figure 3 .

[0033] But the application in the selected SRAM memory cell word line WL switch to high level state VH, and is not directly selected SRAM memory cell connected to the word line switch to the final required preset upper limit voltage value Vmax. But the control word line voltage value VWL in t0 time to boost to the preset lower limit voltage value to achieve switch to high level state, and then from the preset lower limit voltage value according to the preset boost mode gradually increased until the preset upper limit voltage value Vmax. The boost speed of word line voltage value VWL does not exceed the preset boost speed, including from low level state VL voltage value boost to the preset lower limit voltage value, and the boost speed from the preset lower limit voltage value to the preset upper limit voltage value Vmax does not exceed the preset boost speed. That is, the word line voltage value VWL does not realize the step change directly switch to Vmax as the conventional method, but gradually increases the voltage according to the lower boost speed until the preset upper limit voltage value Vmax, thereby avoiding the overshoot phenomenon caused by switching from low level state voltage value to high level state VH preset upper limit voltage value Vmax, thus avoiding the damage to the SRAM memory cell.

[0034] In the process of controlling the word line voltage value VWL boost, the read operation is started synchronously, and the selected SRAM memory cell is read through the bit line in the time range from t0 to t4. The SRAM memory cell can complete the read operation at any time from t0 to t4.

[0035] Please refer to Figure 2 and Figure 3 When the word line voltage value VWL is boosted to the preset upper limit voltage value Vmax, and the valid level of the read enable signal READ_EN is detected, the voltage difference between the two bit lines connected to the selected SRAM memory cell is stored in the data holder.

[0036] In one embodiment, the preset boost mode of the word line voltage value VWL can be various preset continuous curves, that is, the word line voltage value VWL continuously changes to achieve boost. But considering the difficulty of continuous boost control, and considering that the word line voltage value VWL does not need to be continuously boosted, in another embodiment, please refer to Figure 3 The voltage waveform diagram of the word line voltage value VWL, the preset boost mode is a ladder boost mode composed of several gradient voltage values in turn, the word line voltage value VWL is boosted in turn to reach each gradient voltage value, and each gradient voltage value is maintained for a certain period of time, and the voltage difference between adjacent two gradient voltage values does not exceed the voltage difference threshold, so as to control the boost speed, the minimum gradient voltage value is equal to the preset lower limit voltage value, and the maximum gradient voltage value is equal to the preset upper limit voltage value Vmax. Figure 3Take an example of containing 4 gradient voltage values VOL1, VOL2, VOL3 and VOL4, the gradient voltage value VOL4 is the preset upper limit voltage value Vmax. The duration of VOL1 is t0~t1, the duration of VOL2 is t1~t2, the duration of VOL3 is t2~t3, and the duration of VOL4 is t3~t4. In this step-up mode, the duration of each gradient voltage value is equal, or the duration of at least two gradient voltage values is not equal.

[0037] The word line voltage value VWL is controlled by the word line voltage generation circuit, in one embodiment, the circuit of the word line voltage generation circuit is as shown in Figure 4 The word line voltage generation circuit includes a voltage dividing circuit, a multiplexer and a configuration control circuit. The voltage dividing circuit has several voltage dividing ports connected to the inputs of the multiplexer MUX, and the voltage dividing circuit outputs corresponding gradient voltage values through the voltage dividing ports according to the voltage dividing ratio. For example, the voltage dividing circuit has 4 voltage dividing ports to output VOL1, VOL2, VOL3 and VOL4 to the 4 inputs of the multiplexer MUX. Figure 3 The bandgap reference circuit outputs a zero-temperature-coefficient reference voltage VBG as the reference voltage of the gradient voltage values output by the voltage dividing circuit, and the gradient voltage values at each voltage dividing port are output by a resistor voltage dividing string. Figure 4 For example, the resistor voltage dividing string includes resistors R1, R2 and R3 connected in series, and the configuration is applied according to the actual situation.

[0038] The configuration control circuit is connected to the control end of the multiplexer MUX and controls the multiplexer MUX to output the gradient voltage values obtained by each input in ascending order. The gradient voltage value output by the multiplexer MUX is applied to the word line WL connected to the selected SRAM memory cell as the word line voltage value VWL. In one embodiment, the word line voltage value VWL output by the multiplexer MUX is also output to the configuration control circuit through the voltage follower U1 to improve the voltage stability.

[0039] Please refer to Figure 4 The configuration control circuit includes a configuration controller, an address decoder and an address outputter, and the configuration controller controls the voltage value output by the multiplexer MUX. In one embodiment, as shown in Figure 4 The configuration control circuit also includes a reference voltage selection decoder, and the configuration controller outputs control signals SEL1 and SEL2. The control end of the multiplexer MUX is connected to the reference voltage selection decoder to control the gradient voltage value output by the MUX according to SEL1 and SEL2.

[0040] The configuration controller sends the selected SRAM address of the SRAM memory cell to the address decoder, and the address decoder decodes the received SRAM address and outputs a word line enable signal WL_EN. When the address outputter obtains the valid level of the word line enable signal WL_EN, the word line voltage value VWL output by the multiplexer MUX is applied to the word line connected to the selected SRAM memory cell according to the corresponding word line address WL_ADDR obtained from the SRAM address.

[0041] Please refer to Figure 5 The circuit diagram of the address outputter is shown in FIG. 4. The address outputter includes a NAND gate, an inverter and a level conversion unit connected in sequence. The NAND gate obtains the word line enable signal and the word line address. The NAND gate NAND1 and the inverter OR1 are both connected to the power supply voltage VCCINT. The level conversion unit is connected to the word line voltage value VWL output by the multiplexer MUX, and the level conversion unit converts the power supply voltage VCCINT into the word line voltage value VWL. In addition, the configuration controller also outputs a reset enable signal PROG_EN to the NAND gate, so as to control the reset.

[0042] Based on the data reading method of the present application, considering that the size of the FPGA is gradually increasing, the size of the storage array composed of the internal SRAM memory cells is also gradually increasing, which leads to a longer length of the word line WL and a larger number of SRAM memory cells connected to the same word line WL, such as Figure 4 As shown in FIG. 5, N+1 SRAM memory cells are connected to one word line WL, and the N+1 SRAM memory cells are connected to different bit lines, which are respectively denoted as BL<0>~BL <n>, the number of N is usually large. The word line is a metal line, and is affected by the parasitic capacitance and resistance of the metal line. During transmission, the word line voltage value VWL has a certain voltage drop and delay, which causes the data read time of each SRAM memory cell connected to the same word line to be different. Generally, the closer the SRAM memory cell is to the address output device, the earlier the data read time. For example, the data read time of the SRAM memory cell connected to the bit line BL<0> in Figure 4 is the earliest. The farther the SRAM memory cell is from the address output device, the later the data read time. For example, the data read time of the SRAM memory cell connected to the bit line BL Figure 4 in <n>SRAM memory cells. In addition, the read threshold of the SRAM memory cells with the same structure and size is not the same due to the influence of process, voltage and temperature factors. Therefore, the word line voltage value VWL must have a reasonable voltage range and operation range, which can ensure the success of the data read operation and the correctness of the data read.

[0043] Therefore, during the debugging stage of the FPGA, the configuration control circuit adjusts the boost mode of the word line voltage value VWL, and respectively performs data read on each SRAM memory cell through the bit line, and continuously adjusts the boost mode of the word line voltage value VWL until the preset boost mode is finally determined, so as to ensure that when the word line voltage value VWL is boosted according to the preset boost mode, all SRAM memory cells can complete the data read operation within the time range from t0 to t4, thereby ensuring that the word line voltage value VWL has a reasonable voltage range and operation range.

[0044] Based on Figure 4 As shown in the circuit diagram, when the stepped boost mode is adopted, the configuration control circuit adjusts the gradient voltage value output by the voltage dividing circuit by controlling the voltage dividing ratio of the voltage dividing circuit, so as to adjust the boost mode of the word line voltage value VWL.

[0045] In addition, after the preset boost mode is determined during debugging, the programmable fuse array is programmed according to the boost control logic corresponding to the preset boost mode, and the programmed programmable fuse array controls the word line voltage value VWL to boost according to the preset boost mode according to the boost control logic during the working stage of the FPGA. When the stepped boost mode is adopted, the programmable fuse array controls the word line voltage generation circuit to generate each gradient voltage value and apply it to the word line connected to the selected SRAM memory cell, so as to adjust the boost mode of the word line voltage value VWL. Further, when the word line voltage generation circuit is based on Figure 4 As shown in the circuit diagram, when the stepped boost mode is adopted, the configuration control circuit adjusts the gradient voltage value output by the voltage dividing circuit by controlling the voltage dividing ratio of the voltage dividing circuit, so as to adjust the boost mode of the word line voltage value VWL.

[0046] The above is only the preferred embodiment of the present application, and the present application is not limited to the above embodiments. It can be understood that other improvements and changes directly derived or thought by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.< / n> < / n>

Claims

1. A method for reading data from an SRAM memory cell in an FPGA, comprising: The method comprises: The bit line of the selected SRAM memory cell is pre-charged, the word line of the selected SRAM memory cell is switched from a low level state to a high level state from t0 time and switched back to the low level state at t4 time; and the selected SRAM memory cell is read through the bit line within the time range from t0 time to t4 time. The voltage value of the word line of the selected SRAM memory cell is boosted to a preset lower limit voltage value at t0 time to realize the switching to the high level state, and is gradually increased from the preset lower limit voltage value according to a preset boosting mode until the preset upper limit voltage value is reached, and the boosting speed of the voltage value of the word line does not exceed the preset boosting speed, including the boosting speed from the voltage value at the low level state VL to the preset lower limit voltage value does not exceed the preset boosting speed, and the boosting speed from the preset lower limit voltage value to the preset upper limit voltage value Vmax does not exceed the preset boosting speed. In the debugging stage of the FPGA, the boosting mode of the voltage value of the word line is adjusted, and each SRAM memory cell is read through the bit line until the preset boosting mode is determined; when the voltage value of the word line is boosted according to the preset boosting mode, all SRAM memory cells can complete the data reading operation within the time range from t0 time to t4 time.

2. The data reading method according to claim 1, wherein, The method further comprises: The programmable fuse array is programmed according to the boosting control logic corresponding to the preset boosting mode, and the programmed programmable fuse array controls the voltage value of the word line to be boosted according to the preset boosting mode in the working stage of the FPGA.

3. The data reading method according to claim 1, wherein, The method further comprises: When the voltage value of the word line is boosted to reach the preset upper limit voltage value, and the read enable signal of the effective level is detected, the voltage difference between the two bit lines connected to the selected SRAM memory cell is stored in the data holder.

4. The data reading method according to claim 2, characterized by, The preset boosting mode is a stepwise boosting mode composed of a plurality of gradient voltage values increasing in turn, the voltage difference between adjacent two gradient voltage values does not exceed a voltage difference threshold, the smallest gradient voltage value is equal to the preset lower limit voltage value, and the largest gradient voltage value is equal to the preset upper limit voltage value. The programmable fuse array controls the word line voltage generation circuit to generate each gradient voltage value and apply it to the word line connected to the selected SRAM memory cell according to the boosting control logic.

5. The data reading method according to claim 4, wherein The duration of each gradient voltage value is equal, or the duration of at least two gradient voltage values is not equal.

6. The data reading method according to claim 4, wherein The word line voltage generation circuit comprises a voltage dividing circuit, a multiplexer and a configuration control circuit, the voltage dividing circuit leads out a plurality of voltage dividing ports connected to each input end of the multiplexer, and the programmable fuse array controls the voltage dividing ratio of the voltage dividing circuit according to the boosting control logic, so that the voltage dividing circuit outputs each corresponding gradient voltage value through each voltage dividing port. The configuration control circuit is connected to the control end of the multiplexer and controls the multiplexer to output the gradient voltage values obtained by each input end in ascending order, and the gradient voltage values output by the multiplexer are applied to the word line connected to the selected SRAM memory unit as the word line voltage value.

7. The data reading method according to claim 6, wherein The configuration control circuit comprises a configuration controller, an address decoder and an address outputter. The configuration controller sends the SRAM address of the selected SRAM memory unit to the address decoder, and the address decoder decodes the received SRAM address and outputs a word line enable signal. When the address outputter obtains the valid level word line enable signal, the gradient voltage value output by the multiplexer is applied to the word line connected to the selected SRAM memory unit as the word line voltage value according to the corresponding word line address of the obtained SRAM address.

8. The data reading method according to claim 7, wherein, The address outputter comprises a NAND gate, an inverter and a level conversion unit connected in sequence, the input end of the NAND gate obtains the word line enable signal and the word line address, the NAND gate and the inverter are both connected to the power supply voltage, the level conversion unit is connected to the word line voltage value output by the multiplexer, and the level conversion unit converts the power supply voltage into the word line voltage value.

9. The data reading method according to claim 8, wherein, The configuration controller also outputs a reset enable signal to the NAND gate.

Images