CPU scheduling method and related equipment

Abstract

The invention provides a CPU scheduling method and related equipment, and relates to the technical field of computers. The method comprises the following steps: in response to execution of a load process, sampling a last-stage cache failure event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-stage cache failure event is related to a memory access address, and the memory access hotspot address is a first memory address of which the memory access frequency is greater than a first preset threshold value; determining a CPU corresponding to the memory access hotspot address as a first CPU candidate set of the load process; in the first CPU candidate set, determining a target CPU of the load process; and adding the load process into the process scheduling queue of the target CPU. According to the method and the device, the hotspot address is identified by sampling the last-stage cache failure event, the candidate set and the target CPU are determined, the load process is enabled to preferentially run on the CPU with high affinity with the memory hotspot, and the load performance can be effectively improved under a non-uniform cache architecture.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a CPU scheduling method and related devices. Background Art

[0002] CPU scheduling is an operating system feature that determines which process or thread receives CPU resources for execution. Properly allocating CPU time slices can improve overall system performance and resource utilization. CPU affinity is a technique that assigns specific processes or threads to specific CPU cores.

[0003] When dealing with CPU affinity, related technologies use load balancing strategies that focus solely on CPU compute utilization, prioritizing processes using the same CPU's cache. However, modern processors use a non-coherent cache architecture with cache slices. These load balancing strategies fail to meet the performance optimization requirements of this non-coherent cache architecture, resulting in poor load performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] The present disclosure provides a CPU scheduling method and related devices, which can improve load performance.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a CPU scheduling method is provided, the method comprising: in response to executing a load process, sampling a last-level cache failure event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-level cache failure event is related to a memory access address, and the memory access hotspot address is a first memory address whose memory access frequency is greater than a first preset threshold; determining the CPU corresponding to the memory access hotspot address as a first CPU candidate set for the load process; in the first CPU candidate set, determining a target CPU for the load process; and adding the load process to the process scheduling queue of the target CPU.

[0008] In some embodiments, the sampling of the last-level cache failure events of the process to obtain the memory access hotspot address corresponding to the load process includes: sampling the last-level cache failure events of the load process to obtain the memory access address recorded in the last-level cache failure event; using a hardware hash algorithm to slice and map the memory access address to obtain the hotspot cache slice of the load process; and determining the memory access hotspot address corresponding to the load process based on the hotspot cache slice.

[0009] In some embodiments, before sampling the last-level cache failure event of the load process, it also includes: obtaining attribute information of the load process, wherein the attribute information of the load process is used to indicate whether the load process is a load process that can be dynamically controlled by the CPU; sampling the last-level cache failure event of the load process includes: when the load process is a load process that can be dynamically controlled by the CPU, using precise event sampling technology to sample the last-level cache failure event of the load process that can be dynamically controlled by the CPU.

[0010] In some embodiments, the method also includes: obtaining a second CPU candidate set, which is a CPU candidate set pre-defined in the load process; determining a third CPU candidate set based on the first CPU candidate set and the second CPU candidate set; wherein the third CPU candidate set is the intersection of the first CPU candidate set and the second CPU candidate set; determining a second memory address in the third CPU candidate set whose memory access frequency is greater than a second preset threshold; and determining the CPU corresponding to the cache slice to which the second memory address belongs as the target CPU of the load process.

[0011] In some embodiments, the method further includes: saving the CPU adjustment range of the load process in a CPU scheduling range adjustment field, the CPU adjustment range including the target CPU of the load process, and the CPU scheduling range adjustment field is pre-added in the load process.

[0012] In some embodiments, the load process includes a runnable CPU mask pointer field, and adding the load process to the process scheduling queue of the target CPU includes: updating the runnable CPU mask pointer field according to the target CPU of the load process saved in the CPU scheduling range adjustment field to save the target CPU of the load process to the runnable CPU mask pointer field; adding the load process to the process scheduling queue of the target CPU according to the target CPU of the load process saved in the runnable CPU mask pointer field.

[0013] In some embodiments, saving the CPU adjustment range of the load process in the CPU scheduling range adjustment field includes: using an extended Berkeley packet filter to obtain a first CPU function and a second CPU function in the load process, wherein the first CPU function is a function for setting the CPU of the load process, and the second CPU function is a function for obtaining the CPU affinity of the load process; parsing the first CPU function and the second CPU function to obtain the CPU adjustment range of the load process, and saving the CPU adjustment range of the load process to the CPU scheduling range adjustment field.

[0014] According to another aspect of the present disclosure, a CPU scheduling device is also provided, which includes: a sampling module for sampling the last-level cache failure event of the load process in response to the execution of the load process, and obtaining the memory access hotspot address corresponding to the load process; wherein the last-level cache failure event is related to the memory access address, and the memory access hotspot address is a first memory address whose memory access frequency is greater than a first preset threshold; a first determination module for determining the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process; a second determination module for determining the target CPU of the load process in the first CPU candidate set; and a scheduling module for adding the load process to the process scheduling queue of the target CPU.

[0015] According to another aspect of the present disclosure, an electronic device is also provided, which includes: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute any one of the above-mentioned CPU scheduling methods by executing the executable instructions.

[0016] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the CPU scheduling method described above is implemented.

[0017] According to another aspect of the present disclosure, a computer program product is provided, including: a computer program or instructions, wherein when the computer program or instructions are executed by a processor, any one of the above-mentioned CPU scheduling methods is implemented.

[0018] A CPU scheduling method and related equipment are provided in an embodiment of the present disclosure. The method includes: in response to executing a load process, sampling the last-level cache failure event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-level cache failure event is related to the memory access address, and the memory access hotspot address is a first memory address whose memory access frequency is greater than a first preset threshold; determining the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process; in the first CPU candidate set, determining the target CPU of the load process; and adding the load process to the process scheduling queue of the target CPU. The present disclosure identifies the hotspot address by sampling the last-level cache failure event, determines the candidate set and the target CPU, and allows the load process to run preferentially on the CPU with high affinity to the memory hotspot, thereby optimizing CPU scheduling and effectively improving load performance under a non-consistent cache architecture.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0021] Figure 1 A flow chart of a CPU scheduling method according to an embodiment of the present disclosure is shown;

[0022] Figure 2 A flow chart of a method for obtaining a memory access hotspot address according to an embodiment of the present disclosure is shown;

[0023] Figure 3 A flow chart of a method for determining a target CPU according to an embodiment of the present disclosure is shown;

[0024] Figure 4 A flowchart of another CPU scheduling method according to an embodiment of the present disclosure is shown;

[0025] Figure 5 A flow chart of a method for adding a load process to a process scheduling queue of a target CPU according to an embodiment of the present disclosure is shown;

[0026] Figure 6 A specific flow chart of a CPU scheduling method according to an embodiment of the present disclosure is shown;

[0027] Figure 7 A schematic diagram of a CPU scheduling device according to an embodiment of the present disclosure is shown;

[0028] Figure 8 A structural block diagram of an electronic device in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0030] In addition, the accompanying drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0031] Taking the Linux operating system as an example (the principles of other operating systems are similar), processes have states such as ready, running, sleeping, and zombie. The ready state means that the process is ready and has the conditions to run, and is just waiting for the CPU to allocate a time slice. For multi-core CPUs, each CPU has a dedicated scheduling queue to store processes in the ready state. These processes can run on the corresponding CPU at any time, but it has not yet been their turn. The CPU scheduler plays a key role. It will select suitable processes from the scheduling queue based on a specific algorithm and load them into the CPU for execution. For example, the first-come, first-served algorithm selects processes in the order they arrive, and the time slice rotation allocates a fixed time slice to each process for execution in sequence. In this way, CPU resources are reasonably allocated, improving the overall system performance and resource utilization.

[0032] In related technologies, a CPU scheduling queue is selected when a process wakes up or is newly started. Based on the CPU affinity constraint, cache performance (such as shared L1 / L2 / L3) and idle cores are considered when selecting a queue, and the cache hit rate is optimized while satisfying the affinity. That is, based on the CPU affinity constraint, cores with better cache locality are prioritized among the available CPUs to improve performance. In order to balance the load, in multi-core scenarios, the system migrates processes from busy queues to idle queues while complying with affinity constraints. When weighing cache performance and idle core utilization, the current scheduling algorithm is only based on the locality optimization strategy of the traditional cache hierarchy (L1 / L2 / L3 sharing), and does not consider the impact of the last-level cache (LLC) slicing architecture (Cache Slicing) on ​​the inconsistency of cross-core memory access performance. As a result, scheduling decisions may violate the physical topology characteristics of modern CPU cache subsystems, causing potential cache slice contention and memory access delay jitter, resulting in poor load performance.

[0033] In view of this, an embodiment of the present disclosure provides a CPU scheduling method and related equipment. The method includes: in response to executing a load process, sampling the last-level cache failure event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-level cache failure event is related to the memory access address, and the memory access hotspot address is a first memory address whose memory access frequency is greater than a first preset threshold; determining the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process; in the first CPU candidate set, determining the target CPU of the load process; and adding the load process to the process scheduling queue of the target CPU. The present disclosure identifies the hotspot address by sampling the last-level cache failure event, determines the candidate set and the target CPU, and allows the load process to run preferentially on the CPU with high affinity to the memory hotspot, thereby optimizing CPU scheduling and effectively improving load performance under a non-consistent cache architecture.

[0034] For ease of understanding, before introducing the embodiments of the present disclosure, several terms involved in the embodiments of the present disclosure are first explained as follows:

[0035] Last-level cache (LLC): A computer system typically consists of multiple CPU cores connected to a memory hierarchy. For performance reasons, each CPU core must fetch instructions and data from its own cache (typically extremely fast static random access memory). However, this cache memory is an expensive resource, so computer systems employ a memory hierarchy comprised of increasingly cheaper and slower storage media. Given the prevalence of temporal and spatial locality in modern computing systems, faster caches can minimize the performance-reducing effects of multiple memory accesses by retaining recently used data and instructions. For example, modern processors implement this hierarchy as a Level 1 cache (Level 1), a Level 2 cache (Level 2), and a Level 3 cache (Level 3), also known as the last-level cache (LLC). The L1 and L2 caches are specific to each physical CPU core, while the LLC is shared by all CPU cores on the processor.

[0036] Complex Addressing: The last-level cache is usually divided into multiple cache slices, and a hardware hash algorithm (also known as complex addressing) is used to map different parts of the memory address space between these slices to increase the effective memory bandwidth. The processor will assign one to each CPU core, and the cache slices corresponding to all CPU cores are combined to form a shared last-level cache. Take a processor architecture as an example. In this architecture, complex addressing technology is used. On the one hand, the hardware hash algorithm ensures that the memory addresses are reasonably allocated to each cache slice; on the other hand, although each core has an independent slice, the shared last-level cache allows each core to access the slice resources corresponding to other cores when needed.

[0037] Reverse Engineering: Reverse engineering refers to the process of analyzing existing systems, software, devices, and so on to deduce details such as their design principles, structures, and algorithms. It is the process of tracing back to the original design from the final form of a product or system. Currently, there are relevant public reverse engineering methods that analyze the hash algorithms used in complex addressing technologies to facilitate obtaining the output of which last-level cache shard the physical memory address will be cached to, given the total number of cache shards and the physical memory address.

[0038] Non-Uniform Cache Architecture (NUCA): Since the LLC is divided into multiple slices and the CPU cores share all slices, but physically all CPU cores are interconnected through a ring bus or mesh structure, the time spent by each CPU core to access other slices is higher than accessing the local slice.

[0039] Cache Slice-Aware Memory Allocation: In the context of complex addressing, workloads (or operating system processes) running on CPU cores often trigger memory resource requests. These resource requests are typically satisfied by the operating system kernel. Cache slice-aware memory allocation ensures that allocated physical memory is effectively mapped to local cache slices according to complex addressing algorithms, accelerating last-level cache access performance.

[0040] Extended Berkeley Packet Filter (eBPF): is a kernel technology that originates from the traditional Berkeley Packet Filter (BPF). Traditional BPF is mainly used to filter network packets, but eBPF extends its functionality, enabling it to safely and efficiently execute custom programs in the Linux kernel. These programs can be used for a variety of purposes, such as performance analysis, network monitoring, and security policy enforcement. eBPF hook points, or mount points, are predefined locations in the kernel where eBPF programs can be mounted on demand, allowing them to take control and perform corresponding operations when specific events occur or specific functions are called.

[0041] Precise Event Based Sampling (PEBS): A hardware technology used for performance monitoring, primarily in processors with non-coherent cache architectures. PEBS accurately records information about various events during the processor's instruction execution, such as memory operation addresses.

[0042] CPU affinity refers to the tendency of a process or thread to run on a specific CPU core. The operating system binds a process or thread to a given CPU for as long as possible to minimize the chance of it being moved to other CPU cores.

[0043] The specific implementation of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0044] Figure 1 A flow chart of a CPU scheduling method according to an embodiment of the present disclosure is shown as follows: Figure 1 As shown, the CPU scheduling method provided in the embodiment of the present disclosure includes the following steps:

[0045] S102 , in response to executing the load process, sampling the last-level cache invalidation event of the load process to obtain a memory access hotspot address corresponding to the load process.

[0046] In this embodiment, a load process refers to a program process running in a computer and occupying system resources. A last-level cache miss event is an event triggered by a CPU last-level cache (LLC) miss. When a process accesses memory and the required data is not in the LLC, it must load the data from main memory. At this time, the hardware performance monitoring unit (PMU) records detailed information about the event, including the memory address that triggered the miss and the timestamp. Therefore, last-level cache miss events are related to memory access addresses. Memory access hotspot addresses refer to physical memory addresses that are frequently accessed by a process during execution. By counting recurring addresses in LLC miss events, a set of addresses with an access frequency exceeding a preset threshold (e.g., more than 10^6 times per second) is screened. These addresses typically correspond to key data structures of the process (e.g., hash tables, index trees, etc.), and their access efficiency directly affects overall performance. The first preset threshold defines the critical value of a "hotspot address" and can be dynamically set based on experimental data. For example, if an address triggers 1000 LLC miss events within 1 millisecond, it is determined to be a hotspot address. Threshold setting requires a balance between sensitivity and false positive rate: a too low threshold can lead to noise interference, while a too high threshold may miss real hotspots. That is, a memory access hotspot address is the first memory address whose memory access frequency is greater than a first preset threshold.

[0047] In some embodiments, in order to dynamically control the intervention scope of the load, such as performing CPU scheduling control only on certain loads as needed to improve the isolation of CPU scheduling, before sampling the last-level cache failure event of the load process, it also includes: obtaining attribute information of the load process, wherein the attribute information of the load process is used to indicate whether the load process is a load process that can be dynamically controlled by the CPU; sampling the last-level cache failure event of the load process, including: when the load process is a load process that can be dynamically controlled by the CPU, using precise event sampling technology to sample the last-level cache failure event of the load process that can be dynamically controlled by the CPU.

[0048] In this embodiment, the attribute information of the load process is used to determine whether it can be dynamically controlled by the CPU. This is like putting a label on the process to indicate whether it is a type that can be flexibly managed by the CPU. Before sampling the last-level cache failure event of the load process, its attribute information must be obtained first. If the load process is dynamically controllable by the CPU, the last-level cache failure event is sampled using precise event sampling technology. This is like using a special measurement method for a specific type of object. Specifically, by distinguishing the process number, etc., the CPU scheduling control can be performed on certain load processes as needed, thereby improving the isolation of the CPU scheduling and avoiding interference between different loads.

[0049] S104: Determine the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process.

[0050] In this embodiment, the memory access hotspot address refers to a specific address area in the memory that is frequently accessed. When the CPU executes a task, it needs to read data or instructions from the memory. Frequent access to the hotspot address means that the CPU spends more time processing the data or instructions related to these addresses. The load process is a process that consumes more system resources (such as CPU, memory, etc.). Determining the CPU corresponding to the memory access hotspot address as the first CPU candidate set for the load process means that the CPU that frequently interacts with the hotspot memory address is the priority selection object that may undertake the operation of the load process.

[0051] Specifically, the first CPU candidate set consists of CPU cores that can efficiently access the LLC slice (Cache Slice) where the hotspot address resides. The LLC of modern processors uses a non-uniform cache architecture (NUCA), which divides the LLC into multiple physically distributed slices. Each slice maps a specific range of physical addresses using a hardware hash algorithm (such as Intel's CHA hash). A cache slice is the physical partitioning unit of the LLC, with each slice independently managing a portion of the address space. For example, a 16-core CPU might divide the LLC into four slices, each serving four cores. The latency of a core accessing a local slice (a directly connected slice) is significantly lower than accessing across slices. The core-slice mapping table records the topological relationship between CPU physical cores and LLC slices. The hotspot physical address is input into the LLC slice hash function of the target processor to calculate the slice number to which it belongs. For example, the CHA hash function of the Intel Ice Lake processor performs an XOR operation on bits [14:17] of the physical address to generate a slice index. Based on the mapping table, a physical core directly connected to the slice is selected to form the candidate set.

[0052] S106 , determining a target CPU for the load process in the first CPU candidate set.

[0053] In this embodiment, the target CPU is the optimal core selected after comprehensively considering factors such as cache locality, slice contention, and NUMA distance. It should be noted that when determining the target CPU, the selection logic must avoid the following issues: Slice Contention: If the local slices of the target core are frequently accessed by other processes, cache bandwidth saturation may result. NUMA Latency: If the target core and the hot memory page belong to different NUMA nodes, cross-node access will increase latency.

[0054] Exemplarily, the utilization of each LLC slice can be monitored through resource directory technology (RDT). For example, the CMT (Cache Monitoring Technology) of the Intel processor can count the slice cache occupancy, and the MBM (Memory Bandwidth Monitoring) can measure the memory bandwidth usage. If the bandwidth utilization of a slice exceeds the second preset threshold (such as 80%), its associated core is excluded. It is understandable that if the candidate core shares the L1 / L2 cache with the process history running core, the residual cache data can be reused to reduce low-level cache misses. For example, cores belonging to the same CPU Cluster (such as the performance cluster in the ARMbig.LITTLE architecture) are given priority.

[0055] S108: Add the load process to the process scheduling queue of the target CPU.

[0056] In this embodiment, the process scheduling queue is a queue in the Linux kernel for managing processes to be run. The Completely Fair Scheduler (CFS) uses a red-black tree structure and sorts by the virtual runtime (vruntime) of the process to ensure fair distribution of CPU time slices. The Slice Affinity Tag is a new metadata field added to the process control block (task_struct) to record the optimal LLC slice number of the process. During subsequent load balancing, priority is given to migrating to the core with the same slice to avoid cross-slice access overhead. If the target CPU and the original running core belong to different NUMA nodes, the kernel's page migration mechanism is triggered to migrate the physical page corresponding to the hotspot address to the local memory of the target node to reduce remote access latency.

[0057] For example, the wake_up_new_task() or try_to_wake_up() function can be called to add the process to the target CPU's CFS queue. Simultaneously, the migrate_pages() system call migrates hot memory pages and updates the process's NUMA affinity policy (numa_preferred_node). During the load balancing phase (e.g., the scheduler_tick cycle), the scheduler prioritizes migration targets within the slice affinity range. Otherwise, the pre-copy mechanism is triggered to preheat the target slice's cache.

[0058] In this embodiment, after enabling the last-level cache slice-aware memory allocation strategy, the PEBS technology is used to identify the memory access hotspot address for the controlled load process number, calculate the CPU position of the last-level cache slice corresponding to the hotspot address, and optimize the selection of the target CPU scheduling queue in scenarios such as new creation and wake-up, and optimize the CPU scheduling range in the scheduler load balancing scenario, thereby alleviating the problem of load performance impairment caused by uneven access to CPU last-level cache data caused by NUCA.

[0059] Figure 2 A flow chart of a method for obtaining a memory access hotspot address according to an embodiment of the present disclosure is shown. Figure 2 As shown, the embodiment of the present disclosure provides a method for sampling the last-level cache invalidation event of a process to obtain the memory access hotspot address corresponding to the load process, which may include the following steps:

[0060] S202: Sample the last-level cache failure event of the load process to obtain the memory access address recorded in the last-level cache failure event.

[0061] In this embodiment, the last-level cache miss event (LLC.Miss) of the load process can be monitored and recorded through PEBS (Precise Event-Based Sampling) technology. When the process accesses the memory, if the required data does not hit the last-level cache, the CPU hardware will trigger the LLC.Miss event. At this time, the PEBS mechanism will accurately capture the context information when the event occurs, including: failed memory address: the target memory address (virtual address) that triggers the cache miss; instruction pointer (RIP): the instruction address that causes the cache miss; timestamp: the clock cycle count of the event. The virtual address is then converted to a physical address through page table reverse mapping (because cache slice mapping depends on the physical address) in order to count the access frequency of the physical address.

[0062] In this embodiment, compared to traditional sampling statistics, PEBS can capture the precise failure context (RIP + physical address). For example, in a hash table query scenario, PEBS can distinguish access hotspots of different buckets.

[0063] S204: Use a hardware hash algorithm to perform shard mapping on the memory access address, and obtain the hotspot cache shards of the load process through statistics.

[0064] In this embodiment, because modern processors' LLCs utilize a non-uniform cache architecture (NUCA), their physical structure is divided into multiple cache slices. Each slice uses a hardware hash algorithm to map physical addresses to specific slices. By counting the slices to which all addresses belong, we filter out frequently appearing slices, known as hot cache slices. For example, if Slice 2 is mapped 40% of the time during the sampling period, it is determined to be a hot slice.

[0065] Taking the Intel Skylake architecture as an example, its CHA (Cache Home Agent) hash function performs an XOR operation on specific bits of the physical address (e.g., address bits [14:17]) to generate a slice index value (SliceID). The specific process is as follows: Input physical address: for example, 0x7FAB_CDEF_1234; Bit extraction and operation: Extract address bits [14:17] (assuming binary value 1010), and generate a 4-bit slice index (e.g., 0101, corresponding to Slice 5) through multi-level XOR. The LLC slice to which the address belongs is determined based on the index value. This calculation counts accesses to these slices by the load process, identifying the most frequently accessed cache slices, which helps optimize cache performance and other operations.

[0066] In this embodiment, due to differences in LLC shard hash functions across different processor architectures (e.g., AMD Zen3 uses address bits [13:16]), it is necessary to reverse engineer the function logic using a microarchitecture probe or vendor documentation. This embodiment supports flexible adaptation of heterogeneous processors through an abstract hash interface layer.

[0067] S206: Determine the memory access hotspot address corresponding to the load process according to the hotspot cache slice.

[0068] In this embodiment, each hotspot cache slice has a hardware direct connection relationship with a group of physical CPU cores (recorded in the core-slice affinity table). For example, Slice 2 may serve Cores 4-7, and these cores have the lowest latency in accessing the slice.

[0069] Specifically, a shard-core mapping table can be established based on the cache topology specification provided by the processor manufacturer (such as Intel's Uncore document) to clearly define the list of CPU cores served by each LLC shard.

[0070] In this embodiment, real-time hotspot analysis dynamically establishes a three-level mapping between address, shard, and core. Hotspot shards are determined not by static configuration but by dynamic adjustments based on real-time sampled data. In a non-coherent cache architecture, this mechanism can significantly reduce tail latency caused by cross-shard accesses and improve load performance.

[0071] Figure 3 A flow chart of a method for determining a target CPU according to an embodiment of the present disclosure is shown as follows: Figure 3 As shown, the method for determining the target CPU provided by the embodiment of the present disclosure may include the following steps:

[0072] S302: Acquire a second CPU candidate set, where the second CPU candidate set is a CPU candidate set predefined in the load process.

[0073] In this embodiment, the second CPU candidate set refers to a predefined range of CPU cores allowed for scheduling in the workload process. This range is typically determined by the process's CPU affinity policy (e.g., the cpus_ptr mask) or manually configured by the system administrator (e.g., using the taskset command to bind cores). This set represents the range of cores that the process is allowed to run on and is the fundamental constraint for scheduling decisions. For example, if the cpus_ptr mask is 0x0F (binary 1111), the second candidate set is CPUs 0-3.

[0074] S304 : Determine a third CPU candidate set based on the first CPU candidate set and the second CPU candidate set; wherein the third CPU candidate set is the intersection of the first CPU candidate set and the second CPU candidate set.

[0075] In this embodiment, the first CPU candidate set is an optimization candidate set generated based on the cache slice mapping of the memory hotspot address (see preamble S204-S206), which includes cores that can efficiently access the hotspot cache slice. For example, if the hotspot address is hashed to Slice 2, and Slice 2 is directly connected to Core 8-11, the first candidate set is {8, 9, 10, 11}. The third CPU candidate set is obtained by performing an intersection operation (C = A ∩ B) on the first candidate set (A) and the second candidate set (B) to obtain a core set that meets both the cache optimization requirements and the process affinity constraints. For example, if A = {8, 9, 10, 11}, B = {0-3, 8-9}, then C = {8, 9}. This step ensures that the scheduling decision does not violate the core binding restrictions of the process (such as NUMA policy, resource isolation requirements).

[0076] S306: Determine, in the third CPU candidate set, a second memory address whose memory access frequency is greater than a second preset threshold.

[0077] On the CPU cores corresponding to the third candidate set (C), finer-grained memory access records are obtained through secondary sampling (such as reusing PEBS or enabling L2 cache miss event monitoring), filtering out addresses with access frequencies exceeding a second preset threshold. The second preset threshold is typically higher than the first threshold and is used to identify hotspots with strong locality and high cache dependency. For example: the first preset threshold is 10^6 times / second (global hotspot screening); the second preset threshold is 5×10^6 times / second (core-level hotspot precise location).

[0078] For example, the popularity weight calculation is to perform weighted statistics on the popularity of each address, and the weight factors include:

[0079] Temporal locality: access density within a short time window (such as the peak within the last 10ms); spatial locality: address continuity (such as the proportion of accesses within consecutive pages); cross-core contention: the access frequency of this address in other cores (monitored by the CMT counter).

[0080] S308: Determine the CPU corresponding to the cache slice to which the second memory address belongs as the target CPU of the load process.

[0081] In this embodiment, the high-frequency address (second memory address) obtained in S306 is again mapped to the cache slice to which it belongs through the hardware hash algorithm, and the CPU core directly connected to the slice is selected according to the core-slice mapping table.

[0082] In this embodiment, memory address hotspots during load execution are considered, and the CPU scheduling range of the migrated load is dynamically adjusted based on the hotspot information to further optimize load performance and reduce the performance impact of cross-CPU cache slice access.

[0083] In some embodiments, in order to achieve dynamic intervention in the load scheduling range, the disclosed embodiment first adds a CPU scheduling range adjustment field (CPU scheduling range adjustment field) to the task_struct structure allocated by the kernel to each process. This field is initialized to the mask value represented by the CPU mask pointer field (cpus_ptr). Considering that the existing CPU load balancing policy will migrate according to the scheduling range represented by the CPU mask pointer field by default, in order to achieve dynamic intervention in the load scheduling range, the CPU mask pointer field will be directly modified dynamically by this embodiment to intervene in the CPU scheduling range of the load, and the CPU scheduling range adjustment field will save the latest range adjusted by the user. Therefore, Figure 4 A flow chart of another CPU scheduling method according to an embodiment of the present disclosure is shown. Figure 4 As shown, the CPU scheduling method provided by the embodiment of the present disclosure may include the following steps:

[0084] S402 , storing the CPU adjustment range of the load process in the CPU scheduling range adjustment field, where the CPU adjustment range includes the target CPU of the load process. The CPU scheduling range adjustment field is pre-added in the load process.

[0085] In some embodiments, an extended Berkeley packet filter is used to obtain a first CPU function and a second CPU function in a load process, wherein the first CPU function is a function for setting the CPU of the load process, and the second CPU function is a function for obtaining the CPU affinity of the load process; the first CPU function and the second CPU function are parsed to obtain the CPU adjustment range of the load process, and the CPU adjustment range of the load process is saved to the CPU scheduling range adjustment field.

[0086] In this embodiment, the Extended Berkeley Packet Filter (eBPF) is a kernel bytecode execution technology that can dynamically load and run code while the kernel is running, and is used in scenarios such as performance monitoring and network filtering.

[0087] Specifically, eBPF technology is used to hijack the sched_setaffinity and sched_getaffinity functions to save the user-adjusted CPU scheduling range to the cpus_ptr_backup field. For example, sched_setaffinity corresponds to setting this field, and sched_getaffinity corresponds to reading this field, thereby ensuring the semantic consistency of the range adjustment API. Among them, sched_setaffinity and sched_getaffinity are functions used to set and obtain the CPU affinity of a process in the Linux system. The former specifies which CPUs the process runs on, and the latter queries the CPU affinity setting of the process. Hijacking these two functions using eBPF technology means taking advantage of the programmability of eBPF to intercept calls to these two functions at the kernel level. Custom logic can be inserted before and after the call, such as recording call information, modifying parameters or return values, to achieve monitoring and customized control of the process CPU affinity operation without modifying the kernel source code.

[0088] In this embodiment, an extended Berkeley Packet Filter (eBPF) hook is first set for the select_task_rq function of each scheduling class. This hook allows modification of the selected CPU upon the return of select_task_rq. This modification range relies on both the CPU scheduling range indicated by the cpus_ptr_backup field and the optimized scheduling range based on memory hotspot sampling technology, effectively and transparently providing a scheduling range optimization mechanism for last-level cache slice affinity for the CPU scheduling method.

[0089] In some embodiments, the load process includes a runnable CPU mask pointer field. Figure 5 A flow chart of a method for adding a load process to a process scheduling queue of a target CPU according to an embodiment of the present disclosure is shown. Figure 5 As shown, the method for adding a load process to the process scheduling queue of a target CPU provided by an embodiment of the present disclosure may include the following steps:

[0090] S502 : Update the executable CPU mask pointer field according to the target CPU of the load process stored in the CPU scheduling range adjustment field, so as to store the target CPU of the load process in the executable CPU mask pointer field.

[0091] In this embodiment, the maximum adjustment range of the executable CPU mask pointer field (cpus_ptr) is limited by the CPU scheduling range adjustment field (cpus_ptr_backup field), and the CPU scheduling range will be narrowed according to the memory hotspot information of the load. The specific narrowing process is adjusted by the target CPU determination method described above.

[0092] S504 , according to the target CPU of the loaded process stored in the executable CPU mask pointer field, add the loaded process to the process scheduling queue of the target CPU.

[0093] In this embodiment, for the process number of the controlled load, the eBPF program can transparently set the CPU scheduling range according to the above logic, avoiding information inconsistency on the user side, and the actual scheduling range can still meet the user side's requirements for the CPU scheduling range.

[0094] Figure 6 A specific flow chart of a CPU scheduling method according to an embodiment of the present disclosure is shown as follows: Figure 6 As shown, the CPU scheduling method provided by the present disclosure includes:

[0095] S601, enabling a last-level cache slice-aware memory allocation strategy.

[0096] In this embodiment, the complex addressing hash algorithm of the cache slice is constructed and a cache slice-aware memory allocation strategy is enabled through the existing reverse engineering method. The reverse engineering method refers to constructing or optimizing new technologies or methods by analyzing and studying the working principles of existing systems or technologies. It is used here to construct and enable the above-mentioned cache slice-aware memory allocation strategy. Enabling last-level cache slice awareness, that is, considering the characteristics of LLC slices when allocating memory, makes data allocation more reasonable, reduces cache conflicts and failure rates, and improves system performance. This strategy optimizes data access patterns by intelligently allocating data to different cache slices, thereby fully utilizing cache resources.

[0097] S602: The eBPF program loads a list of controlled processes.

[0098] In this embodiment, the eBPF program can operate on processes, and here the process to be controlled is added to the list.

[0099] S603: Perform memory access address heat sampling on the controlled process.

[0100] That is, statistics the heat of its memory access address.

[0101] S604, calculating the CPU set corresponding to the cache slice of the memory hotspot address.

[0102] In this embodiment, based on the memory hotspot addresses, the CPU set corresponding to the cache slice is found, that is, it is determined which CPUs will process cache operations related to these hotspot addresses.

[0103] S605: Update the cpus_ptr field of the controlled process and adjust the target CPU during the process wake-up phase.

[0104] The target CPU is in the CPU set of S604.

[0105] S606, determine whether to close the control, if so, go to step S, if not, go to step S603.

[0106] S607: Restore the cpus_ptr of the controlled process according to the cpus_ptr_backup field.

[0107] Based on the same inventive concept, the present disclosure also provides a CPU scheduling device, as described in the following embodiments. Since the principle of solving the problem in the device embodiment is similar to that in the above method embodiment, the implementation of the device embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0108] Figure 7 A schematic diagram of a CPU scheduling device according to an embodiment of the present disclosure is shown. Figure 7As shown, the device includes: a sampling module 71, a first determination module 72, a second determination module 73 and a scheduling module 74; the sampling module 71 is used to sample the last-level cache failure event of the load process in response to the execution of the load process, and obtain the memory access hotspot address corresponding to the load process; wherein the last-level cache failure event is related to the memory access address, and the memory access hotspot address is the first memory address whose memory access frequency is greater than a first preset threshold; the first determination module 72 is used to determine the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process; the second determination module 73 is used to determine the target CPU of the load process in the first CPU candidate set; the scheduling module 74 is used to add the load process to the process scheduling queue of the target CPU.

[0109] In some embodiments, the sampling module 71 is specifically used to: sample the last-level cache failure event of the load process to obtain the memory access address recorded in the last-level cache failure event; use a hardware hash algorithm to slice and map the memory access address to obtain the hotspot cache slice of the load process; determine the memory access hotspot address corresponding to the load process based on the hotspot cache slice.

[0110] In some embodiments, before sampling the last-level cache failure event of the load process, the sampling module 71 is further used to: obtain attribute information of the load process, wherein the attribute information of the load process is used to indicate whether the load process is a load process that can be dynamically controlled by the CPU; the sampling of the last-level cache failure event of the load process includes: when the load process is a load process that can be dynamically controlled by the CPU, using precise event sampling technology to sample the last-level cache failure event of the load process that can be dynamically controlled by the CPU.

[0111] In some embodiments, the second determination module 73 is further used to: obtain a second CPU candidate set, which is a CPU candidate set pre-defined in the load process; determine a third CPU candidate set based on the first CPU candidate set and the second CPU candidate set; wherein the third CPU candidate set is the intersection of the first CPU candidate set and the second CPU candidate set; determine a second memory address in the third CPU candidate set whose memory access frequency is greater than a second preset threshold; and determine the CPU corresponding to the cache slice to which the second memory address belongs as the target CPU of the load process.

[0112] In some embodiments, the scheduling module 74 is further used to: save the CPU adjustment range of the load process in the CPU scheduling range adjustment field, the CPU adjustment range includes the target CPU of the load process, and the CPU scheduling range adjustment field is pre-added in the load process.

[0113] In some embodiments, the load process includes an executable CPU mask pointer field, and the scheduling module 74 is used to: update the executable CPU mask pointer field according to the target CPU of the load process saved in the CPU scheduling range adjustment field to save the target CPU of the load process to the executable CPU mask pointer field; and add the load process to the process scheduling queue of the target CPU according to the target CPU of the load process saved in the executable CPU mask pointer field.

[0114] In some embodiments, the scheduling module 74 is also used to: use the extended Berkeley packet filter to obtain the first CPU function and the second CPU function in the load process, wherein the first CPU function is a function for setting the CPU of the load process, and the second CPU function is a function for obtaining the CPU affinity of the load process; parse the first CPU function and the second CPU function to obtain the CPU adjustment range of the load process, and save the CPU adjustment range of the load process to the CPU scheduling range adjustment field.

[0115] It should be noted that the examples and application scenarios implemented by the modules in the above-mentioned apparatus embodiment are the same as those implemented by the corresponding steps in the method embodiment, but are not limited to the contents disclosed in the above-mentioned method embodiment. It should be noted that the above-mentioned modules, as part of the apparatus, can be executed in a computer system, such as a set of computer-executable instructions.

[0116] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation that combines hardware and software aspects, which may be collectively referred to herein as a "circuit," "module," or "system."

[0117] Based on the same inventive concept, an embodiment of the present disclosure further provides an electronic device, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute any of the above-mentioned CPU scheduling methods by executing the executable instructions. Since the principles for solving the problem in this electronic device embodiment are similar to those in the above-mentioned method embodiment, the implementation of this electronic device embodiment can refer to the implementation of the above-mentioned method embodiment, and the repeated parts will not be repeated here.

[0118] Refer to the following Figure 8 800 according to this embodiment of the present disclosure will be described. Figure 8 The electronic device 800 shown is merely an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0119] like Figure 8 As shown, electronic device 800 is implemented as a general-purpose computing device. Components of electronic device 800 may include, but are not limited to, the aforementioned at least one processing unit 810, the aforementioned at least one storage unit 820, and a bus 830 connecting various system components (including storage unit 820 and processing unit 810).

[0120] Wherein, the storage unit stores a program code, and the program code can be executed by the processing unit 810, so that the processing unit 810 performs the steps described in the above "Exemplary Method" section of this specification according to various exemplary embodiments of the present disclosure. For example, the processing unit 810 can perform the following steps of the above method embodiment: in response to executing the load process, sampling the last-level cache failure event of the load process to obtain the memory access hotspot address corresponding to the load process; wherein the last-level cache failure event is related to the memory access address, and the memory access hotspot address is the first memory address whose memory access frequency is greater than a first preset threshold; determining the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process; in the first CPU candidate set, determining the target CPU of the load process; and adding the load process to the process scheduling queue of the target CPU.

[0121] The storage unit 820 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 8201 and / or a cache memory unit 8202 , and may further include a read-only memory unit (ROM) 8203 .

[0122] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, such program modules 8205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0123] Bus 830 may represent one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0124] The electronic device 800 can also communicate with one or more external devices 840 (e.g., a keyboard, a pointing device, a Bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 800, and / or any device that enables the electronic device 800 to communicate with one or more other computing devices (e.g., a router, a modem, etc.). Such communication can occur via an input / output (I / O) interface 850. Furthermore, the electronic device 800 can also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter 860. As shown, the network adapter 860 communicates with other modules of the electronic device 800 via a bus 830. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 800, including but not limited to microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0125] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0126] Based on the same inventive concept, embodiments of the present disclosure further provide a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program implements any of the aforementioned CPU scheduling methods. Because the principles underlying the problems solved by this computer-readable storage medium embodiment are similar to those of the aforementioned method embodiment, the implementation of this computer-readable storage medium embodiment can be referenced to the implementation of the aforementioned method embodiment, and any repetitions will not be repeated.

[0127] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fibers, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0128] In the present disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0129] Alternatively, the program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0130] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a standalone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0131] Based on the same inventive concept, embodiments of the present disclosure further provide a computer program product, including a computer program or instructions, which, when executed by a processor, implements the CPU scheduling method of any one of the above-mentioned method embodiments. Since the principles for solving the problems in this computer program product embodiment are similar to those in the above-mentioned method embodiment, the implementation of this computer program product embodiment can refer to the implementation of the above-mentioned method embodiment, and the repeated parts will not be repeated here.

[0132] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0133] Furthermore, although the steps of the method of the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0134] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0135] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A CPU scheduling method, characterized in that: The method comprises: In response to executing a load process, sampling a last-level cache miss event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-level cache miss event is related to the memory access address, and the memory access hotspot address is a first memory address whose memory access frequency is greater than a first preset threshold; Determine the CPU corresponding to the memory access hotspot address as the first CPU candidate set of the load process; Determining a target CPU for the load process in the first CPU candidate set; The load process is added to the process scheduling queue of the target CPU.

2. The CPU scheduling method according to claim 1, wherein: The sampling of the last-level cache invalidation event of the process to obtain the memory access hotspot address corresponding to the load process includes: Sampling the last-level cache failure event of the load process to obtain the memory access address recorded in the last-level cache failure event; Using a hardware hash algorithm to perform shard mapping on the memory access address to obtain a hotspot cache shard of the load process; Determine a memory access hotspot address corresponding to the load process according to the hotspot cache slice.

3. The CPU scheduling method according to claim 1 or 2, characterized in that: Before sampling the last-level cache invalidation event of the load process, the method further includes: Acquiring attribute information of the load process, wherein the attribute information of the load process is used to indicate whether the load process is a load process that can be dynamically controlled by the CPU; The sampling of the last-level cache invalidation event of the load process includes: When the load process is a load process that can be dynamically controlled by the CPU, the last-level cache miss event of the load process that can be dynamically controlled by the CPU is sampled using a precise event sampling technology.

4. The CPU scheduling method according to claim 1, wherein: The method further comprises: Acquire a second CPU candidate set, where the second CPU candidate set is a CPU candidate set predefined in the load process; Determine a third CPU candidate set based on the first CPU candidate set and the second CPU candidate set; wherein the third CPU candidate set is the intersection of the first CPU candidate set and the second CPU candidate set; Determine, in the third CPU candidate set, a second memory address having a memory access frequency greater than a second preset threshold; The CPU corresponding to the cache slice to which the second memory address belongs is determined as the target CPU of the load process.

5. The CPU scheduling method according to claim 1, wherein: The method further comprises: The CPU scheduling range adjustment field stores the CPU adjustment range of the load process, where the CPU adjustment range includes the target CPU of the load process. The CPU scheduling range adjustment field is pre-added in the load process.

6. The CPU scheduling method according to claim 5, wherein: The load process includes an executable CPU mask pointer field, and the step of adding the load process to the process scheduling queue of the target CPU includes: updating the executable CPU mask pointer field according to the target CPU of the load process stored in the CPU scheduling range adjustment field, so as to store the target CPU of the load process in the executable CPU mask pointer field; According to the target CPU of the load process stored in the executable CPU mask pointer field, the load process is added to the process scheduling queue of the target CPU.

7. The CPU scheduling method according to claim 5, wherein: The CPU adjustment range of the load process is stored in the CPU scheduling range adjustment field, including: Using an extended Berkeley packet filter, obtaining a first CPU function and a second CPU function in the load process, wherein the first CPU function is a function for setting a CPU of the load process, and the second CPU function is a function for obtaining CPU affinity of the load process; The first CPU function and the second CPU function are parsed to obtain a CPU adjustment range of the load process, and the CPU adjustment range of the load process is saved in the CPU scheduling range adjustment field.

8. A CPU scheduling device, characterized in that: The device comprises: a sampling module configured to sample, in response to executing a load process, a last-level cache miss event of the load process to obtain a memory access hotspot address corresponding to the load process; wherein the last-level cache miss event is related to a memory access address, and the memory access hotspot address is a first memory address whose memory access frequency is greater than a first preset threshold; A first determining module is configured to determine the CPU corresponding to the memory access hotspot address as a first CPU candidate set for the load process; A second determining module is configured to determine a target CPU for the load process from the first CPU candidate set; The scheduling module is used to add the load process to the process scheduling queue of the target CPU.

9. An electronic device, characterized in that: include: processor; as well as a memory for storing executable instructions of the processor; The processor is configured to execute the CPU scheduling method according to any one of claims 1 to 7 by executing the executable instructions.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the CPU scheduling method according to any one of claims 1 to 7 is implemented.

11. A computer program product comprising: A computer program or instruction, characterized in that when the computer program or instruction is executed by a processor, it implements the CPU scheduling method according to any one of claims 1 to 7.

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