Intelligent semiconductor chip and thermal management method thereof

Abstract

The invention provides an intelligent semiconductor chip and a thermal management method thereof, and the method comprises the steps: extracting the gradient features of the interlayer temperature of each semiconductor chip from the temperature information of each barrier layer of a three-dimensional stacked chip in a high-power-consumption module under a current working condition; constructing a temperature coupling field of the high-power-consumption module in the current working condition through each gradient feature and the heat dissipation feature of the packaging layer; a plurality of heat flux concentration areas of the high-power-consumption module in the current working condition are positioned based on the temperature coupling field and the specified sampling frequency, and thermal runaway risk points in the high-power-consumption module are screened out from all the heat flux concentration areas through peak characteristics in junction temperature information of all the heat flux concentration areas; and determining the vector distribution characteristics of the heat flux density in each thermal runaway risk point, and performing layered heat dissipation on the three-dimensional stacked chip in the high-power-consumption module through the vector distribution characteristics of the heat flux density in each thermal runaway risk point. Based on the scheme, thermal field reconstruction of dynamic thermal management in the three-dimensional stacked chip can be realized.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip technology, and more specifically, to an intelligent semiconductor chip and a thermal management method thereof. Background Art

[0002] With the rapid development of emerging technologies such as artificial intelligence, 5G communications, the Internet of Things, and big data, unprecedented high requirements have been placed on the performance, power consumption, and integration of semiconductor chips. The global digital transformation is accelerating, from smart cars to smart homes, from industrial automation to medical health. As the core component of the digital engine, the demand for semiconductor chips continues to rise.

[0003] Traditional single-point temperature management has significant limitations in the thermal management of three-dimensional stacked chips and cannot effectively capture the vertical thermal coupling effect. In three-dimensional integrated circuits, heat will be rapidly conducted in the vertical direction through silicon vias, bonding interfaces and interlayer dielectrics, forming a complex interlayer thermal coupling network. Existing single-point temperature measurement schemes only arrange discrete sensors on the chip surface or local positions, and cannot obtain the temperature gradient distribution between adjacent chip layers, resulting in errors in the calculation of vertical thermal resistance. At the same time, it is difficult to identify the axial heat leakage path through the vertical interconnection structure, and cannot reflect the directional characteristics of heat flow during interlayer conduction. When power fluctuations exist between different functional layers, single-point data cannot distinguish between the superposition effect of local heating and vertical conduction, which can easily cause thermal assessment deviations. Therefore, how to achieve thermal field reconstruction for dynamic thermal management in three-dimensional stacked chips and thereby improve the chip heat dissipation efficiency of semiconductor chips has become a difficult problem faced by the industry. Summary of the Invention

[0004] The present application provides an intelligent semiconductor chip and a thermal management method thereof, which can realize thermal field reconstruction of dynamic thermal management in three-dimensional stacked chips.

[0005] In a first aspect, the present application provides a thermal management method for an intelligent semiconductor chip, comprising: Embed vertically aligned temperature sensors in key layers of three-dimensionally stacked chips in high-power modules, and use each temperature sensor to collect temperature information of the high-power module's packaging layer and the barrier layer of each semiconductor chip at a specified sampling frequency; Extracting the gradient characteristics of the interlayer temperature in each semiconductor chip from the temperature information of each barrier layer, and then constructing a temperature coupling field of the high-power module in the current operating condition based on the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer, and locating multiple heat flux concentration areas of the high-power module in the current operating condition based on the temperature coupling field and the specified sampling frequency; Collect junction temperature information from each heat flux concentration area and use the peak characteristics in each junction temperature information to screen out thermal runaway risk points in high-power modules from all heat flux concentration areas. The vector distribution characteristics of the heat flux density in each thermal runaway risk point are determined, and then the three-dimensional stacked chips in the high-power consumption module are cooled in layers based on the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

[0006] In some embodiments, extracting the gradient characteristics of the interlayer temperature in each semiconductor chip from the temperature information of each barrier layer specifically includes: For each semiconductor chip, obtaining an interlayer temperature between the semiconductor chip and an adjacent semiconductor chip from the barrier layer temperature information of the semiconductor chip; obtaining a vertical distance between a semiconductor chip and an adjacent semiconductor chip; The gradient characteristics of the interlayer temperature in the semiconductor chip are determined according to the interlayer temperature and the vertical distance, and then the gradient characteristics of the interlayer temperature in each semiconductor chip are obtained.

[0007] In some embodiments, constructing a temperature coupling field of a high power consumption module in a current working condition by using the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer specifically includes: Extracting the heat dissipation characteristics of the high power consumption module in the current working condition from the packaging layer temperature information; determining a characteristic difference between a gradient characteristic of an interlayer temperature in each semiconductor chip and the heat dissipation characteristic; Based on all the characteristic differences, a three-dimensional heat conduction equation for the high-power module in the current working condition is established; The three-dimensional heat conduction equation is discretely solved to output the temperature coupling field of the high power consumption module in the current working condition.

[0008] In some embodiments, locating multiple heat flux concentration areas of the high power consumption module in the current working condition based on the temperature coupling field and the specified sampling frequency specifically includes: Divide high power consumption modules into multiple heat flux areas; Determining the heat flux of each heat flux area of ​​the high power consumption module in the current working condition through the temperature coupling field; Setting a concentration threshold of the high power consumption module in the current working condition based on the specified sampling frequency and the material properties of the semiconductor chips in the three-dimensional stacked chip; The concentration threshold and all heat fluxes are used to screen out multiple heat flux concentration areas in the current working condition from the high power consumption modules.

[0009] In some embodiments, screening out thermal runaway risk points in high power consumption modules from all heat flux concentration areas based on peak characteristics in each junction temperature information specifically includes: Use sliding window algorithm to extract peak features in each junction temperature information; Based on the peak characteristics, all heat flux concentration areas are screened for runaway risks to obtain thermal runaway risk points in high-power consumption modules.

[0010] In some embodiments, performing layered heat dissipation on three-dimensional stacked chips in a high-power consumption module by using vector distribution characteristics of heat flux density at each thermal runaway risk point specifically includes: For each thermal runaway risk point, if the vector distribution characteristics of the heat flux density at the thermal runaway risk point are vertically dominant hot spots, the phase change material in the through-silicon vias in the three-dimensional stacked chip is activated to dissipate heat; If the vector distribution characteristics of the heat flux density in the thermal runaway risk point are horizontally dominant hot spots, the coolant flow rate in the microchannel is adjusted to dissipate heat, thereby completing the layered heat dissipation of each thermal runaway risk point.

[0011] In some embodiments, the temperature sensor is a gallium nitride-based micro-electromechanical system thermocouple, which is embedded under the chip active layer through a through-silicon via process.

[0012] In a second aspect, the present application provides an intelligent semiconductor chip, which includes a thermal management unit, wherein the thermal management unit includes: An acquisition module is used to embed vertically aligned temperature sensors in key layers of three-dimensionally stacked chips in a high-power module, and then use each temperature sensor to collect temperature information of the packaging layer of the high-power module and the barrier layer temperature information of each semiconductor chip according to a specified sampling frequency; a processing module configured to extract, from the temperature information of each barrier layer, the gradient characteristics of the interlayer temperature in each semiconductor chip, and then construct a temperature coupling field of the high-power module in the current operating condition based on the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer, and locate multiple heat flux concentration areas of the high-power module in the current operating condition based on the temperature coupling field and the specified sampling frequency; The processing module is further configured to collect junction temperature information of each heat flux concentration area, and screen out thermal runaway risk points in high power consumption modules from all heat flux concentration areas based on peak characteristics in each junction temperature information; The execution module is used to determine the vector distribution characteristics of the heat flux density in each thermal runaway risk point, and then perform layered heat dissipation on the three-dimensional stacked chips in the high-power consumption module through the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

[0013] In a third aspect, the present application provides a computer device, comprising a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the computer device implements the above-mentioned thermal management method of the intelligent semiconductor chip when executing.

[0014] In a fourth aspect, the present application provides a computer-readable storage medium, in which instructions or codes are stored. When the instructions or codes are run on a computer, the computer implements the above-mentioned thermal management method for the intelligent semiconductor chip when executing the computer.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: In an intelligent semiconductor chip and its thermal management method provided by the present application, vertically aligned temperature sensors are embedded in the key layers of the three-dimensional stacked chips in the high-power consumption module, and then each temperature sensor is used to collect the packaging layer temperature information of the high-power consumption module and the barrier layer temperature information of each semiconductor chip according to a specified sampling frequency; the gradient characteristics of the interlayer temperature in each semiconductor chip are extracted from the temperature information of each barrier layer, and then the temperature coupling field of the high-power consumption module in the current working condition is constructed through the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the packaging layer temperature information, and multiple heat flux concentration areas of the high-power consumption module in the current working condition are located based on the temperature coupling field and the specified sampling frequency; the junction temperature information of each heat flux concentration area is collected, and the thermal runaway risk points in the high-power consumption module are screened out from all the heat flux concentration areas through the peak characteristics in each junction temperature information; the vector distribution characteristics of the heat flux density in each thermal runaway risk point are determined, and then the three-dimensional stacked chips in the high-power consumption module are subjected to layered heat dissipation through the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

[0016] It can be seen that in this application, the three-dimensional stacked chips in the high-power consumption module are heat-dissipated in layers through the vector distribution characteristics of the heat flux density in each thermal runaway risk point; first, the temperature coupling field is determined to obtain a three-dimensional perception of the thermal behavior of the three-dimensional stacked chips, thereby establishing a dynamic thermal field map covering the entire chip system. The temperature coupling field can intuitively present the conduction path and accumulation law of heat in the vertical stacking structure, providing panoramic data support for thermal management decisions. By integrating the interactive characteristics of interlayer heat conduction and package heat dissipation, the high-power consumption module can obtain an overall thermal field that goes beyond traditional point temperature measurement, accurately identify potential thermal coupling risk areas, and thus significantly improve the chip heat dissipation efficiency of the semiconductor chip; then, determine the vector distribution characteristics The essential laws of heat flow transfer can be obtained, thereby forming a targeted heat dissipation control strategy. The vector distribution characteristics can clearly distinguish the dominant direction and intensity differences of heat transfer, revealing the energy transport characteristics of thermal runaway risk points. Based on the dynamic analysis of the vector field, the vector distribution characteristics can intelligently match the optimal heat dissipation method, realizing a qualitative change from passive response to active prevention, and significantly improving the accuracy and predictability of thermal management. The control logic based on the physical essence enables the optimal allocation of heat dissipation resources, avoiding the energy waste caused by traditional uniform heat dissipation, and further improving the chip heat dissipation efficiency of semiconductor chips. In summary, based on the above scheme, the thermal field reconstruction of dynamic thermal management in three-dimensional stacked chips can be realized, thereby improving the chip heat dissipation efficiency of semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 is an exemplary flow chart of a thermal management method for a smart semiconductor chip according to some embodiments of the present application; Figure 2 is a schematic diagram of a process of a stacked structure diagram of a semiconductor chip according to some embodiments of the present application; Figure 3 is a schematic diagram of a process for achieving layered heat dissipation according to some embodiments of the present application; Figure 4 is a schematic structural diagram of a thermal management unit according to some embodiments of the present application; Figure 5 It is a structural diagram of a computer device for implementing a thermal management method for an intelligent semiconductor chip according to some embodiments of the present application. DETAILED DESCRIPTION

[0019] In order to better understand the technical solution of the present application, the technical solution of the present application will be described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] refer to Figure 1 , which is an exemplary flow chart of a thermal management method for an intelligent semiconductor chip according to some embodiments of the present application. The thermal management method for an intelligent semiconductor chip mainly includes the following steps: In step 101, vertically aligned temperature sensors are embedded in key layers of three-dimensionally stacked chips in a high-power module, and then each temperature sensor is used to collect the packaging layer temperature information of the high-power module and the barrier layer temperature information of each semiconductor chip at a specified sampling frequency.

[0021] It should be noted that in this application, the barrier layer temperature information is the temperature that characterizes the thermal resistance distribution characteristics on the heat dissipation path; the packaging layer temperature information is the temperature that reflects the equilibrium state between heat generation and conduction inside the chip; the vertically aligned temperature sensor refers to an array of sensor units strictly arranged along the Z-axis direction in three-dimensional space to ensure that the measurement positions of each layer are spatially consistent. The temperature sensor is a gallium nitride-based micro-electromechanical system thermocouple, which is embedded under the active layer of the chip through a through-silicon via process; the specified sampling frequency is the data acquisition rate dynamically adjusted according to the thermal time constant of the chip, and must meet the Nyquist sampling theorem to avoid signal aliasing.

[0022] In specific implementation, in the thermal management of three-dimensional stacked chips in high-power modules, silicon through-via technology is used in the chip design stage to vertically integrate micro temperature sensors at the junction of the active area and the inactive area of ​​each key functional layer, and the sensors are processed and formed synchronously with the interconnection layer of the chip through semiconductor technology. When the high-power module is running, the high-power module synchronously triggers the temperature sensor arrays of each layer at millisecond intervals (typical value is 1-10ms), and obtains the packaging layer temperature through the distributed sensor grid mounted on the inner side of the heat dissipation cover, so that the collection of packaging layer temperatures is used as the packaging layer temperature information. For each semiconductor chip, the heat distribution at the interface between the dielectric layer and the silicon substrate is measured by an embedded sensor as the barrier layer temperature of the semiconductor chip, so that the collection of all barrier layer temperatures is used as the barrier layer temperature information of the semiconductor chip. The barrier layer temperature information of each semiconductor chip can be obtained in the above manner.

[0023] In some embodiments, reference Figure 2The figure is a schematic diagram of a process flow diagram of a semiconductor chip stacking structure according to some embodiments of the present application. The figure shows the stacking structure of a multi-layer semiconductor chip. As can be seen in the figure, the semiconductor chip is designed in a multi-layer stacked form, and the key layers have complex circuit layouts. The stacking architecture can significantly improve the integration and performance of the chip while reducing its occupied space. In modern electronic devices such as smartphones, computers and servers, this high-density chip stacking technology is widely used to meet the demand for higher performance and smaller size.

[0024] In step 102, the gradient characteristics of the interlayer temperature in each semiconductor chip are extracted from the temperature information of each barrier layer, and then the temperature coupling field of the high-power consumption module in the current working condition is constructed through the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer. Based on the temperature coupling field and the specified sampling frequency, multiple heat flux concentration areas of the high-power consumption module in the current working condition are located.

[0025] In some embodiments, extracting the gradient characteristics of the interlayer temperature in each semiconductor chip from the temperature information of each barrier layer can be achieved by using the following steps: For each semiconductor chip, obtaining an interlayer temperature between the semiconductor chip and an adjacent semiconductor chip from the barrier layer temperature information of the semiconductor chip; obtaining a vertical distance between a semiconductor chip and an adjacent semiconductor chip; The gradient characteristics of the interlayer temperature in the semiconductor chip are determined according to the interlayer temperature and the vertical distance, and then the gradient characteristics of the interlayer temperature in each semiconductor chip are obtained.

[0026] It should be noted that, in this application, the gradient feature represents the temperature change rate per unit distance between adjacent chip layers, and the gradient feature can quantify the conduction intensity of heat flow in the vertical direction; the interlayer temperature represents the temperature difference between the interfaces of the barrier layers of adjacent semiconductor chips, and the interlayer temperature can directly reflect the heat accumulation state at the chip stacking interface; the vertical distance represents the physical spacing between the active layers of adjacent chips.

[0027] In specific implementation, first, for each semiconductor chip, the interlayer temperature between the semiconductor chip and the adjacent semiconductor chip is obtained from the barrier layer temperature information of the semiconductor chip, which can be implemented in the following manner, namely: for each semiconductor chip, all temperature values ​​detected by the temperature sensor between the semiconductor chip and the adjacent semiconductor chip are obtained from the barrier layer temperature information of the semiconductor chip, and the difference between the maximum and minimum values ​​of all temperature values ​​is used as the interlayer temperature between the semiconductor chip and the adjacent semiconductor chip; then, the vertical distance between the semiconductor chip and the adjacent semiconductor chip is obtained, which can be implemented in the following manner, namely: the vertical distance between the semiconductor chip and the adjacent semiconductor chip is obtained from the layout description of the three-dimensional stacked chip; finally, the gradient characteristics of the interlayer temperature in the semiconductor chip are determined according to the interlayer temperature and the vertical distance, and then the gradient characteristics of the interlayer temperature in each semiconductor chip are obtained, which can be implemented in the following manner, namely: the ratio of the interlayer temperature to the vertical distance is used as the gradient characteristics of the interlayer temperature in the semiconductor chip, and the gradient characteristics of the interlayer temperature in each semiconductor chip can be obtained in the above manner.

[0028] In some embodiments, the following steps may be used to construct a temperature coupling field of a high power consumption module in a current working condition by using the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer: Extracting the heat dissipation characteristics of the high power consumption module in the current working condition from the packaging layer temperature information; determining a characteristic difference between a gradient characteristic of an interlayer temperature in each semiconductor chip and the heat dissipation characteristic; Based on all the characteristic differences, a three-dimensional heat conduction equation for the high-power module in the current working condition is established; The three-dimensional heat conduction equation is discretely solved to output the temperature coupling field of the high power consumption module in the current working condition.

[0029] It should be noted that in this application, the temperature coupling field is a composite physical field that integrates the spatial temperature distribution and the heat flow vector field; the heat dissipation characteristics refer to a comprehensive parameter set that reflects the heat dissipation capacity of the system; the characteristic difference indicates the degree of deviation between the theoretical heat dissipation capacity and the actual heat distribution; the three-dimensional heat conduction equation is a mathematical model that describes the law of heat transfer in three-dimensional space.

[0030] In specific implementation, first, the heat dissipation characteristics of the high-power module in the current working condition are extracted from the packaging layer temperature information, which can be achieved in the following way, namely: after using the moving average algorithm to eliminate the measurement noise, the packaging layer temperature information is used as a known condition to establish a mathematical model of heat transfer, and the inverse problem solving algorithm in the mathematical model is used to solve the equivalent thermal conductivity, heat sink contact thermal resistance and air convection heat transfer coefficient of the semiconductor chip in the high-power module, and the set of equivalent thermal conductivity, heat sink contact thermal resistance and air convection heat transfer coefficient is used as the heat dissipation characteristics of the high-power module in the current working condition; secondly, the characteristic difference between the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics is determined in the following way, namely: for each semiconductor chip, the difference between the gradient characteristics and the heat dissipation characteristics is quantified using a feature matching algorithm, that is, the cosine similarity between the gradient characteristics and the heat dissipation characteristics corresponding to the semiconductor chip can be used as the heat dissipation characteristics of the semiconductor chip. The characteristic difference between the gradient characteristics of the interlayer temperature and the heat dissipation characteristics can be obtained by the above method; then, the three-dimensional heat conduction equation of the high-power consumption module in the current working condition is established based on all the characteristic differences, which can be achieved in the following way: using the semiconductor chip material property parameters in the high-power consumption module to initialize the three-dimensional heat conduction partial differential equation, substituting the characteristic difference into the three-dimensional heat conduction partial differential equation as the boundary condition, and using the substituted three-dimensional heat conduction partial differential equation as the three-dimensional heat conduction equation of the high-power consumption module in the current working condition; finally, the three-dimensional heat conduction equation is discretely solved, and the temperature coupling field of the high-power consumption module in the current working condition is outputted in the following way: using the finite volume method to perform spatial discretization and time iterative solution on the three-dimensional heat conduction equation, and then outputting the temperature coupling field including the temperature field and heat flow field distribution after convergence judgment.

[0031] In some embodiments, locating multiple heat flux concentration areas of a high power consumption module in the current working condition based on the temperature coupling field and the specified sampling frequency can be achieved by using the following steps: Divide high power consumption modules into multiple heat flux areas; Determining the heat flux of each heat flux area of ​​the high power consumption module in the current working condition through the temperature coupling field; Setting a concentration threshold of the high power consumption module in the current working condition based on the specified sampling frequency and the material properties of the semiconductor chips in the three-dimensional stacked chip; The concentration threshold and all heat fluxes are used to screen out multiple heat flux concentration areas in the current working condition from the high power consumption modules.

[0032] It should be noted that, in this application, the heat flux concentration area is a local area in the high-power consumption module where the actual heat flux density exceeds the design allowable range; the heat flux area refers to the physical space with continuous heat flow characteristics in the high-power consumption module; the heat flux characterizes the amount of heat energy transferred through a unit area of ​​the semiconductor chip per unit time; the concentration threshold is the critical value for judging whether the heat flow in the high-power consumption module is abnormally accumulated.

[0033] In specific implementation, the high power consumption module is divided into multiple heat flux areas, which can be achieved in the following way: according to the physical layout and power consumption distribution diagram of the semiconductor chip in the high power consumption module, the high power consumption module is divided into multiple areas with similar thermal characteristics as heat flux areas based on the K-means clustering algorithm. The boundary of each heat flux area needs to be aligned with the functional partition of the chip, and multiple heat flux areas can be obtained; secondly, the heat flux of each heat flux area of ​​the high power consumption module in the current working condition is determined by the temperature coupling field, which can be achieved in the following way: for each heat flux area, the heat flux of the heat flux area per unit area is obtained from the spatial temperature distribution of the temperature coupling field, so that the average of all heat fluxes is used as the heat flux of the heat flux area of ​​the high power consumption module in the current working condition. The heat flux of each heat flux area of ​​the high power consumption module in the current working condition can be obtained; then, the concentration threshold of the high power consumption module in the current working condition is set based on the specified sampling frequency and the material properties of the semiconductor chip in the three-dimensional stacked chip, which can be achieved in the following way: comprehensively considering the thermal conductivity, specific heat capacity and the sampling frequency's ability to capture temperature changes of the semiconductor material, a dynamic programming algorithm is used to calculate a threshold adapted to the current working condition as the concentration threshold of the high power consumption module in the current working condition; finally, the concentration threshold and all heat fluxes are used to screen out multiple heat flux concentration areas in the current working condition from the high power consumption module, which can be achieved in the following way: the heat flux area in the high power consumption module with a heat flux greater than the concentration threshold is taken as the heat flux concentration area, and multiple heat flux concentration areas in the current working condition can be obtained.

[0034] In step 103, junction temperature information of each heat flux concentration area is collected, and thermal runaway risk points in high power consumption modules are screened out from all heat flux concentration areas based on peak characteristics in each junction temperature information.

[0035] In some embodiments, the collection of junction temperature information of each heat flux concentration area can be achieved in the following manner, namely: for each heat flux concentration area, three layers of key temperature data need to be obtained simultaneously: the junction temperature of the chip active area is measured by the PN junction forward voltage drop method, and the silicon substrate temperature is collected by the embedded thermocouple, so that the combination of the chip active area junction temperature and the silicon substrate temperature is used as the junction temperature information of the heat flux concentration area.

[0036] In some embodiments, screening out thermal runaway risk points in high-power consumption modules from all heat flux concentration areas based on peak characteristics in each junction temperature information can be achieved by the following steps: Use sliding window algorithm to extract peak features in each junction temperature information; Based on the peak characteristics, all heat flux concentration areas are screened for runaway risks to obtain thermal runaway risk points in high-power consumption modules.

[0037] In specific implementation, first, the sliding window algorithm is used to extract the peak features in each junction temperature information. This can be achieved in the following way, namely: for each junction temperature information, a dynamic sliding time window algorithm is used to process the junction temperature information, and the window width is adaptively adjusted according to the chip thermal time constant. For each heat flux concentration area, a dynamic sliding time window algorithm is used to monitor the local maximum of the absolute value of the temperature, the temperature rise rate per unit time, and the second-order derivative of the temperature fluctuation in real time from the junction temperature information. When the following conditions are met at the same time, it is determined to be a valid peak: the local maximum exceeds the material reliability threshold, the temperature rise rate continues to be positive, and the second-order derivative continues to increase. All valid peaks can be obtained in the above way, and the set of all valid peaks is used as the peak feature in the junction temperature information. The peak feature in each junction temperature information can be obtained in the above way; then, based on each peak The value characteristics are used to screen all heat flux concentration areas for out-of-control, and the thermal runaway risk points in the high-power consumption module can be obtained in the following way, namely: a multi-level evaluation model based on fuzzy logic is established. The first-level screening in the multi-level evaluation model excludes instantaneous pulse interference and requires that the duration of the peak characteristics is greater than the thermal diffusion time constant. The second-level screening in the multi-level evaluation model combines the chip material parameters and uses the Arrhenius equation to calculate the Arrhenius acceleration factor of each peak characteristic to evaluate the impact of the peak characteristic on the device life. The third-level screening in the multi-level evaluation model integrates the thermal coupling effects of adjacent areas, verifies the authenticity of the abnormal area through the heat flow continuity equation, and finally outputs the coordinates of the thermal runaway risk points that meet all risk conditions, so as to obtain the thermal runaway risk points in the high-power consumption module.

[0038] It should be noted that, in this application, the thermal runaway risk point refers to a local high-temperature area that may cause a chain reaction of thermal failures; the peak characteristic is a typical set of waveform parameters that characterizes the abnormal heating pattern; the multi-level evaluation model is a thermal runaway risk grading judgment system constructed based on fuzzy logic. The multi-level evaluation model realizes accurate risk identification through three-level progressive screening. The first level adopts the time domain filtering principle, and by setting the thermal diffusion time constant as the threshold, it filters out transient noise interference and retains the continuous real thermal abnormality signal; the second level introduces the material reliability physical model, and uses the Arrhenius equation to quantify the accelerating effect of the temperature peak on the aging rate of the device, and converts the thermal parameters into life prediction indicators; the third level is based on the law of conservation of energy, and verifies the energy balance relationship of the abnormal area by solving the heat flow continuity equation, and combines the thermal coupling data of adjacent areas to eliminate isolated false signals. The above multi-scale evaluation mechanism integrates the time domain characteristics, material constitutive relations and thermodynamic conservation laws to realize intelligent mapping from original temperature data to risk coordinates, significantly improving the early warning accuracy.

[0039] In step 104, the vector distribution characteristics of the heat flux density in each thermal runaway risk point are determined, and then the three-dimensional stacked chips in the high power consumption module are layeredly cooled based on the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

[0040] In some embodiments, determining the vector distribution characteristics of the heat flux density in each thermal runaway risk point can be achieved in the following manner, namely: for each identified thermal runaway risk point, a local refined heat flux analysis model is established, and three-dimensional temperature gradient data within a radius of 200 μm from the center of the risk point is collected through a high-density temperature sensor array. The least squares method is used to fit the continuous temperature field distribution. Based on this continuous temperature field distribution and the chip anisotropic thermal conductivity matrix, the heat flux density vector of each spatial node is calculated using Fourier's heat conduction law, and the heat flux density vector contains both magnitude and direction information.

[0041] In some embodiments, the three-dimensional stacked chips in the high power consumption module are layered and cooled by using the vector distribution characteristics of the heat flux density in each thermal runaway risk point. Figure 3 The figure is a schematic diagram of the process of implementing layered heat dissipation in some embodiments of the present application. In this embodiment, layered heat dissipation can be implemented by the following steps: In step 1041, for each thermal runaway risk point, if the vector distribution characteristic of the heat flux density in the thermal runaway risk point is a vertically dominant hotspot, the phase change material in the through silicon via in the three-dimensional stacked chip is activated to dissipate heat; In step 1042, if the vector distribution characteristic of the heat flux density in the thermal runaway risk point is a transversely dominant hot spot, the coolant flow rate in the microchannel is adjusted to dissipate heat, thereby completing layered heat dissipation at each thermal runaway risk point.

[0042] It should be noted that the phase-change material within the TSV is a passive heat dissipation element, requiring no additional active control circuitry for activation. When the vertical heat flux exceeds a threshold, the phase-change material reaches a phase transition point (e.g., the melting point of paraffin wax), dissipating heat through a solid-liquid phase transition by absorbing latent heat. This process relies on the physical properties of the material itself. For example, for vertically dominant hotspots, when vector analysis of the heat flux shows a vertical component exceeding 70%, heat conduction primarily occurs longitudinally through the TSV. At this point, the phase-change material within the TSV is activated, leveraging its ability to absorb significant amounts of latent heat during its solid-liquid phase transition to achieve rapid isothermal heat dissipation and effectively block heat diffusion to adjacent chip layers. For lateral-dominant hotspots, when the horizontal component of the heat flux exceeds 60%, heat diffusion primarily occurs within the chip plane. In this case, a micropump (e.g., a piezoelectric pump) can dynamically adjust the coolant flow rate within the microchannels, enhancing lateral heat diffusion efficiency through forced convection. This layered heat dissipation mechanism achieves efficient thermal management of three-dimensional stacked chips through physical property adaptation (vertical phase transition / lateral liquid cooling) and dynamic response (real-time heat flux feedback).

[0043] In addition, in another aspect of the present application, in some embodiments, the present application provides an intelligent semiconductor chip, the intelligent semiconductor chip includes a thermal management unit, reference Figure 4 , which is a schematic diagram of the structure of a thermal management unit according to some embodiments of the present application. The thermal management unit includes: an acquisition module 201, a processing module 202, and an execution module 203, which are described as follows: Acquisition module 201, in this application, is mainly used to embed vertically aligned temperature sensors in key layers of three-dimensionally stacked chips in a high-power module, and then use each temperature sensor to collect the temperature information of the packaging layer of the high-power module and the temperature information of the barrier layer of each semiconductor chip according to a specified sampling frequency; Processing module 202, in this application, is used to extract the gradient characteristics of the interlayer temperature in each semiconductor chip from the temperature information of each barrier layer, and then construct a temperature coupling field of the high-power module in the current operating condition based on the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer, and locate multiple heat flux concentration areas of the high-power module in the current operating condition based on the temperature coupling field and the specified sampling frequency; It should be noted that the processing module 202 is further configured to collect junction temperature information of each heat flux concentration area, and screen out thermal runaway risk points in high power consumption modules from all heat flux concentration areas based on peak characteristics in each junction temperature information; Execution module 203. In this application, execution module 203 is mainly used to determine the vector distribution characteristics of the heat flux density in each thermal runaway risk point, and then perform layered heat dissipation on the three-dimensional stacked chips in the high-power consumption module through the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

[0044] The above describes in detail the examples of the intelligent semiconductor chip and its thermal management method provided by the embodiments of the present application. It can be understood that the corresponding device includes a hardware structure and / or software module corresponding to the execution of each function in order to realize the above functions. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0045] In some embodiments, the present application also provides a computer device, which includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the computer device executes the above-mentioned thermal management method of the intelligent semiconductor chip.

[0046] In some embodiments, reference Figure 5 The dotted line in the figure indicates that the unit or module is optional. The figure is a structural diagram of a computer device for implementing a thermal management method for an intelligent semiconductor chip according to an embodiment of the present application. The thermal management method for an intelligent semiconductor chip described in the above embodiment can be achieved by Figure 5 The computer device shown in the figure is implemented, and the computer device includes at least one processor 301, a memory 302 and at least one communication unit 305. The computer device can be a terminal device, a server or a chip.

[0047] The processor 301 may be a general-purpose processor or a dedicated processor. For example, the processor 301 may be a central processing unit (CPU), which may be used to control the computer device, execute software programs, and process data from the software programs. The computer device may also include a communication unit 305 for inputting (receiving) and outputting (transmitting) signals.

[0048] For example, the computer device may be a chip, the communication unit 305 may be an input and / or output circuit of the chip, or the communication unit 305 may be a communication interface of the chip, and the chip may be a component of a terminal device, a network device, or other device.

[0049] For another example, the computer device may be a terminal device or a server, and the communication unit 305 may be a transceiver of the terminal device or the server, or the communication unit 305 may be a transceiver circuit of the terminal device or the server.

[0050] The computer device may include one or more memories 302, on which a program 304 is stored. The program 304 can be executed by the processor 301 to generate instructions 303, so that the processor 301 executes the method described in the above method embodiment according to the instructions 303. Optionally, data (such as a target audit model) can also be stored in the memory 302. Optionally, the processor 301 can also read data stored in the memory 302. The data can be stored at the same storage address as the program 304, or at a different storage address from the program 304.

[0051] The processor 301 and the memory 302 may be provided separately or integrated together, for example, integrated on a system on chip (SOC) of a terminal device.

[0052] It should be understood that each step of the above method embodiment can be completed by a hardware-based logic circuit or software-based instructions in the processor 301. The processor 301 can be a CPU, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, such as discrete gates, transistor logic devices, or discrete hardware components.

[0053] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0054] For example, in some embodiments, the present application also provides a computer-readable storage medium, in which instructions or codes are stored. When the instructions or codes are run on a computer, the computer implements the above-mentioned thermal management method of the intelligent semiconductor chip when executing.

[0055] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0056] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A thermal management method for an intelligent semiconductor chip, characterized in that: The steps include: Embed vertically aligned temperature sensors in key layers of three-dimensionally stacked chips in high-power modules, and use each temperature sensor to collect temperature information of the high-power module's packaging layer and the barrier layer of each semiconductor chip at a specified sampling frequency; Extracting the gradient characteristics of the interlayer temperature in each semiconductor chip from the temperature information of each barrier layer, and then constructing a temperature coupling field of the high-power module in the current operating condition based on the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer, and locating multiple heat flux concentration areas of the high-power module in the current operating condition based on the temperature coupling field and the specified sampling frequency; Collect junction temperature information from each heat flux concentration area and use the peak characteristics in each junction temperature information to screen out thermal runaway risk points in high-power modules from all heat flux concentration areas. The vector distribution characteristics of the heat flux density in each thermal runaway risk point are determined, and then the three-dimensional stacked chips in the high-power consumption module are cooled in layers based on the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

2. The method according to claim 1, wherein Extracting the gradient characteristics of the interlayer temperature in each semiconductor chip from the temperature information of each barrier layer specifically includes: For each semiconductor chip, obtaining an interlayer temperature between the semiconductor chip and an adjacent semiconductor chip from the barrier layer temperature information of the semiconductor chip; obtaining a vertical distance between a semiconductor chip and an adjacent semiconductor chip; The gradient characteristics of the interlayer temperature in the semiconductor chip are determined according to the interlayer temperature and the vertical distance, and then the gradient characteristics of the interlayer temperature in each semiconductor chip are obtained.

3. The method according to claim 1, wherein Constructing the temperature coupling field of the high power consumption module in the current working condition by using the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer specifically includes: Extracting the heat dissipation characteristics of the high power consumption module in the current working condition from the packaging layer temperature information; determining a characteristic difference between a gradient characteristic of an interlayer temperature in each semiconductor chip and the heat dissipation characteristic; Based on all the characteristic differences, a three-dimensional heat conduction equation for the high-power module in the current working condition is established; The three-dimensional heat conduction equation is discretely solved to output the temperature coupling field of the high power consumption module in the current working condition.

4. The method according to claim 1, wherein Locating multiple heat flux concentration areas of the high power consumption module in the current working condition based on the temperature coupling field and the specified sampling frequency specifically includes: Divide high power consumption modules into multiple heat flux areas; Determining the heat flux of each heat flux area of ​​the high power consumption module in the current working condition through the temperature coupling field; Setting a concentration threshold of the high power consumption module in the current working condition based on the specified sampling frequency and the material properties of the semiconductor chips in the three-dimensional stacked chip; The concentration threshold and all heat fluxes are used to screen out multiple heat flux concentration areas in the current working condition from the high power consumption modules.

5. The method according to claim 1, wherein The peak characteristics of each junction temperature information are used to screen out thermal runaway risk points in high-power modules from all heat flux concentration areas, including: Use sliding window algorithm to extract peak features in each junction temperature information; Based on the peak characteristics, all heat flux concentration areas are screened for runaway risks to obtain thermal runaway risk points in high-power consumption modules.

6. The method according to claim 1, wherein The following are the specific methods used to perform layered heat dissipation for three-dimensional stacked chips in high-power modules by using the vector distribution characteristics of heat flux density at each thermal runaway risk point: For each thermal runaway risk point, if the vector distribution characteristics of the heat flux density at the thermal runaway risk point are vertically dominant hot spots, the phase change material in the through-silicon vias in the three-dimensional stacked chip is activated to dissipate heat; If the vector distribution characteristics of the heat flux density in the thermal runaway risk point are horizontally dominant hot spots, the coolant flow rate in the microchannel is adjusted to dissipate heat, thereby completing the layered heat dissipation of each thermal runaway risk point.

7. The method according to claim 1, wherein The temperature sensor is a gallium nitride-based micro-electromechanical system thermocouple, which is embedded under the chip active layer through a through-silicon via process.

8. An intelligent semiconductor chip, comprising a thermal management unit, characterized in that: The thermal management unit comprises: An acquisition module is used to embed vertically aligned temperature sensors in key layers of three-dimensionally stacked chips in a high-power module, and then use each temperature sensor to collect temperature information of the packaging layer of the high-power module and the barrier layer temperature information of each semiconductor chip according to a specified sampling frequency; a processing module configured to extract, from the temperature information of each barrier layer, the gradient characteristics of the interlayer temperature in each semiconductor chip, and then construct a temperature coupling field of the high-power module in the current operating condition based on the gradient characteristics of the interlayer temperature in each semiconductor chip and the heat dissipation characteristics in the temperature information of the packaging layer, and locate multiple heat flux concentration areas of the high-power module in the current operating condition based on the temperature coupling field and the specified sampling frequency; The processing module is further configured to collect junction temperature information of each heat flux concentration area, and screen out thermal runaway risk points in high power consumption modules from all heat flux concentration areas based on peak characteristics in each junction temperature information; The execution module is used to determine the vector distribution characteristics of the heat flux density in each thermal runaway risk point, and then perform layered heat dissipation on the three-dimensional stacked chips in the high-power consumption module through the vector distribution characteristics of the heat flux density in each thermal runaway risk point.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the computer device executes the thermal management method for the intelligent semiconductor chip according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores instructions or codes, and when the instructions or codes are executed on a computer, the computer implements the thermal management method for an intelligent semiconductor chip according to any one of claims 1 to 7.

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