High-speed serial communication system protocol adaptation layer circuit oriented to interconnection between core particles and working method

Abstract

According to the high-speed serial communication system protocol adaptation layer circuit oriented to interconnection between the core particles and the working method, the circuit serves as a bridging layer between an AXI-S bus and a SerDes physical coding sub-layer, and the problems of reliability and flow control in high-speed data transmission between the core particles are solved. The circuit adopts a modular design idea and comprises a transmitter and a receiver. In the aspect of data packet design, a first packet special processing mechanism is adopted, and an event serial number and target address information are only transmitted in a first packet, so that the bit utilization rate is improved. In the flow control design, a credit-based flow control mechanism is adopted, and the data transmission reliability is guaranteed through a special flow control packet. In addition, the system has a point-to-point retransmission function, data packets which fail in transmission are indexed and retransmitted, and successful data transmission is guaranteed within the configured retransmission times. According to the invention, an efficient and reliable protocol adaptation layer circuit solution is provided for high-speed interconnection requirements in core particle design.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a high-speed serial communication system protocol adaptation layer circuit and a working method for interconnection between chiplets. Background Art

[0002] As integrated circuit design evolves toward higher levels of integration and more complex functionality, chiplet-based design methodologies are gaining increasing attention. In chiplet design, multiple functional modules are divided into independent chiplets, with high-speed data exchange enabled through inter-chiplet interconnections. While this design approach improves chip yield and reduces costs, it also places higher demands on inter-chiplet communication.

[0003] In high-speed serial communication between chiplets, the protocol adaptation layer acts as a bridge between the AXI-S bus and SerDes, responsible for data packaging and unpacking, flow control, and transmission reliability assurance. However, existing adaptation layer solutions have many shortcomings: First, traditional communication protocols have high redundancy in data packaging and are not optimized for the short-distance transmission between chiplets. Second, common flow control mechanisms are mostly based on hardware handshake signals, while SerDes interfaces generally do not support this direct backpressure mechanism. Furthermore, the error detection and recovery mechanisms in existing solutions are often overly complex or inefficient, making them unsuitable for the low-latency requirements of high-speed communication between chiplets.

[0004] Therefore, the industry urgently needs a protocol adaptation layer design solution specifically for inter-chiplet interconnection. This solution should fully consider the characteristics of inter-chiplet interconnection application scenarios, implement an efficient data packaging and unpacking mechanism, provide a lightweight flow control mechanism, and ensure the reliability of data transmission in the event of possible errors, so as to meet the requirements of efficient and reliable data transmission in chiplet design. Summary of the Invention

[0005] The present application provides a high-speed serial communication system protocol adaptation layer circuit and working method for interconnection between chiplets, which can be used to solve the technical problem that efficient and reliable transmission of chiplet design is difficult to meet.

[0006] The present application provides a high-speed serial communication system protocol adaptation layer circuit for chip-to-chip interconnection, including a transmitter module and a receiver module, wherein the transmitter includes a packager, a buffer, a peer information management unit, a flow control unit, and an output controller; the receiver includes a receiving controller, a flow control unit, a buffer, and a depacketizer; the transmitter is responsible for packaging AXI-S bus data into data packets in a specific form and sending them to the physical coding sublayer of the SerDes; the receiver is responsible for receiving data from the SerDes physical coding sublayer and parsing it into AXI-S bus signals.

[0007] The packaging logic splices the TDATA, TID, TDEST, and TKEEP signals of the AXI-S bus into fixed-length data packets. The first channel in each data packet contains event ID and destination address information, and subsequent channels only contain data information.

[0008] The buffer includes data write selection, data alignment processing, elastic storage and data read control, and is used to store data packets to be sent and may need to be retransmitted, wherein the elastic buffer is configured with multiple independent storage units, each storage unit can cache a complete data packet.

[0009] The transmitter flow control unit is responsible for generating and sending flow control packets, wherein the flow control packet contains a type identifier, a sequence ID, packet size information, flow control information and a check code, and the flow control information represents the receiving status of each sequence ID data packet through fixed bit encoding.

[0010] The receiver parses and verifies the data packets received, stores the data packets that pass the verification in the buffer, and discards the data packets and records the corresponding status information when the verification fails or the buffer space is insufficient.

[0011] The depacketization logic parses the verified data packets in the buffer into AXI-S bus signals, including extracting information such as TDATA, TID, TDEST from the data packets and reconstructing the AXI-S bus data in sequence.

[0012] The receiver flow control unit is used to record the receiving status of the data packet at the local end, including three states: successful reception, unreceived and received error, and transmit this information to the other end through the flow control packet.

[0013] The present application also provides a working method for a high-speed serial communication system protocol adaptation layer circuit for chip-to-chip interconnection, including a data sending stage, a flow control stage, and a data receiving stage, wherein the data sending stage packages the AXI-S bus data into a data packet in a specific format and sends it to the physical coding sublayer of the SerDes, the flow control stage transmits data packet reception status information through a dedicated flow control packet and makes different responses according to different situations, and the data receiving stage receives the data packet and parses it into an AXI-S bus signal.

[0014] The data sending phase includes obtaining a sequence ID, data packaging, storing in a buffer, and sending a data packet. After sending a data packet, the data packet is kept in the buffer waiting for confirmation. If a confirmation of a reception error is received, the data packet is retransmitted.

[0015] A flow control packet is generated every preset time period, which contains the reception status of all sequence ID data packets at the local end, and uses fixed bit encoding to represent different data reception status.

[0016] The data receiving stage includes four steps: receiving a data packet, verifying the data packet, storing the data packet in a buffer, and unpacking the data packet. If the verification fails or the buffer space is insufficient, the data packet is discarded and the corresponding status information is recorded.

[0017] This application aims to solve how to implement an efficient data packet packaging and unpacking mechanism, how to achieve reliable flow control when SerDes does not support hardware back pressure, and how to ensure the reliability of data transmission.

[0018] In order to solve the above problems, the technical solution adopted by the present invention is as follows: a high-speed serial communication system protocol adaptation layer circuit and working method for interconnection between core particles are proposed. The protocol adaptation layer circuit includes two main parts: a transmitter and a receiver. The transmitter is responsible for receiving data from the AXI-S bus, packaging it into data packets in a specific format and sending it to the physical coding sublayer of the SerDes; the receiver is responsible for receiving data packets from the physical coding sublayer of the SerDes, verifying them and parsing them into AXI-S bus signals. In terms of flow control mechanism, a credit-based flow control mechanism is designed, which regularly transmits the reception status information of the data packets to both parties through dedicated flow control packets, thereby realizing reliable flow control in the SerDes environment. In terms of data reliability assurance, a point-to-point retransmission function is designed to track and retransmit data packets that have failed to be transmitted, and ensure successful data transmission within a limited number of retransmissions.

[0019] The present invention fully considers the application characteristics of the interconnection between core particles. The transmitter includes five main functional units: a packager, a buffer, a peer information management unit, a flow control information controller, and an output controller. The packager is responsible for packaging the AXI-S bus data into data packets of a specific format; the buffer is responsible for storing data packets to be sent and that may need to be retransmitted; the peer information management unit is responsible for processing the peer data reception status sent by the receiver and providing an idle sequence ID; the flow control information controller is responsible for generating and sending flow control packets; and the output controller is responsible for arbitrating the sending priority of the data load. The receiver module includes a receiving controller, a buffer, a depacketizer, and a flow control recording unit. The receiving controller is responsible for receiving and parsing data packets and performing verification; the buffer is responsible for storing data packets that have passed the verification; the depacketizer is responsible for parsing data packets into AXI-S bus signals; and the flow control recording unit is responsible for recording the receiving status of the data packets at this end.

[0020] In terms of data packet design, this invention employs a mechanism for special first-packet processing. For AXI-S bus signals such as TDATA, TID, TDEST, and TKEEP, the first channel of each packet contains complete sequence ID and destination address information, while subsequent channels contain only valid data information, improving channel bit utilization. Data packets contain fields such as type identification, sequence ID, size information, data payload, and checksum, ensuring the integrity and reliability of data transmission.

[0021] The present invention employs a credit-based flow control mechanism. By periodically sending flow control packets, the sender communicates the reception status of all sequence ID packets. The reception status of each sequence ID is represented by a two-bit code, including successful reception, unreceived, and errored. Based on the received flow control packet information, the sender decides to clear the buffer of confirmed packets or retransmit errored packets.

[0022] To ensure data reliability, this invention implements a point-to-point retransmission function. The transmitter's buffer manages retransmitted data on a packet-by-packet basis. Successfully transmitted packets are overwritten by new packets, while failed packets are retransmitted until the retransmission limit is exceeded or transmission succeeds. The receiver performs data validation upon receiving a packet. If validation fails or the buffer runs out of space, the packet is discarded and the corresponding status information is recorded.

[0023] The advantages of the present invention are mainly reflected in the following aspects: First, based on the application characteristics of chip-to-chip interconnection, an efficient data packaging mechanism is adopted, which includes complete information in the first packet and omits redundant information in subsequent packets, effectively improving bit utilization; second, a flow control mechanism suitable for the SerDes environment based on chip-to-chip interconnection is designed, which realizes reliable flow control without relying on hardware back pressure signals; finally, through point-to-point retransmission function and limited retransmission strategy, it avoids excessive occupation of system resources while ensuring data reliability. These features enable the present invention to provide a lightweight and highly reliable protocol adaptation layer circuit solution for chip-to-chip interconnection scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the overall structure diagram of the protocol adaptation layer circuit of the high-speed serial communication system for chiplet interconnection of the present invention;

[0025] Figure 2 This is a flowchart of the AXIS2SerDes workflow provided by an embodiment of the present application;

[0026] Figure 3 This is a diagram of the data packet format of the data type provided in the embodiment of the present application;

[0027] Figure 4 This is a structural format diagram of the flow control packet provided in an embodiment of the present application;

[0028] Figure 5 is a structural diagram of a transmitter module provided in an embodiment of the present application;

[0029] Figure 6 This is a structural diagram of the receiver module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0031] The following first introduces the embodiments of the present application with reference to the accompanying drawings.

[0032] The protocol adaptation layer circuit provided by the present invention adopts a modular architecture, such as Figure 1 As shown, it includes a transmitter and a receiver; the protocol adaptation layer circuit is used to implement the functional module of data transmission between core particles. One side of the protocol adaptation layer circuit is connected to the AXI-S data side, and the other side is connected to the physical coding sublayer in the SerDes circuit, realizing data transmission and reception of the AXI-S bus based on the SerDes circuit, and packaging each AXI-S signal into a specific form of data packet, and interacting with the SerDes circuit for data.

[0033] The transmitter is used to receive data from the AXI-S bus, package the data from the AXI-S bus into data packets in a preset format, and send them through the SerDes;

[0034] The transmitter generates and sends a flow control packet at a predetermined interval to report the reception status of the local data packet to the other end. When the receiver at the other end receives the flow control packet, the transmitter at the other end will use it to determine whether to retransmit or update the data packet in the buffer area.

[0035] The receiver is used to receive data packets from SerDes and parse the data packets from SerDes into AXI-S bus data; and send the data packet reception status of the other end in the flow control type data packet, that is, the data packet sending status of the local end to the local transmitter. The transmitter will determine whether to update the cache area or retransmit the data packets in the cache area based on the data packet sending status of the local end.

[0036] When interacting with other systems, the protocol adaptation layer circuit exchanges data with other systems via a standard AXI-S bus interface on one side and connects to the physical layer via a SerDes interface on the other. This circuit enables the system to maintain AXI-S bus compatibility while fully utilizing the high-speed transmission capabilities of SerDes technology, providing a reliable data channel for inter-chip communication.

[0037] The transmitter and receiver are described in detail below.

[0038] Transmitter:

[0039] The transmitter structure is as follows Figure 5As shown in the figure, it mainly implements two core functions: packaging AXI-S bus data into packets with a specific format and storing them in a buffer; and generating and sending flow control packets based on flow control information provided by the receiver. The transmitter module also intelligently manages the release or retransmission of packets in the buffer based on the flow control information received from the peer end, ensuring data transmission reliability.

[0040] The transmitter includes a packetizer, a buffer, a peer information management unit, a flow control unit, and an output controller. The packetizer is responsible for constructing data packets, obtaining idle sequence numbers from the peer information management unit, and then encapsulating and processing the AXI-S bus data according to a specific format, adding necessary header information and checksums. The buffer is responsible for storing data packets to be sent and retransmitted, and provides an efficient data management mechanism. The peer information management unit is responsible for sequence number resource allocation and status tracking to ensure the orderly processing of data packets. The flow control information controller generates flow control packets according to a preset period and transmits the local data reception status. The output controller implements priority arbitration of data payloads to ensure the timely delivery of flow control information.

[0041] The work of the packager includes two stages: control and execution. The control stage obtains resources and sets packaging parameters. The execution stage performs actual data packaging operations, splicing the TDATA, TID, TDEST, and TKEEP signals of the AXI-S bus into fixed-length data packets. The first channel in each data packet contains event ID and destination address information, and subsequent channels contain only data information. When the data packet reaches the preset size or no new data is input within the specified time, the current data packet will be automatically packaged and ready to process the next data packet.

[0042] The buffer specifically implements four functional components: data write control, data alignment, elastic storage, and data read control. Write control allocates storage space for data packets and manages write operations. Data alignment ensures that AXI-S bus data is stored according to the specified format. Elastic storage provides a reliable data buffer and releases resources based on transmission results. Read control retrieves data packets from the buffer for transmission and supports packet retransmission as needed, with retransmitted packets receiving priority. The buffer's write control workflow utilizes a state transition mechanism, consisting of three phases: idle waiting, data writing, and resource release. In the idle state, the buffer waits for new data packet processing requests. In the data writing state, it performs actual storage operations. If resources are insufficient, it enters the resource release waiting state. The read control workflow is also based on state transitions, consisting of four main phases: waiting for selection, header transmission, data transmission, and checksum transmission. The buffer determines the read order based on the retransmission flag and packet status, ensuring reliable and efficient data transmission.

[0043] The flow control unit periodically obtains data packet reception status information from the receiver, generates and sends standard flow control packets. If a flow control information transmission failure is detected, it will actively initiate a retransmission to ensure the stable operation of the flow control mechanism and give the flow control packet the highest priority.

[0044] Receiver:

[0045] The receiver module structure of the present invention is as follows Figure 6 As shown in the figure, the receiver receives and processes data from the SerDes circuit, while also recording and managing packet reception status. The receiver passes received flow control packets to the transmitter for processing, and performs packet verification and storage management. If a packet passes verification, it is parsed as an AXI-S bus signal. If verification fails or buffer space is insufficient, appropriate action is taken to ensure stable system operation.

[0046] The receiver module consists of a receive controller, flow control unit, buffer, and depacketizer. The receive controller is responsible for receiving data sequences from the SerDes physical coding sublayer and performing preliminary parsing and classification, differentiating the processing flow based on packet type. The flow control unit is responsible for recording and maintaining packet reception status information, providing necessary status data for the flow control mechanism. The buffer temporarily stores verified packet payloads and performs data retention or clearing operations based on the verification results. The depacketizer reconstructs the stored packet content into standard AXI-S bus signals.

[0047] The receiving controller employs a multi-stage processing mechanism, including key steps such as header recognition, data type determination, data reception, and verification. The receiving controller first identifies the packet header information, distinguishes flow control packets from data packets based on the type identifier, and performs different processing steps. For each data packet, the receiving controller checks the available buffer space. If sufficient, the data is accepted; otherwise, the packet is discarded and the status information is recorded. After data reception is complete, data verification is performed, and the validity of the data is determined based on the verification results.

[0048] The buffer uses a double-buffer design to provide an efficient data storage mechanism. After the data packet is transmitted and verified, the buffer unit marks the packet content as valid and prepares to send it to the depacketization logic. If the verification fails, the corresponding storage space is released to prepare for receiving new data.

[0049] The depacketizer's work consists of three main phases: waiting for processing, data preparation, and information parsing. The depacketizer waits for a packet to pass verification in the buffer. During the preparation phase, it reads information such as TDATA, TID, and TDEST from the buffer, along with the packet contents. During the parsing phase, it reconstructs the packet's payload into the AXI-S bus signal data according to specific rules and passes it sequentially to the upper-layer application.

[0050] The flow control unit tracks and records the status of packet reception. It regularly provides the latest status information to the sender, ensuring that the flow control mechanism can make appropriate decisions based on accurate data. Whenever the sender obtains status information, the flow control unit updates the status record, maintaining the real-time and accuracy of the system status. Status information includes three states: successful reception, unreceived, and received errors.

[0051] The following specifically introduces a working method of a high-speed serial communication system protocol adaptation layer circuit for interconnection between chiplets.

[0052] The protocol adaptation layer circuit of the present invention is located at the data link layer in the transmission layer.

[0053] In the entire workflow, the data to be sent by the AXI-S bus at this end enters the transmitter part, is packaged and transmitted via SerDes, and is received and unpacked by the receiver at the other end, restoring it to the various signal data of the AXI-S bus.

[0054] The work includes the interaction of two protocol adaptation layer circuit modules, such as Figure 2 As shown, the two are cross-connected through the SerDes circuit to connect the transmitter and receiver modules.

[0055] The process of a piece of data from the local end to the remote end after being transmitted via SerDes is as follows:

[0056] First, after a transmission request is received by the local transmitter, the transmitter waits for the buffer in the transmitter to be free and packages the data to be transmitted into data packets. If the transmitter has enough buffer, it temporarily stores the data in the buffer.

[0057] Secondly, when the physical coding sublayer of the SerDes is idle, the data packets in the buffer are read out and sent to the receiver at the other end via the SerDes;

[0058] Then, the receiver at the other end receives the data packet and first checks whether there is enough buffer. If there is no buffer, the data packet is discarded and the local end is notified of the insufficient buffer.

[0059] Finally, wait for the entire data packet to be received, compare the calculated checksum with the checksum attached to the data packet, and discard the data packet if the check fails. If successful, read the data packet in the buffer and unpack it into the corresponding data to complete the transmission.

[0060] This end learns whether its own data packet is sent successfully through the flow control packet sent by the other end. If the data packet is lost, including being discarded by the other end, the data packet in the transmitter module buffer is re-read and transmitted, and the above process is repeated until the data transmission is successful or the number of retransmissions exceeds the limit.

[0061] Special introduction to the packaging mechanism in the application:

[0062] This invention performs structured encoding on AXI-S bus data, designing a dedicated data packet format (preset form) tailored to the channel characteristics. In its implementation, considering that the T channel of the AXI-S bus consists of multiple related signals, this invention employs an efficient data packaging method, ensuring transmission integrity while improving bit utilization.

[0063] The default data packet format is a hierarchical inclusion format for control information, that is, the complete TID and TDEST are included in the first channel transmission of the data packet, and repeated information is omitted in subsequent transmission channels, thereby improving the actual data transmission efficiency. The data packet format of the data type is as follows Figure 3 As shown, it contains multiple functional areas such as type identification field, sequence number field, size field, payload field, alignment field and check code field; among them, the type identification field is used to distinguish data packets and flow control packets, the sequence number field is used to identify and track data packets, the size field indicates the payload length, and the check code is used to ensure the reliability of data transmission.

[0064] The present invention also incorporates a packet completion determination mechanism. When a packet reaches a preset size or no new data is received within a preset time, the current packet is automatically packaged and sent, balancing transmission efficiency and latency. This mechanism avoids transmission delays caused by long wait times for data while ensuring a reasonable packet loading rate.

[0065] The working method of the flow control unit needs special introduction.

[0066] The flow control unit employs a credit-based flow control mechanism: the receiver periodically returns information about its data reception status to the sender, which then determines its data buffer management strategy. This mechanism is particularly well-suited for physical layer transmission environments that don't support direct hardware back pressure, solving flow control issues in high-speed serial communications.

[0067] In order to effectively realize the flow control function, the present invention designs a special flow control package with a compact structure, such as Figure 4 As shown in the figure, a flow control packet has a fixed length and format, containing basic fields such as type identifier, sequence number, and size information. A flow control information field is specifically designed to convey the packet reception status. This flow control information uses an efficient state encoding method to simultaneously convey the reception status of multiple packets, including three basic states: successful reception, non-reception, and reception error. Intelligent packet management is implemented based on this status information, releasing cache resources for successfully received packets, arranging retransmissions for packets with reception errors, and maintaining a waiting state for unreceived packets.

[0068] This well-designed flow control mechanism enables reliable data transmission without hardware backpressure, effectively resolving issues such as traffic congestion and data loss in high-speed serial communications. Furthermore, the mechanism's resource utilization is reasonable, making it particularly well-suited for short-distance, high-speed communication between chips.

[0069] Through the collaborative work of the above modules, the protocol adaptation layer circuit of the present invention realizes an efficient bridge between the data bus and the physical transmission layer in the high-speed serial communication system between chips. This design adopts an optimized data processing flow, a reliable flow control mechanism and a flexible fault-tolerance strategy, which is particularly suitable for the application requirements of short-distance and high-speed communication between chips, and provides an efficient and reliable communication solution for chip design.

[0070] The above-described embodiments of the present application do not constitute a limitation on the scope of protection of the present application.

Claims

1. A high-speed serial communication system protocol adaptation layer circuit for interconnection between chiplets, characterized in that: The protocol adaptation layer circuit includes: Transmitter and receiver; The protocol adaptation layer circuit is a functional module for implementing data transmission between core particles. One side of the protocol adaptation layer circuit is connected to the AXI-S data side, and the other side is connected to the physical coding sublayer in the SerDes circuit, realizing data transmission and reception of the AXI-S bus based on the SerDes circuit, and packaging the AXI-S signals into data packets in a specific form, and interacting with the SerDes circuit for data. The transmitter is used to receive data from the AXI-S bus, package the data from the AXI-S bus into data packets in a preset format, and send them through the SerDes; The transmitter generates and sends a flow control packet at a predetermined interval to report the reception status of the local data packet to the other end. When the receiver at the other end receives the flow control packet, the transmitter at the other end will use it to determine whether to retransmit or update the data packet in the buffer area. The receiver is used to receive data packets from the SerDes and parse the data packets from the SerDes into AXI-S bus data; and send the data packet reception status of the other end in the flow control type data packet, that is, the data packet transmission status of the local end to the transmitter at the local end. The transmitter will determine whether to update the buffer area or retransmit the data packet in the buffer area based on the data packet transmission status of the local end; The transmitter includes a packetizer, a buffer, a peer information management unit, a flow control unit, and an output controller; The receiver module includes a receiving controller, a flow control unit, a buffer and a depacketizer.

2. The protocol adaptation layer circuit according to claim 1, characterized in that: The packager splices the TDATA, TID, TDEST, and TKEEP signals of the AXI-S bus into fixed-length data packets. The first channel in each data packet contains the event ID and destination address information, and the subsequent channels contain only data information.

3. The protocol adaptation layer circuit according to claim 1, wherein: The buffer is specifically used to implement four functional parts: data writing control, data alignment processing, elastic storage and data reading control; Among them, write control allocates storage space for data packets and manages write operations; data alignment ensures that AXI-S bus data is stored according to the standard format; elastic storage provides a data temporary storage mechanism and can release resources based on the transmission results; read control is responsible for extracting data packets from the buffer for transmission and supports data packet retransmission as needed, where retransmitted data packets have priority transmission rights. The workflow of write control in the buffer adopts a state transition mechanism, including three stages: idle waiting, data writing and resource release; the buffer waits for new data packet processing requests in the idle state, performs actual storage operations in the data writing state, and enters the resource release waiting state when resources are insufficient; the workflow of read control; based on state transition, includes four stages: waiting for selection, header sending, data sending and check code sending.

4. The protocol adaptation layer circuit according to claim 1, wherein: The flow control unit of the sending machine is used to periodically obtain data packet reception status information from the receiver, generate and send flow control packets in a standard format. When a flow control information transmission failure is detected, it will actively initiate a retransmission to ensure the stable operation of the flow control mechanism and give the flow control packet the highest priority. The flow control packet includes a type identifier, a sequence ID, packet size information, flow control information and a check code. The flow control information represents the receiving status of each sequence ID data packet through fixed bit coding.

5. The protocol adaptation layer circuit according to claim 1, wherein: The receiving controller adopts a multi-stage processing mechanism, including header recognition, type judgment, data reception, and verification processing; The receiving controller first identifies the data packet header information, distinguishes flow control packets from data packets based on the type identifier, and executes different processing flows; For data packets, the receiving controller checks the available space in the buffer. If there is sufficient space, the data is received; otherwise, the data packet is discarded and status information is recorded. After data reception is completed, data verification is performed and the validity of the data is determined based on the verification result.

6. The protocol adaptation layer circuit according to claim 1, characterized in that: The work of the depacketizer includes waiting for processing, data preparation, and information parsing. The depacketizer waits for a verified data packet to appear in the buffer. During the preparation phase, the data packet content is read from the buffer. During the parsing phase, the payload in the data packet is reconstructed into the various signal data of the AXI-S bus according to specific rules and passed to the upper-layer application in sequence.

7. The protocol adaptation layer circuit according to claim 1, characterized in that: The receiver's flow control unit regularly provides the latest status information to the transmitter. Whenever the transmitter obtains status information, the flow control unit updates the status record to maintain the real-time and accuracy of the system status. The status information includes three states: successful reception, unreceived, and received error.

8. A method for operating a protocol adaptation layer circuit of a high-speed serial communication system for interconnection between chiplets, the method being implemented based on any one of the protocol adaptation layer circuits of claims 1 to 7, characterized in that: The method comprises: Data sending phase, flow control phase and data receiving phase; In the data transmission phase, the AXI-S bus data is packaged into data packets in a specific format and sent to the physical coding sublayer of the SerDes. The flow control phase transmits data packet reception status information through dedicated flow control packets and makes different responses according to different situations; The data receiving stage receives data packets and parses them into AXI-S bus signals; The data transmission phase includes obtaining the sequence ID, packaging the data, storing it in the buffer, and sending the data packet. After the data packet is sent, it is kept in the buffer waiting for confirmation. If a confirmation of reception error is received, the data packet is retransmitted; Generates a flow control packet every preset time period, which contains the reception status of all sequence ID data packets at the local end, and uses fixed bit encoding to represent different data reception status; The data receiving stage includes four steps: receiving a data packet, verifying the data packet, storing the data packet in a buffer, and unpacking the data packet. If the verification fails or the buffer space is insufficient, the data packet is discarded and the corresponding status information is recorded.

9. The method according to claim 8, characterized in that Data packaging adopts the following method: the complete TID and TDEST are included in the first channel transmission of the data packet, and the repeated information is omitted in the subsequent transmission channels; the data packet of the data type contains the type identification field, sequence number field, size field, payload field, alignment field and checksum field; Among them, the type identification field is used to distinguish data packets from flow control packets, the sequence number field is used to identify and track data packets, the size field indicates the payload length, and the check code is used to ensure the reliability of data transmission.

10. The method according to claim 8, characterized in that The flow control unit uses a credit-based flow control mechanism: the receiver periodically returns its data reception status information to the sender, and the sender determines the data cache management strategy based on this information; The flow control packet has a fixed length and format, including type identification, sequence number, and size information; the flow control information field is used to transmit the data packet reception status; the flow control information can simultaneously transmit the reception status of multiple data packets, including three basic states: successful reception, non-reception, and reception error.

Images