Layout method for optimizing fmax of PSRAM

Abstract

The invention provides a layout method for optimizing fmax of a PSRAM. The method comprises the steps that a plurality of I / O of a PSRAM interface are arranged at the upper end and the lower end of one side area of a chip in advance; one part of the EMB connected with the I / O at the upper end of the PSRAM is arranged in the upper half region of the same side of the chip and the I / O, and the other part of the EMB connected with the I / O at the lower end of the PSRAM is arranged in the lower half region of the same side of the chip and the I / O, so that the connection path of the EMB and the I / O is shortened; constraining a logic unit associated with the PSRAM in a region on the same side of the chip and the I / O through a region constraining method; wherein the logic unit comprises an REG and other logic units; a logic unit associated with the PSRAM is arranged in an area on the same side of the chip and the I / O through a layout algorithm; wherein the REG is preferentially arranged in an area on one side of the chip, which is on the same side as the I / O, relative to other logic units. Through the layout method provided by the invention, the delay between the logic units can be reduced, the maximum working frequency of the PSRAM is improved, and the power consumption of a chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip layout, and in particular to a layout method for optimizing the fmax of a PSRAM. Background Art

[0002] In actual engineering projects, there are usually relatively high requirements for the speed of PSRAM (hybrid memory), which requires a relatively high fmax (the maximum clock frequency at which the PSRAM interface can operate reliably) to meet the requirements. Since the dedicated I / O of PSRAM is distributed at the top and bottom of the left or right side of the chip, the I / O is associated with logic resources such as EMB (embedded memory) and REG (register). Due to the lack of centralized location and large span of I / O, and the connection between various modules in the circuit, the final effect of the general layout method is difficult to achieve the target famx (expected maximum operating clock frequency), and cannot meet the actual requirements. There is an urgent need for a layout method to optimize the fmax of the PSRAM module. Summary of the Invention

[0003] In order to solve the above problems, an embodiment of the present application provides a voltage detection power-on reset module, which can detect whether the operating voltage of the circuit is normal and realize full-process monitoring of the power supply voltage.

[0004] To this end, the following technical solutions are adopted in the embodiments of the present application:

[0005] An embodiment of the present application provides a layout method for optimizing the fmax of a PSRAM, the method comprising: pre-laying out multiple I / Os of a PSRAM interface at the upper and lower ends of a side area of ​​a chip; wherein the side area refers to the area on the left or right side of a perpendicular bisector of the chip's long axis; placing a portion of an EMB connected to the I / O at the upper end of the PSRAM in the upper half of the area on the same side of the chip and the I / O, and placing another portion of the EMB block connected to the I / O at the lower end of the PSRAM in the lower half of the area on the same side of the chip and the I / O, so as to shorten the connection path between the EMB and the I / O; constraining logic units associated with the PSRAM to a side area on the same side of the chip and the I / O through a regional constraint method; wherein the logic units include REGs and other logic units; placing the logic units associated with the PSRAM in a side area on the same side of the chip and the I / O through a layout algorithm; wherein the REGs are preferentially placed in the side area on the same side of the chip and the I / O relative to other logic units.

[0006] In one embodiment, the other logic units include one or more of a data bus driver, a data bus receiver, a data multiplexer, an address generator, a control signal logic, a clock tree buffer, and a timing adjustment register.

[0007] The present invention provides a layout method for optimizing PSRAM fmax. I / Os are placed at the top and bottom ends of a chip's side area. The fixed I / Os then locate associated EMB resources. The fixed I / Os and EMBs are then used to position the REGs within this area in a relatively reasonable manner. Finally, other logic units are laid out. This method reduces delays between logic units, PSRAM performance, and chip power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following is a brief introduction to the drawings required for describing the embodiments or prior art.

[0009] Figure 1 Schematic diagram of a flow chart of a layout method for optimizing the fmax of a PSRAM provided in an embodiment of the present application;

[0010] Figure 2 This is a schematic diagram of the PSRAM chip structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0011] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0012] In the description of this application, the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting this application.

[0013] The terms "first" and "second" in this specification and claims are used to distinguish between different objects, rather than to describe a specific order of objects. For example, "a first operational amplifier" and "a second operational amplifier" are used to distinguish between different operational amplifiers, rather than to describe a specific order of operational amplifiers.

[0014] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, a conflicting connection, or an integral connection. A person skilled in the art can understand the specific meanings of the above terms in this application based on the specific circumstances. In the embodiments of this application, "contact" or "coupling" may refer to direct contact between components or contact between components through an adhesive or thermally conductive adhesive.

[0015] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0016] Figure 1 Schematic diagram of a layout method for optimizing the fmax of PSRAM provided in an embodiment of the present application. Figure 1 As shown in FIG. 1 , a layout method for optimizing the fmax of a PSRAM includes:

[0017] Step S101 : pre-layout multiple I / Os of the PSRAM interface at the upper and lower ends of one side area of ​​the chip.

[0018] Specifically, the multiple I / O (input and output pins) of the PSRAM interface can be pre-locked at the upper and lower ends of one side area of ​​the chip. The one side area refers to the left or right area of ​​the perpendicular bisector of the chip's long axis. For example, refer to Figure 2 The right side of the chip refers to the physical area to the right of the perpendicular bisector of the chip's long axis. You can first define this physical area and then use the constraint manager to assign PSRAM-related I / O to this designated area. You can also use SI / PI simulation to check signal quality and adjust the pin order to avoid crossing traces. Similarly, the left side of the chip refers to the physical area to the left of the perpendicular bisector of the chip's long axis. The I / O layout method in this left area is the same as that in the right area, so I will not repeat it here.

[0019] In step S102, a portion of the EMB connected to the I / O at the upper end of the PSRAM is placed in the upper half of the area on the same side of the chip and the I / O, and another portion of the EMB connected to the I / O at the lower end of the PSRAM is placed in the lower half of the area on the same side of the chip and the I / O, so as to shorten the connection path between the EMB and the I / O.

[0020] Specifically, when the I / O locations have been determined, since EMBs (embedded memory blocks) are relatively complex logic resources compared to general logic resources (such as REGs and LUTs), they often have a greater impact on chip performance. Therefore, you can first consider constraining the EMBs. You can first place a portion of the EMBs connected to the I / Os at the top of the PSRAM in the upper half of the chip on the same side as the I / Os, and place another portion of the EMB blocks connected to the I / Os at the bottom of the PSRAM in the lower half of the chip on the same side as the I / Os. Furthermore, you can use layout tools (such as Cadence Innovus / Synopsys ICC2) to define the physical area for the EMB layout, and use netlist constraints to assign the logic modules connected to the top I / Os of the PSRAM to the top EMBs and the bottom I / Os to the bottom EMBs. Enable regional routing, restricting the top EMBs to routing only on the top metal layer and the bottom EMBs to routing only on the bottom metal layer.

[0021] The above embodiments can shorten the connection path between the EMB and the I / O, reduce the delay between the EMB and the I / O, and reduce chip power consumption.

[0022] Step S103: Constrain the logic units associated with the PSRAM to a region on the same side of the chip as the I / O using a region constraint method. The logic units include REGs and other logic units.

[0023] Specifically, since the I / O (input and output pins) and EMB resources of the fixed PSRAM in step S101 are all in the area on one side of the chip, regional constraints (regional constraints are a method of controlling the layout position of modules or units through physical restrictions, with the purpose of optimizing signal paths, reducing delays, reducing congestion, and meeting timing and power consumption requirements) are used to constrain other logic units associated with the PSRAM (such as REGs) to the area on the same side of the chip as the I / O, so as to ensure that there is a smaller delay between the logic units associated with the PSRAM.

[0024] Through the above implementation, the logic association units of the PSRAM can be centralized, while reducing the delay between the logic association units, thereby improving chip performance.

[0025] In one embodiment, the other logic units include, but are not limited to, one or more of a data bus driver, a data bus receiver, a data multiplexer, an address generator, a control signal logic, a clock tree buffer, and a timing adjustment register.

[0026] Step S104: Layout the logic units associated with the PSRAM in a side region on the same side as the I / O using a layout algorithm, wherein the REG is preferentially laid out in the side region on the same side as the I / O relative to other logic units.

[0027] Specifically, placement algorithms are used within electronic design automation tools to determine the physical location of logic cells (such as registers and timing adjustment registers) on a chip. Their core goal is to find the optimal placement of these cells while meeting constraints such as timing, power consumption, and area. During logic cell placement, you can assign a higher weight or priority to each REG in the placement tool, forcing it to be placed first and other logic cells to follow.

[0028] Since the global layout does not give much consideration to DRC constraints (DRC constraints are key rules in chip physical design, used to ensure the feasibility and reliability of chip manufacturing. They define the geometric, electrical and process restrictions that the layout must meet to avoid chip failure or yield degradation due to design violations), some REGs may not work well in the detailed layout stage due to the layout order and DRC constraints. Ultimately, the positions of some REGs cannot be constrained within the target range. Therefore, in the detailed layout, the REGs of the PSRAM module are given priority layout, and the priority of the layout of these REGs is increased to ensure that the REGs in these regional constraints are all within the region, and individual REGs do not appear outside the region.

[0029] The present application also provides test results before and after chip optimization, as shown in the table below. The left side of the table shows the test results of the fmax of each clock of the chip before optimization, and the right side of the table shows the test results of the fmax of each clock of the chip after optimization. As can be seen from the table, there are 10 test results in total. The same clock constraints are used in each experiment before and after optimization. The bottom row of the table is the average of the 10 clock fmax values. It can be seen that the fmax of the PSRAM clock after optimization is improved from 184M to 215M, an increase of about 17%, while the fmax of other clocks is slightly improved or remains unchanged. After optimizing the PSRAM, the fmax is significantly improved.

[0030]

[0031] Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present application. Those skilled in the art should understand that, although the present application has been described in detail with reference to the aforementioned embodiments, the technical solutions described in the aforementioned embodiments may be modified or some of the technical features thereof may be replaced with equivalents. However, such modifications or replacements do not deviate from the spirit and scope of the technical solutions in the various embodiments of the present application.

Claims

1. A layout method for optimizing the fmax of PSRAM, characterized in that: include: Multiple I / Os of the PSRAM interface are pre-placed at the upper and lower ends of one side area of ​​the chip; wherein one side area refers to the area on the left or right side of the perpendicular bisector of the chip's long axis; The EMB blocks connected to the upper I / Os of the PSRAM are placed in the upper half of the chip on the same side as the I / Os, while the EMB blocks connected to the lower I / Os of the PSRAM are placed in the lower half of the chip on the same side as the I / Os to shorten the connection path between the EMBs and the I / Os. The logic cells associated with the PSRAM are constrained to a region on the same side of the chip as the I / O through a region constraint method; wherein the logic cells include REG and other logic cells; The logic units associated with the PSRAM are placed in a side area on the same side of the chip as the I / O through a placement algorithm; wherein the REG is placed in the side area on the same side of the chip as the I / O relative to other logic units.

2. The method according to claim 1, characterized in that Other logic units include one or more of a data bus driver, a data bus receiver, a data multiplexer, an address generator, a control signal logic, a clock tree buffer, and a timing adjustment register.

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