Programmable 0.5 divider

Abstract

The application relates to the field of integrated circuits, and discloses a programmable 0.5 frequency divider, which comprises a programmable integer frequency divider, a coding circuit, a sampling circuit and a selection circuit. The coding circuit utilizes the preliminary output of the integer frequency divider to generate a synchronous control signal. In the 0.5 frequency division mode, the circuit periodically switches the frequency division ratio of the frequency divider between N and N+1, and synchronously switches the selection signal of the subsequent sampling circuit, so that the selection signal alternately selects the sampling results at the rising edge and the falling edge of the input clock. The scheme has simple structure, only needs a programmable integer frequency divider, significantly reduces the chip area and design complexity, and accelerates the development rhythm of the circuit through robust internal timing control.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to frequency divider technology. Background Art

[0002] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of this application.

[0003] In modern integrated circuit systems, especially complex systems-on-chips (SoCs), clock signals play a crucial role, acting as the heart of the system. Typically, the system's clock is generated by one or more phase-locked loop (PLL) circuits. While the PLL's output frequency is typically fixed, different functional modules within the SoC may need to operate at a variety of different clock frequencies. To meet these diverse frequency requirements, frequency division technology is widely used.

[0004] Traditional frequency division technology primarily relies on integer division, or divide-by-N, which reduces the input clock frequency to 1 / N of the original frequency. The main limitation of this type of divider is its inflexible output frequency, which can only be an integer fraction of the input frequency, limiting the flexibility of clock configuration.

[0005] To overcome this limitation, technologies capable of achieving non-integer frequency division have emerged, with divide-by-0.5 (i.e., achieving N+0.5 division) being a common and useful solution. A programmable divider that achieves N+0.5 division typically uses a multi-modulus divider (MMD), a circuit that can change its integer division ratio based on a digital control signal.

[0006] Currently, there are many technical solutions for achieving 0.5 frequency division in the industry, but each has its own shortcomings:

[0007] Dual-divider chain architecture: This approach typically uses two parallel divider paths, one for rising clock edges (positive chain) and one for falling clock edges (negative chain), with selectors switching the outputs. While this design is functional, its primary drawback is the requirement for two complete divider chains, resulting in a circuit with hardware area and power consumption nearly double that of a single divider chain, making it unsuitable for cost- and area-sensitive designs.

[0008] Delay cell solution: This solution uses a controllable delay cell to generate the required half-cycle delay, simulating a 0.5 frequency division effect. However, the delay cell itself is sensitive to process, voltage, and temperature (PVT) variations, requiring additional calibration for delay linearity, and is prone to introducing significant noise. Therefore, this solution is generally not suitable for applications with high noise performance requirements.

[0009] Multi-phase switching: This solution generates multiple (e.g., four) orthogonal phases of the input clock and selectively switches between them to achieve 0.5-step frequency division. The disadvantage of this design is that it requires a clock circuit capable of generating precise multiple phases, which not only increases the design complexity of the front-end circuitry, but also poses challenges in generating and switching multiple phases in high-speed applications.

[0010] In summary, existing 0.5-frequency division technology solutions generally have problems such as large circuit area, high cost, complex design, or poor noise performance. Summary of the Invention

[0011] An object of the present application is to provide a programmable 0.5 frequency divider that is simple in structure, highly area- and cost-effective, and easy to design and implement.

[0012] The present application discloses a programmable 0.5-division frequency divider, comprising:

[0013] A programmable integer frequency divider, whose frequency division ratio is controlled by a frequency division control signal, whose input is an input clock signal, and whose output is a preliminary frequency division signal;

[0014] a sampling circuit comprising a first sampling unit for sampling the preliminary frequency-divided signal at a rising edge of the input clock signal, and a second sampling unit for sampling the preliminary frequency-divided signal at a falling edge of the input clock signal;

[0015] A selection circuit, configured to select one of the outputs of the first sampling unit and the second sampling unit as a final output frequency-divided signal according to a sampling selection signal;

[0016] an encoding circuit that receives the preliminary frequency-divided signal as input and periodically switches between a first state and a second state according to the preliminary frequency-divided signal to synchronously generate the frequency-divided control signal and the sampling selection signal, thereby achieving N+0.5 frequency division, where N is a preset integer greater than 1; wherein,

[0017] In the first state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of one of the first sampling unit and the second sampling unit;

[0018] In the second state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N+1, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the other of the first sampling unit and the second sampling unit.

[0019] In a preferred embodiment, in the first state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the first sampling unit;

[0020] In the second state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N+1, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the second sampling unit.

[0021] In a preferred embodiment, in the first state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the second sampling unit;

[0022] In the second state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N+1, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the first sampling unit.

[0023] In a preferred embodiment, the encoding circuit further receives a mode control signal, wherein the mode control signal is used to instruct the programmable 0.5-division frequency divider to operate in an N+0.5 division mode or an integer-N division mode.

[0024] In a preferred example, when the mode control signal indicates operating in the integer N division mode, the division control signal output by the encoding circuit is constantly a code for setting the division ratio of the programmable integer divider to N, and the synchronously output sampling selection signal is constantly selecting the output of the first sampling unit or constantly selecting the output of the second sampling unit.

[0025] In a preferred embodiment, the encoding circuit includes:

[0026] a first D flip-flop, whose inverting output terminal is connected to its data input terminal, whose clock input terminal is used to receive the preliminary frequency-divided signal, and whose non-inverting output terminal outputs a first switching clock;

[0027] a fifth multiplexer, configured to select between the first switching clock and a fixed logic level according to the mode control signal to output a second switching clock; wherein the fixed logic level is selected when the mode control signal indicates operation in the integer-N division mode, and the first switching clock is selected when the mode control signal indicates operation in the N+0.5 division mode;

[0028] a third multiplexer, wherein a selection control terminal receives the second switching clock and selects between a first code and a second code input according to the second switching clock to output the frequency division control signal; wherein the first code represents a frequency division ratio of N, and the second code represents a frequency division ratio of N+1;

[0029] The fourth multiplexer has a selection control terminal receiving the second switching clock and selecting between the first logic level and the second logic level according to the second switching clock to output the sampling selection signal.

[0030] In a preferred embodiment, the encoding circuit further includes:

[0031] a first multiplexer, configured to generate the first code according to the mode control signal, and output the first code to an input terminal of the third multiplexer;

[0032] The second multiplexer is configured to generate the second code according to the mode control signal and output the second code to another input terminal of the third multiplexer.

[0033] In a preferred embodiment, the programmable integer frequency divider is a multi-modulus frequency divider chain.

[0034] In a preferred embodiment, the first sampling unit includes a third D flip-flop, whose data input terminal receives the preliminary frequency-divided signal, and whose clock input terminal receives the input clock signal;

[0035] The second sampling unit includes a fourth D flip-flop, a data input terminal of which receives the preliminary frequency-divided signal, and a clock input terminal of which receives an inverted signal of the input clock signal;

[0036] The selection circuit includes a sixth multiplexer, whose two data input terminals are respectively connected to the positive phase output terminals of the third D flip-flop and the fourth D flip-flop, whose selection control terminal receives the sampling selection signal, and whose output terminal outputs the final output frequency division signal.

[0037] In a preferred example, the sampling circuit further includes a second D flip-flop, a clock input of the second D flip-flop receiving the input clock signal, a data input of the second D flip-flop receiving the preliminary frequency-divided signal, and a positive phase output of the second D flip-flop connected to the data inputs of the third D flip-flop and the fourth D flip-flop.

[0038] In an embodiment of the present application, an encoding circuit is introduced that uses the programmable divider's own preliminary frequency-divided output as a clock, periodically switching between two states. This circuit synchronously generates a frequency-division control signal for setting the divider's frequency-dividing ratio (switching between N and N+1) and a sampling select signal for selecting different clock edge sampling results (switching between rising and falling edge sampling). This allows the N+0.5 frequency-dividing function to be implemented using only a single programmable integer divider (e.g., a single MMD chain). Compared to existing solutions that require two MMD chains, one positive and one negative, this design significantly saves chip area and reduces hardware costs. Furthermore, this self-synchronizing encoding scheme between the control signal and the data path offers a simple structure and strong robustness, avoiding complex digital and analog co-design and verification, thereby significantly accelerating circuit development cycles.

[0039] Furthermore, the entire divider can be switched between N+0.5 division mode and integer-N division mode via a mode control signal. This design increases the functional versatility of the circuit, enabling it to flexibly adapt to the different clock signal requirements of different modules in an SoC, for example.

[0040] Furthermore, by defining that when the mode control signal indicates operation in integer-N frequency division mode, the encoding circuit outputs a constant frequency division control signal and sampling selection signal, it can be ensured that the frequency divider can stably output a standard N frequency division signal in this mode, avoiding any potential glitches or instability problems caused by state switching logic.

[0041] Furthermore, by implementing the encoding circuit using D-type flip-flops and multiplexers (MUX3, MUX4, and MUX5), a hardware solution with a clear structure, low cost, and ease of implementation is provided. This simple circuit reliably generates the required dynamic switching clock or fixed level based on the mode control signal to drive subsequent control signal generation, effectively accelerating development efforts.

[0042] Furthermore, by using two D flip-flops (one triggered by the input clock and the other triggered by its inverted clock) and a multiplexer to respectively implement the first sampling unit, the second sampling unit and the selection circuit, a mature and reliable circuit implementation method can be provided for the sampling part of the present invention, ensuring that reliable data sampling and selection can be performed on both the rising and falling edges of the input clock.

[0043] Furthermore, by adding an optional D flip-flop before the two sampling D flip-flops to pre-process the preliminary divided signal, the metastable problem that may occur at the intersection of signals from different clock domains (the divided clock and the high-speed input clock) can be effectively solved, thereby improving the timing robustness and reliability of the entire divider under high-frequency operation.

[0044] The various technical features disclosed in the above summary of the invention, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings may be freely combined with each other to form various new technical solutions (all of which should be deemed to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, if one example discloses features A+B+C and another example discloses features A+B+D+E, and features C and D are equivalent technical means that perform the same function, only one of them can be used technically, and it is not possible to use them simultaneously. Feature E can be technically combined with feature C. In this case, the solution A+B+C+D should not be deemed to have been described because it is technically infeasible, while the solution A+B+C+E should be deemed to have been described. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 1 is a schematic structural diagram of a programmable 0.5 frequency divider according to an embodiment of the present application;

[0046] Figure 2 2 is a schematic diagram of the structure of an encoding circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0047] In the following description, many technical details are provided to help readers better understand this application. However, those skilled in the art will understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in this application can be implemented.

[0048] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0049] One embodiment of the present application relates to a programmable 0.5 frequency divider ( Figure 1A specific example is shown, the programmable 0.5 division divider includes:

[0050] a programmable integer divider whose division ratio is determined by a division control signal M <n:1>Control, its input is the input clock signal fin, and its output is the preliminary frequency division signal fout. The programmable integer divider itself is a prior art and can be implemented in many ways, for example, it can be implemented using a multi-mode divider chain (MMD chain), or for example, it can be implemented using a counter with a preset value. In this application, <n:1>It can represent a bus with a bit width of n. This means that it is not a single signal line, but consists of n parallel signal lines, which can transmit an n-bit binary number at the same time.

[0051] The sampling circuit includes a first sampling unit ( Figure 1 In the embodiment, it is implemented by a D flip-flop DFF3), and a second sampling unit ( Figure 1 In the embodiment, it is implemented by a D flip-flop DFF4). Figure 1 The sampling circuit of this embodiment includes three D flip-flops, DFF2, DFF3, and DFF4. The clock input CK of DFF2 receives the input clock signal fin, and the data input D of DFF2 receives the preliminary frequency-divided signal fout from the programmable integer frequency divider. The non-inverting output Q of DFF2 is connected to the data inputs D of DFF3 and DFF4, respectively. The clock input CK of DFF3 receives the input clock signal fin, and the clock input CK of DFF4 receives the inverted signal finb of the input clock signal fin. Alternatively, in another embodiment, DFF2 can be omitted, and the data inputs D of DFF3 and DFF4 can be directly connected to the preliminary frequency-divided signal fout.

[0052] Select Circuit ( Figure 1 In the embodiment, the selector MUX6 is used to select one of the outputs of the first sampling unit and the second sampling unit as the final output frequency division signal DIVOUT according to the sampling selection signal sel. Figure 1 In the embodiment, when sel is at a high level, the output of DFF4 is selected as DIV_OUT, and when sel is at a low level, the output of DFF3 is selected as DIV_OUT. In other embodiments, the opposite may be true.

[0053] The encoding circuit receives the preliminary frequency division signal fout from the programmable integer frequency divider as input, and periodically switches between the first state and the second state according to the preliminary frequency division signal fout to synchronously generate the frequency division control signal M <n:1>and the sampling selection signal sel, thereby achieving N+0.5 frequency division, where N is a preset integer greater than 1.

[0054] exist Figure 1 In the embodiment of the present invention, in the first state, the encoding circuit outputs the frequency division control signal M <n:1>The frequency division ratio of the programmable integer frequency divider is set to N, and the sampling selection signal sel is output synchronously to enable the selection circuit to select the output of the first sampling unit. In the second state, the encoding circuit outputs the frequency division control signal M <n:1>The frequency division ratio of the programmable integer frequency divider is set to N+1, and the sampling selection signal sel is synchronously output to enable the selection circuit to select the output of the second sampling unit.

[0055] In another embodiment, in the first state, the encoding circuit outputs the frequency division control signal M <n:1>The division ratio of the programmable integer frequency divider is set as N, and the sampling selection signal sel is output synchronously to make the selection circuit select the output of the second sampling unit. In the second state, the encoding circuit outputs the frequency division control signal M <n:1>The frequency division ratio of the programmable integer frequency divider is set to N+1, and the sampling selection signal sel is synchronously output to enable the selection circuit to select the output of the first sampling unit.

[0056] The encoding circuit also receives a mode control signal, which is used to instruct the programmable 0.5 frequency divider to operate in N+0.5 frequency division mode or integer N frequency division mode. Figure 1 In the example, the mode control signals include Ctrl <n:1>and fun, where Ctrl <n:1>It indicates N (the integer portion of the frequency division), and fun indicates whether to perform a 0.5 division based on N. fun can be a single-bit signal, where a high level or a low level can indicate whether a 0.5 division is performed or not, respectively. For example, in some embodiments, a high level on fun can indicate a 0.5 division and a low level on fun can indicate no 0.5 division. Alternatively, in other embodiments, a low level on fun can indicate a 0.5 division and a high level on fun can indicate no 0.5 division.

[0057] When the mode control signal indicates that the operation is in integer N frequency division mode, the frequency division control signal M output by the encoding circuit is <n:1>The code for setting the frequency division ratio of the programmable integer frequency divider to N is constant, and the synchronously output sampling selection signal sel is constant for selecting the output of the first sampling unit DFF3 or the output of the second sampling unit DFF4.

[0058] When the mode control signal indicates to work in integer N+0.5 frequency division mode, the frequency division control signal M output by the encoding circuit is <n:1>The frequency division ratio of the programmable integer frequency divider is set to switch continuously between N and N+1, and the output sampling selection signal sel is also synchronously switched between the first sampling unit DFF3 and the second sampling unit DFF4.

[0059] In one embodiment, the encoding circuit may use Figure 2 The circuit shown is implemented. The encoding circuit includes:

[0060] The first D flip-flop DFF1 has its inverting output terminal Qb connected to its data input terminal D, its clock input terminal CK for receiving the preliminary frequency-divided signal fout from the programmable integer frequency divider, and its non-inverting output terminal Q outputting the first switching clock Ck0.5.

[0061] The first multiplexer MUX1 is used to control the Ctrl <n:1>Generate the first code N <n:1>, and the first code N <n:1>+1 is output to one input terminal of the third multiplexer MUX3.

[0062] The second multiplexer MUX2 is used to control the Ctrl <n:1>+1 Generate the second code N <n:1>+1, and the second code N <n:1>+1 is output to the other input terminal of the third multiplexer MUX3. <n:1>+1 means Ctrl in the mode control signal <n:1>1 on the basis of the above.

[0063] A third multiplexer MUX3 receives a second switching clock Ck at a control input and selects, in accordance with the second switching clock Ck, between a first encoded N <n:1>N <n:1>+1 to output the frequency division control signal M <n:1>Among them, the first code N <n:1>Is the code representing the frequency division ratio of N, the second code N <n:1>+1 represents the code with a frequency division ratio of N+1.

[0064] The fourth multiplexer MUX4 receives the second switching clock CK at its selection control terminal and selects between the first logic level and the second logic level according to the second switching clock Ck to output a sampling selection signal sel. Figure 2 The first logic level is a low level and the second logic level is a high level. In another embodiment, the first logic level may be a high level and the second logic level may be a low level.

[0065] The fifth multiplexer MUX5 switches the first switching clock Ck0.5 with the fixed logic level ( Figure 2 The first switching clock Ck0.5 is selected from the ground level (which may also be the power supply level VDD in other embodiments) to output the second switching clock Ck. When the fun signal in the mode control signal indicates operation in integer-N frequency division mode, a fixed logic level is selected. When the fun signal in the mode control signal indicates operation in N+0.5 frequency division mode, the first switching clock Ck0.5 is selected.

[0066] The first multiplexer MUX1 , the second multiplexer MUX2 , and the third multiplexer MUX3 may each be composed of a group (for example, n, where n is a positive integer greater than 1) of single-bit multiplexers MUX.

[0067] Figure 2 In the encoding circuit, MUX1 is used to program the output N value, that is, its output N <n:1>By Ctrl <n:1>Input control; MUX2 is used to program the N+1 value of the output, i.e. its output N <n:1>+1 by Ctrl <n:1>+1 input control, when the frequency is divided by N+0.5, the control signal of the programmable integer divider needs to switch between N and N+1. The switching clock CK is generated by DFF1, and the DFF1 input clock can be Figure 1 In fout, the output Ck0.5 of DFF1 is the switching clock in the 0.5 division state. Ck0.5 is the input of MUX5. MUX5 can be configured by the fun signal. When fun = 1, it is in the 0.5 division state. MUX3 and MUX4 are the output stages of the encoding circuit. When fun = 1, Ck = Ck0.5. At this time, the output of MUX3 is in N <n:1>and N <n:1>+1, the MUX4 output switches between 0 and 1, forming a 0.5 frequency division coding output; and when fun=0, the MUX3 output is always N <n:1>, the output of MUX4 is always 0.

[0068] comprehensive Figure 1 and Figure 2 , as a whole, only a programmable integer divider (such as MMD chain) is used for frequency division, and the post-stage uses DFF for sampling, and performs rising edge sampling and falling edge sampling at the same time. The sampling result is selected by mux, and the control signal sel of mux is controlled by the encoding circuit, which can select whether to divide by 0.5; for the encoding circuit, the frequency division N can be selected and programmed by the ctrl control word and converted into binary code M <n:1>Control the MMD chain; support the switching of the encoding circuit mode by the programmable fun signal, for example, fun = 0, the encoding circuit works in the frequency division N mode; for fun = 1, the encoding circuit works in the frequency division N+0.5 mode; vice versa; if the encoding circuit works in the frequency division N mode, then the encoding circuit outputs M <n:1>The binary code is constant for N and sel is constant for 0; if the encoding circuit works in the division mode N+0.5, the encoding circuit needs to combine with the sel signal for output, in k beats, M <n:1>= N + 1, sel = 1 ; then in k+1 shot M <n:1>= N, sel = 0; under this encoding, the circuit can achieve a 0.5 division output.

[0069] It should be noted that the relationship terms such as first and second, and the like, are used herein only to differentiate one entity or action from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or actions. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including one" does not exclude the presence of another identical element in the process, method, article or device including the element. In this application, if it is mentioned that a certain behavior is performed according to a certain element, it means that the behavior is performed at least according to the element, including two cases: the behavior is performed only according to the element, and the behavior is performed according to the element and other elements. The expressions of multiple, multiple times, multiple, etc. include 2, 2 times, 2 and more than 2, more than 2 times, more than 2.

[0070] The specification includes various embodiments of the various embodiments described herein. Separate references to embodiments (for example, "one embodiment" or "some embodiments" or "a preferred embodiment") do not necessarily refer to the same embodiment; however, such embodiments are not mutually exclusive, unless indicated as such or it is clear from the context that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense, unless otherwise explicitly indicated or required by context.

[0071] All documents referred to in this application are considered to be incorporated in their entirety into the disclosure of this application, so that they can be used as a basis for modification, if necessary. In addition, it should be understood that those skilled in the art can make various modifications or changes to this application after reading the content of this application, and these equivalent forms also fall within the scope of the application claimed.

Claims

1. A programmable 0.5 frequency divider, characterized in that: include: A programmable integer frequency divider, whose frequency division ratio is controlled by a frequency division control signal, whose input is an input clock signal, and whose output is a preliminary frequency division signal; a sampling circuit comprising a first sampling unit for sampling the preliminary frequency-divided signal at a rising edge of the input clock signal, and a second sampling unit for sampling the preliminary frequency-divided signal at a falling edge of the input clock signal; A selection circuit, configured to select one of the outputs of the first sampling unit and the second sampling unit as a final output frequency-divided signal according to a sampling selection signal; an encoding circuit that receives the preliminary frequency-divided signal as input and periodically switches between a first state and a second state according to the preliminary frequency-divided signal to synchronously generate the frequency-divided control signal and the sampling selection signal, thereby achieving N+0.5 frequency division, where N is a preset integer greater than 1; wherein, In the first state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of one of the first sampling unit and the second sampling unit; In the second state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N+1, and simultaneously outputs the sampling selection signal to enable the selection circuit to select the output of the other of the first sampling unit and the second sampling unit; The encoding circuit further receives a mode control signal, wherein the mode control signal is used to instruct the programmable 0.5 frequency divider to operate in an N+0.5 frequency division mode or an integer N frequency division mode; The encoding circuit comprises: a first D flip-flop, whose inverting output terminal is connected to its data input terminal, whose clock input terminal is used to receive the preliminary frequency-divided signal, and whose non-inverting output terminal outputs a first switching clock; a fifth multiplexer, configured to select between the first switching clock and a fixed logic level according to the mode control signal to output a second switching clock; wherein the fixed logic level is selected when the mode control signal indicates operation in the integer-N division mode, and the first switching clock is selected when the mode control signal indicates operation in the N+0.5 division mode; a third multiplexer, wherein a selection control terminal receives the second switching clock and selects between a first code and a second code input according to the second switching clock to output the frequency division control signal; wherein the first code represents a frequency division ratio of N, and the second code represents a frequency division ratio of N+1; The fourth multiplexer has a selection control terminal receiving the second switching clock and selecting between the first logic level and the second logic level according to the second switching clock to output the sampling selection signal.

2. The programmable 0.5 frequency divider according to claim 1, wherein: In the first state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the first sampling unit; In the second state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N+1, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the second sampling unit.

3. The programmable 0.5 frequency divider according to claim 1, wherein: In the first state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the second sampling unit; In the second state, the encoding circuit outputs the frequency division control signal to set the frequency division ratio of the programmable integer frequency divider to N+1, and synchronously outputs the sampling selection signal to enable the selection circuit to select the output of the first sampling unit.

4. The programmable 0.5 frequency divider according to claim 1, wherein: When the mode control signal indicates operation in the integer-N frequency division mode, the frequency division control signal output by the encoding circuit is constantly a code for setting the frequency division ratio of the programmable integer frequency divider to N, and the synchronously output sampling selection signal is constantly selecting the output of the first sampling unit or constantly selecting the output of the second sampling unit.

5. The programmable 0.5 frequency divider according to claim 4, wherein: The encoding circuit further includes: a first multiplexer, configured to generate the first code according to the mode control signal, and output the first code to an input terminal of the third multiplexer; The second multiplexer is configured to generate the second code according to the mode control signal and output the second code to another input terminal of the third multiplexer.

6. The programmable 0.5 frequency divider according to any one of claims 1 to 5, wherein: The first sampling unit includes a third D flip-flop, a data input terminal of which receives the preliminary frequency-divided signal, and a clock input terminal of which receives the input clock signal; The second sampling unit includes a fourth D flip-flop, a data input terminal of which receives the preliminary frequency-divided signal, and a clock input terminal of which receives an inverted signal of the input clock signal; The selection circuit includes a sixth multiplexer, whose two data input terminals are respectively connected to the positive phase output terminals of the third D flip-flop and the fourth D flip-flop, whose selection control terminal receives the sampling selection signal, and whose output terminal outputs the final output frequency division signal.

7. The programmable 0.5 frequency divider according to claim 6, wherein: The sampling circuit also includes a second D flip-flop, wherein a clock input terminal of the second D flip-flop receives the input clock signal, a data input terminal of the second D flip-flop receives the preliminary frequency-divided signal, and a non-inverting output terminal of the second D flip-flop is connected to the data input terminals of the third D flip-flop and the fourth D flip-flop.

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