Radio frequency synchronization signal circuit and method

Abstract

The application discloses a kind of radio frequency synchronous signal circuit and synchronization method, belong to wireless communication technical field, solve the problem that existing device with full integration self-calibration function is difficult to meet miniaturization, low cost and wide frequency range synchronization demand;It includes radio frequency synchronous signal source, radio frequency synchronous signal source includes the phase detection circuit, FPGA circuit, DAC circuit, radio frequency circuit and output port connected in turn;The input end of phase detection circuit is respectively connected with two symmetrically arranged first frequency divider circuit and second frequency divider circuit in parallel.The full integration circuit of radio frequency synchronous signal source and automatic synchronization method are used in the application, miniaturization, low cost, wide frequency range and high-precision synchronization are realized, the port-to-port synchronization output of multi-channel radio frequency signal is realized, and the dependence on external equipment is eliminated and cable phase offset is compensated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a radio frequency synchronization signal circuit and a synchronization method. BACKGROUND

[0002] In modern wireless communication and test technology, high-precision synchronization output of multi-channel radio frequency signals is the core requirement to ensure system performance. The traditional scheme relies on external calibration instruments (such as network analyzers, phase-locked loop modules) and complex cable connections, and compensates for phase errors by periodically injecting reference signals or manual calibration. The following defects exist:

[0003] High cost: external high-precision instruments account for 30%-50% of system cost, and require additional configuration of frequency dividers, temperature-controlled crystal oscillators, etc.

[0004] Bulkiness: multi-device cascade cables, fixtures and external devices cause a significant increase in system volume and weight, making it difficult to meet the needs of mobile scenarios.

[0005] Poor frequency adaptability: existing phase detection chips have a bandwidth of only several GHz, which cannot directly measure higher frequency radio frequency signals, and the non-symmetrical design of the circuit introduces phase errors such as temperature drift and wiring delay. SUMMARY

[0006] In view of the above problems in the prior art, the present application provides a radio frequency synchronization signal circuit and a synchronization method, which solves the problem that existing devices with full-integrated self-calibration function cannot meet the needs of miniaturization, low cost and wide frequency range synchronization.

[0007] In order to achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0008] On the one hand, a radio frequency synchronization signal circuit is provided, which comprises a radio frequency synchronization signal source, the radio frequency synchronization signal source comprising a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port connected in sequence; the input end of the phase detection circuit is connected in parallel with two symmetrically arranged first frequency divider circuits and second frequency divider circuits, the input ends of the first frequency divider circuits and the second frequency divider circuits are electrically connected with a first synchronization port and a second synchronization port respectively, the first synchronization port is electrically connected with the output port, and the second synchronization port is electrically connected with an external radio frequency signal source.

[0009] In the scheme, the first frequency divider circuit and the second frequency divider circuit are symmetrically arranged, so as to convert the high-frequency radio frequency signal into a low-frequency signal that can be detected by the phase detection circuit, cover a wider radio frequency band, and expand the frequency adaptation range. Meanwhile, through the built-in synchronization control algorithm of the FPGA circuit, the real-time adjustment of the signal frequency and phase, and the processing and feedback control of the phase detection data are realized. The DAC circuit can generate an analog voltage according to the control signal output by the FPGA, so as to adjust the output phase of the radio frequency circuit. Therefore, the cooperation of the FPGA circuit and the DAC circuit can synchronize the high-frequency signal of the radio frequency synchronization signal source with the external radio frequency signal source, realize the full-integrated self-calibration function, reduce the dependence on external calibration instruments (such as network analyzers or phase-locked loop modules), significantly reduce the system cost, and the FPGA circuit and the DAC circuit have compact structure and are easy to integrate, supporting miniaturization design.

[0010] Further, the plurality of radio frequency synchronization signal sources are connected in series, wherein adjacent two radio frequency synchronization signal sources are respectively used as a master and a slave, and the output port in the master is connected with the second synchronization port of the slave. The two-by-two synchronization strategy can be used between the radio frequency synchronization signal sources, the master-slave relationship is established through the first synchronization port and the second synchronization port, and then the master is cascaded with other slaves after calibration, so as to build a multi-channel synchronization network.

[0011] Further, the connection line of the output port in the master and the second synchronization port of the slave and the connection line of the first synchronization port in the slave and the output port of the slave are both provided with a cable clamp. The cable clamp ensures the mechanical stability and electrical consistency of the connection cable, expands the use scenarios, and the circuit of the radio frequency synchronization signal source calibrates the error caused by the cable difference, so as to realize the signal synchronization from port to port.

[0012] On the other hand, a synchronization method of a radio frequency synchronization signal circuit is provided, which comprises the following steps:

[0013] A1, generating a frequency division signal S2 through the second synchronization port and the second frequency divider circuit of the radio frequency synchronization signal source from the output signal S1 of the output port of the external radio frequency signal source; generating a frequency division signal S4 through the first synchronization port and the first frequency divider circuit of the radio frequency synchronization signal source from the output signal S3 of the output port of the radio frequency synchronization signal source;

[0014] A2, calculating the phase difference between the detection frequency division signal S2 and the frequency division signal S4 by the FPGA circuit in real time according to the voltage quantization value output by the phase detection circuit;

[0015] A3, adjusting the output signal S3 of the radio frequency synchronization signal source to the optimal detection interval of the phase detection circuit through the FPGA circuit and the DAC circuit;

[0016] ​​A4, calculating the original phase difference between the output signal S1 and the output signal S3 through the FPGA circuit and the DAC circuit , realizing the phase synchronization of the output signal S1 and the output signal S3.

[0017] In this scheme, the indirect accurate synchronization of the high-frequency radio frequency signal is realized through frequency division and phase difference adjustment, which overcomes the limitations of directly measuring the high-frequency signal, expands the frequency range, and realizes the port-to-port synchronization output of the multi-channel radio frequency signal between the FPGA circuit and the DAC circuit, eliminates the dependence on external devices and compensates for the cable phase offset, while realizing the automatic synchronization process, significantly reducing the operation cost and time cost.

[0018] Further, the step A3 comprises:

[0019] A31, judging whether it is in the best detection interval, if yes, entering step A4, otherwise entering the next step;

[0020] A32, increasing the DDS control word M% in the FPGA circuit through the DDS controller in the FPGA circuit within 100 / M cycles to adjust the output frequency period of the FPGA circuit ; wherein, M is a set value, and , is an integer and is the number of;

[0021] A33, calculating the adjustment time offset ;

[0022]

[0023] wherein, is the period of the output signal S1;

[0024] A34, converting to an angular phase adjustment amount ;

[0025] ; ; wherein, is the period of the frequency division signal S2; N is the frequency division ratio, , is the working frequency range of the phase detection circuit, is the frequency of the output signal S1;

[0026] A35, inputting to the DAC circuit as a control signal to change the phase of the frequency division signal S4 so that is close to the best detection interval;

[0027] A36, return to step A31.

[0028] In this scheme, is the core of the synchronization algorithm, and the role is to convert the time offset into an operable phase angle, directly control the radio frequency circuit through the DAC circuit, so that fast convergence to the best detection interval of the phase detection circuit. And this scheme limits the number of operation cycles, and changes the period by changing the DDS control word in a cycle, which will not change the original period in the subsequent cycle.

[0029] Further, the step of calculating the original phase difference in step A4 includes:

[0030] A41, according to Calculate The corresponding time difference of the frequency division signal , .

[0031] A42, according to Calculate The corresponding time difference of the original signal , Where m is an integer, , mod is the modulo operation.

[0032] A43, according to Get , .

[0033] In this scheme, the time difference conversion mechanism compensates for the distortion introduced by frequency division, ensures that the synchronization result truly reflects the original signal state, and improves the system reliability.

[0034] Further, the phase detection circuit uses AD8302 phase detector, and the best detection interval is-120°~ -60° and 60°~120°. AD8302 phase detector is a mature device, which is cost-effective, easy to integrate, and does not increase the additional design complexity

[0035] Further, the frequency division signal S2 and the frequency division signal S4 have equal frequency division link delay. Eliminate the phase error introduced by the inconsistent frequency division link delay, ensure the fairness of the frequency division signal comparison, and improve the synchronization accuracy.

[0036] The present application discloses a kind of radio frequency synchronization signal circuit and synchronization method, and its beneficial effects are:

[0037] ​The application realizes miniaturization, low cost, wide frequency range and high-precision synchronization by the full integrated circuit and automatic synchronization method of the radio frequency synchronization signal source, realizes port-to-port synchronization output of multi-channel radio frequency signals, eliminates the dependence on external devices and compensates for the phase offset of the cable. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 It is a connection diagram of the radio frequency synchronization signal circuit.

[0039] Figure 2 It is a signal frequency division diagram. DETAILED DESCRIPTION

[0040] The specific embodiments of the application are described below to facilitate those skilled in the art to understand the application, but it should be clear that the application is not limited to the scope of the specific embodiments, and for those skilled in the art, it is obvious that various changes are within the spirit and scope of the application defined and determined by the appended claims, and all applications utilizing the concept of the application are within the scope of protection.

[0041] Embodiment 1

[0042] The embodiment provides a radio frequency synchronization signal circuit for solving the problem that the existing device with full integrated self-calibration function is difficult to meet the miniaturization, low cost and wide frequency range synchronization requirements, which is described in detail as follows.

[0043] Reference Figure 1 A radio frequency synchronization signal circuit includes a radio frequency synchronization signal source, and the radio frequency synchronization signal source includes a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port connected in sequence.

[0044] Specifically, the FPGA circuit is used for built-in synchronization control algorithm to realize real-time adjustment of signal frequency and phase, and processing and feedback control of phase detection data.

[0045] Specifically, the DAC circuit is used for generating an analog voltage according to the control signal output by the FPGA circuit to adjust the output phase of the radio frequency circuit. The cooperation of the FPGA circuit and the DAC circuit can synchronize the high-frequency signals of the radio frequency synchronization signal source and the external radio frequency signal source, realize full integrated self-calibration function, reduce the dependence on external calibration instruments (such as network analyzers or phase-locked loop modules), thereby significantly reduce the system cost, and the FPGA circuit and the DAC circuit have compact structure and are easy to integrate, supporting miniaturization design.

[0046] Specifically, the radio frequency circuit is used for generating a radio frequency signal of a target frequency and outputting through the output port.

[0047] The input ends of the phase detection circuit are connected in parallel with two symmetrically arranged first frequency divider circuits and second frequency divider circuits. By symmetrically arranging the first frequency divider circuits and the second frequency divider circuits, high-frequency radio frequency signals are converted into low-frequency signals that can be detected by the phase detection circuit, so that a wider radio frequency band can be covered, and the frequency adaptation range is expanded.

[0048] The input ends of the first frequency divider circuits and the second frequency divider circuits are electrically connected with the first synchronization ports and the second synchronization ports, respectively. The first synchronization ports are electrically connected with the output ports, and the second synchronization ports are electrically connected with external radio frequency signal sources.

[0049] In order to construct a multi-channel synchronization network, a two-by-two synchronization strategy is adopted, and a plurality of radio frequency synchronization signal sources can be connected in series. Adjacent two radio frequency synchronization signal sources are used as master and slave, respectively. The output port in the master is connected with the second synchronization port of the slave.

[0050] Preferably, in order to expand the use scenario, a cable clamp can be arranged on the connection line between the output port in the master and the second synchronization port of the slave, and on the connection line between the first synchronization port in the slave and the output port of the slave. By the circuit of the radio frequency synchronization signal source, the error caused by the cable difference is calibrated, and the signal synchronization from port to port is realized.

[0051] Preferably, the phase detection circuit adopts an AD8302 phase detector to detect the phase difference of the frequency-divided master and slave signals, and outputs a voltage signal representing the phase difference. After being sampled by an ADC, the voltage signal is transmitted to an FPGA circuit.

[0052] Embodiment 2

[0053] This embodiment is a further limitation based on embodiment 1. The specific improvement point is to provide a synchronization method of a radio frequency synchronization signal circuit. The other parts not mentioned refer to embodiment 1 or prior art.

[0054] The embodiment provides a synchronization method of a radio frequency synchronization signal circuit, comprising the following steps:

[0055] A1、Reference Figure 2 The output signal S1 of the output port of the external radio frequency signal source is generated into a frequency-divided signal S2 through the second synchronization port and the second frequency divider circuit of the radio frequency synchronization signal source. The output signal S3 of the output port of the radio frequency synchronization signal source is generated into a frequency-divided signal S4 through the first synchronization port and the first frequency divider circuit of the radio frequency synchronization signal source. The frequency-divided signal S2 and the frequency-divided signal S4 have frequency-divided link delays of and wherein, The phase error introduced by the inconsistent frequency-divided link delays is eliminated, the fairness of the frequency-divided signal comparison is ensured, and the synchronization accuracy is improved.

[0056] A2, receiving the voltage quantization value output by the phase detection circuit in real time through the FPGA circuit, and calculating the phase difference between the detection frequency division signal S2 and the frequency division signal S4 .

[0057] A3, adjusting the output frequency of the FPGA circuit and the DAC circuit to the optimal detection range of the phase detection circuit .

[0058] Step A3 includes:

[0059] A31, judging whether it is in the optimal detection range, if yes, entering step A4, otherwise entering the next step.

[0060] A32, increasing the DDS control word M% in the FPGA circuit through the DDS controller in the FPGA circuit within 100 / M cycles to adjust the output frequency period of the FPGA circuit ; wherein, M is a set value, and , is an integer. Preferably, the range of M is 1 / 1000~1 / 10000. By limiting the number of operation cycles, the change of the DDS control word only occurs within cycles, and the adjustment is immediately stopped beyond this range, ensuring the stability of .

[0061] A33, calculating the adjustment time offset ;

[0062]

[0063] wherein, is the period of the output signal S1.

[0064] A34, converting to the angular phase adjustment amount ; ; ; wherein, is the period of the frequency division signal S2; N is the frequency division ratio, , is the working frequency range of the phase detection circuit, is the frequency of the output signal S1. is the execution core of the synchronization algorithm, which is used to convert the time offset to the operable phase angle, and directly control the radio frequency circuit through the DAC circuit, so that quickly converges to the optimal detection range of the phase detection circuit.

[0065] A35, converting ​As a control signal input to the DAC circuit, the phase of the frequency division signal S4 is changed to make Close to the best detection interval.

[0066] A36, return to step A31.

[0067] A4, calculate the original phase difference between the output signal S1 and the output signal S3 through the FPGA circuit and the DAC circuit , realize the phase synchronization of the output signal S1 and the output signal S3.

[0068] The step of calculating the original phase difference in step A4 Comprise:

[0069] A41, according to Calculate The corresponding frequency division signal time difference , .

[0070] A42, according to Calculate The corresponding original signal time difference , , wherein m is an integer, , mod is the modulus operation.

[0071] A43, according to Get calculation , . At the same time, through the time difference conversion mechanism, the distortion introduced by frequency division is compensated, and the synchronization result is ensured to truly reflect the original signal state, and the system reliability is improved.

[0072] In summary, the scheme realizes the indirect accurate synchronization of high-frequency radio frequency signals through frequency division and phase difference adjustment, overcomes the limitations of directly measuring high-frequency signals, expands the frequency range, and realizes the port-to-port synchronization output of multi-channel radio frequency signals between the FPGA circuit and the DAC circuit. Eliminate the dependence on external equipment and compensate for cable phase offset, while realizing the automatic synchronization process, significantly reducing the operation cost and time cost.

[0073] Although the specific embodiments of the application are described in detail with reference to the accompanying drawings, it should not be understood as limiting the protection scope of the patent. Various modifications and changes made by those skilled in the art within the scope described in the claims are still within the protection scope of the patent.

Claims

1. A radio frequency synchronization signal circuit, characterized in that: The radio frequency synchronization signal source includes a phase detection circuit, an FPGA circuit, a DAC circuit, a radio frequency circuit and an output port connected in sequence; The input end of the phase detection circuit is respectively connected in parallel with two symmetrically arranged first frequency divider circuits and second frequency divider circuits, the input ends of the first frequency divider circuit and the second frequency divider circuit are respectively electrically connected to a first synchronization port and a second synchronization port, the first synchronization port is electrically connected to the output port, and the second synchronization port is electrically connected to an external RF signal source; The plurality of radio frequency synchronization signal sources are sequentially connected in series, wherein two adjacent radio frequency synchronization signal sources serve as a master and a slave respectively, and the output port of the master is signal-connected to the second synchronization port of the slave.

2. The radio frequency synchronization signal circuit according to claim 1, wherein: A cable clamp is provided on a connecting line between the output port of the host and the second synchronization port of the slave and a connecting line between the first synchronization port of the slave and the output port of the slave.

3. The synchronization method of the radio frequency synchronization signal circuit according to claim 1, characterized in that: The following steps are involved: A1, passing the output signal S1 of the output port of the external RF signal source through the second synchronization port of the RF synchronization signal source and the second frequency divider circuit to generate a frequency-divided signal S2; The output signal S3 of the output port of the radio frequency synchronization signal source is passed through the first synchronization port of the radio frequency synchronization signal source and the first frequency divider circuit to generate a frequency-divided signal S4; A2. Receive the voltage quantization value output by the phase detection circuit in real time through the FPGA circuit, and calculate the phase difference between the detection frequency division signal S2 and the frequency division signal S4. ; A3, through FPGA circuit and DAC circuit Adjust to the optimal detection range of the phase detection circuit; A4. Calculate the original phase difference between the output signal S1 and the output signal S3 through the FPGA circuit and the DAC circuit. , achieving phase synchronization of the output signal S1 and the output signal S3.

4. The synchronization method of the radio frequency synchronization signal circuit according to claim 3, wherein: Step A3 includes: A31. Judgment Is it in the optimal detection range? If so, go to step A4, otherwise go to the next step; A32. In 100 / M cycles, the DDS control word M% is increased by the DDS controller in the FPGA circuit to adjust the output frequency cycle of the FPGA circuit. ; Where M is the set value, and , is an integer and the number of A33. Calculate and adjust time offset ; in, is the period of the output signal S1; A34, will Convert to angular phase adjustment ; in, is the period of the frequency division signal S2; N is the frequency division ratio, , is the operating frequency range of the phase detection circuit, is the frequency of the output signal S1; A35, will As a control signal input to the DAC circuit, the phase of the frequency division signal S4 is changed to make Close to the optimal detection interval; A36. Return to step A31.

5. The synchronization method of the radio frequency synchronization signal circuit according to claim 4, characterized in that: Calculate the original phase difference in step A4 The steps include: A41, according to calculate The corresponding frequency division signal time difference , ; A42, according to calculate The corresponding original signal time difference , , where m is an integer, ;mod is the modulo operation; A43, according to Get calculated , .

6. The synchronization method of the radio frequency synchronization signal circuit according to claim 4, characterized in that: The phase detection circuit uses the AD8302 phase detector, and the optimal detection range is -120°~-60° and 60°~120°.

7. The synchronization method of the radio frequency synchronization signal circuit according to claim 4, characterized in that: The frequency division link delays of the frequency division signal S2 and the frequency division signal S4 are equal.

Images