Combination of balanced amplifiers for adaptation to load impedance variations

Abstract

The adaptability of radio frequency power amplifiers (PA) to varying load impedance mismatch is improved through a topology in which a plurality of balanced PAs are combined with delay lines to disperse phase shifts over the VSWR circumference, i.e. Over the entire range of phase values. Balancing PA circuits are arranged in parallel, the balancing PA circuits comprising two parallel PAs operating in an orthogonal fashion, the outputs of which are combined by a quadrature hybrid coupler (QHC). A delay line is interposed between the output of the partial or all parallel balancing PAs and the load. The phase shift introduced by the delay line is combined with the inherent 90-degree phase separation of the PA, and the PA is distributed on the VSWR circumference on the Smith chart. Therefore, the PAs compensate each other, peak outputs are located at different impedance phases, and consistent overall radio frequency signals are generated in the whole impedance mismatch value range. The scheme can be expanded to more than two balance amplifiers, and more PAs are allowed to be connected in parallel. In certain aspects, the termination impedance at the isolated port of the QHC may be controlled to encompass where the circuitry requires reconfigurability.

Description

Technical Field

[0001] The present disclosure relates generally to power amplifiers for antenna arrays and, in particular, to mitigating load impedance variations by combining a balanced amplifier's phase shift with a delay line to distribute the impedance phase across the amplifier. Background Art

[0002] Wireless communication networks are ubiquitous in many parts of the world. These networks continue to grow in capacity and complexity. To accommodate more users, different types of devices, and diverse use cases, the technical standards governing the operation of wireless communication networks continue to evolve. The fourth generation (4G) network standard has already been deployed, the fifth generation (5G) is in development and early deployment, and the sixth generation (6G) is in design. With each generation, technological advances have increased the capacity and spectral efficiency of wireless communication systems. For example, 5G added new frequency bands and implemented beamforming. This trend is expected to continue with 6G by utilizing additional frequency bands and applying more advanced beamforming.

[0003] 5G adds a second frequency range, FR2. This provides a large amount of newly available spectrum in the 24.25-52.6 GHz range. In this frequency range, beamforming is used to improve both coverage and capacity. Because the wavelength is small at these high frequencies, antenna arrays with hundreds or even thousands of antenna elements are feasible.

[0004] An Advanced Antenna System (AAS) is a combination of an AAS radio and AAS features. An AAS radio refers to a large antenna array of individual antenna elements, along with circuitry such as a phase-locked loop (PLL) that provides phase-controlled radio frequency (RF) signals, and RF drivers, including power amplifiers (PAs). AAS features refer to the multi-antenna features implemented in an AAS radio, such as beamforming and multiple-input, multiple-output (MIMO) technology, including spatial diversity and spatial multiplexing.

[0005] Spatial diversity refers to transmitting the same signal over different propagation paths (e.g., different transmit / receive antennas), which increases robustness against fading, co-channel interference, and other harmful effects of RF signal transmission. Spatial multiplexing also uses multiple transmit and receive antennas and refers to transmitting different portions of the data over different propagation paths using space-time coding to increase data rates.

[0006] Beamforming refers to the use of antennas with enhanced and controllable directivity so that the RF transmission is narrow and "aimed" in a specific direction. This is enabled by transmitting or receiving signals with controllable relative phase and gain in an antenna element (or subarray of antenna elements). The relative phase of the transmit signal sent to each antenna element is controlled to create constructive or destructive interference, thereby amplifying the signal in certain directions and attenuating it in other directions, and thereby controlling the direction in which the beam is transmitted. Similar phase manipulation of the signals from the antenna elements (or subarrays) in the receive antenna can also result in beamforming to increase the sensitivity of the antenna array in the received signal. In addition, multiple orthogonal beams can also be formed and pointed in different directions, thus addressing multiple wireless devices, also known as user equipment (UE), simultaneously.

[0007] To form robust beams, antenna elements are typically placed close together. For example, a spacing of λ / 2 (where λ is the RF wavelength) is commonly used to form arbitrary beams without folding. However, close antenna spacing results in high electromagnetic coupling between antennas and, in addition, in signal leakage between antennas. Beam steering, combined with antenna coupling, causes the impedance seen by each power amplifier (PA) driving an antenna element (or subarray) to deviate from the designed impedance.

[0008] PAs are designed assuming a nominal load impedance for optimal output power, linearity, and efficiency. The PA amplifies and transmits electrical energy to the antenna elements / subarrays, which convert the energy into electromagnetic signals. However, if the load impedance seen by the PA deviates from its designed (optimal) value, an impedance mismatch exists, which degrades PA performance.

[0009] To steer the beam in the desired direction, a phase shift is required between the signals sent to different antenna elements (or subarrays). In addition to the phase shift, the same signal is present at all antenna elements, and the electromagnetic energy of this signal leaks between them. This is seen by the PA as a mismatch from the optimal (matched) impedance, which does not exist when no phase shift is introduced to steer the beam. The design impedance seen by the PA is called the impedance in the boresight direction (i.e., the RF signal is radiated perpendicular to the plane of the antenna elements). When there is coupling between the antenna elements (due to spacing), and the same signal is transmitted on all antennas, but with different phases, this is experienced by the PA as a load impedance variation and mismatch, even though it stems from antenna leakage and delay introduced by the phase shifters (i.e., the mismatch generally increases with increasing beam angle due to the increasing relative phase shift between the antennas). Because the impedance mismatch causes the RF signal to partially reflect from the antenna elements (or subarrays) back to the PA, it generates standing waves along the transmission line connecting the two. In the art, standing waves are quantified as the voltage standing wave ratio (VSWR) of the antenna impedance, which is calculated from the reflection coefficient or return loss (also known as the S11 parameter). Assuming that the antenna and PA are impedance-matched for signals transmitted in the boresight direction, the active impedance loading or VSWR generally grows higher with increasing beam angle because the relative phase shift between antenna elements (or subarrays) increases.

[0010] At low frequencies, isolators can be inserted between the PA and its antenna elements / subarrays to ensure that the VSWR is not transmitted to the PA. In high-frequency AAS, there is no space to install isolators at each PA output.

[0011] PAs are typically impedance-matched in the boresight direction to optimize efficiency. Furthermore, the PA is operated near its compression point to maximize efficiency. As the system performs beamforming, the boresight impedance match degrades, effectively presenting a time-varying load to the PA. This time-varying impedance mismatch, expressed as VSWR, degrades the PA's output power, efficiency, and linearity, which in turn adversely affects the phased array beam and its directional control.

[0012] The background section of this document is provided to place various aspects of the present disclosure in technical and operational context to help those skilled in the art understand its scope and applicability. The methods described in the background section may be adopted, but are not necessarily methods that have been previously conceived or adopted. Unless expressly indicated as such, statements herein are not to be admitted to be prior art merely by virtue of their inclusion in the background section. Summary of the Invention

[0013] The following is a brief summary of the present disclosure to provide a basic understanding for those skilled in the art. This summary is not an exhaustive overview of the present disclosure and is not intended to identify key / important elements of various aspects of the present disclosure or to define the scope of the present disclosure. The sole purpose of this summary is to present some of the concepts disclosed herein in a simplified form as a prelude to the more detailed description presented later.

[0014] According to one or more aspects of the present disclosure described and claimed herein, the adaptability of an RF PA to varying load impedance mismatches can be improved by combining a parallel balanced PA topology with a delay line to spread the phase shift of the component PAs' load impedances across a VSWR circle (i.e., over a full range of phase values). As described herein, a balanced PA is a circuit in which two parallel PAs operate in quadrature (i.e., with a 90° phase shift between them). The balanced PA also includes a quadrature hybrid coupler (QHC) as a signal combiner at the PA outputs. The QHC combines the orthogonal RF signal groups from the PAs into a single output signal that drives an antenna element or subarray of antenna elements. In the event of an impedance mismatch, some RF signal energy may be reflected back to the PA; in this case, the QHC acts as a quadrature splitter, applying a 90° phase shift to the reflected signal—effectively placing the PAs' load impedances at opposite locations on the VSWR circle, as plotted on a Smith chart. To further spread the PAs' load impedances in phase, delay lines are selectively inserted between the outputs of some or all of the parallel balanced PAs and the loads. In the various circuit topologies disclosed herein, the distribution of losses and the characteristic impedance presented by the load can be controlled. The use of delay lines offers the advantage of reducing the number of passive components compared to prior art line-averaging schemes. This scheme can be extended to more than two balanced amplifiers, allowing for the parallel connection of more PAs, for example, for higher-power operation. Another aspect includes the additional implementation of termination impedances at the isolated ports of the QHC, which addresses other situations where circuit reconfigurability is required.

[0015] One aspect relates to an amplifier circuit configured to drive an antenna element or a subarray of antenna elements using a radio frequency (RF) signal. The amplifier circuit includes at least two balanced power amplifiers connected in parallel. Each balanced power amplifier includes two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler that connects the outputs of the two power amplifiers into a single RF signal. The amplifier circuit also includes a delay line inserted between the output of at least one balanced power amplifier and the antenna element or subarray. The delay line applies a phase shift to the connected balanced power amplifier relative to at least one other balanced power amplifier.

[0016] Another aspect relates to a method for driving an antenna element or a subarray of antenna elements using an RF signal. The RF signal is amplified in each of at least two balanced power amplifiers connected in parallel. Each balanced power amplifier includes two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler that connects the outputs of the two power amplifiers into a single RF signal. A phase shift is applied to the output of at least one balanced amplifier. The outputs of the at least two balanced power amplifiers and the phase-shifted outputs are combined. The combined RF signal is used to drive the antenna element or subarray of antenna elements.

[0017] Yet another aspect relates to a wireless device operating in a wireless communication network. The wireless device includes: an array of antenna elements; communication circuitry connected to the antenna array and configured to wirelessly communicate with one or more other network nodes; and processing circuitry operably connected to the communication circuitry. The processing circuitry is configured to implement beamforming on the antenna array. The communication circuitry includes a plurality of amplifier circuits. Each amplifier circuit is configured to drive an antenna element or a subarray of antenna elements. Each amplifier circuit includes at least two balanced power amplifiers connected in parallel. Each balanced power amplifier includes two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler that connects the outputs of the two power amplifiers into a single RF signal. Each amplifier circuit also includes a delay line inserted between the output of at least one balanced power amplifier and the antenna element or subarray. The delay line applies a phase shift to the connected balanced power amplifier relative to at least one other balanced power amplifier.

[0018] Yet another aspect relates to a base station operating in a wireless communication network. The base station includes: an array of antenna elements; communication circuitry connected to the antenna array and configured to wirelessly communicate with one or more other network nodes; and processing circuitry operably connected to the communication circuitry. The processing circuitry is configured to implement beamforming on the antenna array. The communication circuitry includes a plurality of amplifier circuits. Each amplifier circuit is configured to drive an antenna element or a subarray of antenna elements. Each amplifier circuit includes at least two balanced power amplifiers connected in parallel. Each balanced power amplifier includes two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler that connects the outputs of the two power amplifiers into a single RF signal. Each amplifier circuit also includes a delay line inserted between the output of at least one balanced power amplifier and the antenna element or subarray. The delay line applies a phase shift to the connected balanced power amplifier relative to at least one other balanced power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various aspects of the present disclosure are shown. However, the present disclosure should not be construed as being limited to the aspects described herein. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the text, like numbers indicate like elements.

[0020] FIG1 depicts an exemplary array of 64 antenna elements connected into 32 2x1 sub-arrays.

[0021] FIG2 is a hardware block diagram of a radio frequency integrated circuit (RFIC) transceiver connected to 32 sub-arrays of antenna elements.

[0022] FIG. 3A is a schematic diagram of a quadrature hybrid coupler.

[0023] FIG3B is a Smith chart of a 40 GHz signal applied to a QHC having a characteristic impedance of 50 Ω, where the load at the output point is set to 17 Ω.

[0024] 3C is a graph of VSWR and real and imaginary impedance at the ports of the QHC as the impedance phase traverses a complete VSWR circle.

[0025] Figure 4 is a schematic diagram of a balanced PA output stage.

[0026] FIG5A is a block diagram of a fully balanced PA.

[0027] FIG. 5B is a graph of the output power of each PA and the balanced PA in FIG. 5A over the entire VSWR circle.

[0028] FIG6 is a schematic diagram of two balanced PAs connected in parallel.

[0029] 7 is a schematic diagram of two balanced PAs connected in parallel with their outputs connected via a Wilkinson power combiner.

[0030] 8A is a block diagram illustrating line averaging by connecting antenna elements in a column of an array to the RFIC of FIG. 2 via traces of varying lengths.

[0031] 8B is a block diagram showing a PA with different length traces connected to the output, represented by different length transmission lines, and corresponding phase offsets at the input.

[0032] FIG. 8C is a Smith chart showing that impedance is evenly distributed on the circumference of the VWSR.

[0033] 9A is a block diagram illustrating line averaging with inverse delays at the input and output of a parallel PA.

[0034] FIG9B shows an equivalent circuit of the output combiner in FIG9A .

[0035] FIG. 9C is a Smith chart showing that impedance is evenly distributed on the circumference of the VSWR circle.

[0036] FIG10 is a block diagram showing the use of QHCs instead of impedance inverters to combine outputs and load modulate the main amplifiers via parallel auxiliary amplifiers.

[0037] Figure 11A Figure 1 is a schematic diagram of two balanced PAs, each built from QHCs, with a delay line at the output of one balanced PA.

[0038] Figure 11B is a delay line with two outputs Figure 11A Schematic diagram of a balanced PA.

[0039] Figure 11C It has a delay line and combines the outputs via a Wilkinson power combiner. Figure 11A Schematic diagram of a balanced PA.

[0040] Figure 11D It has two delay lines and combines the outputs via a Wilkinson power combiner. Figure 11B Schematic diagram of a balanced PA.

[0041] Figure 12 is shown on the VSWR circle Figure 11C Smith chart of the ports of a balanced PA.

[0042] Figure 13A The output load impedance mismatch traverses the complete VSWR circle. Figure 11C A diagram of the VSWR at the ports of a balanced PA.

[0043] Figure 13B The output load impedance mismatch traverses the complete VSWR circle. Figure 11C A plot of the real and imaginary parts of the impedance at the ports of a balanced PA.

[0044] Figure 14A is a schematic diagram of four balanced PAs connected in parallel with delay lines at the outputs of three of them.

[0045] Figure 14B yes Figure 14A Schematic diagram of four balanced PAs and delay lines, with their outputs connected via Wilkinson power combiners.

[0046] Figure 15A yes Figure 14ASchematic diagram of four balanced PAs and delay lines. The isolated ends of the QHCs are connected together and terminated via resistors.

[0047] Figure 15B yes Figure 11A Schematic diagram of two balanced PAs and a delay line. The isolated ends of the QHC are connected together and terminated via a configurable or adjustable impedance element.

[0048] Figure 16 is the block diagram and schematic diagram of the PA used for simulation.

[0049] Figure 17A is a graph showing the variation in output power of the circuit of FIG. 6 over the entire VSWR circle.

[0050] Figure 17B 7 is a graph showing the variation in output power of the circuit of FIG. 7 over the entire VSWR circle.

[0051] Figure 17C It is on the entire VSWR circle Figure 11C Graph showing the output power variation of the circuit.

[0052] Figure 18 is a flow chart of a method of driving an antenna element or a subarray of antenna elements using an RF signal.

[0053] Figure 19 It is a hardware block diagram of a wireless device in a wireless communication network.

[0054] Figure 20 It is a hardware block diagram of a base station in a wireless communication network. DETAILED DESCRIPTION

[0055] For the purpose of simplicity and illustration, the present disclosure is described primarily with reference to its exemplary aspects. In the following description, numerous specific details will be set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to those skilled in the art that the present disclosure may be practiced without limitation to these specific details. In this specification, well-known methods and structures are not described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0056] Figure 1 depicts an example antenna array according to aspects disclosed herein. In this example, the array consists of 8x8 dual-polarized antenna elements. These antenna elements are interconnected in pairs to form 2x1 subarrays, and thereby reduce the number of active radio chains required to connect to the antenna and apply beamforming. The subarrays are numbered SA0 to SA31 (from left to right and from top to bottom). In general, the antenna elements of the array can be grouped into any number of subarrays, each subarray including any number of individual antenna elements. The subarrays in an antenna array do not have to be identical - that is, some antenna elements can be grouped into one or more mxn subarrays, and other antenna elements can be grouped into one or more ixj subarrays, where m≠i and / or n≠j. As used herein, a subarray can include from one antenna element to all antenna elements in the antenna array.

[0057] Figure 2 depicts relevant portions of a radio frequency integrated circuit (RFIC) according to one aspect. The RFIC has eight bidirectional IQ baseband ports, with an internal port expansion of four, resulting in a total of 32 antenna connections. Each antenna branch (also known as an RF tile) has its own PLL to enable beamforming by controlling the relative phase between antenna elements or subarrays. In transmit mode, the IQ baseband signal is divided into four branches, upconverted to RF using an IQ modulator, and amplified by a PA. An antenna switch connects the transmitter or receiver branch to the antenna element subarray. As depicted in Figure 2, the tile is connected to the antenna element subarray in column 1 of the antenna system depicted in Figure 1 (i.e., subarrays SA0, SA8, SA16, and SA24). In receive mode, each antenna element subarray signal is amplified by an LNA, downconverted to baseband, and added to the other three branches that share the IQ interface. The receiver can also be reused as a transmit monitor receiver (TOR) to sense the PA output signal for closed-loop DPD operation (alternatively, the RFIC can contain a separate TOR circuit).

[0058] The transceiver of Figure 2 can be used with the exemplary antenna array of Figure 1. Here, the four RF units sharing a baseband IQ interface are each connected to an antenna element subarray in a column of the antenna array. For example, the antenna connections depicted in Figure 2 can be connected to the antenna element subarrays (SA0, SA8, SA16, and SA24) in column 1. As described above, when coupled to an antenna or subarray such as that shown in Figure 2, the time-varying impedance mismatch due to beamforming using the coupled antenna array elements can affect the PA's output power, efficiency, and linearity.

[0059] One way to reduce the sensitivity of the PA to impedance mismatch is to implement a balanced PA circuit, for example, using a quadrature hybrid coupler (QHC). The QHC is a special case of the general class of directional couplers, with a coupling degree of 3 dB. FIG3A depicts an implementation of a QHC using a transmission line or microstrip line. The transmission line has an electrical length λ / 4, where λ is the fundamental frequency. In other aspects, the QHC can be constructed from lumped reactive components (such as inductors and capacitors). Such an implementation may be attractive for integration because such a QHC can be fabricated in a smaller area than a transmission line or microstrip implementation. For example, Robert C. Frye et al. present a 2GH implemented in CMOS technology in a paper published in the IEEE 2002 Custom Integrated Circuits Conference, page 287. z A CMOS implementation of a QHC suitable for integration on a high-frequency RFIC is described in Quadrature Hybrid Circuits, the disclosure of which is incorporated herein by reference in its entirety.

[0060] The ideal QHC is a symmetrical, lossless, passive four-port network that imposes a 90° phase shift. Because the QHC is symmetrical, it can split an input signal into two output signals (with a 90° phase shift) or combine two input signals (with a 90° phase shift) into one output signal.

[0061] Figure 3B shows a Smith chart of a 40 GHz signal applied to a QHC with a 50 Ω characteristic impedance, with the output load set to 17 Ω. This impedance mismatch produces reflections, quantified as a VSWR of 3. At the input ports (ports 1 and 2 in Figure 3B), the VSWR is identical, but the QHC ensures that the impedance of one input is 90° phase-shifted from the other, representing a semicircle on the Smith chart.

[0062] While Figure 3B shows the PA's load impedance for a specific load value, Figure 3C plots the impedance when the load traverses the entire circle of VSWR = 3. As shown in the upper graph, the VSWR at the PA port is roughly the same. The middle graph (real part) and the lower graph (imaginary part) show that the PA's load impedance at the input is shifted in phase by 90°.

[0063] As disclosed in the Frye paper cited above, one known application of QHCs is to implement balanced PAs that exhibit reduced sensitivity to impedance mismatches caused by loads. This application is further described in the 2006 IEEE paper "Balanced CDMA2000 SiGe HBT Load-Insensitive Power Amplifier" by Guiseppe Berretta et al., the disclosure of which is incorporated herein by reference in its entirety. Figures 5A and 5B, reproduced from Berretta's paper, respectively depict a schematic diagram and output power diagram of a balanced amplifier implemented using two QHCs. As depicted in Figure 5A, an RF signal is input to port 1 of a first QHC configured as a splitter, with a standard 50Ω impedance connected to ground at port 4. The QHC outputs signals at both output ports 2 and 3, with a 90° phase shift. These signals are amplified by a PA, which outputs the amplified quadrature RF signals at input ports 2 and 3 to a second QHC configured as a combiner via impedance matching circuitry. The combined RF signal is output at port 1, with a standard 50Ω impedance connected to ground at port 4.

[0064] Figure 5B shows the output power for each PA as the load impedance varies across the entire VSWR = 4 circle (i.e., 0-360°). Due to quadrature operation, the two PAs compensate for each other, and the output power of the balanced PA circuit (top curve in Figure 5B) is nearly flat. Therefore, the balanced PA architecture exhibits high insensitivity to impedance mismatches caused by coupling between antenna array elements, such as in beamforming operation.

[0065] Figure 6 shows the output side of a balanced PA circuit, with the characteristic impedance Z0 and phase indicated. The inputs to the PAs are not explicitly depicted; those skilled in the art will understand that they may include a QHC acting as a splitter, as depicted in Figure 5A, or that quadrature RF signals input to the PAs may be generated in other ways, such as by mixing with quadrature LO signals. Aspects of the present disclosure relate to combining the outputs of the PAs, and therefore the PA input circuitry is not described in detail. To be clear, as used herein, the term "balanced power amplifier" or "balanced PA" refers to two PAs operating in quadrature (i.e., with a 90° phase shift between them) whose outputs are combined by a QHC. A balanced PA may have another QHC at its input, or quadrature operation of the PAs may be generated in other ways.

[0066] Balanced PA circuits can operate in parallel. In this case, the outputs of the balanced PAs can be combined in a variety of ways. For example, Figure 6 shows the output ports of corresponding QHCs connected together. If the amplifiers have the same characteristic impedance, Z0, then the load impedance has a nominal value of Z0 / 2.

[0067] The output power can be increased by using additional power combiners (e.g., a Wilkinson combiner as depicted in Figure 7). This doubles the impedance, which has an impact on the size of the PA. Furthermore, the additional combiners incur additional losses and require additional area for implementation. The number of combiners increases as the number of balanced PAs that need to be combined increases.

[0068] Currently, prior art solutions for dynamic antenna impedance mismatching are directed to a single PA or include methods such as digital predistortion (DPD), Doherty PA architecture, line averaging, or load modulation. DPD and Doherty structures are well known.

[0069] Line averaging refers to the use of delay lines to distribute the impedance of multiple PAs over a range of, for example, 180°, which can be achieved by deliberately routing conductors (such as PCB traces) to have different physical (and therefore electrical) lengths. U.S. patent application serial number 63 / 271,910 (assigned to the assignee of the present disclosure and incorporated herein by reference in its entirety) describes this technique. Figure 8A shows unequal trace lengths for traces connecting pairs of antenna elements in a column of an antenna element array to the outputs of corresponding PAs on an upper circuit. These traces have lengths L, L-λ / 8, L-λ / 4, and L-3λ / 8. Figure 8B shows that the corresponding delay line pairs apply offset phase shifts of 0°, 45°, 90°, and 135° to the RF signals applied to the PAs. When the antenna elements are matched, all PAs see the same load impedance and operate under nominal conditions. In the case of impedance mismatch (e.g., due to antenna element coupling during beamforming operations), each PA will receive a different phase due to the inconsistent delay lines between the PA and the antenna elements; therefore, a different load impedance is presented to each PA. As shown in Figure 8C, the impedance is evenly distributed around the VWSR circle in the Smith chart.

[0070] A similar technique can be implemented for each antenna using a delay line between the PA and the power combiner. This is described in A. Berthier et al., Active VSWR Robustness Comparison for Different Phase Combining Topologies, published in the 19th IEEE International Conference on New Circuits and Systems (NEWCAS) in 2021, pages 1-4, the disclosure of which is incorporated herein by reference in its entirety. Figure 9A shows a circuit architecture with a divider that splits the input signal, which is routed to an array of PAs through different delay lines. A set of inverse delay lines at the output realigns the amplified signals, which are then combined and applied to the antennas. Figure 9B is an equivalent circuit diagram of the output combiner. Figure 9C shows the amplifier impedances distributed on the VSWR=1.33 circle. On the VSWR=5 circle, the gain difference between the PAs is reduced by 1.8dB compared to the reference design.

[0071] A form of load modulation is described in U.S. Patent No. 6,922,102 to Myer, the disclosure of which is incorporated herein by reference in its entirety. The reference describes the use of auxiliary amplifiers (104, 106, 108) to modulate the load of the main amplifier (102), similar to a Doherty structure, but without the need for a λ / 4 transmission line for impedance inversion, which limits integration and operation at lower frequencies. Instead, the reference uses a QHC to impose a phase shift on the auxiliary amplifier path. Referring to FIG10 (reproducing FIG9 of the '102 patent), as described in column 7, lines 12 to 36, the dummy loads (135, 138, 144) of the QHCs (132, 134, 142) are tuned lines to present an electrical short to the coupler and avoid power splitting when one of the auxiliary amplifiers is turned off. This arrangement provides load modulation for high PAPR signals, but does not provide a line averaging effect.

[0072] Figure 11A An aspect of the present disclosure is shown in which two balanced PAs are combined with at least one delay line. A first balanced amplifier 10, comprising PA1 and PA2, is designed with a characteristic impedance Z0. Amplifiers PA1 and PA2 operate in quadrature, with a relative phase shift of 90°. This balanced amplifier 10 is replicated by a second balanced amplifier 12, comprising PA3 and PA4, resulting in a total of four PAs. A QHC 14, connected to the outputs of PA1 and PA2 in the first balanced PA 10 as a signal combiner, combines the outputs with a -90° phase shift (i.e., a semicircle on a Smith chart). The QHC 16 in the second balanced PA 12 similarly combines the signals with a 90° phase shift between PA3 and PA4. In this regard, the second balanced PA 12 additionally has a delay line 18 at its output, which introduces a further -45° phase shift to PA3 and PA4 relative to PA1 and PA2. As indicated at the outputs of the PAs, there is a -45° phase shift between all four PAs (0° for PA1, -45° for PA3, -90° for PA2, and -135° for PA4). Note that the delay line 18 can additionally introduce a +45° phase shift, which will also introduce a 45° incremental phase shift between the two balanced PAs 10, 12. In this case, the phase shift at the PAs would be -90° for PA2, -45° for PA4, 0° for PA1, and 45° for PA3. Those skilled in the art will understand that it is the incremental phase shift between the PAs that achieves line averaging (due to both the inherent 90° phase shift of the delay line and the QHC), and whether the phase shift introduced by the delay line 18 is positive or negative is merely an implementation detail. The output currents of the two balanced PAs 10, 12 are combined at the output of the delay line 18 (i.e., at the input of the antenna elements of the subarray), so the load impedance has a nominal value of Z0 / 2.

[0073] Figure 11B A different aspect of the present disclosure is shown where two balanced PAs 10, 12 are combined, each with a delay line 20, 22 added to its respective output. One delay line 20 introduces a -22.5° phase shift to the balanced PA 10, and the second delay line 22 introduces a 22.5° phase shift to the balanced PA 12. Thus, here too, there is a 45° phase shift between all four PAs (22.5° for PA3, -22.5° for PA1, -67.5° for PA4, and -112.5° for PA2), as indicated at the outputs of the PAs. Figure 11A , in which the losses introduced by the delay lines 20, 22 are distributed between the two balanced PAs 10, 12. Those skilled in the art will readily recognize that other values ​​for the delay lines may be used for two balanced PAs, as long as the incremental phase shift is + / - 45°.

[0074] Figure 11C Another aspect of the present disclosure is shown, wherein two balanced PAs 10, 12 are as in the first aspect ( Figure 11A ) but with the addition of a power combiner 24, such as a Wilkinson combiner, to combine the outputs of the PAs 10, 12 before the load. The impedance phase is as described with respect to Figure 11A The aspect is distributed as depicted, but in this aspect the characteristic impedance Z0 is preserved.

[0075] Figure 11D Yet another aspect of the present disclosure is shown, wherein two balanced PAs 10, 12 are as in the second aspect ( Figure 11B ) but with a power combiner 24 (e.g. a Wilkinson combiner). The impedance phase is as Figure 11B 1 and the losses of the delay lines 20, 22 are split between the combined PAs 10, 12; however, in this aspect the characteristic impedance Z0 is preserved.

[0076] choose Figure 11C The aspects depicted in [1] were used for simulation. The PA and load were set to a nominal characteristic impedance of 50Ω. The model was simulated using the load impedance angle traversing the entire VSWR=3 circle. PA1 to PA4 were modeled by ports 1 to 4, respectively, and the load was modeled by port 5.

[0077] Figure 12 : is a Smith chart depicting the distribution of the PA load corresponding to a simulation point where the load impedance is equal to 17 Ω. The load impedance of the PA is evenly distributed on the VSWR circumference.

[0078] although Figure 12shows the load impedance of the PA for one particular load value, while Figure 13 plots the impedance as the load traverses the entire VSWR=3 circle. In particular, Figure 13A The VSWR is plotted, and Figure 13B The real and imaginary parts of the impedance at the antenna (port 5) and the PA plane (ports 1 to 4) are plotted as the impedance traverses the entire VSWR circle. As shown in these figures, the PA's load impedance is evenly distributed on the Smith chart as the load impedance varies over the entire range, and the PA's load impedance at the input is shifted 90° in phase.

[0079] Figure 11A The aspects described in -D are extensible. Figure 14A A combined balanced PA according to one aspect of the present invention is depicted. The combined balanced PA includes four balanced PAs 30, 32, 34, and 36, each of which includes two PAs and QHCs 38, 40, 42, and 44, respectively. Each of the balanced PAs 32, 34, and 36 has a delay line 46, 48, and 50 at its respective output, applying a further impedance shift of -22.5° increments. This, combined with the inherent 90° phase shift in the balanced PAs due to the quadrature operation of the PAs, results in each PA being matched to a different impedance phase, shifted by -22.5°, as shown below:

[0080]

[0081] As described above, delay lines 46, 48, and 50 can alternately apply a continuous phase difference of +22.5° while still achieving line balance to mitigate load impedance variations and spread the phase shift of the PA's load impedance across the VSWR circle. The currents of the four balanced PAs 30-36 are combined at the output, resulting in a load impedance with a nominal value of Z0 / 4.

[0082] Typically, the amount of phase shift applied between balanced PAs can be expressed as 90 / N, where N is the number of balanced PAs. Figure 11A As depicted in FIG. 1-D, N=2, and 90 / 2=45. A 45° phase shift can be implemented as: zero delay on one balanced PA 10, and a + / - 45° delay line on the other balanced PA 12 ( Figure 11A 、 11C ), implemented as two delay lines of -22.5° and +22.5°, or any other combination with a total incremental phase shift of + / -45°. Figure 14A 、 14BAs depicted in FIG, N=4, and 90 / 4=22.5. A phase increment of 22.5° can be implemented as: zero delay on one balanced PA 30, and -22.5°, -45°, and -67.5° on the other balanced PAs 32, 34, 36, as shown in FIG. Figure 14A and 14B As shown (or, as described above, 22.5°, 45°, and 67.5°). Alternatively, each balanced PA 30, 32, 34, 36 can be connected to a delay line that applies a phase shift of 45°, 22.5°, -22.5°, and -45°, respectively, or any other combination that produces a 22.5° increment between the balanced PAs.

[0083] Figure 14B An aspect of the present disclosure is depicted in which Wilkinson combiners 52, 54, 56 are used to combine the outputs of balanced PAs 30-36. Figure 14A The delay lines 46, 48, and 50 are identical in aspect to each other, and each of the balanced PAs 30-36 has a 90° phase shift, so the impedance phase shifts are the same as those listed above. However, in this aspect, the Wilkinson combiners 52-56 maintain the characteristic impedance of the system at Z0. Those skilled in the art will readily appreciate that the number of balanced PAs that can be combined in this manner is not limited to the number shown in the figure.

[0084] In a QHC, the amplitude and phase of the reflected signal are determined by the load impedance at the output port and also by the termination impedance at the isolated port. The termination impedance typically consists of a resistor connected to the signal ground. However, a reliable ground reference for the connection of the termination load is not always available, especially at millimeter wave (mmW) frequencies. Certain aspects of the present disclosure address this problem.

[0085] Even if the PAs are orthogonal (90°), it is possible to combine the isolated ports of multiple QHCs. Furthermore, the termination load can take many forms, such as resistors, open circuits, short circuits, transmission lines, impedance tuners that provide complex impedances, etc.

[0086] Figure 15A Depicts one aspect of the present disclosure, similar to Figure 14A , but with the isolated terminals of the QHCs 38, 40, 42, 44 connected and terminated to the RF signal ground via a single resistor 58 having an impedance of Z0 / 4 (to match the antenna load characteristic impedance Z0 / 4). The isolated terminals of the input QHCs of the balanced PA, if any, are not included.

[0087] Figure 15B Depicts the Figure 11A, but the isolated terminals of the QHCs 14 and 16 are connected and terminated to the RF signal ground via a single configurable or variable load 60. The load 60 may be implemented as a switch (providing an open or short circuit to the RF signal ground), a transmission line, a tuner providing a complex impedance a+jb, etc.

[0088] Simulations of various aspects presented herein (eg, as shown in Figures 11, 13, and 14) show that, in the presence of antenna impedance mismatch, each individual PA in this innovative circuit is distributed on a VSWR circle. Now consider output power.

[0089] Right Figure 11C 6 and 7 (two balanced PAs 10, 12, each including a PA and QHC 14, 16, with a -45° delay line at the output of the balanced PA 12, and the balanced PA outputs connected via a Wilkinson combiner 24) were simulated and compared with the two prior art configurations depicted in FIG6 and FIG7.

[0090] Figure 16 A simulation model 62 for each individual PA is depicted, including baluns 64 and 66 at the input and output to convert single-ended signals to differential signals and back to single-ended signals; input and output impedance matching networks (IMN 68 and OMN 70); and a balanced differential power amplifier 72. As shown, the PA 72 is implemented using a differential cross-coupled common-source stage followed by a common-gate stage.

[0091] To evaluate the sensitivity to changes in load impedance, the output power variation over VSWR=3 turns was simulated and the results are presented in Table 1. For accurate comparison, the input power was adjusted in each simulation to ensure that the PA operated at the 1-dB compression point. Figure 16 The results are also depicted graphically in .

[0092]

[0093] Table 1: Simulation results for output power

[0094] These results are plotted in Figure 17A -C. Specifically, Figure 17A The results for the balanced PA of FIG6 are shown, on the circle of VSWR=3, the average output power is 18.45 dBm, and the power variation is 1.5 dB.

[0095] Figure 17BThe results for the two connected balanced PAs of FIG. 7 are shown, with an average output power of 21 dBm and a power variation of 1.4 dB on the circle of VSWR=3.

[0096] Figure 17C Shown for Figure 11C The results of the circuit of the present invention are shown, which utilizes the inherent 90° phase shift of the balanced PAs 10, 12 and the delay line 18 to achieve line averaging of all the PAs in the combined circuit. On the VSWR=3 circle, the circuit has an average output power of 21 dBm with a power variation of only 0.1 dB.

[0097] Figure 18 The steps in a method 100 for driving an antenna element or subarray of antenna elements using a radio frequency (RF) signal are depicted. The RF signal is amplified in each of at least two parallel balanced power amplifiers (block 102). Each balanced power amplifier includes two power amplifiers connected in parallel and operating in quadrature, and an output quadrature hybrid coupler that connects the outputs of the two power amplifiers into a single RF signal. A phase shift is applied to the output of at least one balanced amplifier (block 104). The outputs of the at least two balanced power amplifiers and the phase-shifted outputs are combined (block 106). The combined RF signal is used to drive the antenna element or subarray of antenna elements (block 108).

[0098] The method 100 may be performed by any device or node driving an antenna array that implements beamforming. Figure 19For example, a hardware block diagram of a wireless device 80 as implemented according to one or more embodiments is shown. The wireless device 80 is any type of device capable of communicating with a network node and / or access point using radio signals. Thus, the wireless device 80 may refer to a machine-to-machine (M2M) device, a machine-type communication (MTC) device, a narrowband Internet of Things (NBIoT) device, and the like. The wireless device 80 may also be referred to as a user equipment (UE), such as a cellular phone or a "smartphone," however, the term UE should be understood to encompass any wireless device 80. The wireless device 80 may also be referred to as a radio device, a radio communication device, a wireless device, a wireless terminal, or simply a terminal—unless the context dictates otherwise, the use of any of these terms is intended to encompass device-to-device UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors equipped with wireless devices, wireless-enabled tablets, mobile terminals, smartphones, laptop embedded devices (LEEs), laptop mounted devices (LMEs), USB dongles, wireless client equipment (CPEs), and the like. In the discussion herein, the terms machine-to-machine (M2M) devices, machine-type communication (MTC) devices, wireless sensors, and sensors may also be used. It should be understood that these devices, although referred to as UEs, may be configured to send and / or receive data without direct human interaction.

[0099] In some embodiments, the wireless device 80 includes a user interface 82 (display, touch screen, keyboard or keypad, microphone, speaker, etc.); in other embodiments, such as in many M2M, MTC or NB IoT scenarios, the wireless device 80 may include only a minimal user interface 82, or may not include a user interface 82 (e.g., a user interface 82 provided by a user interface 82). Figure 18 82 in the figure). The wireless device 80 also includes processing circuitry 84, memory 86, and communication circuitry 88 to enable wireless communication with one or more radio network nodes (e.g., base stations and / or access points) over an air interface. The communication circuitry 88 is connected to an antenna element array 89 (e.g., an AAS) that implements beamforming through phase control. As indicated by the dotted lines, the antenna array 89 may extend from the outside of the wireless device 80, or the antenna array 89 may be internal. In some embodiments, the wireless device 80 may include a complex user interface 82 and may additionally include functionality such as a camera, an accelerometer, a satellite navigation signal receiver circuit, a vibration motor, etc. ( Figure 18 not shown).

[0100] According to aspects of the present disclosure, the communication circuit 88 includes a parallel structure of balanced PAs constructed using QHCs as output combiners, wherein the balanced PAs have an inherent 90° phase shift between the PAs, and the parallel structure further includes one or more delay lines between at least one QHC output and the antenna elements in the array 89 to achieve line averaging. This makes the balanced PAs less susceptible to the deleterious effects of dynamically changing impedance mismatches at the antennas, such as those caused by beamforming.

[0101] Figure 20 A hardware block diagram of a base station 90 operating in a wireless communication network is depicted. Base station 90 includes processing circuitry 92; memory 94; and communication circuitry 96 to facilitate wireless communication with one or more wireless devices 80 over the air interface. Communication circuitry 96 is connected to an antenna element array 98 (e.g., an AAS), which implements beamforming through phase control. As indicated by the disconnection of antenna array 98, antenna array 98 may be physically located separately from base station 90, such as mounted on a tower, building, or the like. Although memory 96 is depicted as being internal to processing circuitry 94, those skilled in the art will appreciate that memory 96 may also be external. Furthermore, those skilled in the art will appreciate that virtualization techniques allow some functions nominally performed by processing circuitry 94 to be performed by other hardware, which may be located remotely (e.g., in the so-called "cloud"). Base station 90 is referred to as an eNodeB or eNB in ​​LTE and as a gNB in ​​New Radio (NR). In other wireless communication networks, base station 90 may be referred to as a radio base station, base transceiver station, access point, or the like.

[0102] According to aspects of the present disclosure, communication circuitry 96 includes a parallel configuration of balanced PAs constructed using QHCs as output combiners, wherein the balanced PAs have an inherent 90° phase shift between the PAs, and the parallel configuration additionally includes one or more delay lines between at least one QHC output and the antenna elements in array 98 to implement line averaging. This makes the balanced PAs less susceptible to the deleterious effects of dynamically changing impedance mismatches at the antennas, such as those caused by beamforming.

[0103] Please note that the apparatus described herein can perform method 100 and any other processing described herein by implementing any functional component, module, unit, or circuit. In one embodiment, for example, the apparatus includes corresponding circuits or circuit systems configured to perform the steps shown in the method diagram. In this regard, the circuit or circuit system may include circuits dedicated to performing certain functional processing and / or one or more microprocessors combined with a memory. For example, the circuit may include one or more microprocessors or microcontrollers, as well as other digital hardware, which may include a digital signal processor (DSP), dedicated digital logic, etc. The processing circuit may be configured to execute program code stored in a memory, which may include one or more types of memory, such as read-only memory (ROM), random access memory, cache, flash memory device, optical storage device, etc. In multiple embodiments, the program code stored in the memory may include program instructions for executing one or more telecommunications and / or data communication protocols, as well as instructions for executing one or more of the techniques described herein. In embodiments using a memory, the memory stores program code, and when the program code is executed by one or more processors, the program code will execute the techniques described herein.

[0104] Those skilled in the art will also understand that aspects herein also include corresponding computer programs.

[0105] The computer program includes instructions, and when the instructions are executed on at least one processor of the device, the instructions cause the device to perform any corresponding processing in the above-mentioned corresponding processing. In this regard, the computer program may include one or more code modules corresponding to the above-mentioned components or units.

[0106] The present invention also includes a carrier containing such a computer program. The carrier may include one of an electronic signal, an optical signal, a radio signal or a computer-readable storage medium.

[0107] In this regard, aspects herein also include a computer program product stored on a non-transitory computer-readable (storage or recording) medium, the computer program product including instructions that, when executed by a processor of a device, cause the device to perform the operations described above.

[0108] Aspects also include a computer program product, which includes a program code portion for executing the steps of any embodiment of the present invention when a computing device executes the computer program product. The computer program product can be stored on a computer-readable recording medium.

[0109] Aspects of the present disclosure have been presented in the context of a line-averaged balanced PA employing a 90° phase shift between PAs, and the addition of one or more delay elements at the balanced PA outputs. For clarity of explanation, these delay elements are represented as phase shifters. Those skilled in the art will readily appreciate that, in practice, delays can be introduced by varying the wiring lengths between the parallel balanced PA structure and the antenna elements / subarrays. Alternatively, phase shifting can be achieved using transmission lines, microstrip lines, lumped reactive components, and the like.

[0110] Aspects of the present disclosure offer numerous advantages over the prior art. By leveraging the inherent 90° phase shift in balanced PAs for line averaging using additional delay elements, the number of passive components required after paralleling balanced PAs is reduced, thereby reducing overall losses. The distribution of PA loads provides an averaging effect, so that the sum of each PA's contribution appears under matched conditions. This approach is scalable and allows for large-scale parallelization of balanced PA circuits. Aspects of the present disclosure improve load adaptability for individual amplifiers (i.e., each antenna or antenna element).

[0111] Generally, all terms used in this article will be interpreted according to their ordinary meaning in the relevant technical field, unless clearly given different meanings and / or different meanings are implied in the context in which they are used. Unless otherwise clearly stated, all references to one / a kind of / this element, device, assembly, member, step etc. will be openly interpreted as referring to at least one instance of this element, device, assembly, member, step etc. The steps of any method disclosed herein do not have to be performed in the disclosed exact order, unless clearly describing a certain step after or before another step, and / or implying that a certain step must be after or before another step. Any feature of any aspect disclosed herein can be applied to any other aspect where appropriate. Equally, any advantage of any aspect can be applied to any other aspect, and vice versa. Other targets, features and advantages of disclosed aspects will be apparent from the specification.

[0112] The term "unit" may have a conventional meaning in the field of electronics, electrical devices and / or electronic devices, and may include, for example, electrical and / or electronic circuits, devices, modules, processors, memories, logical solid-state and / or discrete devices, computer programs or instructions for performing corresponding tasks, processes, calculations, output and / or display functions, etc. (such as those described in this document).

[0113] As used herein, the term "configured to" means arranged, organized, adapted, or disposed to operate in a particular manner; this term is synonymous with "designed to."

[0114] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. However, other aspects are also within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as being limited to only the aspects described herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0115] Of course, without departing from the basic characteristics of the present disclosure, the present disclosure can be implemented in other ways different from the way specifically set forth herein. The present aspect will be considered in all respects as illustrative and not restrictive, and all variations within the meaning and equivalent range of the appended aspects are intended to be included herein.

Claims

1. An amplifier circuit configured to drive an antenna element or a subarray of antenna elements using a radio frequency (RF) signal, comprising: At least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises: Two power amplifiers (PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8); and Output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) which connects the two power amplifiers (PA1, The outputs of PA2, PA3, PA4, PA5, PA6, PA7, PA8) are connected into a single RF signal; and a delay line (18, 20, 22, 46, 48, 50) inserted between the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or subarray; The delay lines (18, 20, 22, 46, 48, 50) thus impart a phase shift to the connected balanced power amplifiers (10, 12, 30, 32, 34, 36).

2. The amplifier circuit according to claim 1, wherein The amount of phase shift applied between each of the at least two balanced power amplifiers (10, 12, 30, 32, 34, 36) is 90 / N, where N is the number of balanced power amplifiers (10, 12, 30, 32, 34, 36) in the amplifier circuit.

3. The amplifier circuit according to claim 1, wherein A first balanced power amplifier (10, 30) is directly connected to the antenna element or subarray, and each other balanced power amplifier (12, 32, 34, 36) is connected to the antenna element or subarray via a respective delay line (18, 46, 48, 50) applying a different phase shift.

4. The amplifier circuit according to claim 3, wherein: The amplifier circuit comprises two balanced amplifiers (10, 12), and wherein the delay line (18) at the output of one balanced power amplifier (12) applies a phase shift of -45°.

5. The amplifier circuit according to claim 3, wherein The amplifier circuit comprises four balanced amplifiers (30, 32, 34, 36), and wherein the delay lines (46, 48, 50) on the outputs of the three balanced power amplifiers (32, 34, 36) apply phase shifts of -22.5°, -45° and -67.5°.

6. The amplifier circuit according to claim 1, wherein Each balanced power amplifier (10, 12) is connected to the antenna element or subarray via a delay line (20, 22) which applies a different phase shift.

7. The amplifier circuit according to claim 6, wherein: The amplifier circuit comprises two balanced amplifiers (10, 12), and wherein the delay line (20) at the output of one balanced power amplifier (10) applies a phase shift of -22.5°, and the delay line (22) at the output of the other balanced power amplifier (12) applies a phase shift of 22.5°.

8. An amplifier circuit according to any one of the preceding claims, wherein The connection between the balanced power amplifier output or the output of the delay line and the antenna elements or sub-arrays is via a power combining network (24, 52, 54, 56).

9. The amplifier circuit according to claim 8, wherein The power combining network (24, 52, 54, 56) is a Wilkinson power combining network (24, 52, 54, 56).

10. An amplifier circuit according to any one of the preceding claims, wherein The delay line (18, 20, 22, 46, 48, 50) is implemented as one or more of: a transmission line, a microstrip line, and a circuit including a lumped reactive component.

11. An amplifier circuit according to any one of the preceding claims, wherein Each balanced power amplifier (10, 12, 30, 32, 34, 36) further includes an input quadrature hybrid coupler configured to split the input RF signal between the two parallel power amplifiers.

12. An amplifier circuit according to any one of the preceding claims, wherein The isolation terminal of each output quadrature hybrid coupler is connected to the RF signal ground via a load having a characteristic impedance Z0 matched to that of the power amplifier.

13. An amplifier circuit according to any one of the preceding claims, wherein The isolation terminals of all output quadrature hybrid couplers are connected together and terminated to RF signal ground through circuitry (58, 60) including resistors, switching circuitry configurable to open or short circuit, or an adjustable tuner providing a complex impedance.

14. A method (100) for driving an antenna element or a subarray of antenna elements using a radio frequency (RF) signal, comprising: amplifying (104) the RF signal in each of at least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) includes two power amplifiers (PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8) connected in parallel and operating in quadrature, and an output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) connecting the outputs of the two power amplifiers (PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8) into a single RF signal; applying (106) a phase shift to the output of at least one balanced amplifier (10, 12, 30, 32, 34, 36); and combining (108) the outputs and phase-shifted outputs of the at least two balanced power amplifiers (10, 12, 30, 32, 34, 36); and The antenna element or sub-array of antenna elements is driven (110) using the combined RF signal.

15. The method according to claim 14, wherein Applying (106) a phase shift to the output of at least one balanced amplifier (10, 12, 30, 32, 34, 36) includes applying a phase shift such that the amount of phase shift between the balanced power amplifiers is 90 / N, where N is the number of balanced power amplifiers (10, 12, 30, 32, 34, 36).

16. The method according to claim 14, wherein Applying (106) a phase shift to the output of at least one balanced amplifier (10, 12, 30, 32, 34, 36) includes applying a different phase shift to the output of each of less than the total number of balanced power amplifiers (12, 32, 24, 26) and applying no phase shift to the outputs of the remaining balanced power amplifiers (10, 30).

17. The method according to claim 16, wherein The amplifier circuit includes two balanced power amplifiers (10, 12), and wherein applying a different phase shift to the output of each of less than the total number of balanced power amplifiers includes applying a -45° phase shift to the output of one of the balanced power amplifiers (16).

18. The method according to claim 16, wherein The amplifier circuit includes four balanced amplifiers (30, 32, 34, 36), and wherein applying a different phase shift to the output of each of less than the total number of balanced power amplifiers includes applying a phase shift of 22.5°, -45°, and -67.5° to the output of each of three of the balanced power amplifiers (32, 34, 36).

19. The method according to claim 16, wherein Applying (106) a phase shift to the output of at least one balanced amplifier (10, 12) includes applying a different phase shift to the output of each balanced amplifier (10, 12).

20. The method according to claim 19, wherein The amplifier circuit includes two balanced amplifiers (10, 12), and wherein applying a different phase shift to the output of each balanced amplifier (10, 12) includes applying a phase shift of -22.5° to the output of one balanced power amplifier (10) and applying a phase shift of 22.5° to the output of the other balanced power amplifier (12).

21. The method according to any one of claims 14 to 20, wherein: Combining (108) the outputs and the phase-shifted outputs of the at least two balanced power amplifiers includes combining the outputs via a power combining network (24, 52, 54, 56).

22. The method according to claim 21, wherein The power combining network (24, 52, 54, 56) is a Wilkinson power combining network (24, 52, 54, 56).

23. The method according to any one of claims 14 to 22, wherein: Applying (106) a phase shift to the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) includes applying the phase shift by inserting a delay line (18, 20, 22, 46, 48, 50) between the balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or subarray, the delay line (18, 20, 22, 46, 48, 50) being implemented as one or more of: a transmission line, a microstrip line, and a circuit including a lumped reactive component.

24. The method according to any one of claims 14 to 23, wherein Each balanced power amplifier (10, 12, 30, 32, 34, 36) further includes an input quadrature hybrid coupler configured to split the input RF signal between the two parallel power amplifiers.

25. The method according to any one of claims 14 to 24, further comprising: The isolation terminal of each output quadrature hybrid coupler is terminated to the RF signal ground via a load having a characteristic impedance Z0 matched to the power amplifier.

26. The method according to any one of claims 14 to 25, further comprising: The isolated terminal of each output quadrature hybrid coupler is terminated to an RF signal ground by a circuit (58, 60) comprising a resistor, a switching circuit configurable to an open circuit or a short circuit, or an adjustable tuner providing a complex impedance.

27. A wireless device (80) operating in a wireless communication network, comprising: an array of antenna elements (89); communications circuitry (88) connected to the antenna array (89) and configured to communicate wirelessly with one or more other network nodes; as well as processing circuitry (84) operatively connected to the communication circuitry (88) and configured to implement beamforming on the antenna array (89); The communication circuit (88) comprises a plurality of amplifier circuits, each amplifier circuit being configured to drive an antenna unit or a subarray of antenna units, each amplifier circuit comprising: At least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises: Two power amplifiers (PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8); and Output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) which connects the two power amplifiers (PA1, The outputs of PA2, PA3, PA4, PA5, PA6, PA7, PA8) are connected into a single RF signal; and a delay line (18, 20, 22, 46, 48, 50) inserted between the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or subarray; The delay line (18, 20, 22, 46, 48, 50) thereby applies a phase shift to the connected balanced power amplifier (10, 12, 30, 32, 34, 36) relative to at least one other balanced power amplifier (10, 12, 30, 32, 34, 36).

28. A base station (90) operating in a wireless communication network, comprising: an array of antenna elements (98); Communication circuitry (96) connected to the antenna array (98) and configured to communicate wirelessly with one or more other network nodes; as well as processing circuitry (92) operatively connected to the communication circuitry (96) and configured to implement beamforming on the antenna array (98); The communication circuit (96) includes a plurality of amplifier circuits, each amplifier circuit being configured to drive an antenna unit or a subarray of antenna units, each amplifier circuit including: At least two balanced power amplifiers (10, 12, 30, 32, 34, 36) connected in parallel, wherein each balanced power amplifier (10, 12, 30, 32, 34, 36) comprises: Two power amplifiers (PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8); and Output quadrature hybrid coupler (14, 16, 38, 40, 42, 44) which connects the two power amplifiers (PA1, The outputs of PA2, PA3, PA4, PA5, PA6, PA7, PA8) are connected into a single RF signal; and a delay line (18, 20, 22, 46, 48, 50) inserted between the output of at least one balanced power amplifier (10, 12, 30, 32, 34, 36) and the antenna element or subarray; The delay line (18, 20, 22, 46, 48, 50) thereby applies a phase shift to the connected balanced power amplifier (10, 12, 30, 32, 34, 36) relative to at least one other balanced power amplifier (10, 12, 30, 32, 34, 36).

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