Chip interrupt processing method and device, equipment and storage medium

Abstract

The invention discloses a chip interrupt processing method and device, equipment and a storage medium, and the method comprises the steps: determining a target priority in a hash table according to an interrupt number corresponding to a target interrupt after detecting that the target interrupt in a CPU chip is triggered; the mapping relation between each interrupt number and the priority in the CPU chip is pre-stored in the hash table; determining a target array value in an interrupt enable register array table according to the target priority; the interrupt enabling register array table stores different register array values corresponding to each interrupt in the CPU chip and the peripheral interrupt under different priorities, and the register array values are used for indicating the opening or closing function of each interrupt response process; and processing the target interrupt according to the target array value. According to the technical scheme provided by the embodiment of the invention, the priority of all the native interrupts and the peripheral interrupts in the CPU chip can be independently set, and the software maintenance difficulty is greatly reduced while interrupt nesting is realized.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a chip interrupt processing method, device, equipment and storage medium. Background Art

[0002] Currently, central processing unit (CPU) chips based on the TMS320C28X architecture support only 32 native interrupt lines (RESET, INT1-14, DLOGINT, RTOSINT, Reserved, NMI, ILLEGAL, and USER1-12). Intellectual property (IP) cores are required to expand INT1-12 into 12 interrupt groups, each with 16 interrupt lines, to meet the needs of peripheral interrupts. However, these interrupts have fixed priorities and cannot be programmed. They also lack the ability to nest interrupts, meaning that a higher-priority interrupt cannot interrupt the current interrupt, effectively failing to meet the needs of real-time-sensitive applications.

[0003] In the prior art, a software development toolkit for implementing interrupt nesting is provided. However, the toolkit can only set interrupt priorities by group, and cannot set priorities for each interrupt individually. In addition, the priority is set by manually setting a mask bit in the interrupt, which is not intuitive and greatly increases the difficulty of software maintenance. Summary of the Invention

[0004] The present invention provides a chip interrupt processing method, apparatus, device and storage medium, which can set the priority of all native interrupts and peripheral interrupts in the CPU chip separately, realize interrupt nesting, and greatly reduce the difficulty of software maintenance.

[0005] According to one aspect of the present invention, a chip interrupt processing method is provided, the method comprising:

[0006] After detecting that a target interrupt in a CPU chip is triggered, a target priority corresponding to the target interrupt is determined in a pre-built hash table according to an interrupt number corresponding to the target interrupt;

[0007] The hash table pre-stores the mapping relationship between each interrupt number and priority in the CPU chip;

[0008] Determining, according to the target priority, a target array value corresponding to the target interrupt in a pre-constructed interrupt enable register array table;

[0009] The interrupt enable register array table pre-stores different register array values ​​corresponding to each interrupt in the CPU chip and the peripheral interrupt at different priorities, and the register array values ​​are used to indicate the on or off function of each interrupt response process;

[0010] The target interrupt is processed according to the target array value corresponding to the target interrupt.

[0011] Optionally, before detecting that a target interrupt in the CPU chip is triggered, the method further includes:

[0012] After detecting that a user triggers an interrupt priority setting request, obtaining the interrupt number and priority carried in the setting request;

[0013] Storing the mapping relationship between the interrupt number and the priority in a hash table;

[0014] After detecting that the user triggers a registration function request, the interrupt number corresponding to the registration function request is searched in the hash table, and the interrupt handling function matching the interrupt number is registered according to the registration function request.

[0015] Optionally, after registering the interrupt handling function matching the interrupt number, the method further includes:

[0016] After detecting that a user triggers an interrupt enable request, obtaining an interrupt number in the interrupt enable request and enabling an interrupt corresponding to the interrupt number;

[0017] Querying the priority level corresponding to the interrupt enable request in the hash table;

[0018] According to the priority level corresponding to the interrupt enable request, a register array value matching the interrupt enable request is configured in an interrupt enable register array table.

[0019] Optionally, configuring a register array value that matches the interrupt enable request in an interrupt enable register array table according to a priority corresponding to the interrupt enable request includes:

[0020] In the interrupt enable register array table, query the peripheral register bit and the corresponding CPU register bit of the interrupt enable request;

[0021] Among the peripheral register bits and the CPU register bits, the bit values ​​lower than the priority are set to 1, and the bit values ​​higher than or equal to the priority are set to 0.

[0022] Optionally, the method further includes:

[0023] After detecting that a user has triggered an interrupt disable request, querying the hash table for a priority level corresponding to the interrupt disable request, and updating the priority level corresponding to the interrupt disable request to a lowest priority level;

[0024] According to the lowest priority, a register array value matching the interrupt disable request is configured in an interrupt enable register array table.

[0025] Optionally, processing the target interrupt according to the target array value corresponding to the target interrupt includes:

[0026] According to the interrupt number corresponding to the target interrupt, query the interrupt processing function corresponding to the target interrupt;

[0027] The target interrupt is processed according to the target array value and the interrupt processing function corresponding to the target interrupt.

[0028] According to another aspect of the present invention, a chip interrupt processing device is provided, the device comprising:

[0029] A priority determination module is configured to, after detecting that a target interrupt in a CPU chip is triggered, determine a target priority corresponding to the target interrupt in a pre-built hash table according to an interrupt number corresponding to the target interrupt;

[0030] The hash table pre-stores the mapping relationship between each interrupt number and priority in the CPU chip;

[0031] an array value determination module, configured to determine, according to the target priority, a target array value corresponding to the target interrupt in a pre-built interrupt enable register array table;

[0032] The interrupt enable register array table pre-stores different register array values ​​corresponding to each interrupt in the CPU chip and the peripheral interrupt at different priorities, and the register array values ​​are used to indicate the on or off function of each interrupt response process;

[0033] The interrupt processing module is used to process the target interrupt according to the target array value corresponding to the target interrupt.

[0034] According to another aspect of the present invention, an electronic device is provided, comprising:

[0035] at least one processor; and

[0036] a memory communicatively connected to the at least one processor; wherein,

[0037] The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can execute the chip interrupt processing method described in any embodiment of the present invention.

[0038] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip interrupt processing method according to any embodiment of the present invention when executed.

[0039] According to another aspect of the present invention, a computer program product is provided. When the computer program is executed by a processor, the chip interrupt processing method according to any embodiment of the present invention is implemented.

[0040] The technical solution provided by the embodiment of the present invention, after detecting that a target interrupt in a CPU chip is triggered, determines the target priority corresponding to the target interrupt in a pre-built hash table according to the interrupt number corresponding to the target interrupt, determines the target array value corresponding to the target interrupt in a pre-built interrupt enable register array table according to the target priority, and processes the target interrupt according to the target array value corresponding to the target interrupt. This technical solution can achieve separate priority setting for all native interrupts and peripheral interrupts in the CPU chip, while achieving interrupt nesting and greatly reducing the difficulty of software maintenance.

[0041] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a flowchart of a chip interrupt processing method provided by an embodiment of the present invention;

[0044] Figure 2a is a flowchart of another chip interrupt processing method provided according to an embodiment of the present invention;

[0045] Figure 2b is a schematic diagram of configuring an interrupt enable register array table according to an embodiment of the present invention;

[0046] Figure 3 2 is a schematic structural diagram of a chip interrupt processing device provided according to an embodiment of the present invention;

[0047] Figure 4 The present invention is a schematic diagram of the structure of an electronic device for implementing the chip interrupt processing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1 This is a flowchart of a chip interrupt processing method provided by an embodiment of the present invention. This embodiment is applicable to the case of processing CPU chip interrupts based on the TMS320C28X architecture. The method can be executed by a chip interrupt processing device. The chip interrupt processing device can be implemented in the form of hardware and / or software. The device can be configured in an electronic device. Figure 1 As shown, the method includes:

[0051] Step 110: After detecting that a target interrupt in a CPU chip is triggered, a target priority level corresponding to the target interrupt is determined in a pre-built hash table according to an interrupt number corresponding to the target interrupt.

[0052] In this embodiment, the CPU chip includes 32 native interrupt lines, of which INT1 to INT12 are expanded into 12 groups of interrupts, and each group of interrupts is expanded into 16 interrupt lines. Before the CPU chip actually runs, an interrupt priority hash table can be pre-built. The hash table stores the mapping relationship between each interrupt number and priority in the CPU chip. The interrupt number can be a fixed data value preset by the manufacturer corresponding to the interrupt line. Specifically, the hash table can be shown in Table 1:

[0053] Table 1

[0054] As shown in Table 1, each row of elements in the hash table includes a mapping relationship between an interrupt number (interruptNumber) and an interrupt priority (priority). Each interrupt number and corresponding priority can be stored in the form of a key-value pair (Key-Value).

[0055] In this step, during the actual operation of the CPU chip, if any interrupt is detected to be triggered, this interrupt can be used as the target interrupt, and then the target priority corresponding to the target interrupt is queried in the hash table according to the interrupt number of the target interrupt.

[0056] In a specific embodiment, if the priority level corresponding to the target interrupt does not exist in the hash table, the target interrupt is processed using an assertion mechanism.

[0057] Step 120: Determine a target array value corresponding to the target interrupt in a pre-built interrupt enable register array table according to the target priority.

[0058] In this embodiment, the interrupt enable register array table can be as shown in Table 2. The register array table pre-stores different register array values ​​corresponding to each interrupt in the CPU chip (i.e., the native 32 interrupt lines) and the peripheral interrupt (i.e., the extended 12 groups of interrupts) at different priorities. The register array values ​​are used to indicate the on or off function of each interrupt response process.

[0059] Table 2

[0060] As shown in Table 2, each row in the interrupt enable register array table represents an array element. The index value of each array element is the priority. Each array element includes the CPU register (CPU_IER) value corresponding to the native 32 interrupt lines and the peripheral register (PIE_IER[1~12]) value corresponding to the peripheral interrupt. For example, in Table 2, the 0th bit of CPU_IER corresponds to the interrupt line INT1, the 1st bit corresponds to the interrupt line INT2, the 2nd bit corresponds to the interrupt line INT3, etc., PIE_IER[1] corresponds to the interrupt line extended by the interrupt line INT1, PIE_IER[2] corresponds to the interrupt line extended by the interrupt line INT2, PIE_IER

[12] corresponds to the interrupt line extended by the interrupt line INT12, etc. Each bit value in Table 2 is used to indicate whether the response function of the corresponding interrupt is turned on or off. For example, when the bit value is 0, it indicates that the corresponding interrupt response function is turned off, and when the bit value is 1, it indicates that the corresponding interrupt response function is turned on.

[0061] In this step, the target priority level may be used as an index to search for a corresponding array element in the interrupt enable register array table, and then the array value corresponding to the array element may be used as the target array value.

[0062] Step 130: Process the target interrupt according to the target array value corresponding to the target interrupt.

[0063] In this step, specifically, you can first allocate 12 16-bit spaces in the preset stack, push the values ​​of the 12 PIE_IER registers in the target array value into the stack, then write the target array value into the hardware register, and finally enable the global interrupt according to the array value in the hardware register to complete the processing of the target interrupt.

[0064] In this embodiment, optionally, after detecting that the user triggers an exit interrupt request, the global interrupt can be disabled, and then the values ​​of the 12 PIE_IER registers are popped out and written into the hardware register to make the CPU chip exit the interrupt operation.

[0065] In this embodiment, a simple interrupt initialization method is provided by constructing a hash table and an interrupt enable register array table during the interrupt initialization process. Compared with the method of setting interrupt priorities by group and setting interrupt mask bits in the prior art, it is possible to set priorities for all native interrupts and peripheral interrupts separately. While realizing interrupt nesting, it improves the flexibility of the interrupt configuration process and greatly reduces the difficulty of software maintenance.

[0066] The technical solution provided by the embodiment of the present invention, after detecting that a target interrupt in a CPU chip is triggered, determines the target priority corresponding to the target interrupt in a pre-built hash table according to the interrupt number corresponding to the target interrupt, determines the target array value corresponding to the target interrupt in a pre-built interrupt enable register array table according to the target priority, and processes the target interrupt according to the target array value corresponding to the target interrupt. This technical solution can achieve separate priority setting for all native interrupts and peripheral interrupts in the CPU chip, while achieving interrupt nesting and greatly reducing the difficulty of software maintenance.

[0067] Figure 2a A flowchart of another chip interrupt processing method provided by an embodiment of the present invention is shown in FIG. Figure 2a As shown, the method includes:

[0068] Step 210: After detecting that the user triggers an interrupt priority setting request, obtain the interrupt number and priority carried in the setting request; and store the mapping relationship between the interrupt number and priority in a hash table.

[0069] In this step, the interrupt priority setting request may specifically include an interrupt number and a corresponding priority. After receiving the setting request, the interrupt number may be queried from a hash table. If a matching interrupt number exists in the hash table, the priority corresponding to the interrupt number is modified to the priority specified in the setting request. If a matching interrupt number does not exist in the hash table, a new row of elements is created in the hash table, and the mapping relationship between the interrupt number and priority is stored in the new row of elements.

[0070] Step 220: After detecting that the user triggers a registration function request, query the hash table for an interrupt number corresponding to the registration function request, and register an interrupt handling function that matches the interrupt number according to the registration function request.

[0071] In this step, the registration function request may specifically include an interrupt number and a corresponding interrupt handling function. After receiving the registration function request, the interrupt number may be queried from a hash table. If a matching interrupt number exists in the hash table, the interrupt handling function matching the interrupt number is registered. If a matching interrupt number does not exist in the hash table, a new row element is created in the hash table, and the lowest priority corresponding to the interrupt number is set in the new row element, and the interrupt handling function matching the interrupt number is then registered.

[0072] Step 230: After detecting that the user has triggered an interrupt enable request, obtain the interrupt number in the interrupt enable request, enable the interrupt corresponding to the interrupt number, query the priority corresponding to the interrupt enable request in the hash table, and configure the register array value matching the interrupt enable request in the interrupt enable register array table according to the priority corresponding to the interrupt enable request.

[0073] In this step, specifically, the interrupt enable request may include an interrupt number. After obtaining the interrupt enable request, the interrupt number may be queried from the hash table. If a consistent interrupt number exists in the hash table, the register array value in the interrupt enable register array table is configured according to the priority corresponding to the interrupt number. If a consistent interrupt number does not exist in the hash table, a new row of elements is created in the hash table, and the lowest priority corresponding to the interrupt number is set in the new element. Then, the register array value in the interrupt enable register array table is configured according to the lowest priority.

[0074] In one implementation of this embodiment, according to the priority corresponding to the interrupt enable request, the register array value matching the interrupt enable request is configured in the interrupt enable register array table, including: in the interrupt enable register array table, querying the peripheral register bit and the CPU register bit corresponding to the interrupt enable request; among the peripheral register bits and the CPU register bits, setting the bit values ​​lower than the priority to 1, and setting the bit values ​​higher than or equal to the priority to 0.

[0075] In a specific embodiment, Figure 2b This is a schematic diagram of configuring the interrupt enable register array table in this embodiment, such as Figure 2b As shown, assuming that the interrupt number included in the interrupt enable request triggered by the user corresponds to priority 4, corresponding to the interrupt line indicated by the third bit in the PIE_IER2 register, since PIE_IER2.Bit3 belongs to CPU_IER.Bit1, the values ​​with a priority equal to or higher than 4 in PIE_IER2.Bit3 and CPU_IER.Bit1 can be set to 0, and the values ​​with a priority lower than 4 can be set to 1.

[0076] Step 240: After detecting that a target interrupt in the CPU chip is triggered, determine the target priority corresponding to the target interrupt in a pre-built hash table according to the interrupt number corresponding to the target interrupt.

[0077] Step 250: Determine a target array value corresponding to the target interrupt in a pre-built interrupt enable register array table according to the target priority.

[0078] Step 260 : query the interrupt processing function corresponding to the target interrupt according to the interrupt number corresponding to the target interrupt; and process the target interrupt according to the target array value and the interrupt processing function corresponding to the target interrupt.

[0079] The technical solution provided by the embodiment of the present invention detects that a user triggers an interrupt priority setting request, obtains the interrupt number and priority carried in the setting request; stores the mapping relationship between the interrupt number and the priority in a hash table; detects that a user triggers a registration function request, queries the hash table for the interrupt number corresponding to the registration function request, registers the interrupt processing function matching the interrupt number according to the registration function request; detects that a user triggers an interrupt enable request, enables the interrupt corresponding to the interrupt number, queries the hash table for the priority corresponding to the interrupt enable request, configures the matching register array value in the interrupt enable register array table; detects that a target interrupt in a CPU chip is triggered, determines the target priority in the hash table according to the interrupt number corresponding to the target interrupt, determines the target array value in the interrupt enable register array table according to the target priority, and queries the interrupt processing function according to the interrupt number corresponding to the target interrupt; and processes the target interrupt according to the target array value and the interrupt processing function corresponding to the target interrupt. This technical means can realize the separate setting of priorities for all native interrupts and peripheral interrupts in the CPU chip, while realizing interrupt nesting and greatly reducing the difficulty of software maintenance.

[0080] Based on the above embodiment, the method also includes: after detecting that the user triggers an interrupt disable request, querying the priority corresponding to the interrupt disable request in the hash table, and updating the priority corresponding to the interrupt disable request to the lowest priority; according to the lowest priority, configuring the register array value matching the interrupt disable request in the interrupt enable register array table.

[0081] Figure 3 A schematic diagram of a chip interrupt processing device according to an embodiment of the present invention is provided. The device is applied to electronic equipment, such as Figure 3 As shown, the device includes: a priority determination module 310 , an array value determination module 320 and an interrupt processing module 330 .

[0082] The priority determination module 310 is configured to, after detecting that a target interrupt in the CPU chip is triggered, determine the target priority corresponding to the target interrupt in a pre-built hash table according to the interrupt number corresponding to the target interrupt;

[0083] The hash table pre-stores the mapping relationship between each interrupt number and priority in the CPU chip;

[0084] An array value determination module 320 is configured to determine a target array value corresponding to the target interrupt in a pre-built interrupt enable register array table according to the target priority;

[0085] The interrupt enable register array table pre-stores different register array values ​​corresponding to each interrupt in the CPU chip and the peripheral interrupt at different priorities, and the register array values ​​are used to indicate the on or off function of each interrupt response process;

[0086] The interrupt processing module 330 is configured to process the target interrupt according to the target array value corresponding to the target interrupt.

[0087] The technical solution provided by the embodiment of the present invention, after detecting that a target interrupt in a CPU chip is triggered, determines the target priority corresponding to the target interrupt in a pre-built hash table according to the interrupt number corresponding to the target interrupt, determines the target array value corresponding to the target interrupt in a pre-built interrupt enable register array table according to the target priority, and processes the target interrupt according to the target array value corresponding to the target interrupt. This technical solution can achieve separate priority setting for all native interrupts and peripheral interrupts in the CPU chip, while achieving interrupt nesting and greatly reducing the difficulty of software maintenance.

[0088] Based on the above embodiment, the device further includes:

[0089] The priority setting module is configured to, upon detecting that a user triggers an interrupt priority setting request, obtain the interrupt number and priority level carried in the setting request; and store the mapping relationship between the interrupt number and priority level in a hash table;

[0090] a registration function module configured to, upon detecting that a user triggers a registration function request, search the hash table for an interrupt number corresponding to the registration function request, and register an interrupt handling function that matches the interrupt number according to the registration function request;

[0091] an array value configuration module, configured to, upon detecting that a user has triggered an interrupt enable request, obtain an interrupt number in the interrupt enable request, enable the interrupt corresponding to the interrupt number, query the hash table for a priority corresponding to the interrupt enable request, and configure a register array value matching the interrupt enable request in an interrupt enable register array table according to the priority corresponding to the interrupt enable request;

[0092] An interrupt disabling module is used to detect that a user has triggered an interrupt disabling request, query the priority corresponding to the interrupt disabling request in the hash table, and update the priority corresponding to the interrupt disabling request to the lowest priority; according to the lowest priority, configure the register array value matching the interrupt disabling request in the interrupt enable register array table.

[0093] The array value configuration module includes:

[0094] A bit query unit, configured to query the peripheral register bit and the corresponding CPU register bit of the interrupt enable request in the interrupt enable register array table;

[0095] The bit value setting unit is used to set the bit values ​​of the peripheral register bits and the CPU register bits that are lower than the priority to 1, and set the bit values ​​of the bits that are higher than or equal to the priority to 0.

[0096] The interrupt processing module 330 includes:

[0097] The interrupt response unit is used to query the interrupt processing function corresponding to the target interrupt according to the interrupt number corresponding to the target interrupt; and process the target interrupt according to the target array value and the interrupt processing function corresponding to the target interrupt.

[0098] The above device can execute the methods provided by all the above embodiments of the present invention, and has the corresponding functional modules and beneficial effects of executing the above methods. For technical details not fully described in the embodiments of the present invention, please refer to the methods provided by all the above embodiments of the present invention.

[0099] Figure 4 A schematic diagram of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0100] like Figure 4As shown, electronic device 10 includes at least one processor 11 and memory, such as read-only memory (ROM) 12 and random access memory (RAM) 13, communicatively connected to at least one processor 11. The memory stores computer programs executable by the at least one processor. Processor 11 can perform various appropriate actions and processes based on the computer programs stored in ROM 12 or loaded from storage unit 18 into RAM 13. RAM 13 can also store various programs and data required for the operation of electronic device 10. Processor 11, ROM 12, and RAM 13 are interconnected via bus 14. An input / output (I / O) interface 15 is also connected to bus 14.

[0101] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0102] Processor 11 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any other suitable processor, controller, microcontroller, etc. Processor 11 executes the various methods and processes described above, such as the chip interrupt handling method.

[0103] In some embodiments, the chip interrupt handling method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the chip interrupt handling method described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the chip interrupt handling method in any other appropriate manner (e.g., by means of firmware).

[0104] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0105] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0106] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or apparatus. A computer-readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0107] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device that has: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0108] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0109] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0110] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0111] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A chip interrupt processing method, characterized in that: The method comprises: After detecting that a target interrupt in a central processing unit (CPU) chip is triggered, a target priority corresponding to the target interrupt is determined in a pre-built hash table according to an interrupt number corresponding to the target interrupt; The hash table pre-stores the mapping relationship between each interrupt number and priority in the CPU chip; Determining, according to the target priority, a target array value corresponding to the target interrupt in a pre-constructed interrupt enable register array table; The interrupt enable register array table pre-stores different register array values ​​corresponding to each interrupt in the CPU chip and the peripheral interrupt at different priorities, and the register array values ​​are used to indicate the on or off function of each interrupt response process; The target interrupt is processed according to the target array value corresponding to the target interrupt.

2. The method according to claim 1, characterized in that Before detecting that a target interrupt is triggered in a central processing unit CPU chip, the following steps are also included: After detecting that a user triggers an interrupt priority setting request, obtaining the interrupt number and priority carried in the setting request; Storing the mapping relationship between the interrupt number and the priority in a hash table; After detecting that the user triggers a registration function request, the interrupt number corresponding to the registration function request is searched in the hash table, and the interrupt handling function matching the interrupt number is registered according to the registration function request.

3. The method according to claim 2, characterized in that After registering the interrupt handling function matching the interrupt number, the method further includes: After detecting that a user triggers an interrupt enable request, obtaining an interrupt number in the interrupt enable request and enabling an interrupt corresponding to the interrupt number; Querying the priority level corresponding to the interrupt enable request in the hash table; According to the priority level corresponding to the interrupt enable request, a register array value matching the interrupt enable request is configured in an interrupt enable register array table.

4. The method according to claim 3, characterized in that According to the priority corresponding to the interrupt enable request, a register array value matching the interrupt enable request is configured in an interrupt enable register array table, including: In the interrupt enable register array table, query the peripheral register bit and the CPU register bit corresponding to the interrupt enable request; Among the peripheral register bits and the CPU register bits, the bit values ​​lower than the priority are set to 1, and the bit values ​​higher than or equal to the priority are set to 0.

5. The method according to claim 3, characterized in that The method further comprises: After detecting that a user has triggered an interrupt disable request, querying the hash table for a priority level corresponding to the interrupt disable request, and updating the priority level corresponding to the interrupt disable request to a lowest priority level; According to the lowest priority, a register array value matching the interrupt disable request is configured in an interrupt enable register array table.

6. The method according to claim 2, characterized in that Processing the target interrupt according to the target array value corresponding to the target interrupt includes: According to the interrupt number corresponding to the target interrupt, query the interrupt processing function corresponding to the target interrupt; The target interrupt is processed according to the target array value and the interrupt processing function corresponding to the target interrupt.

7. A chip interrupt processing device, characterized in that: The device comprises: The priority determination module is used to determine the target priority corresponding to the target interrupt in a pre-built hash table according to the interrupt number corresponding to the target interrupt after detecting that the target interrupt in the central processing unit CPU chip is triggered; The hash table pre-stores the mapping relationship between each interrupt number and priority in the CPU chip; an array value determination module, configured to determine, according to the target priority, a target array value corresponding to the target interrupt in a pre-built interrupt enable register array table; The interrupt enable register array table pre-stores different register array values ​​corresponding to each interrupt in the CPU chip and the peripheral interrupt at different priorities, and the register array values ​​are used to indicate the on or off function of each interrupt response process; The interrupt processing module is used to process the target interrupt according to the target array value corresponding to the target interrupt.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to execute the chip interrupt processing method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip interrupt processing method according to any one of claims 1 to 6 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the chip interrupt processing method according to any one of claims 1 to 6 is implemented.

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