Circuit wiring system and method based on AI, medium and equipment

Abstract

The invention relates to the technical field of circuit wiring, in particular to an AI-based circuit wiring system, method, medium and equipment, and the system comprises an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a man-machine interaction module and an output module. The input module is used for receiving each device of an analog circuit and physical size information thereof, and describing a description file of a topology constraint relationship between device pairs; the preprocessing module performs normalization processing on the size information of the device; the deep learning module is a graph structure neural network, and an output layer of the graph structure neural network outputs two-dimensional plane position coordinates corresponding to the devices; the topology loss calculation module defines a topology loss function and calculates an error value in a graph structure neural network training process, and the candidate layout generation module automatically generates a plurality of device candidate layout schemes meeting the topology loss function based on the trained graph structure neural network; the graphical user interface module is used for displaying candidate layout schemes and the error component value of each scheme; the man-machine interaction module provides a layout fine tuning function through a graphical user interface; the output module is used for outputting a final device layout scheme after manual fine tuning or automatic generation; according to the invention, the design efficiency and quality of the layout of the analog integrated circuit are improved, and the requirements of modern integrated circuit design for rapid iteration and efficient layout are met.

Description

Technical Field

[0001] The present invention relates to the field of circuit wiring technology, and in particular to an AI-based circuit wiring system, method, medium and device. Background Art

[0002] The layout design of analog integrated circuits (Analog ICs) is typically a complex manual process that faces numerous topological constraints, such as device symmetry, proximity, and current flow paths. Furthermore, to optimize circuit performance, designers must repeatedly experiment and adjust layout positions, often requiring numerous iterations and a long, time-consuming process. This process also requires a high level of experience and skill, significantly impacting design efficiency and quality.

[0003] With the rapid development of artificial intelligence, especially deep learning, some approaches have attempted to use machine learning or deep learning to automate analog integrated circuit layout. However, existing automatic layout tools often fail to effectively combine the advantages of automatic layout generation with interactive human adjustments. The lack of effective human-computer interaction feedback makes it difficult for designers to intuitively understand the impact of layout adjustments on overall performance, resulting in difficulties in effectively improving design efficiency and layout quality. Summary of the Invention

[0004] In view of the above technical problems, the present invention provides an AI-based circuit wiring system, method, medium and equipment to improve the design efficiency and quality of analog integrated circuit layout, and meet the needs of modern integrated circuit design for fast iteration and efficient layout.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0006] According to one aspect of the present invention, an AI-based circuit routing system is proposed. The system includes an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a human-computer interaction module, and an output module, wherein:

[0007] The input module is used to receive information about each device of the analog circuit and its physical dimensions, and to receive a description file describing a topological constraint relationship between the device pairs;

[0008] The pre-processing module normalizes the size information of the devices to obtain relative size ratios, and converts the topological constraint relationship into a graph structure adjacency matrix corresponding to the device pairs;

[0009] The deep learning module is a graph structure neural network, which includes an input layer, a plurality of hidden layers and an output layer, wherein the input layer receives the relative size ratio and the adjacency matrix representing the symmetry constraint, the proximity constraint and the current flow constraint from the preprocessing module as input, and the output layer outputs the two-dimensional plane position coordinates corresponding to each device;

[0010] The topology loss calculation module defines a topology loss function and calculates an error value during the graph structure neural network training process, wherein the error value of the topology loss function includes a symmetry constraint error, a proximity constraint error, a current flow constraint error, a device overlap error, and an area waste error;

[0011] The candidate layout generation module automatically generates a plurality of device candidate layout solutions that meet the topology loss function based on the trained graph structure neural network;

[0012] The graphical user interface module is used to display a preview of the layout of the candidate layout solutions and the area, width, height, total topological error value and each error component value of each solution, and provide a function for screening and sorting the candidate solutions according to size indicators and error components;

[0013] The human-computer interaction module provides a layout fine-tuning function through the graphical user interface, wherein the layout fine-tuning function includes performing device selection, error visualization, topology error component switch adjustment, constraint weight adjustment, moving symmetrical device pairs, displaying error contours, performing layout packaging, and local optimization interactive operations on the visual layout interface to achieve manual fine-tuning of the selected candidate solution;

[0014] The output module is used to output the final device layout solution after manual fine-tuning or automatic generation.

[0015] Furthermore, the input layer of the graph structure neural network is a vector of size 2×N, where N is the number of devices in the circuit, and the vector of the input layer contains the normalized width and height of each device; the graph structure neural network also receives three unweighted adjacency matrices of size N×N, which are used to encode symmetry constraints, proximity constraints and current flow constraints, respectively; the graph structure neural network includes four hidden layers, and the number of neurons in each layer is 2500, 1000, 250 and 100 respectively; the output layer of the graph structure neural network generates the x and y coordinates of N devices in a two-dimensional plane.

[0016] Furthermore, the calculation of the topological loss function includes symmetry constraint loss, proximity constraint loss, current flow constraint loss, device overlap loss and area waste loss, and each loss is normalized and summed to form a total loss; wherein, the symmetry constraint loss is obtained by calculating the deviation of the spacing between paired symmetrical devices, the proximity constraint loss is obtained by calculating the deviation between the actual spacing between devices and the specified minimum distance, the current flow constraint loss is obtained by evaluating the connectivity or distance deviation of the devices on the current path, the device overlap loss is obtained by calculating the overlapping area between devices, and the area waste loss is obtained by calculating the difference between the area occupied by all devices and the area of ​​their minimum enclosing rectangle.

[0017] Furthermore, the graphical user interface module includes a candidate layout inspection window and a layout fine-tuning window; the candidate layout inspection window displays a preview image, layout size and corresponding total error and error component information of each candidate layout scheme in the form of a card, and provides users with the function of filtering and sorting according to total error, a certain error component value or layout size range; the layout fine-tuning window provides interactive adjustment functions based on the selected candidate layout scheme, including viewing its related errors by selecting devices on the layout diagram, dynamically adjusting the weights of each topological error component, switching to display or hiding a certain error component, enabling symmetrical device pairs for moving selected devices, superimposing contour lines of the selected device movement error, and performing layout packaging and local optimization operations on demand, so as to assist designers in intuitively analyzing errors and fine-tuning the layout.

[0018] Furthermore, the preprocessing module independently scales the physical dimensions of each device according to the overall size for each training example or user-input circuit to maintain relative proportions, and the value range of the relative size ratio is normalized to a unified scale, so that the graph structure neural network can be applied at different process nodes and size scales; the preprocessing module also converts the topological constraint relationship of a given circuit into a corresponding adjacency matrix, where each element of the adjacency matrix is ​​1, indicating that there is a corresponding symmetry, proximity or current flow relationship between the related devices, and is 0, indicating that there is no constraint.

[0019] Furthermore, the graph-structured neural network performs unsupervised training using unlabeled training examples containing only circuit schematic constraint information and device dimensions, wherein each training example consists of normalized dimension information of multiple circuit devices and a corresponding topological constraint adjacency matrix; the graph-structured neural network is driven to learn device layout through the topological loss function; the device dimensions of each training example are independently scaled at input to maintain relative proportions, so that the graph-structured neural network can generalize to new topologies and circuits of different process nodes that did not appear in training.

[0020] Furthermore, after automatically generating candidate solutions, the candidate layout generation module selects the desired solution in the graphical user interface and performs layout fine-tuning. During the layout fine-tuning process, the human-computer interaction module uses error visualization and interactive operations to provide real-time feedback to designers on the impact of the changes on the layout quality, and can assist in decision-making by performing synchronous movement of selected devices, displaying error contours, or recalculating topological errors.

[0021] According to a second aspect of the present disclosure, there is provided an AI-based circuit routing method, which is applied to the above-mentioned system, and includes:

[0022] Obtaining physical size information and topological constraint information of each device of the analog integrated circuit, wherein the topological constraint information includes symmetry constraint, proximity constraint and current flow constraint;

[0023] Normalizing the size information of the devices to obtain relative size ratios of the devices, and converting the topological constraint information into a graph structure adjacency matrix representing relative relationships between the devices;

[0024] Constructing a graph structure neural network model, taking the relative size ratio of the device and the adjacency matrix representing the symmetry constraint, the proximity constraint, and the current flow constraint as input, and taking the two-dimensional coordinates of the device as output, defining a topology loss function during training, calculating the error of the topology loss function, wherein the error of the topology loss function includes symmetry error, proximity error, current flow error, device overlap error, and area waste error, and completing model training by optimizing the topology loss function;

[0025] Automatically generate a plurality of candidate layout solutions that meet topological constraints using the trained graph structure neural network model, each candidate layout solution having corresponding device position coordinates;

[0026] Displaying a layout diagram of each candidate layout solution through a graphical user interface, and providing the area, width, height, corresponding topological error value, and each error component of each candidate layout solution, so that a user can filter and sort the candidate layout solutions according to the error components and area, width, and height;

[0027] For the selected candidate layout solution, based on human-computer interactive operations, device movement, error component weight adjustment, error contour visualization, moving symmetrical devices, layout packaging and local optimization are performed in a graphical user interface, and error changes caused by layout adjustment are fed back in real time;

[0028] Output the final layout plan after automatic generation and human-computer interaction.

[0029] According to a third aspect of the present disclosure, a computer-readable storage medium is provided, storing a computer program, wherein when the computer program is executed by a processor, the AI-based circuit wiring method as described above is implemented.

[0030] According to a fourth aspect of the present disclosure, there is provided an AI-based circuit routing device, comprising: a processor; and a memory arranged to store computer-executable instructions, which, when executed, cause the processor to perform the above-mentioned AI-based circuit routing method.

[0031] The technical solution disclosed in this disclosure has the following beneficial effects:

[0032] The present invention can automatically and quickly generate multiple layout candidate solutions that meet topological constraints, and assist designers in making fine adjustments through an intuitive human-computer interaction interface. It can greatly reduce the complexity and time consumption of analog integrated circuit layout design, reduce the workload of repeated iterations, and thus significantly improve design efficiency and layout quality.

[0033] Furthermore, the topological loss function and device size normalization method proposed in this disclosure enable the toolbox to effectively handle analog circuit layout tasks across diverse circuit topologies and process nodes, demonstrating excellent generalization and practicality. This disclosure allows designers to intuitively understand the impact of layout adjustments on various layout quality metrics, enabling them to quickly develop optimized layout solutions that balance layout compactness, constraint satisfaction, and circuit performance, demonstrating high engineering application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a structural block diagram of an AI-based circuit wiring system in an embodiment of this specification;

[0035] Figure 2 This is a flow chart of an AI-based circuit wiring method in an embodiment of this specification;

[0036] Figure 3 A terminal device for implementing an AI-based circuit wiring method in an embodiment of this specification;

[0037] Figure 4 A computer-readable storage medium storing an AI-based circuit wiring method in an embodiment of this specification. DETAILED DESCRIPTION

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0039] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated description will be omitted. Some of the blocks shown in the accompanying drawings represent functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0040] The present invention provides a product based on AI circuit wiring system. Figure 1 As shown, an AI-based circuit routing system includes an input module 101, a preprocessing module 102, a deep learning module 103, a topology loss calculation module 104, a candidate layout generation module 105, a graphical user interface module 106, a human-computer interaction module 107, and an output module 108, wherein:

[0041] The input module 101 is used to receive information about the physical dimensions of each device in the analog circuit, as well as a description file describing the topological constraints between the device pairs. Specifically, the detailed dimension information of each device in the circuit includes parameters such as the width and height of each device. The description file is a file or data structure used to clearly describe various topological constraints between devices in the analog integrated circuit layout design. For example, these constraints include symmetry constraints, that is, the positions of two devices in the layout must be mirrored along the symmetry axis; proximity constraints, that is, several devices must be close to each other in the layout to reduce parasitic effects; and current flow constraints, that is, the relative positions between devices must satisfy a specific current or signal flow order.

[0042] The pre-processing module 102 normalizes the size information of the components to obtain relative size ratios, and converts the topological constraint relationship into a graph structure adjacency matrix corresponding to the component pairs.

[0043] Specifically, for each training example or user-input circuit, the preprocessing module independently scales the physical dimensions of each device according to the overall size to maintain the relative proportions, and the value range of the relative size ratios is normalized to a unified scale, so that the graph structure neural network can be applied at different process nodes and size scales; the preprocessing module also converts the topological constraint relationship of a given circuit into a corresponding adjacency matrix, where each element of the adjacency matrix is ​​1, indicating that there is a corresponding symmetry, proximity or current flow relationship between the related devices, and 0 indicates that there is no constraint.

[0044] As explained above, the pre-processing module independently scales the device size information in each training example or user-input circuit according to the overall size to maintain the relative proportional relationship between the device sizes, and at the same time normalizes the obtained size ratio values ​​to a fixed scale range. Through this normalization process, the graph structure neural network can maintain good generalization and adaptability when facing device sizes under different process nodes. The pre-processing module also converts the topological constraint relationship of a given circuit into a corresponding plurality of graph structure adjacency matrices based on the topological constraint relationship description file input above. Specifically, for each constraint type (including symmetry constraints, proximity constraints, and current flow constraints), a separate adjacency matrix is ​​generated to describe whether there is a corresponding topological constraint relationship between the device pairs. Each element in the adjacency matrix takes a value of 1 or 0, where a value of 1 indicates that the constraint relationship exists between the corresponding device pairs, and a value of 0 indicates that there is no constraint relationship. This method of describing topological constraints in the form of an adjacency matrix is ​​conducive to efficient training and reasoning of subsequent neural networks.

[0045] The deep learning module 103 is a graph structure neural network, which includes an input layer, several hidden layers and an output layer, wherein the input layer receives the relative size ratio and the adjacency matrix representing the symmetry constraint, proximity constraint and current flow constraint from the preprocessing module as input, and the output layer outputs the two-dimensional plane position coordinates corresponding to each device.

[0046] Specifically, the input layer of the graph structure neural network is a vector of size 2×N, where N is the number of devices in the circuit, and the vector of the input layer contains the normalized width and height of each device; the graph structure neural network also receives three unweighted adjacency matrices of size N×N, which are used to encode symmetry constraints, proximity constraints and current flow constraints, respectively; the graph structure neural network contains four hidden layers, and the number of neurons in each layer is 2500, 1000, 250 and 100 respectively; the output layer of the graph structure neural network generates the x and y coordinates of N devices in a two-dimensional plane.

[0047] During training, the graph-structured neural network performs unsupervised training using unlabeled training examples containing only circuit schematic constraint information and device dimensions, where each training example consists of normalized dimension information of multiple circuit devices and a corresponding topological constraint adjacency matrix. The graph-structured neural network is driven to learn device layout using the topological loss function. The device dimensions of each training example are independently scaled at input to maintain relative proportions, so that the graph-structured neural network can generalize to new topologies and circuits of different process nodes that did not appear in training.

[0048] The topology loss calculation module 104 defines a topology loss function and calculates an error value during the graph structure neural network training process, wherein the error value of the topology loss function includes symmetry constraint error, proximity constraint error, current flow constraint error, device overlap error and area waste error.

[0049] Specifically, the calculation of the topological loss function includes symmetry constraint loss, proximity constraint loss, current flow constraint loss, device overlap loss and area waste loss, and each loss is normalized and summed to form a total loss; wherein, the symmetry constraint loss is obtained by calculating the deviation of the spacing between paired symmetrical devices, the proximity constraint loss is obtained by calculating the deviation between the actual spacing between devices and the specified minimum distance, the current flow constraint loss is obtained by evaluating the connectivity or distance deviation of the devices on the current path, the device overlap loss is obtained by calculating the overlapping area between devices, and the area waste loss is obtained by calculating the difference between the area occupied by all devices and the area of ​​their minimum enclosing rectangle.

[0050] As a supplementary explanation, the topology loss function refers to a mathematical expression used to quantify the difference between the current layout solution and the ideal layout solution when training the graph-structured neural network. By minimizing this loss function, the generated layout can maximize the satisfaction of the topological constraints defined in the circuit design, ultimately improving the quality of the layout solution. Symmetry constraint error refers to the degree to which the actual positions of paired components in the layout deviate from the ideal symmetric positions relative to the specified symmetry axis. For example, if the actual positions of two components that are required to be placed symmetrically are not precisely symmetrical, a certain symmetry constraint error will be generated. This error is specifically calculated by calculating the distance deviation between the actual and ideal symmetric positions of the symmetrical component pair in the layout. Proximity constraint error refers to the error caused by the actual layout spacing of several components that should be closely spaced greater than the expected ideal proximity distance. For example, if certain components need to be close together to reduce parasitic capacitance effects, but are actually farther apart in the layout, this error is reflected by calculating the difference between the actual spacing and the specified minimum ideal spacing. Current flow constraint error refers to the error caused by the relative positioning of components in the layout not strictly adhering to the order of current or signal flow. Specifically, this error is manifested as the degree of deviation caused by components in the defined current flow path in the circuit being positioned outside the specified flow order or being spaced far from the ideal path. For example, if a signal flows from component A to component B and then to component C, a certain order or specific path must exist between components A, B, and C in the layout. Deviation from this path results in a corresponding error. Component overlay error occurs when multiple components overlap or partially overlap in the layout. This error is calculated by directly summing the areas of the actual overlapping regions between components, reflecting the severity of the overlap in the layout. Area waste error, which is the compactness of the layout scheme, has a significant impact on chip manufacturing cost and performance. Area waste error is calculated by calculating the difference between the actual area occupied by all components in the current layout scheme and the area of ​​the smallest rectangle that completely encloses these components (i.e., the minimum bounding rectangle area). It measures the spatial efficiency of the layout scheme. A smaller area waste error indicates a more compact layout and more efficient use of chip area. The various error values ​​included in the topological loss function typically have different dimensions and numerical ranges. To ensure that different error values ​​can be reasonably superimposed and a fair optimization evaluation can be performed, each error term needs to be normalized so that they can be compared and summed on a unified scale. For example, maximum and minimum value normalization or standard deviation normalization can be used. Each error term in the topological loss function can be assigned a corresponding weight coefficient to adjust the importance and influence of each error in the overall layout optimization. If the designer is more concerned with proximity and area waste errors, they can be assigned higher weights, thereby guiding the graph structure neural network training to focus more on optimizing the satisfaction of these constraints.

[0051] The candidate layout generation module 105 automatically generates a plurality of candidate device layout solutions that satisfy the topology loss function based on the trained graph structure neural network.

[0052] Among them, after the candidate layout generation module automatically generates candidate solutions, it selects the required solution in the graphical user interface and performs layout fine-tuning; during the layout fine-tuning process, the human-computer interaction module uses error visualization and interactive operations to provide real-time feedback to designers on the impact of the changes on the layout quality, and can assist decision-making by performing synchronous movement of selected devices, displaying error contours, or recalculating topological errors.

[0053] The graphical user interface module 106 is used to display the layout preview of the candidate layout solutions and the area, width, height, total topological error value and each error component value of each solution, and provides the function of filtering and sorting candidate solutions according to size indicators and error components.

[0054] Specifically, the graphical user interface module includes a candidate layout inspection window and a layout fine-tuning window; the candidate layout inspection window displays a preview image, layout size and corresponding total error and error component information of each candidate layout scheme in the form of a card, and provides users with the function of filtering and sorting according to total error, a certain error component value or layout size range; the layout fine-tuning window provides interactive adjustment functions based on the selected candidate layout scheme, including viewing its related errors by selecting devices on the layout diagram, dynamically adjusting the weights of each topological error component, switching to display or hiding a certain error component, enabling symmetrical device pairs for moving selected devices, superimposing contour lines of the selected device movement error, and performing layout packaging and local optimization operations on demand, so as to assist designers in intuitively analyzing errors and fine-tuning the layout.

[0055] The human-computer interaction module 107 provides a layout fine-tuning function through the graphical user interface. The layout fine-tuning function includes device selection, error visualization, topology error component switch adjustment, constraint weight adjustment, moving symmetrical device pairs, displaying error contours, executing layout packaging and local optimization interactive operations on the visual layout interface to achieve artificial fine-tuning of the selected candidate solutions. By providing real-time feedback on the layout adjustment effect, it helps designers to optimize and fine-tune the layout efficiently and accurately.

[0056] The output module 108 is used to output the final device layout solution after manual fine-tuning or automatic generation.

[0057] Based on the same idea, Figure 2FIG2 is a flow chart of an AI-based circuit wiring method according to an embodiment of the present invention. The method can be applied to electronic devices such as personal computers and servers. The method can be performed by a device, which can be implemented by software and / or hardware. The method can specifically include the following steps S101 to S102:

[0058] In step S101, physical size information and topology constraint information of each device of the analog integrated circuit are obtained, wherein the topology constraint information includes symmetry constraint, proximity constraint and current flow constraint;

[0059] In step S102, the size information of the device is normalized to obtain the relative size ratio of the device, and the topology constraint information is converted into a graph structure adjacency matrix representing the relative relationship of the devices;

[0060] In step S103, a graph structure neural network model is constructed, with the relative size ratio of the device and the adjacency matrix representing the symmetry constraint, the proximity constraint, and the current flow constraint as input, and the two-dimensional coordinates of the device as output. During the training process, a topology loss function is defined, and an error of the topology loss function is calculated, wherein the error of the topology loss function includes a symmetry error, a proximity error, a current flow error, a device overlap error, and an area waste error. Model training is completed by optimizing the topology loss function.

[0061] In step S104, the trained graph structure neural network model is used to automatically generate a number of candidate layout solutions that meet the topological constraints, each of which has corresponding device position coordinates;

[0062] In step S105, a layout diagram of each candidate layout solution is displayed through a graphical user interface, and the area, width, height, corresponding topological error value and each error component of each candidate layout solution are provided, so that a user can filter and sort the candidate layout solutions according to the error components and area, width and height;

[0063] In step S106, for the selected candidate layout solution, based on human-computer interactive operations, component movement, error component weight adjustment, error contour visualization, moving symmetrical components, layout packaging and local optimization are performed in a graphical user interface, and error changes caused by layout adjustment are fed back in real time;

[0064] In step S107 , the final layout solution after automatic generation and human-computer interaction is output.

[0065] Based on this method, it is possible to automatically and quickly generate multiple layout candidate solutions that meet topological constraints, and assist designers in making fine adjustments through an intuitive human-computer interaction interface, which can greatly reduce the complexity and time consumption of analog integrated circuit layout design, reduce the workload of repeated iterations, and thus significantly improve design efficiency and layout quality. In addition, the topological loss function and device size normalization processing method proposed in this method enable the toolbox to effectively handle analog circuit layout tasks of different circuit topologies and process nodes, and has good generalization ability and practicality. With the help of this disclosure, designers can intuitively understand the impact of layout adjustments on various layout quality indicators, and can quickly obtain an optimized layout solution that takes into account layout compactness, constraint satisfaction and circuit performance, which has high engineering application value.

[0066] The specific details of the above method have been described in detail in the implementation of the system part. For the undisclosed details, please refer to the implementation of the system part, so they will not be repeated here.

[0067] Based on the same idea, the embodiment of this specification also provides an AI-based circuit wiring device, such as Figure 4 shown.

[0068] The AI-based circuit wiring device may be the terminal device or server provided in the above-mentioned embodiment.

[0069] AI-based circuit wiring devices can vary significantly due to different configurations or performance. They can include one or more processors 301, memory 302, and a bus. The memory 302 can store one or more storage applications or data. The memory 302 can include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) and / or a cache storage unit, such as a plug-in mobile hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash card (FlashCard), etc. equipped on an electronic device, and can further include a read-only storage unit. The application stored in the memory 302 can include one or more program modules (not shown in the figure). Such program modules include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each of these examples or some combination may include the implementation of a network environment. Furthermore, the processor 301 can be configured to communicate with the memory 302 to execute a series of computer-executable instructions in the memory 302 on the AI-based circuit wiring device. The AI-based circuit wiring device may also include one or more power supplies 303, one or more wired or wireless network interfaces 304, one or more I / O interfaces (input and output interfaces) 305, one or more external devices 306 (e.g., a keyboard), and may also communicate with one or more devices that enable a user to interact with the device, and / or any device that enables the device to communicate with one or more other computing devices (e.g., a router, a network switch, etc.). Such communication may be performed via the I / O interface 305. Furthermore, the device may also communicate with one or more networks (e.g., a local area network (LAN)) via the wired or wireless interface 304.

[0070] In some embodiments, the processor 301 may be composed of an integrated circuit, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and a combination of various control chips. The processor 301 is the control core (Control Unit) of the electronic device, connecting the various components of the entire electronic device using various interfaces and lines, and executing or executing programs or modules stored in the memory 11 (such as the product's AI-based circuit wiring program, etc.), as well as calling data stored in the memory, to perform various functions of the processing device and process data.

[0071] The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable connection and communication between the memory 302 and at least one processor 301, etc.

[0072] The power supply can be logically connected to the at least one processor 301 via a power management device, thereby implementing functions such as charging management, discharging management, and power consumption management through the power management device. The power supply can also include one or more DC or AC power supplies, a recharging device, a power failure detection circuit, a power converter or inverter, a power status indicator, and other arbitrary components. The electronic device 1 can also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which are not further described here.

[0073] Optionally, the processing device may further include a user interface, which may be a display. Optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED display.

[0074] (Organic Light-Emitting Diode, organic light-emitting diode) touch screen, etc. Among them, the display can also be appropriately called a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0075] Figure 3 Only an AI-based circuit wiring device with components is shown, and it can be understood by those skilled in the art that Figure 3 The illustrated structure does not constitute a limitation on the AI-based circuit wiring device, and may include fewer or more components than shown, or combine certain components, or arrange the components differently.

[0076] Specifically, in this embodiment, the AI-based circuit wiring device includes a memory and one or more programs, wherein the one or more programs are stored in the memory, and the one or more programs may include one or more modules, and each module may include a series of computer-executable instructions for the AI-based circuit wiring device, and the one or more programs are configured to be executed by one or more processors, including computer-executable instructions for performing the following:

[0077] Obtaining physical size information and topological constraint information of each device of the analog integrated circuit, wherein the topological constraint information includes symmetry constraint, proximity constraint and current flow constraint;

[0078] Normalizing the size information of the devices to obtain relative size ratios of the devices, and converting the topological constraint information into a graph structure adjacency matrix representing relative relationships between the devices;

[0079] Constructing a graph structure neural network model, taking the relative size ratio of the device and the adjacency matrix representing the symmetry constraint, the proximity constraint, and the current flow constraint as input, and taking the two-dimensional coordinates of the device as output, defining a topology loss function during training, calculating the error of the topology loss function, wherein the error of the topology loss function includes symmetry error, proximity error, current flow error, device overlap error, and area waste error, and completing model training by optimizing the topology loss function;

[0080] Automatically generate a plurality of candidate layout solutions that meet topological constraints using the trained graph structure neural network model, each candidate layout solution having corresponding device position coordinates;

[0081] Displaying a layout diagram of each candidate layout solution through a graphical user interface, and providing the area, width, height, corresponding topological error value, and each error component of each candidate layout solution, so that a user can filter and sort the candidate layout solutions according to the error components and area, width, and height;

[0082] For the selected candidate layout solution, based on human-computer interactive operations, device movement, error component weight adjustment, error contour visualization, moving symmetrical devices, layout packaging and local optimization are performed in a graphical user interface, and error changes caused by layout adjustment are fed back in real time;

[0083] Output the final layout plan after automatic generation and human-computer interaction.

[0084] Based on the same idea, the exemplary embodiments of the present invention further provide a computer-readable storage medium storing a program product capable of implementing the methods described above. In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product comprising program code. When the program product is executed on a terminal device, the program code is configured to cause the terminal device to execute the steps described in the "Exemplary Methods" section above according to various exemplary embodiments of the present disclosure.

[0085] refer to Figure 4As shown, a program 400 for implementing the above method according to an exemplary embodiment of the present disclosure is described. The program 400 may be a portable compact disc read-only memory (CD-ROM) and include program code, and may be run on a terminal device, such as a personal computer. However, the program product of the present disclosure is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0086] The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0087] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0088] Program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, CSS, HTML, and the like, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a standalone software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving a remote computing device, the remote computing device may be connected to the user computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0089] Through the description of the above embodiments, it is easy for those skilled in the art to understand that the example embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the exemplary embodiment of the present disclosure.

[0090] Furthermore, the figures above are merely illustrative of the processes included in the methods according to exemplary embodiments of the present disclosure and are not intended to be limiting. It is readily understood that the processes illustrated in the figures above do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0091] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the exemplary embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0092] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and embodiments are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0093] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An AI-based circuit routing system, characterized in that: The system includes an input module, a preprocessing module, a deep learning module, a topology loss calculation module, a candidate layout generation module, a graphical user interface module, a human-computer interaction module, and an output module, wherein: The input module is used to receive information about each device of the analog circuit and its physical dimensions, and to receive a description file describing a topological constraint relationship between the device pairs; The pre-processing module normalizes the size information of the devices to obtain relative size ratios, and converts the topological constraint relationship into a graph structure adjacency matrix corresponding to the device pairs; The deep learning module is a graph structure neural network, which includes an input layer, a plurality of hidden layers and an output layer, wherein the input layer receives the relative size ratio and the adjacency matrix representing the symmetry constraint, the proximity constraint and the current flow constraint from the preprocessing module as input, and the output layer outputs the two-dimensional plane position coordinates corresponding to each device; The topology loss calculation module defines a topology loss function and calculates an error value during the graph structure neural network training process, wherein the error value of the topology loss function includes a symmetry constraint error, a proximity constraint error, a current flow constraint error, a device overlap error, and an area waste error; The candidate layout generation module automatically generates a plurality of device candidate layout solutions that meet the topology loss function based on the trained graph structure neural network; The graphical user interface module is used to display a preview of the layout of the candidate layout solutions and the area, width, height, total topological error value and each error component value of each solution, and provide a function for screening and sorting the candidate solutions according to size indicators and error components; The human-computer interaction module provides a layout fine-tuning function through the graphical user interface, wherein the layout fine-tuning function includes performing device selection, error visualization, topology error component switch adjustment, constraint weight adjustment, moving symmetrical device pairs, displaying error contours, performing layout packaging, and local optimization interactive operations on the visual layout interface to achieve manual fine-tuning of the selected candidate solution; The output module is used to output the final device layout solution after manual fine-tuning or automatic generation.

2. The AI-based circuit routing system according to claim 1, characterized in that: The input layer of the graph structure neural network is a vector of size 2×N, where N is the number of devices in the circuit, and the vector of the input layer contains the normalized width and height of each device; the graph structure neural network also receives three unweighted adjacency matrices of size N×N, which are used to encode symmetry constraints, proximity constraints, and current flow constraints, respectively; the graph structure neural network includes four hidden layers, and the number of neurons in each layer is 2500, 1000, 250, and 100, respectively; the output layer of the graph structure neural network generates the x and y coordinates of N devices in a two-dimensional plane.

3. The AI-based circuit routing system according to claim 1, wherein: The calculation of the topological loss function includes symmetry constraint loss, proximity constraint loss, current flow constraint loss, device overlap loss and area waste loss, and each loss is normalized and summed to form a total loss; wherein, the symmetry constraint loss is obtained by calculating the deviation of the spacing between paired symmetrical devices, the proximity constraint loss is obtained by calculating the deviation between the actual spacing between devices and the specified minimum distance, the current flow constraint loss is obtained by evaluating the connectivity or distance deviation of the devices on the current path, the device overlap loss is obtained by calculating the overlapping area between devices, and the area waste loss is obtained by calculating the difference between the area occupied by all devices and the area of ​​their minimum enclosing rectangle.

4. The AI-based circuit routing system according to claim 1, wherein: The graphical user interface module includes a candidate layout inspection window and a layout fine-tuning window; the candidate layout inspection window displays a preview image, layout size, and corresponding total error and error component information of each candidate layout scheme in the form of a card, and provides users with the function of filtering and sorting according to total error, a certain error component value, or layout size range; the layout fine-tuning window provides interactive adjustment functions based on the selected candidate layout scheme, including viewing its related errors by selecting devices on the layout diagram, dynamically adjusting the weights of each topological error component, switching to display or hiding a certain error component, enabling symmetrical device pairs for moving selected devices, superimposing contour lines of the selected device movement error, and performing layout packaging and local optimization operations on demand, to assist designers in intuitively analyzing errors and fine-tuning the layout.

5. The AI-based circuit routing system according to claim 1, wherein: The preprocessing module independently scales the physical dimensions of each device in accordance with the overall size for each training example or user-input circuit to maintain relative proportions. The range of values ​​of the relative size ratios is normalized to a uniform scale, thereby making the graph structure neural network applicable at different process nodes and size scales. The pre-processing module also converts the topological constraint relationship of a given circuit into a corresponding adjacency matrix, wherein an element of each adjacency matrix is ​​1, indicating that there is a corresponding symmetry, proximity or current flow relationship between related devices, and 0 indicates no constraint.

6. The AI-based circuit routing system according to claim 1, wherein: The graph-structured neural network performs unsupervised training using unlabeled training examples containing only circuit schematic constraint information and device dimensions, where each training example consists of normalized dimension information of multiple circuit devices and a corresponding topological constraint adjacency matrix. The graph-structured neural network is driven to learn device layout using the topological loss function. The device dimensions of each training example are independently scaled upon input to maintain relative proportions, enabling the graph-structured neural network to generalize to new topologies and circuits of different process nodes that did not appear in training.

7. The AI-based circuit routing system according to claim 1, wherein: After automatically generating candidate solutions, the candidate layout generation module selects the desired solution in the graphical user interface and performs layout fine-tuning. During the layout fine-tuning process, the human-computer interaction module uses error visualization and interactive operations to provide real-time feedback to designers on the impact of the changes on the layout quality, and can assist in decision-making by performing synchronous movement of selected devices, displaying error contours, or recalculating topological errors.

8. An AI-based circuit wiring method, the method being applied to the system according to any one of claims 1 to 7, characterized in that: The method comprises: Obtaining physical size information and topological constraint information of each device of the analog integrated circuit, wherein the topological constraint information includes symmetry constraint, proximity constraint and current flow constraint; Normalizing the size information of the devices to obtain relative size ratios of the devices, and converting the topological constraint information into a graph structure adjacency matrix representing relative relationships between the devices; Constructing a graph structure neural network model, taking the relative size ratio of the device and the adjacency matrix representing the symmetry constraint, the proximity constraint, and the current flow constraint as input, and taking the two-dimensional coordinates of the device as output, defining a topology loss function during training, calculating the error of the topology loss function, wherein the error of the topology loss function includes symmetry error, proximity error, current flow error, device overlap error, and area waste error, and completing model training by optimizing the topology loss function; Automatically generate a plurality of candidate layout solutions that meet topological constraints using the trained graph structure neural network model, each candidate layout solution having corresponding device position coordinates; Displaying a layout diagram of each candidate layout solution through a graphical user interface, and providing the area, width, height, corresponding topological error value, and each error component of each candidate layout solution, so that a user can filter and sort the candidate layout solutions according to the error components and area, width, and height; For the selected candidate layout solution, based on human-computer interactive operations, device movement, error component weight adjustment, error contour visualization, moving symmetrical devices, layout packaging and local optimization are performed in a graphical user interface, and error changes caused by layout adjustment are fed back in real time; Output the final layout plan after automatic generation and human-computer interaction.

9. An AI-based circuit wiring device, characterized in that: The device comprises: and a memory arranged to store computer executable instructions, which, when executed, cause the processor to perform the AI-based circuit wiring method according to claim 8.

10. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the circuit wiring method based on AI according to claim 8 is implemented.

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