Class-AB output stage biasing circuit and method changing along with load current

Abstract

The invention relates to the technical field of integrated circuit design, and particularly discloses a class-AB output stage biasing circuit and method changing along with load current, the circuit comprises an IBOOSTP sink current source, the two ends of the IBOOSTP sink current source are connected in parallel with the source drain electrode of a PMOS tube connected with a power supply in a grid biasing circuit for determining the static current of an output NMOS tube of class-AB, and the IBOOSTP sink current source is connected with the grid biasing circuit. The magnitude of the current is in proportion to the current flowing through the output PMOS tube of the class-AB; two ends of the IBOOSTN pull current source are connected in parallel with a source and a drain of an NMOS (N-channel metal oxide semiconductor) tube connected to the ground in the grid bias circuit for determining the static current of the output PMOS tube of the class-AB, and the size of the IBOOSTN pull current source is proportional to the current flowing through the output NMOS tube of the class-AB. According to the invention, the size of the IBOOSTP sink current source and the size of the IBOOSTN pull current source are respectively proportional to the current flowing through the output PMOS tube and the output NMOS tube of the class-AB, so that the overall gain of the class-AB is increased under the large load current, and the output error is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a class-AB output stage bias circuit and method that follows load current changes. Background Art

[0002] Figure 1 This is a traditional Class AB output op amp that uses a floating current source bias circuit to support bidirectional load current sourcing and sinking. The floating current source bias circuit accurately controls the quiescent current of the Class AB output stage using the following formula.

[0003] The P-side formula is: ; ; The N-side formula is: ; ; Under no-load conditions, the currents of MPOUT and MNOUT are equal, iMPOUT = iMNOUT. Setting the currents of MP9 and MP11 to the same ratio as the width-to-length ratio yields: ; Setting the current of MPOUT / MP10 to the same ratio as the width to length ratio yields: ; So that ; Similarly, set the current and width-to-length ratio of MN9 / MN11 to be the same; ; Set the current of MNOUT / MN10 to be the same as the width-to-length ratio; ; So that ; The total current of MN9 and MP9 is a fixed current 2 i0; When the output needs to support a large source current, the current of MN9 increases and the current of MP9 decreases. The absolute value decreases, The absolute value increases so that the output MPOUT can provide sufficient source current; similarly, when the output needs to support a large sink current, the current of MP9 increases and the current of MN9 decreases. Reduce, Increase so that the output MNOUT can provide sufficient sink current.

[0004] The problems with traditional class AB output op amps are: When the output stage needs to drive a large load current, assuming the load current reaches ground (current sourcing mode), the absolute value of MPOUT's VGS is large, while the absolute value of MP9's VGS is small, causing MP9 to shut down. The entire current flows through MN9, increasing MN9's VGS and lowering VG_NOUT. This excessively low VG_NOUT reduces the Vds of the cascode transistor MN8, forcing MN8 into its linear region. This significantly reduces the gain of the op amp's first stage, lowering the overall gain and increasing the output error.

[0005] Similarly, when the current is poured out and a large current load is applied, the MP8 tube will enter the linear region, which will cause the overall gain of the op amp to decrease and the output error to increase.

[0006] Based on this technical background, the present invention studies a class-AB output stage bias circuit and method that follows load current changes. Summary of the Invention

[0007] To address the shortcomings of the existing technology, the present invention proposes a class-AB output stage bias circuit and method that follows the changes in load current. The circuit increases the overall gain of the class-AB under large load current by setting the sizes of the IBOOSTP sink current source and the IBOOSTN source current source to be proportional to the current flowing through the output PMOS transistor and the output NMOS transistor of the class-AB, respectively.

[0008] To achieve the above objectives, the present invention provides, in a first aspect, a class-AB output stage bias circuit that follows load current variations, comprising: IBOOSTP current sink, with both ends connected in parallel to the source and drain of the PMOS transistor connected to the power supply in the gate bias circuit that determines the static current of the class-AB output NMOS transistor, and the current flowing through the class-AB output PMOS transistor; IBOOSTN pull-up current source, both ends of which are connected in parallel to the source and drain of the NMOS transistor connected to the ground in the gate bias circuit that determines the static current of the output PMOS transistor of the class-AB, and the magnitude of which is proportional to the current flowing through the output NMOS transistor of the class-AB; The IBOOSTP current sink and IBOOSTN current source are used to increase the overall gain of the class-AB under large load current, thereby reducing output error.

[0009] A second aspect of the present invention provides a class-AB output stage biasing method that follows load current changes in the above-mentioned circuit, comprising: In the gate bias circuit that determines the static current of the class-AB output NMOS tube, the source and drain of the PMOS tube connected to the power supply are connected in parallel with the IBOOSTP current sink source; In the gate bias circuit for determining the static current of the class-AB output PMOS tube, a IBOOSTN current source is connected in parallel to the source and drain of the grounded NMOS tube; By setting the sizes of the IBOOSTP current sink and the IBOOSTN current source to be proportional to the currents flowing through the output PMOS transistor and the output NMOS transistor of the class-AB, the overall gain of the class-AB is increased under large load current.

[0010] The beneficial effects of the present invention include: (1) The class-AB output stage bias circuit proposed in the present invention follows the load current change, and by setting the sizes of the IBOOSTP current source and the IBOOSTN current source to be proportional to the current flowing through the output PMOS transistor and the output NMOS transistor of the class-AB, the overall gain of the class-AB is increased under large load current.

[0011] (2) The class-AB output stage bias circuit proposed in the present invention follows the load current change. It can still keep the op amp at high gain output under large current load conditions and supports current source / current sink mode. It accurately replicates the output tube gate-source voltage / drain-source voltage, thereby achieving accurate load current mirroring. When the output is unloaded, the IBOOSTP current source and the IBOOSTN current source are both 0, and the quiescent current does not increase. It adopts open-loop control, which does not affect the stability of the amplifier itself and has a very small area.

[0012] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0014] Figure 1 This is a structural diagram of a traditional class AB output op amp.

[0015] Figure 2 This is a simplified structural diagram of the class-AB output stage bias circuit proposed by the present invention that follows the load current changes.

[0016] Figure 3 This is a structural diagram of a specific embodiment of a class-AB output stage bias circuit that follows load current changes proposed by the present invention.

[0017] Description of reference numerals: MN18-first NMOS input transistor, MN17-second NMOS input transistor, MN16-first NMOS bias transistor, MN14-second NMOS bias transistor, R1-first load resistor, MP16-first PMOS load transistor, MP14-second PMOS load transistor, MP17-first PMOS source output transistor, MPOUT_COPY-second PMOS source output transistor, MP19-first PMOS input transistor, MP20-second PMOS input transistor, MP18-first PMOS bias transistor, MP15-second PMOS bias transistor, R2-second load resistor, MN19-first NMOS load transistor, MN15-second NMOS load transistor Load transistor, MN20 - first NMOS source input transistor, MNOUT_COPY - second NMOS source input transistor, MPOUT - output PMOS transistor, MNOUT - output NMOS transistor, MP9 - PMOS current regulating transistor, MN9 - NMOS current regulating transistor, MN4 - load NMOS transistor adjacent to the PMOS differential input transistor, MN3 - load NMOS transistor not adjacent to the PMOS differential input transistor, MP4 - load PMOS transistor adjacent to the NMOS differential input transistor, MP3 - load PMOS transistor not adjacent to the NMOS differential input transistor, MP13 - PMOS transistor connected to the power supply in the gate bias circuit, MN12 - NMOS transistor connected to the ground in the gate bias circuit; VDD - power supply, VSS - ground, Vnb - second NMOS bias, Vncas - first NMOS bias, Vpb - second PMOS bias, Vpcas - first PMOS bias, VOUT - class-AB output voltage, IL - load current, iMPOUT - PMOS output current, iMN UT - NMOS output current, VOUT_TRACKP - first output voltage follower circuit follower voltage, TRACKPN - second output voltage follower circuit follower voltage, K - ratio, i1 - current flowing through the PMOS current regulator, i2 - current flowing through the NMOS current regulator, i0 - total current flowing through the PMOS and NMOS current regulators, VG_NB - gate voltage of the NMOS current regulator, VG_NOUT - output NMOS gate voltage, VG_PB - gate voltage of the PMOS current regulator, VG_POUT - output PMOS gate voltage, Track Pside - follow P side, Track Nside - follower N side, VG_PCAS - bias voltage, VD_MPOUT_COPY - source voltage of the first PMOS source output tube, VD_MNOUT_COPY - source voltage of the first NMOS source input tube. DETAILED DESCRIPTION

[0018] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0019] In the present invention, unless otherwise specified, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of a device in normal use, and "inner" and "outer" refer to positions relative to the device's outline. Furthermore, the terms "first, second, and third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Therefore, features defined as "first, second, and third" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise explicitly and specifically defined.

[0020] The present invention provides a class-AB output stage bias circuit that follows the load current change, such as Figure 2-3 Shown, including: IBOOSTP is a current sink, with both ends connected in parallel to the source and drain of the PMOS transistor MP13 connected to the power supply VDD in the gate bias circuit that determines the static current of the class-AB output NMOS transistor MNOUT. Its current is proportional to the current flowing through the class-AB output PMOS transistor MPOUT. IBOOSTN pull-up current source, both ends of which are connected in parallel to the source and drain of the NMOS transistor MN12 connected to the ground VSS in the gate bias circuit that determines the static current of the output PMOS transistor MPOUT of the class-AB, and the current flowing through the output NMOS transistor MNOUT of the class-AB; The IBOOSTP current sink and IBOOSTN current source are used to increase the overall gain of the class-AB converter under large load current IL, thereby reducing the output error.

[0021] According to the present invention, the IBOOSTP current sink includes a first output voltage follower circuit and a PMOS source circuit; The first output voltage follower circuit is used to follow the output voltage VOUT of the class-AB and provide a bias voltage for the PMOS source circuit; The source end of the PMOS source circuit is electrically connected to the drain of the PMOS transistor MP13 connected to the power supply VDD in the gate bias circuit that determines the static current of the class-AB output NMOS transistor MNOUT.

[0022] According to the present invention, the IBOOSTN current source includes a second output voltage follower circuit and an NMOS source input circuit; The second output voltage follower circuit is used to follow the output voltage VOUT of the class-AB and provide a bias voltage for the NMOS source input circuit; The source input terminal of the NMOS source input circuit is electrically connected to the drain of the NMOS transistor MN12 connected to the ground VSS in the gate bias circuit that determines the static current of the output PMOS transistor MPOUT of the class-AB.

[0023] According to the present invention, the first output voltage follower circuit includes: A first NMOS input transistor MN18, the gate of which is electrically connected to the output voltage VOUT of class-AB; The source of the second NMOS input transistor MN17 is electrically connected to the source of the first NMOS input transistor MN18; A first NMOS bias transistor MN16, having a drain electrically connected to the source of the first NMOS input transistor MN18, and a gate electrically connected to a first NMOS bias voltage Vncas of class-AB; A second NMOS bias transistor MN14, having a drain electrically connected to the source of the first NMOS bias transistor MN16, a source electrically connected to the ground VSS, and a gate electrically connected to a second NMOS bias voltage Vnb of class-AB; A first load resistor R1, one end of which is electrically connected to the power supply VDD, and the other end of which is electrically connected to the drain of the first NMOS input transistor MN18; The first PMOS load transistor MP16 has a drain electrically connected to the drain of the second NMOS input transistor MN17 and a gate electrically connected to its own drain; The second PMOS load transistor MP14 has a drain electrically connected to the gate of the second NMOS input transistor MN17 and the source of the first PMOS load transistor MP16, a source electrically connected to the power supply VDD, and a gate electrically connected to the second PMOS bias voltage Vpb of class-AB; The PMOS source circuit includes: A first PMOS source transistor MP17, having a drain electrically connected to the drain of a PMOS transistor MP13 connected to a power supply VDD in a gate bias circuit for determining a static current of a class-AB output NMOS transistor MNOUT, and a gate electrically connected to the gate of a first PMOS load transistor MP16; The second PMOS source output transistor MPOUT_COPY has a drain electrically connected to the source of the first PMOS source output transistor MP17, a source electrically connected to the power supply VDD, and a gate electrically connected to the gate of the class-AB output PMOS.

[0024] According to the present invention, the second output voltage follower circuit includes: A first PMOS input transistor MP19, the gate of which is electrically connected to the output voltage VOUT of class-AB; The second PMOS input transistor MP20 has a source electrically connected to the source of the first PMOS input transistor MP19; A first PMOS bias transistor MP18, having a drain electrically connected to the source of the first PMOS input transistor MP19, and a gate electrically connected to a first PMOS bias voltage Vpcas of class-AB; A second PMOS bias transistor MP15, having a drain electrically connected to the source of the first PMOS bias transistor MP18, a source electrically connected to the power supply VDD, and a gate electrically connected to the second PMOS bias voltage Vpb of the class-AB input stage; A second load resistor R2, one end of which is electrically connected to the ground VSS, and the other end of which is electrically connected to the drain of the first PMOS input transistor MP19; The first NMOS load transistor MN19 has a drain electrically connected to the drain of the second PMOS input transistor MP20 and a gate electrically connected to its own drain; The second NMOS load transistor MN15 has a drain electrically connected to the gate of the second PMOS input transistor MP20 and the source of the first NMOS load transistor MN19, a source electrically connected to the power supply VDD, and a gate electrically connected to the second NMOS bias voltage Vnb of class-AB; The NMOS source input circuit includes: A first NMOS source input transistor MN20, having a drain electrically connected to the drain of the NMOS transistor MN12 connected to the ground VSS in the gate bias circuit for determining the static current of the class-AB output PMOS transistor MPOUT, and a gate electrically connected to the gate of the first NMOS load transistor MN19; The second NMOS source input transistor MNOUT_COPY has a drain electrically connected to the source of the first NMOS source output transistor, a source electrically connected to the ground VSS, and a gate electrically connected to the gate of the class-AB output NMOS.

[0025] According to the present invention, the first NMOS bias voltage Vncas is the gate bias voltage of the load NMOS transistor MN4 adjacent to the class-AB PMOS differential input transistor; The second NMOS bias voltage Vnb is the gate bias voltage of the non-adjacent load NMOS transistor MN3 of the class-AB PMOS differential input transistor; The first PMOS bias voltage Vpcas is the gate bias voltage of the load PMOS transistor MP4 adjacent to the class-AB NMOS differential input transistor; The second PMOS bias voltage Vpb is a gate bias voltage of a non-adjacent load PMOS transistor MP3 of a class-AB NMOS differential input transistor.

[0026] According to the present invention, the first NMOS input transistor MN18 and the second NMOS input transistor MN17 have the same size; The first PMOS input transistor MP19 and the second PMOS input transistor MP20 have the same size; The ratio of the size of the second PMOS source output tube MPOUT_COPY to the size of the output PMOS of class-AB, the ratio of the size of the second NMOS source output tube to the size of the output NMOS of class-AB, the ratio of the IBOOSTP sink current source to the current flowing through the output PMOS tube MPOUT of class-AB, and the ratio of the IBOOSTN source current source to the current flowing through the output NMOS tube MNOUT of class-AB are all the same, and the value of this ratio is much less than 1.

[0027] According to the present invention, the class-AB input stage adopts a rail-to-rail folded cascode structure.

[0028] The present invention also provides a method performed in the above bias circuit, comprising: In the gate bias circuit for determining the static current of the class-AB output NMOS transistor MNOUT, the source and drain of the PMOS transistor MP13 connected to the power supply VDD is connected in parallel with the IBOOSTP current sink source; In the gate bias circuit for determining the static current of the class-AB output PMOS transistor MPOUT, a current source IBOOSTN is connected in parallel to the source and drain of the NMOS transistor MN12 connected to the ground VSS; By setting the sizes of the IBOOSTP sink current source and the IBOOSTN source current source to be proportional to the current flowing through the output PMOS transistor MPOUT and the output NMOS transistor MNOUT of the class-AB, the overall gain of the class-AB can be increased under large load current IL.

[0029] According to the present invention, it also includes: Set the first NMOS input transistor MN18 and the second NMOS input transistor MN17 of the IBOOSTP current sink to have the same size, and set the first PMOS input transistor MP19 and the second PMOS input transistor MP20 of the IBOOSTN current source to have the same size; The ratio of the size of the second PMOS source transistor MPOUT_COPY to the size of the output PMOS of class-AB, the ratio of the size of the second NMOS source transistor to the size of the output NMOS of class-AB, the ratio of the IBOOSTP current source to the current flowing through the output PMOS transistor MPOUT of class-AB, and the ratio of the IBOOSTN current source to the current flowing through the output NMOS transistor MNOUT of class-AB are all the same, and the value of this ratio is much less than 1. While achieving accurate load current IL mirroring, it is ensured that the quiescent current of class-AB does not increase when the output is no-loaded. The gate voltage of the output PMOS transistor MPOUT of class-AB is VG_POUT, and the gate voltage of the output NMOS transistor MNOUT of class-AB is VG_NOUT.

[0030] The present invention will be described in more detail below through specific examples.

[0031] Example 1

[0032] like Figure 2-3 As shown, this embodiment provides a class-AB output stage bias circuit that follows the load current, including: IBOOSTP is a current sink, with both ends connected in parallel to the source and drain of the PMOS transistor MP13 connected to the power supply VDD in the gate bias circuit that determines the static current of the class-AB output NMOS transistor MNOUT. Its current is proportional to the current flowing through the class-AB output PMOS transistor MPOUT. IBOOSTN pull-up current source, both ends of which are connected in parallel to the source and drain of the NMOS transistor MN12 connected to the ground VSS in the gate bias circuit that determines the static current of the output PMOS transistor MPOUT of the class-AB, and the current flowing through the output NMOS transistor MNOUT of the class-AB; The IBOOSTP current sink includes a first output voltage follower circuit and a PMOS source circuit; The first output voltage follower circuit is used to follow the output voltage VOUT of the class-AB and provide a bias voltage for the PMOS source circuit; The source end of the PMOS source circuit is electrically connected to the drain of the PMOS transistor MP13 connected to the power supply VDD in the gate bias circuit for determining the static current of the output NMOS transistor MNOUT of the class-AB; The IBOOSTN pull-up current source includes a second output voltage follower circuit and an NMOS source input circuit; The second output voltage follower circuit is used to follow the output voltage VOUT of the class-AB and provide a bias voltage for the NMOS source input circuit; The source input terminal of the NMOS source input circuit is electrically connected to the drain of the NMOS transistor MN12 connected to the ground VSS in the gate bias circuit that determines the static current of the output PMOS transistor MPOUT of the class-AB; The first output voltage follower circuit includes: A first NMOS input transistor MN18, the gate of which is electrically connected to the output voltage VOUT of class-AB; The source of the second NMOS input transistor MN17 is electrically connected to the source of the first NMOS input transistor MN18; A first NMOS bias transistor MN16, having a drain electrically connected to the source of the first NMOS input transistor MN18, and a gate electrically connected to a first NMOS bias voltage Vncas of class-AB; A second NMOS bias transistor MN14, having a drain electrically connected to the source of the first NMOS bias transistor MN16, a source electrically connected to the ground VSS, and a gate electrically connected to a second NMOS bias voltage Vnb of class-AB; A first load resistor R1, one end of which is electrically connected to the power supply VDD, and the other end of which is electrically connected to the drain of the first NMOS input transistor MN18; The first PMOS load transistor MP16 has a drain electrically connected to the drain of the second NMOS input transistor MN17 and a gate electrically connected to its own drain; The second PMOS load transistor MP14 has a drain electrically connected to the gate of the second NMOS input transistor MN17 and the source of the first PMOS load transistor MP16, a source electrically connected to the power supply VDD, and a gate electrically connected to the second PMOS bias voltage Vpb of class-AB; The PMOS source circuit includes: A first PMOS source transistor MP17, having a drain electrically connected to the drain of a PMOS transistor MP13 connected to a power supply VDD in a gate bias circuit for determining a static current of a class-AB output NMOS transistor MNOUT, and a gate electrically connected to the gate of a first PMOS load transistor MP16; The second PMOS source output transistor MPOUT_COPY has a drain electrically connected to the source of the first PMOS source output transistor MP17, a source electrically connected to the power supply VDD, and a gate electrically connected to the gate of the class-AB output PMOS; The second output voltage follower circuit includes: A first PMOS input transistor MP19, the gate of which is electrically connected to the output voltage VOUT of class-AB; The second PMOS input transistor MP20 has a source electrically connected to the source of the first PMOS input transistor MP19; A first PMOS bias transistor MP18, having a drain electrically connected to the source of the first PMOS input transistor MP19, and a gate electrically connected to a first PMOS bias voltage Vpcas of class-AB; A second PMOS bias transistor MP15, having a drain electrically connected to the source of the first PMOS bias transistor MP18, a source electrically connected to the power supply VDD, and a gate electrically connected to the second PMOS bias voltage Vpb of the class-AB input stage; A second load resistor R2, one end of which is electrically connected to the ground VSS, and the other end of which is electrically connected to the drain of the first PMOS input transistor MP19; The first NMOS load transistor MN19 has a drain electrically connected to the drain of the second PMOS input transistor MP20 and a gate electrically connected to its own drain; The second NMOS load transistor MN15 has a drain electrically connected to the gate of the second PMOS input transistor MP20 and the source of the first NMOS load transistor MN19, a source electrically connected to the power supply VDD, and a gate electrically connected to the second NMOS bias voltage Vnb of class-AB; The NMOS source input circuit includes: A first NMOS source input transistor MN20, having a drain electrically connected to the drain of the NMOS transistor MN12 connected to the ground VSS in the gate bias circuit for determining the static current of the class-AB output PMOS transistor MPOUT, and a gate electrically connected to the gate of the first NMOS load transistor MN19; A second NMOS source input transistor MNOUT_COPY, having a drain electrically connected to the source of the first NMOS source output transistor, a source electrically connected to ground VSS, and a gate electrically connected to the gate of the class-AB output NMOS; In this embodiment, the first NMOS bias voltage Vncas is the gate bias voltage of the load NMOS transistor MN4 adjacent to the class-AB PMOS differential input transistor; The second NMOS bias voltage Vnb is the gate bias voltage of the non-adjacent load NMOS transistor MN3 of the class-AB PMOS differential input transistor; The first PMOS bias voltage Vpcas is the gate bias voltage of the load PMOS transistor MP4 adjacent to the class-AB NMOS differential input transistor; The second PMOS bias voltage Vpb is the gate bias voltage of the non-adjacent load PMOS transistor MP3 of the class-AB NMOS differential input transistor; In this embodiment, the first NMOS input transistor MN18 and the second NMOS input transistor MN17 have the same size; The first PMOS input transistor MP19 and the second PMOS input transistor MP20 have the same size; The ratio of the size of the second PMOS source output transistor MPOUT_COPY to the size of the output PMOS transistor of class-AB, the ratio of the size of the second NMOS source output transistor to the size of the output NMOS transistor of class-AB, the ratio of the IBOOSTP current source to the current flowing through the output PMOS transistor MPOUT of class-AB, and the ratio of the IBOOSTN current source to the current flowing through the output NMOS transistor MNOUT of class-AB are all the same, and the values ​​of these ratios are much less than 1; In this embodiment, the class-AB input stage adopts the existing rail-to-rail folded cascode structure.

[0033] The working principle of the class-AB output stage bias circuit that follows the load current change proposed by the present invention is: like Figure 2 As shown, the current IBOOSTP / IBOOSTN proportional to the output current iMPOUT / iMNOUT of the PMOS / NMOS tube is added to the existing class-AB structure; Taking the source output current as an example, assuming that the load current IL increases, iMPOUT increases, and IBOOSTP increases proportionally; the VGS of MN10 / MN11 in the gate bias circuit of the NMOS current regulating transistor MN9 increases, and the gate voltage VG_NB of the NMOS current regulating transistor MN9 becomes higher; even if MP9 is completely turned off, 2 The entire current i0 (the total current flowing through the PMOS and NMOS current regulating transistors) flows through the NMOS current regulating transistor MN9. As the gate voltage VG_NB of the NMOS current regulating transistor MN9 increases, the gate voltage VG_NOUT of the output NMOS transistor increases, which increases the Vds of the NMOS transistor MN8, allowing it to operate in the saturation region. Under high load current, the overall gain of the op amp is higher than that of the traditional structure, and the output absolute error is smaller. The sink current output is similar to the source current mode. As the load current IL increases, IBOOSTN increases proportionally, resulting in lower gate voltages of the PMOS current regulator and output PMOS gate voltages VG_PB and VG_POUT. The absolute value of Vds across the PMOS MP8 increases, allowing it to operate in the saturation region. Under high load current IL, the overall gain of the op amp is higher than with conventional gain, and the absolute output error is smaller. Under low current load or no-load conditions, IBOOSTP / IBOOSTN are very small. Compared with the traditional structure, the quiescent current remains unchanged and the gain is similar. The specific working principle of the class-AB output stage bias circuit that follows the load current change proposed by the present invention is: like Figure 3 As shown, take Track Pside as an example. The same applies to Track Nside: The output voltage VOUT of class-AB is connected to the gate of the first NMOS input transistor MN18, which is the input of the first output voltage follower circuit that follows the P-side Track Pside. The second NMOS input transistor MN17 and the first NMOS input transistor MN18 have the same size. The current of the second NMOS bias transistor MN14 is twice the current of the second PMOS load transistor MP14, so that the current flowing through the second NMOS input transistor MN17 and the first NMOS input transistor MN18 are equal. , so the voltage of the first output voltage follower circuit following the voltage VOUT_TRACKP is approximately equal to the output voltage VOUT of class-AB; Current flows through the diode-connected first PMOS load transistor MP16 MP16 to generate a bias voltage VG_PCAS to bias the first PMOS source output transistor MP17. The source voltage VD_MPOUT_COPY of the first PMOS source output transistor MP17 is approximately equal to the first output voltage follower circuit follower voltage VOUT_TRACKP (class-AB output voltage VOUT). The gate voltage VG_POUT of the class-AB output PMOS transistor MPOUT is connected to the source voltage MPOUT_COPY of the first PMOS source transistor MP17. The VGS voltages of the class-AB output PMOS transistor MPOUTMPOUT and the second PMOS source transistor MPOUT_COPY are equal, and their VDS voltages are also similar. Therefore, the size of the second PMOS source transistor MPOUT_COPY is set to K times the size of the class-AB output PMOS transistor MPOUT. The K-fold current can be obtained as follows: IBOOSTP=K iMPOUT; (usually set K<<1); The same principle is used to implement Track Nside following P side: IBOOSTN=K iMNOUT.

[0034] The class-AB output stage bias circuit proposed in the embodiments of the present invention, which follows the load current changes, can still enable the op amp to maintain high gain output under large current load conditions, while supporting current sourcing / sinking modes; accurately replicate the output tube gate-source voltage / drain-source voltage, thereby achieving accurate load current mirroring; when the output is unloaded, the IBOOSTP sink current source and the IBOOSTN source current source are both 0, and the quiescent current does not increase; open-loop control is adopted, which does not affect the stability of the amplifier itself and has a very small area.

[0035] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A class-AB output stage bias circuit that follows load current variations, characterized in that: include: IBOOSTP current sink, with both ends connected in parallel to the source and drain of the PMOS transistor connected to the power supply in the gate bias circuit that determines the static current of the class-AB output NMOS transistor, and the current flowing through the class-AB output PMOS transistor; IBOOSTN pull-up current source, both ends of which are connected in parallel to the source and drain of the NMOS transistor connected to the ground in the gate bias circuit that determines the static current of the output PMOS transistor of the class-AB, and the magnitude of which is proportional to the current flowing through the output NMOS transistor of the class-AB; The IBOOSTP current sink and IBOOSTN current source are used to increase the overall gain of the class-AB under large load current, thereby reducing output error.

2. The bias circuit according to claim 1, wherein: The IBOOSTP current sink includes a first output voltage follower circuit and a PMOS source circuit; The first output voltage follower circuit is used to follow the output voltage of the class-AB and provide a bias voltage for the PMOS source circuit; The source end of the PMOS source circuit is electrically connected to the drain of the PMOS tube connected to the power supply in the gate bias circuit that determines the static current of the class-AB output NMOS tube.

3. The bias circuit according to claim 1, wherein: The IBOOSTN current source includes a second output voltage follower circuit and an NMOS source input circuit; The second output voltage follower circuit is used to follow the output voltage of the class-AB and provide a bias voltage for the NMOS source input circuit; The source input terminal of the NMOS source input circuit is electrically connected to the drain of the NMOS tube connected to the ground in the gate bias circuit that determines the static current of the output PMOS tube of the class-AB.

4. The bias circuit according to claim 2, wherein: The first output voltage follower circuit includes: A first NMOS input transistor, the gate of which is electrically connected to the output voltage of the class-AB; a second NMOS input tube, a source of which is electrically connected to the source of the first NMOS input tube; a first NMOS bias transistor, the drain of which is electrically connected to the source of the first NMOS input transistor, and the gate of which is electrically connected to the first NMOS bias of the class-AB transistor; a second NMOS bias transistor, wherein the drain is electrically connected to the source of the first NMOS bias transistor, the source is electrically connected to the ground, and the gate is electrically connected to the second NMOS bias transistor of class-AB; a first load resistor, one end of which is electrically connected to the power supply, and the other end of which is electrically connected to the drain of the first NMOS input transistor; a first PMOS load transistor, having a drain electrically connected to the drain of the second NMOS input transistor and a gate electrically connected to its own drain; A second PMOS load transistor, whose drain is electrically connected to the gate of the second NMOS input transistor and the source of the first PMOS load transistor, whose source is electrically connected to a power supply, and whose gate is electrically connected to the second PMOS bias of the class-AB; The PMOS source circuit includes: A first PMOS source transistor, having a drain electrically connected to the drain of a PMOS transistor connected to a power supply in a gate bias circuit for determining a static current of a class-AB output NMOS transistor, and a gate electrically connected to the gate of the first PMOS load transistor; A second PMOS source-output transistor has a drain electrically connected to the source of the first PMOS source-output transistor, a source electrically connected to a power supply, and a gate electrically connected to the gate of the class-AB output PMOS transistor.

5. The bias circuit according to claim 3, wherein: The second output voltage follower circuit includes: A first PMOS input transistor, a gate of which is electrically connected to the output voltage of the class-AB; a second PMOS input tube, a source of which is electrically connected to the source of the first PMOS input tube; a first PMOS bias transistor, having a drain electrically connected to the source of the first PMOS input transistor and a gate electrically connected to the first PMOS bias of the class-AB transistor; a second PMOS bias transistor, having a drain electrically connected to the source of the first PMOS bias transistor, a source electrically connected to a power supply, and a gate electrically connected to the second PMOS bias of the class-AB input stage; a second load resistor, one end of which is electrically connected to the ground, and the other end of which is electrically connected to the drain of the first PMOS input transistor; a first NMOS load transistor, having a drain electrically connected to the drain of the second PMOS input transistor and a gate electrically connected to its own drain; A second NMOS load transistor, the drain of which is electrically connected to the gate of the second PMOS input transistor and the source of the first NMOS load transistor, the source of which is electrically connected to a power supply, and the gate of which is electrically connected to the second NMOS bias of the class-AB; The NMOS source input circuit includes: a first NMOS source input transistor, whose drain is electrically connected to the drain of an NMOS transistor connected to ground in a gate bias circuit for determining the static current of the class-AB output PMOS transistor, and whose gate is electrically connected to the gate of the first NMOS load transistor; The second NMOS source input tube has a drain electrically connected to the source of the first NMOS source output tube, a source electrically connected to the ground, and a gate electrically connected to the gate of the class-AB output NMOS tube.

6. The bias circuit according to claim 4 or 5, characterized in that: The first NMOS bias voltage is the gate bias voltage of the load NMOS transistor adjacent to the class-AB PMOS differential input transistor; The second NMOS bias voltage is the gate bias voltage of the non-adjacent load NMOS transistor of the class-AB PMOS differential input transistor; The first PMOS bias voltage is the gate bias voltage of the load PMOS transistor adjacent to the class-AB NMOS differential input transistor; The second PMOS bias voltage is a gate bias voltage of a non-adjacent load PMOS transistor of the class-AB NMOS differential input transistor.

7. The bias circuit according to claim 4 or 5, characterized in that: The first NMOS input tube has the same size as the second NMOS input tube; The first PMOS input tube has the same size as the second PMOS input tube; The ratio of the size of the second PMOS source tube to the size of the output PMOS tube of the class-AB, the ratio of the size of the second NMOS source tube to the size of the output NMOS tube of the class-AB, the ratio of the IBOOSTP current sink and the current flowing through the output PMOS tube of the class-AB, and the ratio of the IBOOSTN current source and the current flowing through the output NMOS tube of the class-AB are all the same, and the value of the ratio is much less than 1.

8. The bias circuit according to claim 1, wherein: The class-AB input stage adopts a rail-to-rail folded cascode structure.

9. A method performed in the bias circuit according to any one of claims 1 to 8, characterized in that: include: In the gate bias circuit that determines the static current of the class-AB output NMOS tube, the source and drain of the PMOS tube connected to the power supply are connected in parallel with the IBOOSTP current sink source; An IBOOSTN current source is connected in parallel to the source and drain of an NMOS transistor connected to ground in a gate bias circuit that determines the static current of the output PMOS transistor of the class-AB; By setting the sizes of the IBOOSTP current sink and the IBOOSTN current source to be proportional to the currents flowing through the output PMOS transistor and the output NMOS transistor of the class-AB, the overall gain of the class-AB is increased under large load current.

10. The method according to claim 9, characterized in that Also includes: Setting the size of the first NMOS input tube and the second NMOS input tube in the IBOOSTP current sink to be the same as that of the second NMOS input tube, and setting the size of the first PMOS input tube and the second PMOS input tube in the IBOOSTN current source to be the same as that of the first PMOS input tube; The ratio of the size of the second PMOS source tube to the size of the output PMOS tube of the class-AB, the ratio of the size of the second NMOS source tube to the size of the output NMOS tube of the class-AB, the ratio of the IBOOSTP current sink and the current flowing through the output PMOS tube of the class-AB, and the ratio of the IBOOSTN current source and the current flowing through the output NMOS tube of the class-AB are all the same, and the value of the ratio is much less than 1, while achieving accurate load current mirroring and ensuring that the static current of the class-AB does not increase when the output is no-loaded.

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