On-chip calibration source circuit and chip for radio frequency direct acquisition receiving link

Abstract

The invention provides an on-chip calibration source circuit and a chip for a radio frequency direct acquisition receiving link, the on-chip calibration source circuit comprises a clock signal output circuit and a differential current signal output circuit, the output end of the clock signal output circuit is connected with the input end of the differential current signal output circuit; the output end of the differential current signal output circuit is movably connected with the input end of the variable gain amplifier; the clock signal output circuit is used for outputting a clock signal to the differential current signal output circuit; the differential current signal output circuit is used for generating a first calibration signal according to an input clock signal and outputting the first calibration signal to the variable gain amplifier, and the first calibration signal is a differential current signal; the first calibration signal is used for performing error calibration on the variable gain amplifier; the variable gain amplifier is used for outputting a second calibration signal to the time-interleaved analog-to-digital converter according to the first calibration signal; the second calibration signal is used for performing error calibration on the time-interleaved analog-to-digital converter.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an on-chip calibration source circuit and chip for a radio frequency direct acquisition receiving link. Background Art

[0002] With the rapid development of 5G communications in recent years, low-cost, high-performance RF receive links have become a new research hotspot with broad application prospects. Among these, direct RF receive links (RX) have gradually become the mainstream. Compared with traditional frequency conversion receive solutions, they eliminate the need for frequency mixing and numerous passive matching circuits, offering significant cost and size advantages and strong competitiveness.

[0003] A high-speed RF direct-source receiver link typically consists of a cascaded digital variable gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC). The DVGA receives the RF signal and performs amplification, attenuation, and filtering. The TI-ADC samples and quantizes the analog output signal, converting it into a digital signal. DVGAs often exhibit phase shift errors, while TI-ADCs often exhibit errors such as sub-channel gain mismatch (TI gain), sub-channel sampling time mismatch (TI skew), and sub-channel offset mismatch (TI offset). These errors affect the normal operation and performance of the RX, necessitating error calibration.

[0004] In related technologies, commonly used calibration methods include off-chip and on-chip. The off-chip calibration method involves injecting a required calibration signal (typically a square wave or sinusoidal signal) into the RX from the outside. However, the off-chip calibration method suffers from poor integration and inconvenience, requiring complex test instruments and precise manual intervention. On-chip calibration typically requires calibrating the TI-ADC and DVGA separately through different paths, and the calibration source typically uses voltage signal transmission, which can cause signal distortion during transmission. Therefore, additional AC (Alternating Current) coupling capacitors are required when calibrating the DVGA to prevent affecting the DVGA's common-mode operating point. Summary of the Invention

[0005] The present application provides an on-chip calibration source circuit and chip for a radio frequency direct acquisition receiving link.

[0006] An embodiment of the present application provides an on-chip calibration source circuit for a radio frequency direct acquisition receive link, the radio frequency direct acquisition receive link including a variable gain amplifier and a time-interleaved analog-to-digital converter. The on-chip calibration source circuit includes: a clock signal output circuit and a differential current signal output circuit, wherein the output of the clock signal output circuit is connected to the input of the differential current signal output circuit, the output of the differential current signal output circuit is movably connected to the input of the variable gain amplifier, and the output of the variable gain amplifier is connected to the input of the time-interleaved analog-to-digital converter;

[0007] The clock signal output circuit is used to output a clock signal to the differential current signal output circuit;

[0008] The differential current signal output circuit is used to generate a first calibration signal according to the input clock signal, and output the first calibration signal to the variable gain amplifier, where the first calibration signal is a differential current signal;

[0009] The first calibration signal is used to perform error calibration on the variable gain amplifier;

[0010] The variable gain amplifier is used to output a second calibration signal to the time-interleaved analog-to-digital converter according to the first calibration signal, where the second calibration signal is a voltage signal;

[0011] The second calibration signal is used to perform error calibration on the time-interleaved analog-to-digital converter.

[0012] An embodiment of the present application provides a chip, including a radio frequency direct acquisition receiving link and an on-chip calibration source circuit, wherein the radio frequency direct acquisition receiving link includes a variable gain amplifier and a time-interleaved analog-to-digital converter, and the on-chip calibration source circuit includes the above-mentioned on-chip calibration source circuit.

[0013] According to an on-chip calibration source circuit and chip for a radio frequency direct acquisition receive link according to an embodiment of the present application, a differential current signal output circuit generates a first calibration signal for calibrating the radio frequency direct acquisition receive link under the action of a clock signal output by a clock signal output circuit. The first calibration signal is a differential current signal. The use of differential current signal transmission reduces the requirements for the signal transmission path, effectively ensures the quality of the signal during transmission, and obtains an undistorted, high-quality calibration signal. No coupling capacitor is required on the transmission path, and the equivalent parasitic capacitance on the transmission path is small, which has little impact on the RX link. Since the variable gain amplifier is a resistive load and the time-interleaved analog-to-digital converter is a capacitive load, these two load characteristics are utilized to directly inject the first calibration signal at the input of the variable gain amplifier to perform error calibration of the variable gain amplifier. The first calibration signal can then be restored to a voltage signal after passing through the variable gain amplifier and input into the time-interleaved analog-to-digital converter for error calibration. That is, the first calibration signal output by the on-chip calibration source circuit is directly injected into the input of the RX, which can complete the error calibration of the variable gain amplifier and the time-interleaved analog-to-digital converter at one time, without adding additional paths to calibrate the time-interleaved analog-to-digital converter.

[0014] With respect to the above embodiments and other aspects of the present application and their implementation, further description is provided in the accompanying drawings, detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the accompanying drawings of the embodiments of the present application:

[0016] Figure 1 A schematic diagram showing the working principle of a time-interleaved analog-to-digital converter provided in an embodiment of the present application is shown.

[0017] Figure 2 A block diagram of the composition of an on-chip calibration source circuit for a radio frequency direct acquisition receiving link provided in an embodiment of the present application is shown.

[0018] Figure 3 A block diagram of a differential current driving circuit provided in an embodiment of the present application is shown.

[0019] Figure 4 A circuit structure schematic diagram of a differential current driving circuit provided in an embodiment of the present application is shown.

[0020] Figure 5 A circuit structure schematic diagram of a differential current signal output circuit provided in an embodiment of the present application is shown.

[0021] Figure 6 A timing diagram of n groups of clock signals corresponding to n groups of differential current driving circuits in an embodiment of the present application is shown.

[0022] Figure 7A schematic diagram showing waveforms of voltage signals restored from signals output by n groups of differential current driving circuits in an embodiment of the present application.

[0023] Figure 8 A block diagram showing the composition of another on-chip calibration source circuit provided in an embodiment of the present application is shown.

[0024] Figure 9 A block diagram showing the composition of another on-chip calibration source circuit provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0026] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0027] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0028] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0029] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0030] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0032] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0033] In related technologies, a high-speed RF direct-source receive link typically consists of a cascaded variable-gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC). The DVGA receives the RF signal and performs amplification, attenuation, and filtering. The TI-ADC samples and quantizes the analog signal output by the DVGA, converting it into a digital signal.

[0034] The analog-to-digital converter (ADC) of the high-speed RF direct sampling receiving link basically uses TI-ADC to increase the operating frequency. Figure 1 FIG. 1 is a schematic diagram showing the working principle of a time-interleaved analog-to-digital converter provided by an embodiment of the present application. Figure 1 As shown, the TI-ADC uses M sub-analog-to-digital converters (subADCs) with a sampling rate of Fs / M, alternating and sampling in parallel with a fixed phase offset of 360° / M, achieving a total sampling rate M times that of the subADCs. Each ADC sequentially samples, quantizes, and encodes the input signal, then outputs it through a multiplexer (MUX). However, due to circuit design limitations and manufacturing process variations, mismatches and inconsistent performance will inevitably exist between the M subADCs, which are more pronounced at high frequencies. Consequently, TI-ADCs often exhibit errors such as sub-channel gain mismatch (TI gain), sub-channel sampling time mismatch (TI skew), and sub-channel offset mismatch (TI offset), severely impacting performance. A wideband RF direct-visible gain amplifier (DVGA) typically consists of an adjustable attenuator (ATT) and a low-noise amplifier (LNA). However, each gain adjustment produces a different phase shift, resulting in phase shift errors. These errors can affect the normal operation and performance of the RX, necessitating error calibration.

[0035] In related technologies, commonly used calibration methods include off-chip and on-chip. The off-chip calibration method involves injecting a required calibration signal (typically a square wave or sinusoidal signal) into the RX from the outside. However, the off-chip calibration method suffers from poor integration and inconvenience, requiring complex test instruments and precise manual intervention. On-chip calibration typically requires calibrating the TI-ADC and DVGA separately through different paths, and the calibration source typically uses voltage signal transmission, which can cause signal distortion during transmission. Therefore, additional AC (Alternating Current) coupling capacitors are required when calibrating the DVGA to prevent affecting the DVGA's common-mode operating point.

[0036] To this end, the present application provides an on-chip calibration source circuit and chip for a radio frequency direct acquisition receiving link, aiming to solve the technical problems existing in the above-mentioned related technologies.

[0037] Figure 2 FIG. 1 shows a block diagram of an on-chip calibration source circuit for a radio frequency direct sampling receiving link provided by an embodiment of the present application, as shown in FIG. Figure 2 As shown, an embodiment of the present application provides an on-chip calibration source circuit for error calibration of a radio frequency direct acquisition receiving link. The radio frequency direct acquisition receiving link includes a variable gain amplifier (DVGA) and a time-interleaved analog-to-digital converter (TI-ADC). The on-chip calibration source circuit includes: a clock signal output circuit 11 and a differential current signal output circuit 12. The output end of the clock signal output circuit 11 is connected to the input end of the differential current signal output circuit 12. The output end of the differential current signal output circuit 12 can be movably connected to the input end of the variable gain amplifier 13. The output end of the variable gain amplifier 13 is connected to the input end of the time-interleaved analog-to-digital converter 14.

[0038] Among them, the clock signal output circuit 11 is used to output a clock signal to the differential current signal output circuit 12; the differential current signal output circuit 12 is used to generate a first calibration signal according to the input clock signal, and output the first calibration signal to the variable gain amplifier 13, the first calibration signal is a differential current signal; the first calibration signal is used to perform error calibration on the variable gain amplifier 13; the variable gain amplifier 13 is used to output a second calibration signal to the time-interleaved analog-to-digital converter 14 according to the first calibration signal, the second calibration signal is a voltage signal; the second calibration signal is used to perform error calibration on the time-interleaved analog-to-digital converter 14.

[0039] In some embodiments, in the RF direct acquisition receiving link, the output of the variable gain amplifier 13 is connected to the input of the time-interleaved analog-to-digital converter 14 through an input buffer (inbuf) 15 .

[0040] The on-chip calibration source circuit provided by the embodiment of the present application utilizes a differential current signal output circuit to generate a first calibration signal for calibrating the RF direct acquisition receive link under the action of a clock signal output by a clock signal output circuit. The first calibration signal is a differential current signal. The use of differential current signal transmission reduces the requirements for the signal transmission path, effectively ensuring the quality of the signal during transmission, and obtaining an undistorted, high-quality calibration signal. Furthermore, no coupling capacitor is required on the transmission path, and the equivalent parasitic capacitance on the transmission path is small, which has little impact on the RX link. Because the variable gain amplifier is a resistive load and the time-interleaved analog-to-digital converter is a capacitive load, these two load characteristics are utilized to directly inject the first calibration signal at the input of the variable gain amplifier to perform error calibration of the variable gain amplifier. The first calibration signal is then restored to a voltage signal after passing through the variable gain amplifier and input into the time-interleaved analog-to-digital converter for error calibration. That is, the first calibration signal output by the on-chip calibration source circuit is directly injected into the input of the RX, completing error calibration of the variable gain amplifier and the time-interleaved analog-to-digital converter at one time, without requiring additional paths to calibrate the time-interleaved analog-to-digital converter.

[0041] In some embodiments, the clock signal output by the clock signal output circuit 11 is a differential clock signal, which includes a first clock signal and a second clock signal, and the first clock signal and the second clock signal are square wave signals with opposite phases to each other; the first calibration signal includes a first differential current signal and a second differential current signal;

[0042] In some embodiments, the differential current signal output circuit 12 includes at least one set of differential current driving circuits. In some embodiments, the differential current driving circuits are low-voltage differential signaling (LVDS) generating circuits.

[0043] Figure 3 FIG. 1 shows a block diagram of a differential current driving circuit provided in an embodiment of the present application, as shown in FIG. Figure 3 As shown, each differential current driving circuit includes a first output circuit 121 and a second output circuit 122. The first output circuit 121 has a first output terminal, and the second output circuit 122 has a second output terminal. The first output circuit is configured to generate a first differential current signal based on a first clock signal and a second clock signal and output it to the first output terminal. The second output circuit is configured to generate a second differential current signal based on the first clock signal and the second clock signal and output it to the second output terminal.

[0044] Figure 4 FIG. 1 shows a circuit structure diagram of a differential current driving circuit provided by an embodiment of the present application. In some embodiments, as shown in FIG. Figure 4As shown, the first output circuit 121 includes a first transistor T1 and a second transistor T2.

[0045] The control electrode of the first transistor T1 is connected to the output terminal of the clock signal output circuit 11 that outputs the first clock signal clk_n; the first electrode of the first transistor T1 is connected to the first power supply terminal; and the second electrode of the first transistor T1 is connected to the first output terminal Voutn of the differential current signal output circuit. The control electrode of the second transistor T2 is connected to the output terminal of the clock signal output circuit 11 that outputs the second clock signal clk_p; the first electrode of the second transistor T2 is connected to the second power supply terminal; and the second electrode of the second transistor T2 is connected to the first output terminal Voutn of the differential current signal output circuit.

[0046] In some embodiments, as Figure 4 As shown, the second output circuit 122 includes a third transistor T3 and a fourth transistor T4.

[0047] The control electrode of the third transistor T3 is connected to the output terminal of the clock signal output circuit 11 that outputs the second clock signal clk_p; the first electrode of the third transistor T3 is connected to the first power supply terminal; and the second electrode of the third transistor T3 is connected to the second output terminal Voutp of the differential current signal output circuit. The control electrode of the fourth transistor T4 is connected to the output terminal of the clock signal output circuit 11 that outputs the first clock signal clk_n; the first electrode of the fourth transistor T4 is connected to the second power supply terminal; and the second electrode of the fourth transistor T4 is connected to the second output terminal Voutp of the differential current signal output circuit.

[0048] In some embodiments, the first power supply terminal and the second power supply terminal are both current power supply terminals for generating current signals.

[0049] In some embodiments, the amplitude of the first calibration signal output by the on-chip calibration source circuit can be adjusted by adjusting the current output by the first power supply terminal and the second power supply terminal in the differential current driving circuit to meet calibration requirements.

[0050] In some embodiments, as Figure 4As shown, each differential current drive circuit further includes a common-mode feedback circuit 123. The common-mode feedback circuit includes an operational amplifier A, the output of which is connected to a first power supply terminal, a first input terminal Vref serving as a reference voltage terminal, and a second input terminal Vcom connected via a resistor to a first output terminal Voutn and a second input terminal Voutp of the differential current signal output circuit. Specifically, the second input terminal Vcom is connected to the first output terminal Voutn of the differential current signal output circuit via a resistor, and the second input terminal Vcom is connected to the second output terminal Voutp of the differential current signal output circuit via another resistor. The common-mode feedback circuit provides a stable common-mode voltage for the output of the differential current signal output circuit.

[0051] In some embodiments, the differential current signal output circuit 12 includes multiple sets of differential current drive circuits. During each error calibration, the output of the clock signal output circuit 11 is connected to one set of differential current drive circuits in the differential current signal output circuit 12. The multiple sets of differential current drive circuits receive clock signals of different frequencies, and the multiple sets of differential current drive circuits output current signals of different magnitudes. Different differential current drive circuits can be selected to provide calibration signals based on calibration requirements, thereby outputting calibration signals of different magnitudes for calibration.

[0052] Figure 5 FIG. 1 is a circuit diagram showing a differential current signal output circuit provided by an embodiment of the present application. In some embodiments, as shown in FIG. Figure 5 As shown, the differential current signal output circuit 12 includes n (n is greater than or equal to 2) groups of differential current driving circuits, each corresponding to n current power supply terminals. The currents output by the n current power supply terminals are 1, 2I, 4I, ..., 2 n I, each group of differential current driving circuits corresponds to an input of a group of clock signals, each group of clock signals includes a clock signal clk_n and a clock signal clk_p, the clock signal clk_n and the clock signal clk_p are differential clock signals, which are mutually inverted square wave signals. Among them, the circuit structure of each group of differential current driving circuits can refer to the above Figure 4 The circuit structure of the differential current driving circuit is shown.

[0053] The frequencies of the n groups of clock signals corresponding to the n groups of differential current driving circuits are different. The n groups of clock signals are recorded as clk1, clk2, ...clkn. Figure 6 A timing diagram of n groups of clock signals corresponding to n groups of differential current driving circuits in an embodiment of the present application is shown as follows: Figure 6 As shown, the frequency of clk2 is 1 / 2 of clk1, the frequency of clk3 is 1 / 4 of clk1, and so on. The frequency of clkn is 1 / 2 of clk1. n-1clk1 is the clock signal output by the clock signal output circuit, and clk2~clkn can be obtained by continuously dividing clk1 by two using a D flip-flop.

[0054] For ease of description, Figure 5 The transistors in each group of differential current driving circuits are described as switches, and the clock signal clk_n and the clock signal clk_p are used to control the connection or disconnection of the switches. It can be understood that when the switch controlled by the clock signal clk_n is connected, the switch controlled by clk_p is disconnected, and when the switch controlled by the clock signal clk_n is disconnected, the switch controlled by clk_p is connected.

[0055] In some embodiments, the waveform of the voltage signal restored from the differential current signal output by one group of differential current driving circuits after passing through the variable gain amplifier is a square wave waveform, while the waveform of the voltage signal restored from the signals output by n groups of differential current driving circuits after passing through the variable gain amplifier is a step-shaped waveform, with the number of steps being n. Figure 7 FIG. 1 is a schematic diagram showing waveforms of signals output by n groups of differential current driving circuits in an embodiment of the present application being restored to voltage signals, as shown in FIG. Figure 7 As shown, the waveform of the voltage signal restored from the output signals of n groups of differential current driving circuits after passing through the variable gain amplifier is a step-like waveform with n steps. If n is large enough, the step-like waveform will approach a sine waveform.

[0056] In some embodiments, a differential current signal output circuit is formed using n groups of differential current driving circuits. The signal amplitude corresponding to the output of each group of differential current driving circuits is different. A group of differential current driving circuits can be selected in turn to output the required calibration signal to perform error calibration on the RF direct sampling receiving link, thereby effectively improving the accuracy of the calibration.

[0057] Figure 8 FIG. 1 shows a block diagram of another on-chip calibration source circuit provided by an embodiment of the present application. In some embodiments, as shown in FIG. Figure 8As shown, an impedance adjustment circuit 16 is further connected between the differential current signal output circuit 12 and the variable gain amplifier 13, and the impedance adjustment circuit 16 is used to adjust the impedance between the output end of the differential current signal output circuit 12 and the input end of the variable gain amplifier 13; the differential current signal output circuit 12 has two output ends, namely a first output end and a second output end, and the variable gain amplifier 13 has two input ends; the impedance adjustment circuit 16 includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is connected to an output end of the differential current signal output circuit 12, and the other end of the first resistor R1 can be movably connected to an input end of the variable gain amplifier 13; one end of the second resistor R2 is connected to the other output end of the differential current signal output circuit 12, and the other end of the second resistor R2 can be movably connected to the other input end of the variable gain amplifier 13.

[0058] In some embodiments, as Figure 8 As shown, the impedance adjustment circuit 16 also includes a third resistor R3, and the third resistor R3 is connected between the two output ends of the differential current signal output circuit 12; one end of the third resistor R3 is connected to one output end of the differential current signal output circuit 12, and the other end of the third resistor R3 can be movably connected to the other output end of the differential current signal output circuit 12.

[0059] In some embodiments, the movable connection includes connection via a switch element. Figure 8 As shown, the other end of the first resistor R1 is connected to one input terminal of the variable gain amplifier 13 via a switch S1. Specifically, the other end of the first resistor R1 is connected to one end of the switch S1, and the other end of the switch S1 is connected to one input terminal of the variable gain amplifier 13. Similarly, the other end of the second resistor R2 is connected to the other input terminal of the variable gain amplifier 13 via a switch S2. Specifically, the other end of the second resistor R2 is connected to one end of the switch S2, and the other end of the switch S2 is connected to the other input terminal of the variable gain amplifier 13. Similarly, the other end of the third resistor R3 is connected to the other output terminal of the differential current signal output circuit 12 via a switch S0. Specifically, the other end of the third resistor R3 is connected to one end of the switch S0, and the other end of the switch S0 is connected to the other output terminal of the differential current signal output circuit 12.

[0060] In some embodiments, the first resistor R1 , the second resistor R2 , and the third resistor R3 may be fixed resistors or adjustable resistors.

[0061] In some embodiments, during calibration, switches S1 and S2 are closed, so that the output end of the differential current signal output circuit 12 is connected to the input end of the variable gain amplifier 13, and switch S0 is opened. When adjusting the impedance, switch S0 can be closed. After the calibration is completed, when the RF direct sampling receiving link is operating normally, switches S1 and S2 are opened, and the input end of the RF direct sampling receiving link, that is, the input end of the variable gain amplifier 13, can normally input the RF signal and operate normally.

[0062] In some embodiments, the signal source and impedance of the input terminal of variable gain amplifier 13 differ when the on-chip calibration source circuit is turned on and off. When the on-chip calibration source circuit is operating, the signal is generated by the on-chip calibration source circuit, while when the on-chip calibration source circuit is not operating, the signal is an external RF signal. Therefore, it is necessary to ensure good phase consistency in these two situations to facilitate subsequent phase calibration. During calibration, the impedance at the input terminal of variable gain amplifier 13 can be adjusted using impedance adjustment circuit 16, thereby improving the phase error calibration effect of the variable gain amplifier and improving phase consistency when the calibration source is turned on and off.

[0063] In some embodiments, the clock signal output circuit 11 includes a digital phase locked loop (DPLL) circuit.

[0064] Figure 9 FIG. 1 shows a block diagram of another on-chip calibration source circuit provided by an embodiment of the present application. In some embodiments, as shown in FIG. Figure 9 As shown, in order to enhance the driving capability and quality of the clock signal, a buffer circuit 17 and a duty cycle correction (DCC) circuit 18 are also connected between the clock signal output circuit 11 and the differential current signal output circuit 12; the buffer circuit 17 is configured to receive and store the clock signal output by the clock signal output circuit 11; the duty cycle correction circuit 18 is configured to receive the clock signal from the buffer circuit 17, adjust the duty cycle of the clock signal, and output the adjusted clock signal to the differential current signal output circuit 12.

[0065] In some embodiments, in order to enhance the quality of the clock signal and ensure the stability of the clock signal, Figure 9 As shown, a latch circuit 19 is also connected between the duty cycle correction circuit 18 and the differential current signal output circuit 11; the latch circuit 19 is configured to receive and cache the adjusted clock signal from the duty cycle correction circuit, and output the adjusted clock signal to the differential current signal output circuit 12.

[0066] In some embodiments, the on-chip calibration source circuit also includes a power supply module (not shown in the figure), which is used to provide the required operating voltage to all circuit modules and provide the required current to the differential current signal output circuit 11. The current size can be adjusted by changing the register configuration.

[0067] In some embodiments, the power module may include but is not limited to: a low-dropout regulator (LDO), a current mirror (Current_mirror), etc.

[0068] An embodiment of the present application also provides a chip, which includes a radio frequency direct acquisition receiving link and an on-chip calibration source circuit. The radio frequency direct acquisition receiving link includes a variable gain amplifier and a time-interleaved analog-to-digital converter. The on-chip calibration source circuit includes the on-chip calibration source circuit provided in the above embodiment.

[0069] An embodiment of the present application also provides a communication device, comprising the above-mentioned chip.

[0070] For the relevant description of the on-chip calibration source circuit, reference may be made to the specific description of the on-chip calibration source circuit in the above embodiment, which will not be repeated here.

[0071] The above description of exemplary embodiments of the present application has been provided by way of exemplary and non-limiting examples. However, various modifications and adaptations of the above embodiments will be apparent to those skilled in the art, when considered in conjunction with the accompanying drawings and the appended claims, without departing from the scope of the present application. Therefore, the proper scope of the present application will be determined by reference to the appended claims.

Claims

1. An on-chip calibration source circuit for a radio frequency direct acquisition receive link, the radio frequency direct acquisition receive link including a variable gain amplifier and a time-interleaved analog-to-digital converter, the on-chip calibration source circuit comprising: a clock signal output circuit and a differential current signal output circuit, wherein the output end of the clock signal output circuit is connected to the input end of the differential current signal output circuit, the output end of the differential current signal output circuit is movably connected to the input end of the variable gain amplifier, and the output end of the variable gain amplifier is connected to the input end of the time-interleaved analog-to-digital converter; The clock signal output circuit is used to output a clock signal to the differential current signal output circuit; The differential current signal output circuit is used to generate a first calibration signal according to the input clock signal, and output the first calibration signal to the variable gain amplifier, where the first calibration signal is a differential current signal; The first calibration signal is used to perform error calibration on the variable gain amplifier; The variable gain amplifier is used to output a second calibration signal to the time-interleaved analog-to-digital converter according to the first calibration signal, where the second calibration signal is a voltage signal; The second calibration signal is used to perform error calibration on the time-interleaved analog-to-digital converter.

2. The on-chip calibration source circuit according to claim 1, wherein: The clock signal is a differential clock signal, and the clock signal includes a first clock signal and a second clock signal; the first calibration signal includes a first differential current signal and a second differential current signal; The differential current signal output circuit includes at least one group of differential current driving circuits, and each group of differential current driving circuits includes a first output circuit and a second output circuit; The first output circuit is configured to generate the first differential current signal according to the first clock signal and the second clock signal, and the second output circuit is configured to generate the second differential current signal according to the second clock signal and the first clock signal.

3. The on-chip calibration source circuit according to claim 2, wherein: The first output circuit includes a first transistor and a second transistor; The control electrode of the first transistor is connected to the output terminal of the clock signal output circuit outputting the first clock signal; the first electrode of the first transistor is connected to the first power supply terminal; the second electrode of the first transistor is connected to the first output terminal of the differential current signal output circuit; The control electrode of the second transistor is connected to the output terminal of the clock signal output circuit that outputs the second clock signal; the first electrode of the second transistor is connected to the second power supply terminal; the second electrode of the second transistor is connected to the first output terminal of the differential current signal output circuit.

4. The on-chip calibration source circuit according to claim 2, wherein: The second output circuit includes a third transistor and a fourth transistor; The control electrode of the third transistor is connected to the output terminal of the clock signal output circuit outputting the second clock signal; the first electrode of the third transistor is connected to the first power supply terminal; the second electrode of the third transistor is connected to the second output terminal of the differential current signal output circuit; The control electrode of the fourth transistor is connected to the output end of the clock signal output circuit that outputs the first clock signal; the first electrode of the fourth transistor is connected to the second power supply end; and the second electrode of the fourth transistor is connected to the second output end of the differential current signal output circuit.

5. The on-chip calibration source circuit according to claim 3 or 4, wherein: Each group of the differential current driving circuits further includes a common-mode feedback circuit; The common-mode feedback circuit includes an operational amplifier, the output end of the operational amplifier is connected to the first power supply end, the first input end is a reference voltage end, and the second input end is connected to the first output end and the second input end of the differential current signal output circuit through a resistor.

6. The on-chip calibration source circuit according to claim 2, wherein: The differential current signal output circuit includes a plurality of differential current driving circuits, and each time the error calibration is performed, the output end of the clock signal output circuit is connected to a group of differential current driving circuits of the differential current signal output circuit; The frequencies of clock signals inputted by the multiple sets of differential current driving circuits are different, and the magnitudes of current signals outputted by the multiple sets of differential current driving circuits are different.

7. The on-chip calibration source circuit according to claim 1, wherein: An impedance adjustment circuit is further connected between the differential current signal output circuit and the variable gain amplifier; The differential current signal output circuit has two output terminals, and the variable gain amplifier has two input terminals; The impedance adjustment circuit includes a first resistor and a second resistor, one end of the first resistor is connected to an output end of the differential current signal output circuit, and the other end of the first resistor can be movably connected to an input end of the variable gain amplifier; one end of the second resistor is connected to the other output end of the differential current signal output circuit, and the other end of the second resistor can be movably connected to the other input end of the variable gain amplifier.

8. The on-chip calibration source circuit according to claim 7, wherein: The impedance adjustment circuit further includes a third resistor, and the third resistor is connected between the two output terminals of the differential current signal output circuit; One end of the third resistor is connected to one output end of the differential current signal output circuit, and the other end of the third resistor is movably connected to the other output end of the differential current signal output circuit.

9. The on-chip calibration source circuit according to claim 7 or 8, wherein: The movable connection includes connection via a switch.

10. The on-chip calibration source circuit according to claim 1, wherein: The clock signal output circuit includes a digital locked loop phase circuit.

11. The on-chip calibration source circuit according to claim 1 , wherein: A buffer circuit and a duty cycle correction circuit are further connected between the clock signal output circuit and the differential current signal output circuit; The buffer circuit is configured to receive and store the clock signal output by the clock signal output circuit; The duty cycle correction circuit is configured to receive the clock signal from the buffer circuit, adjust the duty cycle of the clock signal, and output the adjusted clock signal to the differential current signal output circuit.

12. The on-chip calibration source circuit according to claim 11, wherein: A latch circuit is further connected between the duty cycle correction circuit and the differential current signal output circuit; The latch circuit is configured to receive and buffer the adjusted clock signal from the duty cycle correction circuit, and output the adjusted clock signal to the differential current signal output circuit.

13. A chip comprising a radio frequency direct acquisition receiving link and an on-chip calibration source circuit, wherein the radio frequency direct acquisition receiving link comprises a variable gain amplifier and a time-interleaved analog-to-digital converter, and the on-chip calibration source circuit comprises the on-chip calibration source circuit according to any one of claims 1 to 12.

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