Synchronization method and device, equipment, storage medium and program product

Abstract

The invention provides a synchronization method and device, equipment, a storage medium and a program product, and relates to the technical field of wireless, the method is applied to an accelerator card, the accelerator card is inserted into a server through a golden finger of a communication interface, and the method comprises the following steps: processing a first PP1S signal of a GNSS by using a two-stage clock circuit to obtain a first pulse signal; according to the first pulse signal, synchronization information is generated, and the synchronization information comprises a frame header, a frame number, a time slot header and a time slot number; sending the frame header and the frame number to an active antenna unit (AAU), and sending the frame number, the time slot header and the time slot number to the server through the communication interface; the frame header and the frame number are used for the AAU to perform clock synchronization, and the frame number, the time slot header and the time slot number are used for the server to perform clock synchronization. Therefore, the acceleration card can obtain the stable pulse signal so as to provide stable synchronization information for the server and the AAU, and synchronization of the server, the AAU and the acceleration card is realized.

Description

Technical Field

[0001] The present application relates to the field of wireless technology, and in particular to a synchronization method, apparatus, device, storage medium, and program product. Background Art

[0002] The current structure of wireless communication base stations consists of a baseband processing unit (BBU) and an active antenna processing unit (AAU). The BBU is composed of a general-purpose field programmable gate array (FPGA) / application specific integrated circuit (ASIC) chip and a general-purpose X86 / digital signal processing (DSP) chip. Its clock supply method is generally to use a complex programmable logic device (CPLD) / FPGA chip to receive the pulse per second (PP1S) signal of the global navigation satellite system (GNSS). After de-jittering and frequency division, it is hard-wired to provide clocks to the FPGA / ASIC chip and the general-purpose X86 / DSP chip respectively. No clock signal is transmitted between the FPGA / ASIC chip and the general-purpose X86 / DSP chip. The synchronization between the two is based on the same clock pulse signal. The two calculate the frame number, time slot number and other synchronization information based on the clock pulse signal. The BBU clock connection synchronization scheme is as follows: Figure 1 shown.

[0003] In a base station system combining an FPGA accelerator card with a general-purpose X86 server, the interface between the FPGA accelerator card and the X86 server is only a high-speed Peripheral Component Interconnect Express (PCIE) interface. Therefore, the clock supply synchronization solution for the BBU in current wireless communication base stations is not applicable to base station systems combining FPGA accelerator cards with general-purpose X86 servers. Summary of the Invention

[0004] The embodiments of the present application provide a synchronization method, apparatus, device, storage medium, and program product, which solve the problem that the clock supply synchronization solution of the BBU in the current wireless communication base station is not suitable for the base station system composed of an FPGA accelerator card and a general X86 server.

[0005] In a first aspect, to achieve the above-mentioned objectives, embodiments of the present application provide a synchronization method, which is applied to an accelerator card. The accelerator card is inserted into a server via a gold finger of a communication interface. The method includes:

[0006] A first pulse signal is obtained by processing a first pulse-per-second signal of a global satellite navigation system (GNSS) using a two-stage clock circuit.

[0007] Generate synchronization information according to the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number;

[0008] The frame header and the frame number are sent to the active antenna unit AAU, and the frame number, the time slot header and the time slot number are sent to the server through the communication interface; wherein the frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header and the time slot number are used for clock synchronization of the server.

[0009] The first PP1S signal of the GNSS is processed using a two-stage clock circuit to obtain a first pulse signal, including:

[0010] Locking the first PP1S signal to obtain a second PP1S signal;

[0011] Performing frequency division processing on the second PP1S signal to obtain a periodic second pulse signal;

[0012] The second pulse signal is locked to obtain the first pulse signal.

[0013] The step of locking the first PP1S signal to obtain a second PP1S signal includes:

[0014] Perform at least one of de-jittering, signal tracking, signal tracking switching, and error elimination processing on the first PPIS signal to obtain the second PPIS signal.

[0015] The step of sending the frame number, the time slot header, and the time slot number to the server through the communication interface includes:

[0016] The frame number, the time slot header and the time slot number are sent to the server through the communication interface using a time slot timing method.

[0017] Wherein, using a time slot timing method, sending the frame number, the time slot header, and the time slot number to the server through the communication interface includes:

[0018] Converting the frame number, the time slot header, and the time slot number into fourth-generation Advanced eXtensible Interface (AXI4) synchronization information;

[0019] Writing the AXI4 synchronization information into a first module for data transmission in the accelerator card according to the time slot header timing of the time slot number, wherein the first module is used to write the AXI4 synchronization information into the memory of the server through the communication interface.

[0020] Before writing the AXI4 synchronization information into the first module for data transmission in the accelerator card, the method further includes:

[0021] When the AXI4 synchronization information and the service data packet arrive at the same time, the priority of the AXI4 synchronization information is set to the highest priority by arbitrating the AXI4 synchronization information and the service data packet;

[0022] Writing the AXI4 synchronization information into a first module for data transmission in the accelerator card includes:

[0023] The AXI4 synchronization information and the service data packet are written into the first module in order from high to low priority.

[0024] In a second aspect, to achieve the above-mentioned objectives, embodiments of the present application provide a synchronization device, which is applied to an accelerator card. The accelerator card is inserted into a server via a gold finger of a communication interface. The device includes:

[0025] A signal processing module is used to process the first pulse per second PP1S signal of the global satellite navigation system GNSS using a two-stage clock circuit to obtain a first pulse signal;

[0026] An information generating module, configured to generate synchronization information according to the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number;

[0027] A sending module is used to send the frame header and the frame number to the active antenna unit AAU, and to send the frame number, the time slot header and the time slot number to the server through the communication interface; wherein, the frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header and the time slot number are used for clock synchronization of the server.

[0028] In the third aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a synchronization device, including a transceiver, a processor, a memory, and a program stored on the memory and runnable on the processor; the transceiver is used to send and receive data under the control of the processor, and the processor implements the synchronization method described in the first aspect when executing the program.

[0029] In a fourth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a readable storage medium on which a program or instruction is stored, and when the program or instruction is executed by a processor, the synchronization method as described in the first aspect is implemented.

[0030] In a fifth aspect, in order to achieve the above-mentioned purpose, an embodiment of the present application provides a computer program product, including computer instructions, which, when executed by a processor, implement the synchronization method as described in the first aspect.

[0031] The beneficial effects of the above technical solution of this application are as follows:

[0032] In an embodiment of the present application, an accelerator card is inserted into a server via a gold finger of a communication interface. On this basis, first, the accelerator card processes the first pulse per second (PP1S) signal of the global satellite navigation system (GNSS) using a two-stage clock circuit to obtain a first pulse signal. In this way, a stable pulse signal can be obtained. Secondly, the accelerator card generates synchronization information based on the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number. Thirdly, the accelerator card sends the frame header and the frame number to the active antenna unit (AAU), and sends the frame number, the time slot header, and the time slot number to the server via the communication interface. The frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header, and the time slot number are used for clock synchronization of the server. In this way, through the processing of the two-stage clock circuit, the accelerator card can obtain a stable pulse signal, thereby generating stable synchronization information, so that the accelerator card can provide synchronization information to the server and AAU, achieving synchronization between the three, and solving the problem that the current BBU clock supply solution is not suitable for base station systems that combine accelerator cards and servers. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of an existing BBU clock connection synchronization solution;

[0034] Figure 2 A flowchart of a synchronization method according to an embodiment of the present application;

[0035] Figure 3 This is a schematic diagram of a base station composed of an accelerator card and a server in an embodiment of the present application;

[0036] Figure 4 A schematic diagram of a two-stage clock circuit system design in an embodiment of the present application;

[0037] Figure 5 This is a schematic diagram of data transmission between the accelerator card and the server in an embodiment of the present application;

[0038] Figure 6 A schematic diagram of data transmission competition in an embodiment of the present application;

[0039] Figure 7 This is a schematic diagram of the delay test results of writing data from the accelerator card to the server in an embodiment of the present application;

[0040] Figure 8 This is a schematic structural diagram of a synchronization device according to an embodiment of the present application;

[0041] Figure 9 This is a structural diagram of a synchronization device according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and advantages to be solved by this application clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0043] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0044] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0045] Additionally, the terms "system" and "network" are often used interchangeably herein.

[0046] In the embodiments provided herein, it should be understood that "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0047] An embodiment of the present application provides a synchronization method, which is applied to an accelerator card. The accelerator card is inserted into a server through a gold finger of a communication interface. For example, the accelerator card is, for example, an FPGA accelerator card, the server is, for example, an X86 server, and the communication interface is, for example, a PCIE interface. That is, the FPGA accelerator card is inserted into the X86 server through the gold finger of the PCIE interface. Figure 2 As shown, the method includes:

[0048] Step 201: Process the first pulse per second (PP1S) signal of the global satellite navigation system (GNSS) using a two-stage clock circuit to obtain a first pulse signal. The two-stage clock circuit is a circuit provided in the accelerator card, for example, a two-stage de-jitter and pulse locking circuit. In this step, the accelerator card receives the first P1S signal sent by the GNSS and uses the two-stage clock circuit therein to perform two-stage de-jitter and pulse locking processing on the received first P1S signal to obtain a stable first pulse signal. Exemplarily, the first pulse signal is a pulse signal with a period of 10ms. The processing of the first P1S signal by the two-stage clock circuit in this step includes: locking the first P1S signal and locking the pulse signal (hereinafter referred to as the second pulse signal) obtained by frequency-dividing the locked first P1S signal (hereinafter referred to as the second P1S signal).

[0049] Step 202: Generate synchronization information based on the first pulse signal, wherein the synchronization information includes: frame header, frame number, time slot header and time slot number. Figure 4 The frame number and time slot number output module is implemented in .

[0050] Step 203: Send the frame header and the frame number to the active antenna unit AAU, and send the frame number, the time slot header and the time slot number to the server through the communication interface; wherein, the frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header and the time slot number are used for clock synchronization of the server. In this step, the accelerator card sends synchronization information to the AAU and the server respectively, thereby achieving synchronization between the accelerator card and the AAU, and finally achieving synchronization of the base station. For example, this can be achieved by Figure 4 The Common Public Radio Interface (CPRI) shown in FIG. 1 sends the frame header and the frame number to the AAU, which can be done as follows: Figure 4 The fourth-generation Advanced eXtensible Interface 4 (AXI4) interface and XDMA module shown in the figure send the frame number, time slot header, and time slot number to the server. The XDMA module is a high-performance data transmission module in Xilinx FPGAs, primarily used for efficient data transmission over the PCIe interface. The XDMA module integrates DMA (Direct Memory Access) functionality with the PCIe interface, enabling high-speed, low-latency data transmission. The process of sending the frame number, time slot header, and time slot number to the server will be described in detail later.

[0051] In an embodiment of the present application, an accelerator card is inserted into a server via a gold finger of a communication interface. On this basis, first, the accelerator card processes the first GNSS P1S signal using a two-stage clock circuit to obtain a first pulse signal; thus, a stable periodic pulse signal can be obtained; secondly, the accelerator card generates synchronization information based on the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number; thirdly, the accelerator card sends the frame header and the frame number to the AAU, and sends the frame number, the time slot header, and the time slot number to the server via the communication interface, so that the AAU synchronizes the clock with the accelerator card based on the frame header and the frame number, and the server synchronizes the clock with the accelerator card based on the frame number, the time slot header, and the time slot number. In this way, by setting up a two-stage clock circuit processing in the accelerator card, the accelerator card can obtain a stable pulse signal, thereby generating stable synchronization information, so that the accelerator card provides synchronization information to the server and AAU, achieving synchronization between the three, and solving the problem that the current BBU clock supply solution is not suitable for base station systems combining accelerator cards and servers.

[0052] As an optional implementation, step 201 includes:

[0053] The first PPIS signal is locked to obtain a second PPIS signal. For example, this step may be to perform de-jittering, tracking, tracking switching, and error elimination operations on the first PPIS signal to achieve locking of the first PPIS signal. Figure 4 The PP1S signal locking module in is implemented.

[0054] Perform frequency division processing on the second PP1S signal to obtain a periodic second pulse signal; illustratively, this step can be performed by Figure 4 The frequency division module is implemented in .

[0055] Lock the second pulse signal to obtain the first pulse signal. Exemplarily, this step can be performed by Figure 4 The pulse signal locking module in is implemented, wherein locking the second pulse signal includes, for example, de-jittering the second pulse to eliminate errors, so that a stable first pulse signal can be obtained.

[0056] As a specific implementation, the step of “locking the first PPIS signal to obtain the second PPIS signal” in the above optional implementation includes:

[0057] Perform at least one of de-jittering, signal tracking, signal tracking switching, and error elimination processing on the first PPIS signal to obtain the second PPIS signal.

[0058] An implementation process of the above specific implementation method can be as follows:

[0059] Step 1: Eliminate the jitter error of the first PPIS signal and the error of the crystal oscillator clock by performing error processing on a plurality of continuously received first PPIS signals, lock the locking circuit, and obtain current locking parameters, wherein the locking parameters include a locking difference and a locking relative difference.

[0060] Step 2: Obtain a second PPIS signal based on the current locking parameters.

[0061] The above-mentioned step 1 may include: after receiving each of the first m first P1S signals among the consecutively received multiple first P1S signals, starting the locking circuit and locking twice in succession according to the count value recorded by the local free counter; and after the locking circuit is locked twice in succession, after receiving each of the next n first P1S signals among the consecutively received multiple first P1S signals, performing error calculation, error tracking, and error elimination according to the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain the current locking parameter; wherein the last P1S signal among the first m P1S signals is the first P1S signal among the next n P1S signals; and secondly, obtaining the second P1S signal based on the current locking parameter. More specifically:

[0062] After receiving each of the first m first P1S signals, the locking circuit is activated and locked twice continuously according to the count value recorded by the local free counter, including:

[0063] After receiving the first PP1S signal for the first time, assigning the first count value currently recorded by the local free counter to the error variable;

[0064] After receiving the first PP1S signal for the second time, calculating the absolute value of the first difference between the second count value currently recorded by the local free counter and the error variable, and when the absolute value of the first difference is less than a first threshold, setting the flag indicating that the locking circuit is locked to 1, thereby starting the locking circuit and locking the locking circuit once;

[0065] After receiving the first PPIS signal for the third time, the absolute value of the second difference between the third count value currently recorded by the local free counter and the error variable is calculated, and when the absolute value of the second difference is less than the first threshold, it is determined that the locking circuit is locked twice for the second time.

[0066] After receiving each of the next n first P1S signals, error calculation, error tracking, and error elimination are performed based on the count value recorded by the local free counter and the count value recorded by the PP1S counter to obtain the current locking parameters, including:

[0067] for each of the last n first PPIS signals, after receiving the first PPIS signal, in a case where it is determined that the locking circuit is in a locked state according to a difference between a count value currently recorded by the local free counter and the error variable, determining a real-time error of the currently received first PPIS signal according to a difference between a fourth count value currently recorded by the PPIS counter and a preset maximum count value of the PPIS counter, and updating the error variable according to the real-time error;

[0068] For non-first first PPIS signals among the last n first PPIS signals, determining a locking difference in the locking parameter according to the current error variable and a count value currently recorded by the local free counter;

[0069] For each first PPIS signal after the second first PPIS signal among the last n first PPIS signals, determine a relative difference in the locking parameter according to a difference between a locking difference corresponding to a current first PPIS signal and a locking difference corresponding to a previous first PPIS signal adjacent to the current first PPIS signal.

[0070] The above-mentioned step 2 may include: using the sum of the relative error and a preset maximum count value of the PPIS counter as the maximum count value of the PPIS output counter, and periodically timing by the PPIS output counter, outputting a stable second PPIS signal when the count value of the PPIS output counter reaches the maximum count value of the PPIS output counter, and updating the count value of the PPIS output counter to 1.

[0071] An example of the implementation process of the above specific implementation method is as follows:

[0072] 1) First reception of the first PP1S signal: First, compare the difference between Local_cnt (the current count value of the local free counter) and Iterate_cnt (the error variable). The initial value of Iterate_cnt is 0. The time of the locking process can be adjusted by setting the initial value of Iterate_cnt to a value between 0 and MAX_num_1s. This difference |Local_cnt-Iterate_cnt|≤10. If 10×4 (crystal oscillator clock) = 40ns, the PP1S is considered reliable. If it is greater than 40ns, the first PP1S is considered unreliable and a first PP1S abnormality alarm needs to be issued. After the comparison, Local_cnt is assigned to Iterate_cnt. The current circuit state is lock_vld = 0, where lock_vld is the circuit state flag.

[0073] 2) Second reception of the first PP1S signal: First, compare the difference between Local_cnt and Iterate_cnt. If the first PP1S signal has a small deviation and no abnormality, since Local_cnt has already been assigned to Iterate_cnt, the difference between Local_cnt and Iterate_cnt will be less than 10. Lock_vld = 1, and the locking circuit begins to operate. If the first PP1S signal has a large deviation or abnormality at power-up, it can always wait until the first lock is achieved. For the sake of simplicity, it is assumed that the second lock is achieved. The locking circuit then determines the first lock.

[0074] 3) The first PP1S signal is received for the third time. If there is no abnormality in the PP1S signal, it is considered locked. The locking circuit obtains the second lock.

[0075] The first three steps are to obtain two consecutive locks. If there is no abnormality in PP1S after power-on, it is considered that two locks can be obtained in the third step.

[0076] 4) The first PP1S signal is received a third time. After comparison, lock_vld = 1, and the locking circuit achieves a second lock. After lock, the debounce tracking and error elimination design begins. The first step is error calculation: PP1S_cnt (the current count value of the PP1S counter) is compared with MAX_num_1s (the preset maximum count value of the PP1S counter). Calibration = PP1S_cnt - MAX_num_1s. The second step is count update (error tracking): Iterate_cnt (after update) = Iterate_cnt (before update) + calibration.

[0077] 5) The first P1S signal is received a fourth time, and the difference between Local_cnt and Iterate_cnt is compared. The locking circuit achieves a third lock. Steps 1 through 3 are identical to the process after the first P1S signal is received. Step 4 outputs the locked difference Δ1 = Iterate_cnt - Local_cnt. This third lock is performed to achieve a stable locked difference Δ1, where Δ is an unsigned number.

[0078] 6) The first PP1S signal is received for the fifth time. The difference between Local_cnt and Iterate_cnt is compared, and the locking circuit achieves a fourth lock. Steps 1 through 4 are identical to those in step 5). In step 5, the locked relative difference Ω1 = Δ2 - Δ1 is output, where Ω is a signed number.

[0079] 7) The first PP1S signal is received for the sixth time, and the maximum value of the PP1S_out_cnt counter is set to M=MAX_num_1s+Ω n , n=1,Ω n is the tracking error, Ω n =Δ n -Δ n-1 Every time the PP1S_out_cnt counter reaches M, the number is reset to 1 and the second PP1S signal is output.

[0080] Among them, in actual engineering implementation, the PP1S signal arrives early or late; the crystal oscillator frequency is affected by the quality performance and becomes slower or faster, and the phase changes, which will affect the stability of the circuit. For example, when the crystal oscillator frequency decreases, the clock slows down, the count remains unchanged, the time increases, and the time is inaccurate. We found in engineering tests that after a year of testing, the crystal oscillator occasionally deviated. W counts should be counted in 1 second, and the crystal oscillator clock may slow down a little. In fact, only W-offset counts are needed. The offset is a random value. If we count according to W, the time will exceed 1 second. Therefore, it is necessary to introduce error variables to eliminate the influence of crystal oscillator instability. This solution designs a de-jitter tracking fluctuation algorithm, which will reduce the impact of crystal oscillator deviation and ensure that the PP1S signal has a stable output PP1S signal within a certain jitter range. The following is a detailed introduction to the source of error and the error elimination method:

[0081] Iterate_cnt is initialized to 0. After the first PP1S signal is received, the current value of the ratio point, Local_cnt, is assigned to Iterate_cnt. When the first PP1S signal is received a second time, the difference between Iterate_cnt and Local_cnt is again compared, resulting in Iterate_cnt = Local_cnt_old (the previous value of Local_cnt) and Local_cnt (the current value). When the first PP1S signal is received a third time, the jitter and tracking design begins, as detailed below.

[0082] As indicated in the previous steps:

[0083]

[0084] The simplification of formula variation 1 is that after the first PP1S arrives, Local_cnt (the first value) is assigned to Iterate_cnt, and then Iterate_cnt = Iterate_cnt + calibration. The update of Iterate_cnt is the first obtained Local_cnt plus the calibration each time.

[0085] The simplification of formula variation 2 is to simplify the complex formula, decomposing PP1S_cnt into a fixed value MAX_num_1s+η, where η is a variable value and can be positive or negative; Local_cnt_new is decomposed into a fixed value Local_cnt_old (the value obtained by the first lock)+δ2, where δ2 is a variable value and can be positive or negative.

[0086] The simplification of formula variation 3 is to let The jitter error η of PP1S usually obeys a normal distribution, and δ1=0 after a large amount of data accumulation.

[0087] About error Δ n =δ1-δ2, here we consider four cases:

[0088] Here, it is important to note that Local_cnt is a periodic count, and Iterate_cnt is the updated value each time. If there is no error, both are the values ​​after the first PP1S signal is received, and the circuit perfectly locks and outputs the second PP1S signal. The existence of errors causes the values ​​of the two to change. Compared with the previous value, if both values ​​are larger than the previous value, but the difference Δ n =δ1-δ2 remains unchanged, which means the ratio point is delayed, otherwise the ratio point is advanced.

[0089] Case 1: The PP1S signal is accurate, but the crystal oscillator clock (including frequency and phase) is inaccurate:

[0090] Formula Δ n =δ1-δ2. Since the two counters are caused by the same clock, the actual test crystal oscillator will be slower and need to be less counted. If δ1 is less than 0, it will change. If δ2 is less than 0, it will change. The difference Δ n =δ1-δ2 first becomes smaller and then tends to remain unchanged. If the clock speeds up, it will overcount. δ1 will change if it is greater than 0, and δ2 will change if it is greater than 0. The difference Δ n =δ1-δ2, first increases and then remains unchanged. Ω n =Δ n -Δ n-1 , changes in the crystal oscillator change stage, and does not change when the crystal oscillator tends to a certain stability. In the stage of faster frequency, Ω n When the frequency increases to a positive value, M needs to count more; conversely, when the frequency slows down, M needs to count less.

[0091] Case 2: The crystal oscillator clock is accurate, but the first PP1S signal is inaccurate:

[0092] If the first PP1S signal arrives late for the first time, calibration>0, Local_cnt>Local_cnt_old, δ1 and δ2 are both greater than 0. If it arrives late for the second time, the error is accumulated and the ratio point is delayed. If it arrives on time for the second time, calibration=0 and the ratio point remains unchanged. If it arrives early for the second time, calibration<0, δ1 and δ2 are less than 0, and the ratio point is advanced. Local_cnt_new becomes smaller, indicating that the ratio point is advanced. By introducing calibration, it can follow the changes in the ratio point. Although the data changes, the difference Δ n =δ1-δ2 remains unchanged, which can avoid the loss of lock caused by data changes, causing the circuit to repeatedly lose and lock and change Δ n and Ω n The value of affects the output PP1S signal.

[0093] Case 3: The crystal oscillator clock and the first PP1S signal are both accurate, the Local_cnt and Iterate_cnt data remain unchanged, and the difference is Δ n =δ1-δ2 unchanged, Ω n =Δ n -Δ n-1 The value of remains unchanged.

[0094] Case 4: Both the crystal oscillator clock and the first PP1S signal are inaccurate. According to the first and second cases, Δ n =δ1-δ2 may vary, but as long as |Δ n |≤10, it can be considered that the first PP1S signal of GNSS is reliable and the circuit crystal oscillator clock is reasonable and normal. Otherwise, an abnormal alarm is issued. n =Δn -Δ n-1 The value of changes with the change, in this state the output PP1S is stable.

[0095] As an optional implementation, in step 203, sending the frame number, the time slot header, and the time slot number to the server through the communication interface includes:

[0096] The frame number, the time slot header, and the time slot number are sent to the server via the communication interface using a time slot timing method. That is, in this optional implementation, the frame number, the time slot header, and the time slot number are periodically sent to the server (X86 server) via the communication interface (PCIE interface) to achieve clock synchronization of the server based on the received data.

[0097] As a specific implementation, using a time slot timing method, sending the frame number, the time slot header, and the time slot number to the server through the communication interface includes:

[0098] Converting the frame number, the time slot header, and the time slot number into fourth-generation Advanced eXtensible Interface 4 (AXI4) synchronization information;

[0099] Writing the AXI4 synchronization information into a first module for data transmission in the accelerator card according to the time slot header timing of the time slot number, wherein the first module is used to write the AXI4 synchronization information into the memory of the server through the communication interface, for example, the first module is an XDMA module.

[0100] Simply put, the accelerator card sends the frame number, time slot header, and slot number to the server, or writes data to the server's memory as follows: first, the frame number, time slot number, and slot header are converted into an AXI4 protocol interface. Second, the data is written to the XDMA module using the AXI4 interface according to the time slot header of each time slot number. The data is then written to the server's (X86 server's) memory via the communication interface (PCIE interface). Each time the data is written to the server's (X86 server's) memory, a flag bit is inverted to notify the server (X86 server) to retrieve synchronization information parameters. This allows the server to synchronize with the accelerator card's system synchronization information.

[0101] Here, it should be noted that since the data transmission between the accelerator card and the server is only through the aforementioned communication interface (PCIE interface), Figure 5As shown, the PCIE interface is a PCIE3.0-X16 full-duplex interface with a theoretical maximum bandwidth of 128Gbps. In actual tests, the upstream and downstream bandwidths can reach 93-96Gbps. The data written by all servers share the PCIE upstream interface. Therefore, when the accelerator card transmits upstream services to the server, it may conflict with the AXI4 synchronization information (or AXI4 synchronization information data packet), resulting in a transmission delay of the synchronization information.

[0102] Based on this, further, as an optional implementation, before writing the AXI4 synchronization information into the first module for data transmission in the accelerator card, the method further includes:

[0103] In the case where the AXI4 synchronization information and the service data packet arrive at the same time, the priority of the AXI4 synchronization information is set to the highest priority by arbitrating the AXI4 synchronization information and the service data packet; illustratively, this step can be specifically performed by Figure 5 The arbitration module is implemented in .

[0104] On this basis, writing the AXI4 synchronization information into the first module for data transmission in the accelerator card includes:

[0105] The AXI4 synchronization information and the service data packet are written into the first module in order from high to low priority.

[0106] That is to say, when the data packet and the AXI4 synchronization information arrive at the same time, the priority of the AXI4 synchronization information can be set to the highest to give priority to the transmission of the AXI4 synchronization information, thereby achieving the purpose of reducing the transmission delay.

[0107] However, in scenarios where AXI4 synchronization information arrives while service packets are being transmitted, the latency caused by the service packet transmission cannot be eliminated. For example, when transmitting at high bandwidths such as 90Gbps, burst contention is inevitable. The following analysis examines the magnitude of this error, its impact on system performance, and how to optimize the design.

[0108] exist Figure 6 In the figure, the vertical dotted line indicates the moment when the timer module receives the time slot header and outputs the AXI4 data packet. This moment is also the input time of the arbitration (Interconnect) module. The time slot header is a periodic signal. For example, the time slot period of the current millimeter wave frame structure is about 125us.

[0109] Figure 6In the two scenarios of Example 1 (Case 1), in Scenario 1, when the synchronization information packet T is transmitted, there is no business data packet UL_bag, so there is no waiting delay; in Scenario 2, when the synchronization information packet T is transmitted, there is also a business data packet UL_bag transmitted, but the two do not conflict at the same time, so there is no waiting delay.

[0110] Figure 6 In the three scenarios of Case 2, in scenario 3, when the synchronization information packet T is transmitted, the business data packet starts to be transmitted. Therefore, the synchronization information packet needs to wait for the business data packet to be transmitted before it can be transmitted, and the waiting delay is the largest; in scenario 4, when the synchronization information packet T is transmitted, there is a business data packet UL_bag in transmission, and it is also necessary to wait at this time, and the waiting delay is moderate; in scenario 5, when the synchronization information packet T is transmitted, the transmission of the business data packet UL_bag is about to end, and it is also necessary to wait at this time, and the waiting delay is relatively small.

[0111] Since AXI4 synchronization information (or called synchronization information data packets) is transmitted periodically, it is uncertain whether there are business data packets, so a mechanism must be designed that can meet the efficiency of transmitting a large number of data packets without wasting PCIE bandwidth and minimize the waiting delay of synchronization information data packet transmission.

[0112] When performing XDMA operations, the PCIE interface must comply with the 4KB boundary alignment requirement. This is because the memory management in the server (X86 server) is based on page management, and the size of each page is usually 4KB. If data is transmitted across the 4KB boundary, it may lead to inefficient memory access and even cause errors. Therefore, it is necessary to design data transmission so that it does not cross the 4KB boundary. Based on this design, the maximum transmission data packet of the accelerator card (FPGA accelerator card) is 4KB. That is, the AXI4 synchronization information should be less than or equal to 4KB, and the business data packet transmitted between the accelerator card and the server should also be less than or equal to 4KB.

[0113] The data packets inside the accelerator card (FPGA accelerator card) are calculated based on a 512-bit bit width, and the maximum length of the data packet is 64*512 bits. The synchronization information data packet has a fixed length of 512 bits. The clock frequency of the AXI4 interface, XDMA module, and PCIE interface are all 250MHz. The time it takes to transmit a 4KB data packet inside the accelerator card (FPGA accelerator card) is 64*4ns=256ns, which is also the time Figure 6The maximum latency of the synchronization packet T in Case 2 scenario 3 is as follows: considering that the actual bandwidth of the PCIE interface is 93-96Gbps, the actual test shows that the time from transmitting the synchronization information from the accelerator card (FPGA accelerator card) through the PCIE hardware connection to the write server (X86 server) memory and receiving the write success reply is (551-512)*4ns=156ns. The test results are as follows: Figure 7 As shown, the round-trip time is 156ns, while the one-way time is 78ns. Adding the other beat waiting delays, set to 16ns, this indicates that the maximum delay for the synchronization packet to reach the server (X86 server) memory is: 256 + 78 + 16 = 360ns, and the minimum is 78 + 16 = 94ns. In the millimeter wave frame structure, the slot period is approximately 125µs. The minimum jitter coefficient is 94ns / 125000ns = 0.000752, and the maximum jitter coefficient is 360ns / 125000ns = 0.00288. These coefficients are very small. Based on theoretical analysis and actual engineering test results, this design can meet the service processing performance requirements of the server (X86 server). The X86 server processes services using the arrival of synchronization information as the slot boundary and transmits the data results to the FPGA accelerator card, and finally to the AAU, achieving base station synchronization. In other words, compared to the AXI4 synchronization information transmission period (125µs), the aforementioned delay waiting for service packet transmission is relatively small and negligible.

[0114] Therefore, in the embodiment of the present application, only the situation where the business data packet and the AXI4 synchronization information arrive at the same time is considered, that is, in this case, the priority of the AXI4 synchronization information is set to the highest to give priority to transmitting the AXI4 synchronization information.

[0115] In addition, it should be noted that if Figure 7 As shown in the figure, according to actual test results, to ensure that the timeslot headers of the X86 server and the FPGA accelerator card are basically aligned, the synchronization time within the FPGA and to the AAU needs to be delayed by 94-120ns (the specific delay value can be selected based on actual conditions). In other words, after writing the synchronization information to the X86 server, the FPGA accelerator card is delayed by a value between 94-120ns, and the synchronization information sent to the AAU is also delayed by the same amount. In this way, the timeslot headers of the synchronization information reaching the X86 server, the synchronization information reaching the AAU, and the FPGA accelerator card are basically aligned, and the synchronization mechanism between the three parties is implemented.

[0116] Below, Figure 3 The base station shown in the figure is combined with the FPGA accelerator card and the X86 server as an example. Figure 4 and Figure 5 , an implementation example of the synchronization method of an embodiment of the present application is described.

[0117] like Figure 3 As shown, the FPGA accelerator card transmits data to the X86 server via the PCIE interface. Together, the FPGA accelerator card and the X86 server form the base station's BBU. The FPGA accelerator card connects to AAU1 and AAU2 via a 100G optical port via optical fiber. The FPGA accelerator card incorporates a well-designed internal frame structure for clock information, providing synchronization information to the X86 server and each AAU. This ensures that the entire base station's synchronization information is synchronized to the GNSS-based system clock circuitry of the FPGA accelerator card. This solves the problem that existing clock synchronization methods are unsuitable for base station systems combining FPGA accelerator cards with general-purpose X86 servers.

[0118] in, Figure 3 The two-stage clock circuit of the FPGA accelerator card is as follows Figure 4 As shown in the figure, a GNSS-based FPGA synchronization signal processing flow chart is presented. Specifically, a two-stage clock circuit is used to achieve 10ms pulse lock. First, the PP1S signal lock module de-jitters, tracks, switches, and eliminates errors in the received PP1S signal (corresponding to the aforementioned first PP1S signal), outputting a stable PP1S signal (corresponding to the aforementioned second PP1S signal). Next, the frequency division module divides the frequency and outputs a periodic pulse signal (corresponding to the aforementioned second pulse signal), such as 10ms. Furthermore, considering possible deviations in the output pulse signal, the periodic pulse signal is input into the pulse lock module to de-jitter and eliminate errors, ultimately outputting a locked, stable pulse signal (corresponding to the aforementioned first pulse signal). The pulse header is then fed into the frame number and time slot number calculation unit module, which outputs synchronization information. Finally, the frame header and frame number are sent to the AAU via the CPRI module. Furthermore, the frame number, time slot number, and time slot header are sent to the AXI4 interface. Using time slot timing, these information is written to the X86 server memory via the PCIE interface via the XDMA module, providing synchronization information such as the frame number and time slot number.

[0119] Specifically, the frame number and time slot number output module calculates the frame number, time slot number, frame header, and time slot header based on the frame structure synchronization information. For designs that output to the CPRI module, it is only necessary to pass the frame number and frame header to the CPRI module and then transmit them to the AAU via optical fiber. For designs that output to the X86 server, first, the signal frame number, time slot number, and time slot header are converted into an AXI4 protocol interface. Then, the AXI4 interface is used to write the data into the XDMA module based on the time slot header of each time slot number, and then the data is written into the memory of the X86 server via the PCIE interface. The flag signal written each time is inverted to notify the X86 server to obtain the synchronization information parameters, so that the X86 server can be synchronized to the system synchronization information of the FPGA acceleration card.

[0120] Among them, the FPGA accelerator card transmits the frame header and frame number to the AAU through the optical fiber. Since there is only a delay of the optical fiber length and no other delay, the delay of the frame header reaching the AAU is known and determined, and there is no random error.

[0121] The FPGA accelerator card writes synchronization information to the X86 memory through the PCIE interface, which results in time slot synchronization jitter. The main reason is that when the FPGA accelerator card has business data to write to the X86 server, it may conflict with the data packet that writes the synchronization information, resulting in competition. For example, Figure 5 As shown in the figure, both the synchronization information (AXI4 synchronization information generated by the RPT_timer based on the information output by the frame number and time slot number output module) and the service data packet (uplink information) are written to the X86 server. At high bandwidths, such as transmission rates above 90Gbps, burst contention between the two is inevitable. Based on this, the process of writing synchronization information from FPGA accelerator card 2 to the X86 server is as follows:

[0122] First, synchronization information such as the frame number, timeslot number, and timeslot header is sent to the RPT_Timer module. This module converts these signals into an AXI4 interface. An AXI4 synchronization packet consists of 512 bits of data. When each timeslot header arrives, a write operation is initiated to the X86 server. When the FPGA accelerator card transmits uplink services to the X86 server, conflicts with synchronization packets may occur. This is mainly because data transmission between the FPGA accelerator card and the X86 server is only via the PCIE interface. All data written to the X86 server shares the same PCIE uplink interface, requiring arbitration. Therefore, the arbitration module (interconnect) sets the synchronization packet to the highest priority. When both packets arrive simultaneously, the synchronization packet is transmitted first, which can eliminate some latency. However, in some scenarios, latency cannot be eliminated. For example, when transmitting at high bandwidths such as 90 Gbps (where the synchronization packet arrives while the service packet is already being transmitted), burst contention is inevitable. As previously analyzed, the latency caused by this inevitable burst contention is negligible compared to the period required to write data to the X86 server using timeslot timing.

[0123] In the above-mentioned embodiments of the present application, based on a base station BBU composed of an FPGA accelerator card and an X86 server, an FPGA accelerator card clock synchronization circuit is designed based on the GNSS PPIS signal. This solution uses a two-stage clock circuit design to achieve de-jitter processing and error elimination, aiming to provide accurate clock synchronization information, ensuring that the X86 server and AAU are synchronized to the clock information of the FPGA accelerator card, and providing a new clock synchronization design for future 6G wireless networks. The design of the synchronization information supply scheme based on the FPGA accelerator card is simple, easy to implement, and practical. The FPGA accelerator card uses XDMA to periodically use the AXI4 bus based on the time slot header of the frame structure to write synchronization information such as frame number and time slot number to the memory of the X86 server through the PCIE interface of the FPGA accelerator card through a reasonable packet grouping method. The design method is simple, ingenious, and practical. Moreover, the cause of the conflict is clearly analyzed, the method for resolving sudden contention is simple, and more importantly, the analysis and calculation process of the waiting delay is clear and reasonable, which is convenient for reference. In summary, this solution provides a very practical reference solution for the transmission of synchronization information between FPGA accelerator cards and X86 servers.

[0124] The embodiment of the present application also provides a synchronization device, which is applied to an accelerator card. The accelerator card is inserted into a server through a gold finger of a communication interface, such as Figure 8 As shown, the device includes:

[0125] The signal processing module 801 is configured to process a first pulse per second (PP1S) signal of a global satellite navigation system (GNSS) using a two-stage clock circuit to obtain a first pulse signal.

[0126] An information generating module 802 is configured to generate synchronization information according to the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number;

[0127] The sending module 803 is used to send the frame header and the frame number to the active antenna unit AAU, and send the frame number, the time slot header and the time slot number to the server through the communication interface; wherein, the frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header and the time slot number are used for clock synchronization of the server.

[0128] The signal processing module 801 includes:

[0129] a first locking submodule, configured to lock the first PPIS signal to obtain a second PPIS signal;

[0130] A frequency division processing submodule, configured to perform frequency division processing on the second PPIS signal to obtain a periodic second pulse signal;

[0131] The second locking submodule is used to lock the second pulse signal to obtain the first pulse signal.

[0132] The first locking submodule is specifically configured to perform at least one of de-jittering, signal tracking, signal tracking switching, and error elimination on the first PPIS signal to obtain the second PPIS signal.

[0133] Wherein, the sending module includes:

[0134] The first sending submodule is used to send the frame number, the time slot header and the time slot number to the server through the communication interface by using a time slot timing method.

[0135] Wherein, the first sending submodule includes:

[0136] A conversion unit, configured to convert the frame number, the time slot header, and the time slot number into fourth-generation Advanced eXtensible Interface (AXI4) synchronization information;

[0137] A data writing unit is used to write the AXI4 synchronization information into the first module for data transmission in the acceleration card according to the time slot header timing of the time slot number, wherein the first module is used to write the AXI4 synchronization information into the memory of the server through the communication interface.

[0138] Furthermore, the first sending submodule further includes:

[0139] an arbitration unit, configured to, when the AXI4 synchronization information and the service data packet arrive at the same time, arbitrate the AXI4 synchronization information and the service data packet, and set the priority of the AXI4 synchronization information to the highest priority;

[0140] The data writing unit is specifically configured to write the AXI4 synchronization information and the service data packet into the first module in descending order of priority.

[0141] It should be noted here that the above-mentioned synchronization device provided in the embodiment of the present application can implement all the method steps implemented in the above-mentioned synchronization method embodiment, and can achieve the same technical effect. The parts and beneficial effects of this embodiment that are the same as those in the method embodiment will not be described in detail here.

[0142] An embodiment of the present application also provides a synchronization device, including a transceiver 910, a processor 900, a memory 920, and a program stored in the memory 920 and executable on the processor 900; wherein, when the processor 900 executes the program, the synchronization method described above is implemented.

[0143] The transceiver 910 is configured to receive and send data under the control of the processor 900 .

[0144] Among them, Figure 9 In the present disclosure, the bus architecture may include any number of interconnected buses and bridges, specifically linking various circuits such as one or more processors represented by processor 900 and memory represented by memory 920. The bus architecture may also link various other circuits such as peripherals, voltage regulators, and power management circuits, all of which are well known in the art and are not further described herein. The bus interface provides an interface. The transceiver 910 may be a plurality of components, namely, a transmitter and a receiver, providing a means for communicating with various other devices over a transmission medium.

[0145] The processor 900 is responsible for managing the bus architecture and general processing, and the memory 920 can store data used by the processor 900 when performing operations.

[0146] The present application also provides a readable storage medium having a program stored thereon. When the program is executed by a processor, the synchronization method described above is implemented and the same technical effects are achieved. To avoid repetition, the details are not described here. The readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0147] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course, by hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for executing the methods described in each embodiment of the present application.

[0148] Therefore, an embodiment of the present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the synchronization method described above and can achieve the same technical effect. To avoid repetition, they will not be described here.

[0149] In embodiments of the present application, modules can be implemented in software so that they can be executed by various types of processors. For example, an identified executable code module can include one or more physical or logical blocks of computer instructions, for example, which can be constructed as objects, processes, or functions. Nevertheless, the executable code of the identified module does not need to be physically located together, but can include different instructions stored in different locations, which, when logically combined together, constitute the module and achieve the specified purpose of the module.

[0150] In fact, executable code module can be a single instruction or many instructions, and can even be distributed on a plurality of different code segments, distributed in the middle of different programs, and distributed across a plurality of memory devices.Similarly, operating data can be identified in the module, and can be implemented and organized in the data structure of any appropriate type according to any appropriate form.Described operating data can be collected as a single data set, or can be distributed in different locations (including on different storage devices), and can only be present on a system or network as an electronic signal at least in part.

[0151] When a module can be implemented using software, given the current state of hardware technology, those skilled in the art can build corresponding hardware circuits to implement the corresponding functions of the module, regardless of cost. The hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays, as well as existing semiconductors such as logic chips and transistors, or other discrete components. Modules may also be implemented using programmable hardware devices, such as field programmable gate arrays, programmable array logic, or programmable logic devices.

[0152] The above exemplary embodiments are described with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this application. Therefore, this application should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this application will be complete and impartial and will convey the scope of this application to those skilled in the art. In the drawings, component sizes and relative sizes may be exaggerated for clarity. The terminology used herein is for purposes of describing specific exemplary embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are intended to encompass such plural forms. It will be further understood that the terms "comprising" and / or "including," when used in this specification, indicate the presence of the stated features, integers, steps, operations, components, and / or elements, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, elements, and / or groups thereof. Unless otherwise indicated, when stated, a range of values ​​includes the upper and lower limits of that range and any subranges therebetween.

[0153] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A synchronization method, characterized in that: Applied to an accelerator card, the accelerator card is inserted into a server via a gold finger of a communication interface, and the method includes: A first pulse signal is obtained by processing a first pulse-per-second signal of a global satellite navigation system (GNSS) using a two-stage clock circuit. Generate synchronization information according to the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number; The frame header and the frame number are sent to the active antenna unit AAU, and the frame number, the time slot header and the time slot number are sent to the server through the communication interface; wherein the frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header and the time slot number are used for clock synchronization of the server.

2. The method according to claim 1, characterized in that The first PP1S signal of the GNSS is processed using a two-stage clock circuit to obtain a first pulse signal, including: Locking the first PP1S signal to obtain a second PP1S signal; Performing frequency division processing on the second PP1S signal to obtain a periodic second pulse signal; The second pulse signal is locked to obtain the first pulse signal.

3. The method according to claim 2, characterized in that Locking the first PP1S signal to obtain a second PP1S signal includes: Perform at least one of de-jittering, signal tracking, signal tracking switching, and error elimination processing on the first PPIS signal to obtain the second PPIS signal.

4. The method according to claim 1, wherein Sending the frame number, the time slot header, and the time slot number to the server through the communication interface includes: The frame number, the time slot header and the time slot number are sent to the server through the communication interface using a time slot timing method.

5. The method according to claim 4, characterized in that Using a time slot timing method, sending the frame number, the time slot header, and the time slot number to the server through the communication interface includes: Converting the frame number, the time slot header, and the time slot number into fourth-generation Advanced eXtensible Interface (AXI4) synchronization information; Writing the AXI4 synchronization information into a first module for data transmission in the accelerator card according to the time slot header timing of the time slot number, wherein the first module is used to write the AXI4 synchronization information into the memory of the server through the communication interface.

6. The method according to claim 5, characterized in that Before writing the AXI4 synchronization information into the first module for data transmission in the accelerator card, the method further includes: When the AXI4 synchronization information and the service data packet arrive at the same time, the priority of the AXI4 synchronization information is set to the highest priority by arbitrating the AXI4 synchronization information and the service data packet; Writing the AXI4 synchronization information into a first module for data transmission in the accelerator card includes: The AXI4 synchronization information and the service data packet are written into the first module in order from high to low priority.

7. A synchronization device, characterized in that: Applied to an accelerator card, the accelerator card is inserted into a server through the gold finger of a communication interface, and the device includes: A signal processing module is used to process the first pulse per second PP1S signal of the global satellite navigation system GNSS using a two-stage clock circuit to obtain a first pulse signal; An information generating module, configured to generate synchronization information according to the first pulse signal, wherein the synchronization information includes: a frame header, a frame number, a time slot header, and a time slot number; A sending module is used to send the frame header and the frame number to the active antenna unit AAU, and to send the frame number, the time slot header and the time slot number to the server through the communication interface; wherein, the frame header and the frame number are used for clock synchronization of the AAU, and the frame number, the time slot header and the time slot number are used for clock synchronization of the server.

8. A synchronization device comprising a transceiver, a processor, a memory, and a program stored in the memory and executable on the processor; The transceiver is used to send and receive data under the control of the processor, and the processor implements the synchronization method according to any one of claims 1 to 6 when executing the program.

9. A readable storage medium having a program or instruction stored thereon, characterized in that: When the program or instruction is executed by a processor, the synchronization method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that The method comprises computer instructions, which implement the synchronization method according to any one of claims 1 to 6 when the computer instructions are executed by a processor.

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