Micro-nano vacuum triode based on self-packaging vacuum channel and semi-surrounding grid electrode

Abstract

The invention discloses a micro-nano vacuum triode based on a self-packaging vacuum channel and a semi-surrounding grid electrode. The triode comprises a substrate, a hyperbolic nanostructure and a semi-surrounding grid electrode, the hyperbolic nanostructure and the semi-surrounding grid electrode are arranged on the upper surface of the substrate, and the hyperbolic nanostructure penetrates through the semi-surrounding grid electrode; in the vertical direction of the substrate, the height of the semi-surrounding grid electrode is greater than that of the hyperbolic nanostructure; the hyperbolic nano structure comprises a nano micro-tip cathode, a nano micro-tip anode, a self-packaging oxide layer and a vacuum channel; the nanometer micro-tip cathode and the nanometer micro-tip anode are located on a first straight line, and a gap between the tip of the nanometer micro-tip cathode and the tip of the nanometer micro-tip anode is a vacuum channel; and the self-packaging oxide layer wraps the nano micro-tip cathode, the vacuum channel and the nano micro-tip anode. The triode has the characteristics of good grid control capability and no dependence on a high-vacuum-degree environment.

Description

Technical Field

[0001] The present invention relates to the technical field of vacuum electronic devices, and more particularly to a micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate. Background Art

[0002] Vacuum electron devices, one of the core components of early electronics, utilize vacuum as a carrier transport medium. They offer several distinct advantages: vacuum allows for ballistic electron propagation, eliminating optical and acoustic phonon scattering, resulting in minimal signal distortion; electrons in a vacuum can be accelerated to near the speed of light, enabling fast switching speeds; and electrons in a vacuum can operate at very high voltages and currents, enabling high power output. Furthermore, vacuum tubes outperform solid-state devices in harsh environments, both in terms of heat resistance and radiation resistance. This radiation resistance is due to the absence of radiation-induced defects found in solid semiconductors in a vacuum environment, as well as protection from direct damage by particle bombardment. Consequently, they hold broad application prospects in aerospace, defense, and communications. Traditional vacuum electron devices utilize hot cathodes for electron emission, resulting in large size and high power consumption. Due to limitations in machining processes, they cannot be integrated or miniaturized to meet the demands of high-speed information processing and high-frequency communication integrated circuits, and have therefore been gradually replaced by solid-state devices. Breakthroughs in nanometer field emission materials and devices, along with advances in micro- and nanofabrication technologies, have made it possible to fabricate highly integrated, novel vacuum micro- and nano-triodes. The micro-nano vacuum triode based on the field emission cathode structure is a type of field effect device that uses a vacuum channel as a "medium" for carrier transmission. It has the advantages of fast response speed, high operating frequency, low device power consumption, wide operating temperature range, and strong anti-radiation interference ability.

[0003] Currently, the submicron-scale electron transport distances of micro-nano vacuum transistors still require a high turn-on voltage and a high vacuum operating and testing environment. This, in turn, prevents the full utilization of the high-frequency advantages of vacuum devices, which, to a certain extent, limits the miniaturization and integration of micro-nano vacuum transistors. To address this issue, various approaches exist in the prior art, such as optimizing the gate structure (using the wrap-gate structure as an example) to enhance gate control capability, thereby achieving a lower turn-on voltage and larger device transconductance, thus enhancing frequency characteristics. Alternatively, shortening the device's vacuum channel to a length less than the mean free path of electrons in air reduces the device's high vacuum requirement. While these approaches enable the integration and operation of micro-nano vacuum transistors in low-vacuum environments, a stable, packaged operating environment that can be considered a "vacuum" is still necessary for long-term stable operation. Therefore, most research on micro-nano vacuum transistors still requires conducting them in vacuum chambers with high vacuum levels.

[0004] Prior art discloses a side-anode vacuum channel nanogap triode and its fabrication method. The nanogap triode comprises a cathode, an anode, a gate, and an oxide insulating layer. A nanogap refers to a device with electrical properties similar to those of a traditional field-effect transistor. Electrons are transported within the vacuum channel by ballistic transport or tunneling. Because the vacuum channel is smaller than or close to the mean free path of electrons in air, the driving voltage is less than the first ionization potential of molecules, allowing the device to function normally without strict vacuum packaging. The performance of this triode structure still has room for improvement, as the gate has a weak influence on the cathode. Summary of the Invention

[0005] The present invention addresses the shortcomings of existing technologies, such as poor gate control capability and high vacuum environment requirements, by providing a micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate. This triode has the characteristics of good gate control capability and is independent of a high vacuum environment.

[0006] The primary purpose of the present invention is to solve the above technical problems, and the technical solutions of the present invention are as follows:

[0007] A micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate, comprising: a substrate, a hyperbolic nanostructure, and a semi-surrounding gate;

[0008] The hyperbolic nanostructure and the semi-surrounding gate are both arranged on the upper surface of the substrate, and the hyperbolic nanostructure vertically passes through the semi-surrounding gate; in the vertical direction of the substrate, the height of the semi-surrounding gate is greater than the height of the hyperbolic nanostructure;

[0009] The hyperbolic nanostructure includes: a nano-micro tip cathode, a nano-micro tip anode, a self-encapsulated oxide layer and a vacuum channel;

[0010] The nano-micro tip cathode and the nano-micro tip anode are on a first straight line, and the gap between the tip of the nano-micro tip cathode and the tip of the nano-micro tip anode is a vacuum channel; the self-encapsulated oxide layer wraps the nano-micro tip cathode, the vacuum channel and the nano-micro tip anode.

[0011] Furthermore, the length of the vacuum channel is 50 to 250 nm.

[0012] Furthermore, the thickness of the self-encapsulation oxide layer is 50-75 nm.

[0013] Furthermore, the material of the semi-surrounding gate is platinum metal, the material of the nano-micro-tip anode is Si, and the material of the nano-micro-tip anode is Si.

[0014] Furthermore, the material of the self-encapsulation oxide layer is SiO2.

[0015] Furthermore, the tip curvature radius of the nano-micro-tip cathode or the nano-micro-tip anode is 5 to 20 nm.

[0016] Furthermore, the height difference between the semi-surrounding gate and the substrate is 100-400 nm.

[0017] Furthermore, the substrate includes a base layer and an insulating layer, wherein the upper surface of the base layer is connected to the lower surface of the insulating layer, and the hyperbolic nanostructure is arranged on the upper surface of the insulating layer.

[0018] Furthermore, the material of the insulating layer is SiO2.

[0019] An electronic device comprises a micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] The triode of the present invention utilizes a self-encapsulated vacuum channel, allowing the micro-nano vacuum triode to operate in atmospheric environments, thereby reducing costs and enabling downsizing and integration. Furthermore, the semi-surrounding gate structure, compared to single- and double-gate structures, improves the gate control capability of the planar micro-nano vacuum triode, resulting in a lower turn-on voltage and a larger device transconductance, enhancing the device's frequency characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a structural diagram of the micro-nano vacuum triode based on the self-encapsulated vacuum channel and semi-surrounding gate provided in Example 1.

[0023] Figure 2 This is a cross-sectional view of the micro-nano vacuum triode based on the self-encapsulated vacuum channel and semi-surrounding gate provided in Example 1.

[0024] Figure 3 A top view of the micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate provided in Example 2.

[0025] Figure 4 A top view of the micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate provided in Example 3.

[0026] Figure 5 A top view of the micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate provided in Example 4.

[0027] Figure 6 A top view of the micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate provided in Example 5.

[0028] Figure 7 This is a diagram showing the relationship between the gate-cathode height difference and the gate control capability provided in Example 5.

[0029] Figure 8 A diagram showing the relationship between the gate structure and gate control capability provided in Example 5.

[0030] Figure 9 A top view of the micro-nano vacuum triode based on the self-encapsulated vacuum channel and double-side gate structure provided in Example 5.

[0031] Figure 10 A top view of the micro-nano vacuum triode based on the self-packaged vacuum channel and buried gate structure provided in Example 5.

[0032] Figure 11 A top view of the micro-nano vacuum triode based on the self-encapsulated vacuum channel and back-gate structure provided in Example 5. DETAILED DESCRIPTION

[0033] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting this patent;

[0034] In order to better illustrate this embodiment, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product size;

[0035] It is understandable to those skilled in the art that some well-known structures and descriptions thereof may be omitted in the drawings.

[0036] The technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

[0037] Example 1

[0038] like Figure 1 、 Figure 2 As shown, a micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate comprises: a substrate 1, a hyperbolic nanostructure 2, and a semi-surrounding gate 3;

[0039] The hyperbolic nanostructure 2 and the semi-surrounding gate 3 are both arranged on the upper surface of the substrate 1, and the hyperbolic nanostructure 2 vertically passes through the semi-surrounding gate 3; in the vertical direction of the substrate 1, the height of the semi-surrounding gate 3 is greater than the height of the hyperbolic nanostructure 2;

[0040] The hyperbolic nanostructure 2 includes: a nano-micro-tip cathode 201, a nano-micro-tip anode 202, a self-encapsulated oxide layer 203 and a vacuum channel 204;

[0041] The nano-micro-tip cathode 201 and the nano-micro-tip anode 202 are on a first straight line, and the gap between the tip of the nano-micro-tip cathode 201 and the tip of the nano-micro-tip anode 202 is a vacuum channel 204; the self-encapsulated oxide layer 203 wraps the nano-micro-tip cathode 201, the vacuum channel 204 and the nano-micro-tip anode 202.

[0042] It should be noted that the symmetry axis of the semi-surrounding gate 3 and the first straight line are located on the same plane.

[0043] It should be noted that, compared with the double-side gate structure, buried gate structure and back gate structure, the semi-surrounding gate structure is beneficial to enhancing the gate control capability of the device.

[0044] It should be noted that a preferred solution is to have the first side of the semi-surrounding gate 3 pass through the midpoint of the vacuum channel 204, and the second side be 250 nm away from the tip of the nano-micro-tip cathode, with the first and second sides positioned opposite each other. The vertical projection of the semi-surrounding gate 3 does not overlap with the nano-micro-tip anode. This improves gate control performance and, because it maintains a distance from the anode, reduces gate leakage current.

[0045] It should be noted that the horizontal distance (gate-cathode height difference) from the side of the semi-surrounding gate 3 close to the nano-micro-tip anode to the tip of the nano-micro-tip cathode 201 is in the range of -260 nm to 260 nm.

[0046] Furthermore, the length of the vacuum channel 204 is 50-250 nm.

[0047] Furthermore, the thickness of the self-encapsulation oxide layer 203 is 50-75 nm.

[0048] Furthermore, the material of the semi-surrounding gate is platinum metal, the material of the nano-micro tip anode 202 is Si, and the material of the nano-micro tip anode 202 is Si.

[0049] It should be noted that arcs 205 are respectively provided on both sides of the hyperbolic nanostructure 2 at positions opposite to the vacuum channel 204, and the line connecting the centers of the arcs 205 is perpendicular to the first straight line. The diameter of the arcs 205 is 300-500 nm.

[0050] Furthermore, the material of the self-encapsulation oxide layer 203 is SiO 2 .

[0051] It should be noted that the length of the semi-surrounding gate 3 in the first straight line direction ranges from 200 nm to 500 nm.

[0052] Furthermore, the tip curvature radius of the nano-micro-tip cathode 201 or the nano-micro-tip anode 202 is 5 to 20 nm.

[0053] Furthermore, the height difference between the semi-surrounding gate 3 and the substrate 1 is 100-400 nm.

[0054] Furthermore, the substrate 1 includes a base layer 101 and an insulating layer 102 , wherein the upper surface of the base layer 1 is connected to the lower surface of the insulating layer 102 , and the hyperbolic nanostructure 2 is disposed on the upper surface of the insulating layer 102 .

[0055] In a specific embodiment, the base layer 101 of the substrate 1 is made of P-type silicon.

[0056] Furthermore, the material of the insulating layer 102 is SiO 2 .

[0057] An electronic device comprises the micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate.

[0058] Example 2

[0059] Based on the micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate described in Example 1, that is, this embodiment adopts the same micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate as in Example 1. Figure 3 As shown, the semi-surrounding gate 3 of the triode of this embodiment wraps around three sides of a bowtie-shaped hyperbolic nanostructure. Its geometric coverage along the axial direction is strictly limited to the cathode cone region and part of the adjacent vacuum channel, maintaining a 100nm spacing from the anode cone region. The vacuum channel is located between the cathode and anode cones and is self-aligned along the same axial direction with the cathode and anode. The oxide layer wraps around the entire structure, achieving self-encapsulation of the anode, cathode, and vacuum channel.

[0060] The thickness of the self-encapsulated oxide layer (60nm), the vacuum channel length (100nm), and the curvature radius of the cone (10nm) were set to fixed values. The gate width was 250nm, and the gate-cathode height difference was 0. A simulation model was built in COMSOL Multiphysics software and finite element analysis was performed. An electrostatic module was added, and the cathode was always grounded. When a 10V voltage was applied to the anode and gate respectively and the other electrode was grounded, the electric field strength on the cathode cone surface was recorded as F. a and F g Finally, we get F g 1.75×10 8 V / m, F a 1.64×10 8 V / m, the ratio of the two is F g / F a is 1.06.

[0061] Example 3

[0062] Based on the micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate described in Example 1, that is, this embodiment adopts the same micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate as in Example 1. Figure 4 As shown, the self-encapsulation oxide layer thickness (60nm), vacuum channel length (100nm) and cone curvature radius (10nm) are set to fixed values, while the gate width is 225nm, and the gate-to-cathode height difference is -25nm.

[0063] Add an electrostatic module and keep the cathode always grounded. Get the electric field strength on the cathode cone surface when 10V voltage is applied to the anode and grid respectively and the other electrode is grounded, which is recorded as F a and F g Finally, we get F g 1.14×10 8 V / m, F a 1.81×10 8 V / m, the ratio of the two is F g / F a It is 0.63.

[0064] Example 4

[0065] Based on the micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate described in Example 1, that is, this embodiment adopts the same micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate as in Example 1. Figure 5 As shown, the self-encapsulation oxide layer thickness (60nm), vacuum channel length (100nm) and cone curvature radius (10nm) are set as fixed values, while the gate width is 275nm, and the gate-to-cathode height difference is 25nm.

[0066] Add an electrostatic module and keep the cathode always grounded. The simulation results show the electric field strength on the cathode cone surface when the anode and the gate are both applied with 10V voltage and the other electrode is grounded, which is recorded as F. a and F g . The simulation results show that F g 2.47×10 8 V / m, F a 1.34×10 8 V / m, the ratio of the two is F g / F a It is 1.87.

[0067] Example 5

[0068] Based on the micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate described in Example 1, that is, this embodiment adopts the same micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate as in Example 1. Figure 6As shown, the self-encapsulation oxide layer thickness (60nm), vacuum channel length (100nm) and cone curvature radius (10nm) are set as fixed values, while the gate width is 300nm, and the gate-to-cathode height difference is 50nm.

[0069] Add an electrostatic module and keep the cathode always grounded. The simulation results show the electric field strength on the cathode cone surface when the anode and the gate are both applied with 10V voltage and the other electrode is grounded, which is recorded as F. a and F g . The simulation results show that F g 3.02×10 8 V / m, F a 9.72×10 7 V / m, the ratio of the two is F g / F a It is 3.11.

[0070] like Figure 7 As shown, the greater the height difference between the gate and cathode, the greater the F of the micro-nano vacuum triode. g and F g / F a This indicates that the gate of this structure has a stronger influence on the cathode tip surface, which is beneficial to enhance the gate control capability of the device.

[0071] F of half-surround gate, double-side gate, buried gate and back gate structures when the gate is flat (the height difference between the gate and the cathode is 0) a 、F g and F g / F a ,like Figure 8 As shown. It can be seen that the semi-surrounding gate structure has the largest F g (1.75×10 8 V / m) and F g / F a The value is (1.06, 32.5% higher than that of the double-side gate structure), which indicates that the gate of this structure has a stronger influence on the cathode cone surface, which is beneficial to enhancing the gate control capability of the device.

[0072] The following is Figure 8 Specific parameters of double side gate, buried gate and back gate structures:

[0073] like Figure 9As shown in the figure, the double-side-gate micro-nano vacuum triode comprises a silicon oxide insulating layer, a metal gate, and a hyperbolic nanostructure (comprising an oxide layer, a Si cathode, a Si anode, and a vacuum channel). The vacuum channel is located between the cathode and anode cones, self-aligned along the same axis as the cathode and anode. The oxide layer wraps around the entire structure, achieving self-encapsulation of the anode, cathode, and vacuum channel. The metal gate and the hyperbolic nanostructure are located in the same plane, symmetrically distributed on either side of the bowtie-shaped hyperbolic nanostructure, with the gate orientation perpendicular to the device axis.

[0074] The oxide layer thickness (60nm), channel length (100nm), and cone curvature radius (10nm) are set to fixed values, the gate width is 250nm, and the gate-cathode height difference is 0. Add an electrostatic module and keep the cathode always grounded. The simulation obtains the electric field strength on the cathode cone surface when 10V voltage is applied to the anode and gate respectively and the other electrode is grounded, which is recorded as F a and F g . The simulation results show that F g 1.38×10 8 V / m, F a 1.72×10 8 V / m, the ratio of the two is F g / F a is 0.80.

[0075] like Figure 10 As shown in the figure, the buried-gate micro-nano vacuum triode comprises a silicon oxide insulating layer, a metal gate, and a hyperbolic nanostructure (comprising an oxide layer, a Si cathode, a Si anode, and a vacuum channel). The vacuum channel is located between the cathode and anode cones, self-aligned along the same axis as the cathode and anode. The oxide layer wraps around the entire structure, achieving self-encapsulation of the anode, cathode, and vacuum channel. The metal gate is buried in the silicon oxide insulating layer beneath the hyperbolic nanostructure, separated from the cathode by the oxide layer, and the gate orientation is perpendicular to the device axis.

[0076] The oxide layer thickness (60nm), channel length (100nm), and cone curvature radius (10nm) are set to fixed values, the gate width is 250nm, and the gate-cathode height difference is 0. Add an electrostatic module and keep the cathode always grounded. The simulation obtains the electric field strength on the cathode cone surface when 10V voltage is applied to the anode and gate respectively and the other electrode is grounded, which is recorded as F a and F g . The simulation results show that F g 7.30×10 7 V / m, F a 1.79×10 8 V / m, the ratio of the two is F g / F a It is 0.41.

[0077] like Figure 11 As shown in the figure, the back-gate micro-nano vacuum triode comprises a silicon oxide insulating layer, a metal gate, and a hyperbolic nanostructure (comprising an oxide layer, a Si cathode, a Si anode, and a vacuum channel). The vacuum channel is located between the cathode and anode cones, self-aligned along the same axis as the cathode and anode. The oxide layer wraps around the entire structure, achieving self-encapsulation of the anode, cathode, and vacuum channel. The metal gate is located in the silicon oxide insulating layer beneath the hyperbolic nanostructure, covering the entire plane and separated from the cathode by an oxide layer.

[0078] Set the oxide layer thickness (60nm), channel length (100nm) and cone curvature radius (10nm) to fixed values. Add an electrostatic module and keep the cathode always grounded. The simulation obtains the electric field strength on the cathode cone surface when the anode and gate are applied with 10V voltage respectively and the other electrode is grounded, which is recorded as F a and F g . The simulation results show that F g 1.23×10 8 V / m, F a 1.43×10 8 V / m, the ratio of the two is F g / F a It is 0.86.

[0079] The same or similar reference numerals correspond to the same or similar components;

[0080] The terms used in the drawings to describe positional relationships are for illustrative purposes only and should not be construed as limiting this patent;

[0081] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the claims of the present invention.

Claims

1. A micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate, characterized in that: include: Substrate (1), hyperbolic nanostructure (2), semi-surrounding gate (3); The hyperbolic nanostructure (2) and the semi-surrounding gate (3) are both arranged on the upper surface of the substrate (1), and the hyperbolic nanostructure (2) vertically passes through the semi-surrounding gate (3); in the vertical direction of the substrate (1), the height of the semi-surrounding gate (3) is greater than the height of the hyperbolic nanostructure (2); The hyperbolic nanostructure (2) comprises: a nanometer micro-tip cathode (201), a nanometer micro-tip anode (202), a self-encapsulated oxide layer (203) and a vacuum channel (204); The nano-micro tip cathode (201) and the nano-micro tip anode (202) are on a first straight line, and a gap between the tip of the nano-micro tip cathode (201) and the tip of the nano-micro tip anode (202) is a vacuum channel (204); the self-encapsulated oxide layer (203) wraps the nano-micro tip cathode (201), the vacuum channel (204) and the nano-micro tip anode (202).

2. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The length of the vacuum channel (204) is 50 to 250 nm.

3. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The thickness of the self-encapsulation oxide layer (203) is 50-75 nm.

4. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The material of the semi-surrounding gate (3) is platinum metal, the material of the nano-micro tip anode (202) is Si, and the material of the nano-micro tip anode (202) is Si.

5. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The material of the self-encapsulation oxide layer (203) is SiO2.

6. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The tip curvature radius of the nanometer micro-tip cathode (201) or the nanometer micro-tip anode (202) is 5 to 20 nm.

7. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The height difference between the semi-surrounding gate (3) and the substrate (1) is 100-400 nm.

8. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 1, characterized in that: The substrate (1) comprises a base layer (101) and an insulating layer (102), wherein the upper surface of the base layer (1) is connected to the lower surface of the insulating layer (102), and the hyperbolic nanostructure (2) is arranged on the upper surface of the insulating layer (102).

9. The micro-nano vacuum triode based on a self-encapsulated vacuum channel and a semi-surrounding gate according to claim 8, characterized in that: The material of the insulating layer (102) is SiO2.

10. An electronic device, characterized in that: The invention comprises the micro-nano vacuum triode based on the self-encapsulated vacuum channel and the semi-surrounding gate as claimed in any one of claims 1 to 9.

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