Data interaction adaptive method of photovoltaic protocol converter

Abstract

The invention discloses a data interaction self-adaptive method for a photovoltaic protocol converter, and particularly relates to the technical field of power grid dispatching cooperative control. The method comprises the following steps: monitoring and calculating a voltage instantaneous change rate of a grid-connected point of a power grid in real time, and comparing the voltage instantaneous change rate with a threshold value; when a threshold value is exceeded, synchronously collecting a current phase and generating a voltage and current phase difference change direction; extracting a voltage high-frequency component, analyzing frequency band energy distribution through wavelet packet decomposition, and calculating a Shannon entropy representing an energy concentration ratio; when the phase difference change direction accords with a preset power grid short-circuit fault feature and the Shannon entropy value is lower than a preset entropy threshold value, determining that a power grid transient event occurs; at the moment, a data caching mechanism of the protocol converter is stopped immediately, and a real-time stream transmission channel is activated; an emergency control instruction issued by a power grid dispatching system is directly transmitted to the photovoltaic inverter through the channel; and when the voltage instantaneous change rate is continuously lower than the preset threshold value for a preset duration, recovering the data caching mechanism of the protocol converter.

Description

Technical Field

[0001] The present invention relates to the technical field of power grid dispatching coordinated control, and more specifically, to a data interaction adaptive method for a photovoltaic protocol converter. Background Art

[0002] In photovoltaic power plant monitoring systems, protocol converters serve as the key link between photovoltaic equipment and the grid dispatching platform, facilitating the conversion and transmission of heterogeneous data from multiple sources. To improve communication efficiency, current mainstream protocol converters generally employ a data caching mechanism—storing collected device status information (such as inverter output and grid connection point voltage) locally in batches until the data packet reaches a preset capacity or time window, before sending it to the higher-level system. This design significantly reduces communication link load, meeting the requirements of industrial control systems for optimizing resource utilization.

[0003] However, when transient events such as short circuit faults and voltage drops occur in the power grid, the dispatching system needs to issue emergency control instructions to the photovoltaic power station in a very short time. The inherent data delay characteristics of the existing cache mechanism prevent key instructions from penetrating the protocol conversion layer in a timely manner, causing the dynamic response capability of the photovoltaic power station to lag behind the time window requirements for grid safety protection. This contradiction between the timeliness of data transmission and the real-time nature of grid transient processes has become a technical bottleneck that restricts photovoltaic power stations from actively supporting the safe operation of the grid. Summary of the Invention

[0004] In order to overcome the above-mentioned defects of the prior art, the present invention provides a data interaction adaptive method of a photovoltaic protocol converter to solve the problems raised in the above-mentioned background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A data interaction adaptive method for a photovoltaic protocol converter includes the following steps:

[0007] S1. Real-time monitoring of the grid connection point voltage, calculation of the instantaneous rate of change of the grid connection point voltage and comparison with the preset threshold in real time;

[0008] S2. When the instantaneous rate of change exceeds a preset threshold, synchronously collect the current phase of the grid connection point and generate the phase difference change direction between the grid connection point voltage and the grid connection point current phase;

[0009] S3. Extract the high-frequency component of the grid connection point voltage, analyze the frequency band energy distribution of the high-frequency component through wavelet packet decomposition, and obtain the Shannon entropy value that represents the energy concentration;

[0010] S4. When the phase difference change direction meets the preset grid short-circuit fault characteristics and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a grid transient event;

[0011] S5. When the current event is a transient power grid event, the data buffering mechanism of the protocol converter is immediately stopped, and the real-time streaming transmission channel is activated;

[0012] S6. Forwarding the emergency control command issued by the grid dispatching system directly to the photovoltaic inverter through the real-time streaming transmission channel;

[0013] S7. When the instantaneous change rate continues to be lower than the preset threshold for a preset time period, the data cache mechanism of the protocol converter is restored.

[0014] Furthermore, the voltage at the grid connection point is monitored in real time, the instantaneous rate of change of the voltage at the grid connection point is calculated and compared with a preset threshold in real time, including:

[0015] Continuously collect the instantaneous value of the grid connection point voltage;

[0016] Calculate the instantaneous rate of change based on the difference between adjacent sampling points of the instantaneous value of the grid connection point voltage;

[0017] Compare the instantaneous rate of change with the preset threshold in real time;

[0018] When the absolute value of the instantaneous rate of change is continuously greater than a preset threshold value for more than a preset time, a flag signal for triggering synchronous acquisition of the grid connection point current phase is generated.

[0019] Furthermore, when the instantaneous change rate exceeds a preset threshold, the current phase of the grid connection point is synchronously collected to generate a phase difference change direction between the grid connection point voltage and the grid connection point current phase, including:

[0020] Based on the flag signal, the voltage phase sequence and the current phase sequence at the grid connection point are synchronously obtained within the first power frequency cycle after the fault occurs.

[0021] Calculate the instantaneous phase difference between the grid connection point voltage phase and the grid connection point current phase at each sampling moment;

[0022] Perform trend fitting on the instantaneous phase difference values ​​at multiple consecutive sampling moments;

[0023] The slope value of the trend fitting result is used as the direction of phase difference change.

[0024] Furthermore, the high-frequency component of the grid connection point voltage is extracted, and the frequency band energy distribution of the high-frequency component is analyzed by wavelet packet decomposition to obtain the Shannon entropy value that represents the energy concentration, including:

[0025] Intercepting the grid connection point voltage waveform within a preset time period after the fault determination moment as the signal to be analyzed;

[0026] Perform wavelet packet decomposition on the signal to be analyzed to obtain multiple sub-band signals;

[0027] Calculate the energy value of each sub-band signal;

[0028] calculating frequency band energy distribution based on the energy values;

[0029] The frequency band energy distribution is input into the Shannon entropy formula, and the Shannon entropy value representing the energy concentration is output.

[0030] Furthermore, when the phase difference change direction meets the preset grid short circuit fault characteristics and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a grid transient event, including:

[0031] Perform pattern matching on the phase difference change direction and the preset power grid short circuit fault feature library;

[0032] At the same time, the Shannon entropy value is compared with the preset entropy threshold;

[0033] When the phase difference change direction matches the preset power grid short circuit fault characteristics and the Shannon entropy value is less than the preset entropy threshold, a power grid transient event determination signal is generated.

[0034] Furthermore, the grid transient event determination signal is used to trigger the termination of the data buffering mechanism of the protocol converter.

[0035] Furthermore, when a transient power grid event occurs, the data buffering mechanism of the protocol converter is immediately stopped, and the real-time streaming transmission channel is activated, including:

[0036] receiving a power grid transient event determination signal;

[0037] Stop writing newly acquired device status information to the data buffer of the protocol converter;

[0038] Clear the unsent data in the data buffer of the protocol converter;

[0039] A real-time streaming transmission channel independent of a buffer mechanism is established at the communication link layer of the protocol converter.

[0040] Furthermore, the real-time streaming transmission channel is used to transmit emergency control instructions issued by the power grid dispatching system.

[0041] Furthermore, the emergency control instructions issued by the grid dispatching system are directly forwarded to the photovoltaic inverter through the real-time streaming channel, including:

[0042] Receive the original data stream of emergency control instructions issued by the power grid dispatching system through the real-time streaming channel;

[0043] Keep the protocol encapsulation format of the original data stream of the emergency control command unchanged;

[0044] Transmit the original data stream of emergency control instructions to the communication interface of the photovoltaic inverter;

[0045] No protocol parsing or data caching is performed during transparent transmission.

[0046] Furthermore, when the instantaneous rate of change is continuously lower than a preset threshold for a preset period of time, the data caching mechanism of the protocol converter is restored, including:

[0047] Monitor the absolute value of the instantaneous rate of change of the voltage at the grid connection point;

[0048] When the absolute value of the instantaneous change rate is continuously lower than the preset threshold for a preset period of time, a cache recovery instruction is generated;

[0049] Re-enable the data buffer write function of the protocol converter according to the buffer recovery instruction;

[0050] Restore the normal caching operation of the data cache mechanism of the protocol converter for device status information.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] The photovoltaic protocol converter data interaction and adaptive method provided by the present invention uses real-time monitoring of the instantaneous rate of change of the grid connection point voltage as a preliminary trigger signal, and combines the phase difference change direction characteristics of the grid connection point voltage and current phase and the Shannon entropy value of the energy distribution of the voltage high-frequency component to make a collaborative judgment. It can accurately identify transient events such as grid short-circuit faults. This multi-dimensional, multi-criteria recognition mechanism effectively reduces the risk of misjudgment of single-feature judgment and significantly improves the accuracy and reliability of grid transient event judgment.

[0053] After accurately determining a grid transient event, the original data caching mechanism of the protocol converter is immediately terminated, and a dedicated real-time streaming transmission channel is synchronously activated, allowing the emergency control instructions issued by the grid dispatching system to bypass conventional data caching and processing procedures and be directly transmitted to the photovoltaic inverter for execution with extremely low latency. At the same time, this method also has self-recovery capabilities. After the grid state returns to stability, it can automatically restore the data caching mechanism of the protocol converter based on the duration that the instantaneous rate of voltage change remains continuously below the threshold. This effectively solves the key problem of transmission delay of emergency control instructions during grid transients, ensures the rapid response capability of photovoltaic power stations in the event of grid faults, improves the safe and stable operation level of the grid, and takes into account the communication efficiency optimization needs of the system under normal operating conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 The present invention provides a flow chart of a data interaction and self-adaptation method for a photovoltaic protocol converter. DETAILED DESCRIPTION

[0055] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] Example: Figure 1 The present invention provides a data interaction adaptive method for a photovoltaic protocol converter, which includes the following steps:

[0057] S1. Real-time monitoring of the grid connection point voltage, calculation of the instantaneous rate of change of the grid connection point voltage and comparison with the preset threshold in real time;

[0058] S2. When the instantaneous rate of change exceeds a preset threshold, synchronously collect the current phase of the grid connection point and generate the phase difference change direction between the grid connection point voltage and the grid connection point current phase;

[0059] S3. Extract the high-frequency component of the grid connection point voltage, analyze the frequency band energy distribution of the high-frequency component through wavelet packet decomposition, and obtain the Shannon entropy value that represents the energy concentration;

[0060] S4. When the phase difference change direction meets the preset grid short-circuit fault characteristics and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a grid transient event;

[0061] S5. When the current event is a transient power grid event, the data buffering mechanism of the protocol converter is immediately stopped, and the real-time streaming transmission channel is activated;

[0062] S6. Forwarding the emergency control command issued by the grid dispatching system directly to the photovoltaic inverter through the real-time streaming transmission channel;

[0063] S7. When the instantaneous change rate continues to be lower than the preset threshold for a preset time period, the data cache mechanism of the protocol converter is restored.

[0064] Continuously collect instantaneous voltage values ​​at the grid connection point: This system uses a voltage transformer to obtain instantaneous voltage measurements at the grid connection point at a fixed sampling frequency. The sampling frequency is set based on the transient characteristics of the power system to ensure that sudden voltage changes can be captured. The specific sampling frequency is determined according to the Nyquist sampling theorem and must be greater than twice the highest frequency component of interest in the grid. For example, in a system containing 20th harmonics, this frequency is set to 10 kHz.

[0065] The instantaneous rate of change is calculated based on the difference between the instantaneous voltage values ​​at adjacent sampling points at the grid connection point. The instantaneous voltage values ​​at two consecutive sampling moments are subtracted from the previous instantaneous voltage value. The resulting difference is divided by the time interval between the two sampling points to obtain the voltage change per unit time, which is the instantaneous rate of change. The time interval is determined by the inverse of the sampling frequency; for example, a 10 kHz sampling rate corresponds to a 0.1 millisecond interval. The calculation process is performed in real time by the arithmetic logic unit, ensuring that the calculation result is updated at each sampling point.

[0066] The instantaneous rate of change is compared in real time against a preset threshold. The threshold is set based on the maximum voltage mutation rate allowed for safe grid operation. This value is obtained through power system stability simulation and historical fault data analysis. This comparison is implemented using a hardware comparator. When the absolute value of the instantaneous rate of change is input into the comparator, a high or low level signal is output in real time to indicate whether the threshold has been exceeded. The threshold setting must account for equipment measurement errors and include a margin of, for example, 3% to 5%, above the standard value.

[0067] When the absolute value of the instantaneous rate of change remains above a preset threshold for a predetermined period, a flag signal is generated to trigger synchronous acquisition of the grid connection point current phase. This preset period is determined by the grid fault duration characteristics. This is determined by statistically analyzing the voltage dip duration distribution of typical short-circuit faults and taking the median value from the interval with the highest probability density. For example, for medium-voltage distribution networks, this is set to 2 milliseconds. Duration verification is implemented using a timer: When the comparator first outputs an over-limit signal, a timer is started. If the over-limit condition persists for a predetermined period, a flag signal is triggered. If the condition falls below the threshold during this period, the timer is reset. The flag signal is a digital level signal and is transmitted to the current phase acquisition module via the control bus.

[0068] The voltage transformer's measurement accuracy must meet the 0.2-level precision specified by the International Electrotechnical Commission (IEC) standard. The sampling clock must be strictly synchronized with the current acquisition system, with a synchronization error of less than 1 microsecond. The division operation in the instantaneous rate of change calculation is implemented using a fixed-point arithmetic unit, and the data bit width is set according to the measurement range, for example, using a 16-bit signed integer bit width. Thresholds are stored in non-volatile memory and can be modified online via host computer software. The timer uses a high-frequency crystal oscillator as its clock source, with a timebase resolution of 100 nanoseconds, ensuring the accuracy of the preset time determination. The flag signal generation logic is implemented using a programmable logic device, and the output interface conforms to standard serial communication electrical specifications.

[0069] The calculation of the difference between adjacent sampling points includes a data validity check: if the difference between the instantaneous voltage value at the current sampling point and the previous sampling point exceeds a specific ratio of the rated voltage, for example, 30% of the rated voltage, the abnormal data filtering mechanism is activated, discarding the current value and replacing it with the previous valid value. The preset time can be adjusted from 1 millisecond to 5 milliseconds and is dynamically configured by writing register parameters based on the short-circuit capacity level of the grid connection point. Digital filtering is implemented during the instantaneous voltage acquisition process, using a low-pass filter with a specific cutoff frequency, such as a fourth-order Butterworth low-pass filter with a cutoff frequency of 500 Hz, to eliminate the impact of measurement noise on the instantaneous rate of change calculation.

[0070] The secondary output signal of the voltage transformer is converted by a signal conditioning circuit into a voltage range suitable for sampling, for example, converting a 100V AC input into a 0 to 3.3V DC signal. The accuracy of the sampling time is ensured by a phase-locked loop circuit, whose reference signal is derived from the grid voltage fundamental component. The calculation process for the instantaneous rate of change includes sign manipulation: a positive value is output when the voltage rises and a negative value is output when the voltage falls. Absolute value calculation uses a full-wave rectifier circuit or digital absolute value operation. The threshold setting range of the hardware comparator covers the maximum transient rate of change that may occur in the grid, for example, it is adjustable from 0.1 per unit per second to 1 per unit per second.

[0071] The continuous over-limit determination mechanism includes anti-interference design: When the instantaneous rate of change fluctuates near the threshold, a hysteresis interval is set to avoid frequent triggering, such as a 5% hysteresis band at the threshold boundary. After the flag signal is generated, it remains valid until the system is reset, ensuring reliable triggering of subsequent steps. The accuracy of the time interval between adjacent sampling points is guaranteed by a temperature-compensated crystal oscillator, maintaining a frequency stability of 50 parts per million across the full operating temperature range. The replacement strategy of the abnormal data filtering mechanism includes a linear interpolation option: when two consecutive sampling points are judged to be abnormal, the abnormal value is replaced by the linear interpolation result of the previous and next valid sampling points.

[0072] The design parameters of the digital filter are adjusted based on the spectral characteristics of the power grid's background noise. For example, the cutoff frequency is increased to 1 kHz in environments with strong harmonics. The program logic of the programmable logic device includes a watchdog timer to prevent program errors and false triggering. The control bus uses differential signal transmission, such as the RS-485 physical layer protocol, to enhance immunity to electromagnetic interference. The host computer software configuration interface provides engineering unit conversion for threshold preset values, supporting bidirectional conversion between per-unit values ​​and volts per millisecond, for example.

[0073] The calculation results of the arithmetic logic unit are managed in a circular storage buffer, retaining a historical record of the instantaneous rate of change for the last 100 sampling points. The reset timer condition includes a timeout reset mechanism: if the over-limit state persists for less than a preset time, and the duration exceeds the maximum allowable value, such as 10 milliseconds, the timer is forced to reset and a device abnormality alarm is issued. The frequency response characteristics of the voltage transformer are calibrated, with an amplitude error of less than 0.5% and a phase offset of less than 0.1 degrees within the range of 50 Hz to 2 kHz.

[0074] The division operation in calculating the difference between adjacent sampling points is implemented using shift-and-add, avoiding the use of the floating-point unit and reducing latency. Write operations to the non-volatile memory include power-off protection, preserving the most recent configuration parameters in the event of a power failure. The fourth-order Butterworth filter is implemented using a direct type-II structure, with coefficients dynamically calculated based on the sampling rate. The control bus transmission protocol includes an error check field and uses a cyclic redundancy check (CRC) to ensure signal transmission reliability. The host computer software provides a threshold optimization function that automatically recommends threshold ranges by analyzing historical fault data.

[0075] The configuration data of programmable logic devices (PLDs) includes multiple backups, and the primary and backup configuration data are compared in real time for consistency and integrity. The frequency calibration of the high-frequency crystal oscillator uses an automatic temperature compensation algorithm, dynamically adjusting the oscillation parameters based on temperature sensor data. The activation conditions for the linear interpolation substitution strategy are configurable, for example, allowing for a threshold for the number of consecutive abnormal sampling points. The watchdog timer's timeout is set to twice the preset time; for example, when the preset time is 2 milliseconds, the watchdog timeout is set to 4 milliseconds. Data updates in the circular storage buffer are managed using head and tail pointers, automatically overwriting the oldest historical data after each sampling.

[0076] The synchronous acquisition process is initiated based on a flag signal: Upon receiving the flag signal generated by the real-time grid connection point voltage monitoring step, the synchronous acquisition timing control of the grid connection point voltage phase and the grid connection point current phase is immediately triggered. This flag signal is a digital pulse signal, and its rising edge marks the starting point of the fault determination. The startup delay of the synchronous acquisition is controlled within the microsecond level, ensuring that data capture is completed within the first power frequency cycle after the fault occurs.

[0077] During the first power frequency cycle after a fault occurs, the voltage and current phase sequences at the grid connection point are synchronously acquired. Phase-locked loop (PLL) technology is used to lock the sampling clock to the grid fundamental frequency, ensuring strict synchronization of voltage and current sampling. The voltage phase sequence is calculated by continuously measuring the time intervals between the zero-crossing points of the instantaneous voltage at the grid connection point. The current phase sequence is processed using the same method for the instantaneous current at the grid connection point. The sampling frequency is set based on the power frequency cycle. For example, when a 50 Hz system uses a 10 kHz sampling rate, phase data is collected from 200 sampling points within a single power frequency cycle. The signal transmission delays of the voltage transformer and current transformer are calibrated and compensated, and the compensation values ​​are stored in non-volatile memory.

[0078] Calculate the instantaneous phase difference between the grid connection point voltage phase and the grid connection point current phase at each sampling moment: Subtract the voltage and current phase values ​​at the same sampling moment to obtain the phase difference in radians. The phase value calculation uses the inverse tangent function to process the quadrature components, which are obtained by Hilbert transform or hardware quadrature sampling. For example, the instantaneous voltage value is input to the quadrature decomposition module of a digital signal processor, which outputs the in-phase and quadrature components and calculates the phase angle. The calculated instantaneous phase difference is stored in a circular buffer with a buffer depth equal to the number of sampling points within the power frequency cycle.

[0079] Perform trend fitting on the instantaneous phase difference values ​​at multiple consecutive sampling moments: select all instantaneous phase difference values ​​within the first power frequency cycle after the fault occurs as the fitting data set. Trend fitting uses the least squares linear fitting method, with the independent variable being the sampling time series and the dependent variable being the instantaneous phase difference value sequence. The least squares calculation process includes the following steps: calculating the arithmetic mean of the sampling time series, calculating the arithmetic mean of the instantaneous phase difference value sequence, calculating the covariance between the sampling time series and the instantaneous phase difference value sequence, calculating the variance of the sampling time series, and dividing the covariance by the variance to obtain the slope value. The fitting process includes an outlier filtering mechanism. If the instantaneous phase difference value of a sampling point differs from the previous point by more than 0.1 radians, the point is marked as invalid and replaced by linear interpolation.

[0080] The slope of the trend fitting result is used as the direction of phase difference change. The slope value is set in radians per millisecond, and the sign indicates the direction of change: a positive sign indicates an increase in the phase difference, and a negative sign indicates a decrease. The calculated slope value is stored in a register and serves as an input parameter for subsequent grid transient event determination. The accuracy of the slope value calculation is ensured by the floating-point unit, with a mantissa width of at least 24 bits.

[0081] The reference signal for the phase-locked loop circuit is derived from the fundamental component of the grid connection point voltage and implemented using a digital phase detector, achieving a phase lock accuracy of 0.01 degrees. The quadrature decomposition module utilizes a finite impulse response filter, with the filter order set according to the sampling rate; for example, a 64-order filter is used at a 10 kHz sampling rate. The calculated instantaneous phase difference is subjected to a range check. If it exceeds the range of plus or minus π radians, a circular correction is applied. For example, if the difference exceeds π radians, 2π radians is subtracted. The time series used in the least-squares fitting method is zeroed at the fault trigger time, with time units in microseconds, and stored as 32-bit unsigned integers.

[0082] The outlier filtering mechanism's threshold is dynamically configurable, ranging from 0.05 radians to 0.2 radians, with a default of 0.1 radians. Linear interpolation replaces the interpolation calculation using the values ​​of two adjacent valid sampling points. The interpolation formula is the previous point value plus the difference between the previous and next points multiplied by the time scale factor. Slope values ​​are output as 32-bit floating-point numbers, with the sign bit representing the direction. The read and write pointers of the circular buffer are managed by the direct memory access controller, ensuring that data access does not consume CPU resources.

[0083] The Hilbert transform is implemented using a 90-degree phase-shift circuit combined with a finite impulse response filter, resulting in a phase-shift error of less than 0.5 degrees across the entire frequency band. The digital signal processor's operation cycle is strictly synchronized with the sampling cycle, completing the phase calculation within each sampling interval. The covariance calculation process uses an iterative algorithm, updating the cumulative sum and sum of squares after each sample, avoiding the delay caused by centralized calculation after the power frequency cycle ends. The circular correction logic includes boundary condition processing: when the instantaneous phase difference approaches negative π, if the difference at the new sampling point suddenly changes to near positive π, the curve is corrected to a continuously varying curve.

[0084] The burst transfer length of the direct memory access controller is set to an integer multiple of the number of sampling points in the power frequency cycle, for example, 200 sampling points are transmitted each time. The rounding mode of the floating-point unit is set to round towards zero to avoid cumulative errors. The division operation in the least squares calculation is accelerated using the Newton iteration method, with the number of iterations fixed at 3 to meet real-time requirements. The trend fitting result is determined by a confidence test: if the root mean square value of the fitting residual exceeds a threshold, for example, more than 0.05 radians, the current calculation result is discarded and an alternative calculation strategy is used.

[0085] The backup calculation strategy uses a median filter combined with a differential calculation: A five-point median filter is first applied to the instantaneous phase difference sequence. The difference between the first and last sampling points is then calculated and divided by the time interval to obtain the alternative slope value. The confidence threshold is stored in rewritable memory and can be modified remotely. The time scale factor is calculated using a hardware divider, with the numerator being the time difference between the current invalid point and the previous point, and the denominator being the time difference between the previous and next valid points. The residual root mean square (RMS) is calculated using a square root lookup table combined with linear interpolation, with a lookup table depth of 1024 points.

[0086] The timestamps for the sampling time series are generated by a high-precision timer with a clock frequency of 100 MHz and a time resolution of 10 nanoseconds. An adaptive algorithm is used to track the grid fundamental frequency. When the system frequency fluctuates between 49 Hz and 51 Hz, the phase-locked loop automatically adjusts the sampling timing. Quadrature component calibration is performed during equipment commissioning: a standard phase difference signal is applied and the filter coefficients are adjusted until the output phase error is less than 0.1 degrees. Invalid sampling points are marked in a separate status register, with each sampling point corresponding to a single flag bit.

[0087] The least-squares fitting process includes a data alignment mechanism. During each sampling interrupt service routine, the newly acquired instantaneous phase difference value is written to a specified buffer location and an accumulation counter is updated. When the counter reaches the number of sampling points in the power frequency cycle, a direct memory access (DMA) is triggered to transfer the data block to the coprocessor. After the coprocessor completes the slope calculation, it notifies the main processor via an interrupt to read the result. The time tolerance for data alignment is set to one-tenth of the sampling interval; for example, a 10-microsecond deviation is allowed at a 10-kHz sampling rate.

[0088] The circular correction of the instantaneous phase difference is conditional: if the jump between the current difference and the previous valid difference exceeds π radians, a correction of plus or minus 2π radians is applied. The corrected difference sequence undergoes a first-order difference operation, and the difference result is used to detect the instantaneous jump point. The phase-locked loop phase error detection uses a multiplicative phase detector, with a loop filter bandwidth of 10 Hz and a damping factor of 0.707. Direct digital frequency synthesis is used to generate the quadrature sampling clock, achieving a frequency resolution of 0.001 Hz.

[0089] The sampling buffer utilizes a dual-buffered storage structure: the current power frequency cycle data collection area is physically isolated from the previous cycle data processing area to prevent access conflicts. The slope value output register features dual redundant copies: a primary copy for output and a secondary copy for anomaly verification. When the difference between the primary and secondary copies exceeds a set threshold, for example, 5%, an invalid slope value alarm is triggered. This invalid alarm signal is synchronously output along with the slope value to subsequent decision steps for reliability assessment.

[0090] The covariance accumulator for the least squares method uses a 40-bit width to prevent overflow when accumulating 200 sampling points. The arithmetic mean of the time series is calculated by dividing the stored total value by the number of sampling points. This division is performed using a combination of table lookup and shifting. The instantaneous phase difference is stored in a fixed-point format, with a 3-bit integer representing positive and negative π radians and a 13-bit decimal corresponding to a resolution of 0.0001 radians. The interrupt response latency of the digital signal processor has been measured to be less than 500 nanoseconds, ensuring that every sampling point is processed completely.

[0091] The voltage waveform of the grid connection point within the preset time after the fault judgment moment is intercepted as the signal to be analyzed: the fault judgment moment is based on the rising edge of the marker signal from the phase difference change direction generation step. The preset time is set according to the duration of the transient process and is determined by analyzing the attenuation characteristics of the voltage high-frequency oscillation in the historical fault recording data, for example, 5 milliseconds. The interception operation is implemented through a circular storage buffer, and the buffer depth is designed according to the maximum preset time, for example, 10 milliseconds corresponds to 500 sampling points (10 kHz sampling rate). The interception starting point is the triggering moment of the marker signal, and the end point is the starting point plus the preset time, and the time mark alignment accuracy is 100 nanoseconds.

[0092] The signal to be analyzed is subjected to wavelet packet decomposition to obtain multiple subband signals. The mother wavelet for wavelet packet decomposition is selected based on the characteristics of high-frequency noise in the power grid, for example, a Daubechies 4th-order wavelet. The number of decomposition layers is determined by the preset time duration and frequency resolution requirements; for example, a three-layer decomposition produces eight subbands. The decomposition process includes the following steps: low-pass and high-pass filtering of the signal to be analyzed to obtain approximate coefficients and detail coefficients; recursively performing the same operation on the approximate coefficients and detail coefficients until the set number of layers is reached; and finally, a reconstruction algorithm is used to obtain the time domain signal for each subband. The filtering operation is implemented using convolution, and the convolution kernel coefficients are stored in read-only memory.

[0093] Calculate the energy of each subband signal: The energy value is defined as the sum of the squares of the amplitudes of all sampling points in the subband signal. This calculation is implemented using a hardware multiply-accumulator (M / A) function. Each sampling cycle completes the square operation for each point and accumulates the result in the corresponding band accumulator. The energy result is stored by band index as a 32-bit unsigned integer. A data range check is performed before the amplitude square operation. If the sample value exceeds 80% of the full-scale range, overflow protection is activated and the value is truncated to the maximum representable value.

[0094] The sub-band energy value is calculated as:

[0095]

[0096] Among them, E k is the energy value of the kth sub-band; k is the sub-band number; x k(n) represents the amplitude of the nth sampling point; n is the number of the sampling point; N is the number of sampling points.

[0097] Calculate the band energy distribution based on the energy values: The band energy distribution represents the proportion of each sub-band's energy to the total energy. The calculation process includes: summing all sub-band energy values ​​to obtain the total energy; and dividing each sub-band energy value by the total energy to obtain the energy proportion of the band.

[0098] The formula for calculating the frequency band energy ratio is:

[0099]

[0100] Among them, EnergyRatio specificBand Indicates the energy ratio value of the specificBand sub-band; EnergyValue specificBand Indicates the energy measurement value of the specificBand-th sub-band; TotalEnergy indicates the total energy value of all sub-bands; specificBand indicates the specific sub-band number currently being calculated.

[0101] The division operation uses the floating-point unit, and the scale value is stored as a single-precision floating-point number. The scale value calculation result is normalized and verified: the difference between the sum of the scale values ​​of all frequency bands and 1 is less than a certain tolerance, such as less than 0.001.

[0102] The frequency band energy distribution is input into the Shannon entropy formula, which outputs the Shannon entropy value representing the energy concentration. The Shannon entropy formula is defined as the negative sum of the energy ratio values ​​of each frequency band multiplied by the base-2 logarithm value of the ratio value. The calculation process is performed in three steps: calculating the base-2 logarithm value of each energy ratio value; multiplying the energy ratio value by the corresponding logarithm value; and summing and negating the product of all frequency bands. Logarithmic operations are implemented using a table lookup combined with linear interpolation. The lookup table covers the range of 0 to 1 with a step size of 0.001. The final entropy value is output as a single-precision floating-point number with three decimal places.

[0103] The Shannon entropy calculation formula is:

[0104]

[0105] Among them, ShannonEntropyResult represents the calculated Shannon entropy value; numberOfBand represents the total number of sub-bands; currentBand represents the sub-band number currently calculated (range 1 to numberOfBand); EnergyRatio currentBand It represents the energy ratio value of the currentBandth sub-band; log2 represents the logarithm operation with base 2.

[0106] The circular storage buffer uses a dual-pointer mechanism for address management: a write pointer tracks the latest sampling point in real time, while a read pointer locks the intercept interval when a flag signal is triggered. The recursive depth of the wavelet packet decomposition is controlled by a configurable register, allowing for 1 to 5 decomposition levels, with a default of 3 levels. The multiplication and accumulation results of the multiplier-accumulator are cleared after each subband calculation to prevent cross-band interference. The overflow protection threshold is adjustable online from 50% to 95% of full scale.

[0107] Normalization verification failure handling strategy: If the sum of the proportion values ​​differs from 1 by more than the tolerance, the total energy is recalculated and the proportion values ​​are redistributed. The logarithmic operation in the Shannon entropy calculation uses a piecewise approximation: when the proportion value is less than 0.001, the minimum value -10 is directly returned to avoid invalid calculations. Entropy values ​​are checked for validity before output: if all proportion values ​​are equal, the maximum entropy value is output; for example, if all eight sub-bands are equal, 3.0 is output; if a single sub-band accounts for 100%, 0 is output.

[0108] The mother wavelet coefficients are stored using symmetric compression: only half of the coefficients are stored by taking advantage of the symmetry of the wavelet function. The reconstruction algorithm uses tree-structured inverse filtering, first performing upsampling and then performing convolution operations. The multiplication and accumulation bit width is designed to take into account the worst case: the preset duration is 500 sampling points, the full-scale value is 32767, and the maximum sum of squares is 500×32767. 2 , corresponding to a 48-bit accumulator width. Floating-point division uses the Goldschmidt iterative algorithm with a fixed number of 3 iterations.

[0109] Logarithmic lookup table data generation: 1000 logarithmic values ​​are pre-calculated during device initialization and stored in static memory. The linear interpolation process involves calculating the fractional portion of the lookup table index based on the scale value and taking the weighted average of the two integer values. Negative signs in entropy calculations are handled using two's complement arithmetic, with the sign bit set separately. The maximum entropy value for validity checks is dynamically calculated based on the number of subbands, using the logarithm of the number of subbands.

[0110] Interval boundary processing: When the preset duration exceeds the end of the buffer, circular address mapping is used to access the beginning of the buffer. The filter convolution implementation of wavelet packet decomposition uses a transposed structure to reduce computational latency. When the multiplier-accumulator overflow protection is triggered, an event log is recorded, containing the overflow band index and sampling point location. The tolerance value for normalization verification is software-configurable, ranging from 0.0001 to 0.01. Sum correction of proportional values ​​uses a scaling method: each proportional value is multiplied by a correction factor to make the sum equal to 1.

[0111] Special value handling for logarithmic operations: When the scale value is 0, the logarithmic value is defined as negative infinity; in practice, the preset minimum value is used instead. The entropy calculation result is limited to a range from 0 to the maximum entropy value; saturation is applied if it exceeds the range. The synchronization signal at the time of fault determination is timestamped, and the timestamp counter is driven by a 100 MHz clock. Data updates in the circular storage buffer use a ping-pong operation: the current write buffer is physically separated from the historical read buffer.

[0112] The frequency bands of wavelet packet decomposition are indexed in ascending order by frequency, with index 0 being the lowest frequency band. The squaring operation in the multiply-accumulate operation uses a multiplier reuse strategy, completing one squaring calculation per clock cycle. Input and output range checks are performed for floating-point division operations. Intermediate variables in the Shannon entropy calculation process are stored in double precision, and the final result is converted to single precision for output.

[0113] The product of the proportional value and the logarithmic value is calculated using a hardware multiplier with a bit width of 24 bits x 24 bits. The entropy accumulator is initialized to 0, and the product value is accumulated after each frequency band calculation. The maximum entropy value for validity check is calculated using the floating-point logarithm unit and pre-calculated and stored when the configuration changes. The accuracy of the output entropy value is verified by inputting data with a known distribution and comparing the output value with the theoretical value to ensure that the error is within one thousandth.

[0114] The start delay of the interception operation is controlled within two sampling cycles to ensure that the fault onset is included. The filter coefficients for wavelet packet decomposition are loaded using burst transmission mode, and the coefficient memory is updated before each decomposition. The number of sampling points for energy calculation varies with the actual interception length and is dynamically determined by multiplying the preset duration by the sampling rate. The frequency band energy distribution is stored in an array structure with an array size equal to the number of subbands. The number of Shannon entropy calculation loops is equal to the total number of subbands, and loop control is implemented by a state machine.

[0115] The reference time for fault determination is synchronized with the power grid's power frequency clock and generated using phase-locked loop frequency division. Once the buffer read pointer is positioned, direct memory access is triggered, transferring the intercepted data block to the signal processing unit. The recursive wavelet packet decomposition operation utilizes a dedicated coprocessor, supporting a multi-layer decomposition pipeline. The energy calculation unit operates in parallel with the decomposition unit, initiating energy calculation immediately after each subband signal is generated. The band energy distribution calculation unit receives the energy values ​​of all subbands and initiates the total energy summation operation.

[0116] The Shannon entropy calculation unit includes a proportional value input interface, a logarithmic lookup table interface, and an accumulation output interface. The entropy output register is directly connected to the input register of the subsequent judgment step, with a transmission delay of less than 100 nanoseconds. The header information of the intercepted data block contains the fault timestamp and the actual number of sampling points for verification in subsequent steps. The intermediate coefficients of the wavelet packet decomposition are stored in a hierarchical memory, with each layer of coefficients allocated an independent storage area. The energy calculation unit includes a squaring operation pipeline, completing one sampling point processing per cycle.

[0117] The division instructions used in the band energy distribution calculation are supported by the floating-point unit's proprietary instruction set. The logarithmic base conversion in the Shannon entropy formula is implemented using a base conversion formula: the natural logarithm result is multiplied by a pre-stored constant 1.442695 (i.e., 1 / ln²). The entropy value accumulation process uses a Kaiser window accumulator to reduce the cumulative effect of roundoff errors. The output interface includes a data valid signal, which is set when the entropy calculation is complete.

[0118] The phase difference change direction is pattern-matched against a pre-set short-circuit fault signature library. The phase difference change direction is derived from the 32-bit floating-point slope value output in step S2, which is measured in radians per millisecond. The pre-set short-circuit fault signature library is stored in non-volatile memory and contains phase change pattern data for typical short-circuit faults. The pattern matching process performs the following steps: reading the sign and amplitude of the current slope value; comparing the sign and direction with the consistency of each record in the signature library; and verifying whether the amplitude is within the preset range for the corresponding fault type. The signature library is constructed by simulating 10 standard short-circuit faults (e.g., three-phase short circuit and single-phase ground fault) in the laboratory. The phase difference change slope during the first power frequency cycle of each fault is recorded. The average of 200 experiments is used as the baseline value, with a 20% fluctuation range as the matching range. The matching result is output as a Boolean flag, for example, a logic 1 is output when the sign matches and the amplitude is within the range.

[0119] The Shannon entropy value is also compared with a preset entropy threshold. The Shannon entropy value is derived from the single-precision floating-point number output in step S3 and represents the concentration of energy in the voltage's high-frequency components. The preset entropy threshold is set based on the difference in Shannon entropy values ​​between normal grid operation and fault conditions. This is determined by the following steps: During a fault-free period, the voltage waveform is continuously collected for 1000 power frequency cycles. The Shannon entropy value is calculated and statistically distributed, with the 5th percentile value used as the threshold reference. For example, a typical threshold for a medium-voltage distribution network is 2.3. This comparison is implemented using a hardware comparator: the Shannon entropy value is input to port A of the comparator, and the preset entropy threshold is input to port B. When the value at port A is less than the value at port B, the comparator outputs a high level. The entropy threshold is dynamically adjusted by re-collecting the latest operating data quarterly, and the stored value is updated by the host computer software.

[0120] When the direction of phase difference change matches the preset grid short-circuit fault characteristics and the Shannon entropy value is less than the preset entropy threshold, a grid transient event judgment signal is generated: This step is a logical AND operation, with the input being the high-level signal from the Boolean flag of the pattern match and the entropy value comparison result. The implementation method uses a dual-input AND gate circuit, which outputs a high-level pulse only when both inputs are valid at the same time. Signal generation timing control: The judgment is completed within 5 milliseconds after the fault judgment moment, and the output pulse width is fixed at 10 microseconds. The judgment signal is isolated and output through an optocoupler to ensure anti-interference capability. Electrical characteristics of the output signal: The high level is 5 V DC, and the driving current capacity is up to 20 mA.

[0121] The grid transient event determination signal is used to trigger the data caching mechanism that terminates the protocol converter: the determination signal is connected to the hardware interrupt pin of the protocol converter, triggering the following operations immediately: suspending the current data transmission process; clearing the temporary data in the buffer for data to be sent; and resetting the data frame assembly state machine to the initial state. The recovery condition of the termination mechanism: after the determination signal fails, a specific delay (for example, 100 milliseconds) is applied to automatically restart data transmission. The data buffer is cleared using a memory block zeroing instruction, which takes less than 10 microseconds to execute. The state machine reset includes loading the register initial values, which are stored in the read-only memory.

[0122] The preset power grid short-circuit fault signature library is stored as a two-dimensional array: the first dimension indexes the fault type number (e.g., 0 for a three-phase short circuit, 1 for a single-phase ground fault), and the second dimension stores the sign flag (1 for positive, -1 for negative) and the upper and lower limits of the amplitude range. Pattern matching amplitude range verification uses an interval comparator: the current slope value is connected to both the lower limit comparator (greater than or equal to) and the upper limit comparator (less than or equal to). The outputs of these two comparators are logically ANDed with the sign comparison result. The storage address of the entropy threshold is mapped to a specific memory page with write protection.

[0123] The input signal of the dual-input AND gate circuit is processed synchronously: the pattern matching result and the entropy comparison signal are aligned via a clock edge trigger with a clock frequency of 100 MHz. The optocoupler selection parameters include an insulation voltage of 4000 volts and a transmission delay of less than 1 microsecond. The protocol converter's interrupt service routine is stored in flash memory and contains three core instructions: loading the data buffer's first address into the address register; loading the buffer length into the counter; and executing a memory block clear loop. The initial values ​​for the state machine reset include the data frame header identifier, the initial checksum value, and the byte counter reset.

[0124] Signature library maintenance interface: Receives signature library update data packets from the host computer via the serial communication interface. The data packets contain four fields: fault type number, symbol flag, lower amplitude limit, and upper amplitude limit. Validity check during amplitude range updates: The lower limit must be less than the upper limit, and the upper limit must not exceed the maximum allowable rate of change of 1.5 per second. Online entropy threshold calibration function: When a calibration command is manually entered, the entropy value of the current 100 power frequency cycles is automatically collected and the 5th percentile is calculated to cover the original threshold.

[0125] The default fault type for pattern matching is configured as a three-phase short circuit, and other fault types can be selected using a DIP switch. The reference voltage for the interval comparator is generated by a digital potentiometer, which is controlled by the value stored in the signature library. The optimized design of the memory block clear loop: a single instruction using a 32-bit wide data bus clears 4 bytes of data, improving clearing efficiency. The state machine reset signal generation path: The determination signal triggers a monostable flip-flop, generating a 50 nanosecond reset pulse.

[0126] The protocol converter's data buffer address pointer hard reset mechanism: A fixed initial address value of 0000H is loaded via the address generator. The checksum register reset value is set to 0xFFFF. A synchronous reset signal is used to clear the byte counter to avoid metastability issues. Interrupt response latency safeguards: A check signal is connected to the processor's non-maskable interrupt pin, ensuring response latency is less than 500 nanoseconds. Clear operation completion confirmation signal: When the data buffer is cleared, a hardware comparator detects the all-zero state and outputs a confirmation flag.

[0127] The signature database update packet verification mechanism includes a 16-bit cyclic redundancy check (CRC) field, which must pass verification before it can be written to the memory. The digital potentiometer has a 12-bit resolution, corresponding to 4096 levels of voltage adjustment. The timing capacitor of the monostable trigger uses a ceramic capacitor with a temperature stability of 30 parts per million. The initial value of the address generator is stored in the fuse configuration memory and is automatically loaded upon power-up. The all-zero state detection uses a 1024-bit wide OR gate tree structure, outputting a valid flag when all input bits are 0.

[0128] Fault type switching priority logic: When multiple fault signatures match simultaneously, the highest priority fault type number is output (for example, a three-phase short circuit has priority 0, while a single-phase ground fault has priority 1). The entropy comparator's hysteresis design: A 3% hysteresis band is set around the threshold to prevent frequent flip-flops caused by noise. A Schmitt trigger is configured at the optocoupler output to eliminate signal edge jitter. Direct memory access requests are suspended during data buffer clearing to prevent data conflicts. After the state machine is reset, data transmission must wait two clock cycles before resuming.

[0129] Failure detection of the determination signal is monitored via a pulse width counter. If the high-level duration exceeds 1 millisecond, the output is forced low. The protocol converter's restart delay is controlled by a programmable timer. The timer base clock is 10 kHz, and the prescaler factor is set to 1000, corresponding to a 100 millisecond timer. The opcode for the memory zero instruction is hardwired into a specific encoding in the processor's instruction decoder. The entry point of the interrupt service routine is fixed at the interrupt vector table location 0xFFF0.

[0130] Confidence output for feature library matching results: When the current slope value deviates from the reference value by less than 10%, a confidence flag is output. Entropy threshold comparison results include a margin indicator: If the Shannon entropy value falls below the threshold by more than 10%, a strong judgment flag is output. AND gate circuit fail-safe design: Automatically locks the output low if any input signal is abnormal. Real-time monitoring of data buffer clearing progress: A progress status code is generated every time 25% of the data area is cleared. Self-test process after state machine reset: Each register's initial value is verified sequentially and the verification results are output.

[0131] Receiving the grid transient event determination signal: This signal is a 5V DC high-level pulse signal from step S4, with a fixed pulse width of 10 microseconds. A Schmitt trigger is configured at the signal receiving end for edge shaping to eliminate oscillation interference during transmission. The shaped signal is connected to the protocol converter's non-maskable interrupt pin, with the interrupt priority set to the highest level. The interrupt trigger condition is rising edge detection, and the response delay has been measured to be less than 200 nanoseconds. Signal level validity verification: When the input voltage exceeds 3.5V, it is determined to be a valid high level; when it is below 1.5V, it is determined to be an invalid low level.

[0132] Stop writing newly collected device status information to the data buffer of the protocol converter: immediately execute the write enable flag reset operation in the interrupt service program. The specific implementation is: set the output enable register of the data acquisition module to zero. This register bit controls the data flow to the write gating circuit of the cache. Timing control of stopping the write operation: freeze the write pointer after the end of the current data transmission cycle, and the freezing action is completed within 2 clock cycles. The device status information includes the effective value of the voltage, effective value of the current, and active power value of the grid connection point. Each type of data is updated at a fixed period. For example, the effective value of the voltage is updated 100 times per second. Data disposal after writing stops: the newly collected data is temporarily stored in a first-in-first-out queue with a queue depth of 10 groups of data. The earliest data is automatically discarded when it overflows.

[0133] Clear the unsent data in the data buffer of the protocol converter: The data buffer is implemented using a dual-port static memory with a capacity of 1 megabyte. The clear operation executes a block erase instruction through the direct memory access controller. The starting address is the cache base address 0000H, and the end address is the current write pointer position minus one. The erase mode is full zero fill, and the value 0x00 is written to each storage unit. Clear progress monitoring mechanism: The status register is updated every 256 bytes erased, and the lower 8 bits of the status register indicate the completion percentage. Clear completion flag generation: When the end address is equal to the current erase address, a completion interrupt is triggered. Exception handling: If the erase time exceeds the preset value of 50 microseconds, the backup erase circuit is started to force the chip select signals of all storage units to be pulled low.

[0134] A real-time streaming transmission channel, independent of the caching mechanism, is established at the protocol converter's communication link layer. The communication link layer is based on an Ethernet physical layer chip, and the real-time streaming channel is isolated via virtual local area network (VLAN) identifiers. Channel establishment steps: 1) Configure the network protocol stack's priority flag and set the service type field to the highest priority; 2) Assign an independent media access control address suffix, such as appending 0xFF to the base address; 3) Preset a dedicated routing table entry in the switching chip to direct packets destined for the power grid dispatching system to the physical layer's send queue. Channel bandwidth guarantee mechanism: 30% of the total bandwidth is reserved, and traffic shaping is implemented using a token bucket algorithm. Channel heartbeat detection: A 1-byte heartbeat packet is sent every millisecond. If no response is received after a 3-millisecond timeout, the channel is reestablished.

[0135] The real-time streaming transmission channel is used to transmit emergency control instructions issued by the power grid dispatching system: the instruction transmission format adopts a simplified frame structure, the frame header is fixed with the 0xAA55 identifier, and the payload part contains the instruction code (1 byte) and the parameter value (4 bytes). The transmission process omits the transmission control protocol handshake link and adopts the user datagram protocol broadcast mode. Instruction reception verification: a hardware filtering circuit is set at the receiving end of the protocol converter to only allow data packets whose source media access control address is the dispatching system registration address to pass. Instruction execution delay constraint: the delay from receiving the instruction to output to the actuator shall not exceed 500 microseconds. Instruction security verification: a 2-byte cyclic redundancy check code is attached to each frame of the instruction, and the frame is discarded if the verification fails.

[0136] The reset operation of the data cache write enable register includes state synchronization: the reset signal is synchronized to the clock domain of the data acquisition module to avoid metastability. The overflow discard strategy of the first-in-first-out queue adopts a ring buffer design, and the write pointer automatically overwrites the oldest data. The address generation of the block erase instruction uses a linear up-counter with a counter step frequency of 200 MHz. The configuration range of the virtual local area network identifier is set to 4096 to 4100 and is dynamically written through the management information base variable. The parameters of the token bucket algorithm are configured: the bucket depth is set to 10 frames of data, and the token generation rate is fixed at 1000 frames per second.

[0137] Storage and mapping of the emergency control instruction code table: Instruction code 0x01 represents circuit breaker tripping, and 0x02 represents capacitor bank input. A total of 16 instructions are defined. Parameter value parsing rules: The first 2 bytes are the device address code, and the last 2 bytes are the action parameters (such as tripping time). The media access control address whitelist of the hardware filtering circuit is stored in the content-addressable memory, which has a capacity that supports 8 address registrations. The user datagram protocol port number is fixed to 9999, and the destination Internet Protocol address is preset to the primary and backup addresses of the dispatching system. The cyclic redundancy check code generator polynomial adopts the CRC-16-CCITT standard, with an initial value of 0xFFFF.

[0138] Position locking mechanism during write pointer freeze: The current write pointer value is captured via a latch, and the latch enable signal is synchronized with the interrupt signal. Read / write pointer difference calculation for a first-in, first-out queue: The overflow flag is triggered when the write pointer minus the read pointer exceeds the queue depth. Power supply guarantee for block erase operations: During the erase process, a backup supercapacitor is activated to maintain power supply for at least 100 milliseconds. VLAN tag insertion location: Located 4 bytes after the source media access control address in the Ethernet frame, the tag format complies with the IEEE 802.1Q standard. Token bucket status update: Each received frame consumes one token, and the token count increases by one every millisecond.

[0139] Method for measuring instruction execution delay: Start a high-precision timer when the instruction frame header arrives and stop timing after the actuator responds. Hardware acceleration of cyclic redundancy check code calculation: Use a 16-bit linear feedback shift register to process 1 byte of data per clock cycle. State recovery process after the data buffer is cleared: Set the write enable register, unfreeze the write pointer, and reset the read and write pointers of the first-in-first-out queue. Abnormal reconstruction process of the real-time streaming channel: Release the current virtual LAN configuration, re-apply for the media access control address, and reload the routing table entry. Priority override mechanism for emergency control instructions: Once the channel is established, regular telemetry data transmission is automatically suspended until the instruction transmission is completed.

[0140] Clock synchronization guarantee for the protocol converter: Utilizing the IEEE 1588 precision time protocol, the time deviation from the scheduling system is less than 1 microsecond. Send queue management for the physical layer chip: Dual-priority queues are set up, and real-time streaming channel data packets are always inserted at the head of the high-priority queue. Instruction execution feedback mechanism: After the actuator responds, a 4-byte status code is generated and transmitted back in real time through the original channel. Interrupt nesting processing for flush operations: If a new judgment signal is received during the flush process, the current flush is terminated and the entire process is immediately restarted. Channel heartbeat response mechanism: After receiving the heartbeat packet, the scheduling system returns a response packet containing a timestamp for transmission delay compensation.

[0141] The data cache base address is fixed by hardware: locked by the address decoder's fuse configuration and cannot be modified by software. The media access control address suffix is ​​generated by performing a logical OR operation on the base address and 0x0000FFFF. Switch chip routing table entries are pre-set during protocol converter initialization via the serial peripheral interface. Actuator interface electrical isolation utilizes magnetic isolation technology with a dielectric strength of 5000 volts AC. Cyclic redundancy check error count: Three consecutive check failures trigger the channel self-test routine. Real-time streaming channel bandwidth monitoring: Actual bandwidth usage is calculated every second, and a warning event is generated when the reserved bandwidth exceeds 80%.

[0142] Receive the original data stream of emergency control instructions issued by the power grid dispatching system through the real-time streaming transmission channel: the real-time streaming transmission channel is based on the dedicated link with the virtual local area network identifier 4096 to 4100 established in step S5. Data reception adopts the direct memory access mode of the physical layer chip. When it is detected that the target media access control address matches the registered whitelist and the virtual local area network tag value is within the preset range, a direct memory access request is triggered. The receiving buffer is configured as a ping-pong double buffer structure, and the capacity of each buffer is 1526 bytes (the maximum size of a standard Ethernet frame). Receiving timing control: During the complete frame transmission process from the detection of the frame start delimiter to the end of the frame check sequence, the hardware automatically masks interrupt requests. Data flow verification mechanism: Check that the frame length is within the valid range of 64 bytes to 1526 bytes. If it exceeds the limit, the frame is discarded and an error log is generated.

[0143] The protocol encapsulation format of the original emergency control command data stream remains unchanged: Format preservation involves processing at the following three levels: 1) The physical layer maintains the original Manchester-encoded waveform, regenerating the original timing through clock and data recovery circuitry; 2) The data link layer maintains the original frame structure, including the complete bit sequence of the preamble, start of frame delimiter, destination media access control address, source media access control address, virtual local area network tag, and Ethernet type field; 3) The payload content at the network layer and above is prohibited from being modified. This implementation utilizes hardware-level signal relaying: the serial output of the receiving physical layer chip directly drives the differential input of the transmitting physical layer chip, passing only through two signal shaping amplifiers. The shaping amplifier gain is set to unity gain, and the bandwidth is limited to 100 MHz to suppress high-frequency noise.

[0144] The raw data stream of emergency control commands is transparently transmitted to the communication interface of the PV inverter. The transparent transmission path is a dedicated physical channel, with the protocol converter's media-independent interface directly connected to the PV inverter's media-independent interface. Interface electrical characteristics are matched: The transmitter differential voltage level is adjusted to the 1.8 volt peak-to-peak voltage required by the PV inverter, and the common-mode voltage offset is compensated to 1.25 volts. The connector uses an industrial-grade RJ45 socket with a contact resistance of less than 20 milliohms. Transparent transmission start condition: When a valid frame start delimiter is detected, the transmit driver is automatically enabled. Transmission delay compensation mechanism: The inherent channel delay is measured and a compensation value (e.g., 200 nanoseconds) is pre-stored. An equal-length prefix extension is inserted during frame transmission.

[0145] Protocol parsing and data caching are not performed during transparent transmission. This prohibition of protocol parsing is reflected in: 1) the media access control controller is prohibited from accessing the receive frame buffer; 2) the network protocol stack processing thread is prohibited from running; and 3) the transmission control protocol / internet protocol demultiplexer enable signal is disabled. Data caching is prohibited through the following design: a point-to-point direct data bus connects the receive buffer to the transmit buffer, with a bus width of 4 bits (corresponding to a 100 Mbps rate), and bus control is exclusively controlled by the physical layer chip. A hardware watchdog monitoring mechanism: If a buffer enable signal transition is detected during transmission, the transmission channel is immediately reset.

[0146] Ping-Pong buffer switching logic: Buffer A's receive completion flag triggers three actions: 1) switching buffer B to the receive state; 2) starting data transmission from buffer A to the transmitter; and 3) setting buffer A's status flag to "sending." Transmission completion determination: Buffer A is released when the transmitter's physical layer chip returns an end-of-frame signal. The Manchester-encoded clock regeneration circuit uses a phase-locked loop (PLL) structure with a damping coefficient set to 0.707 and a bandwidth set to 10% of the data rate. Temperature compensation for the signal shaping amplifier: Dynamically adjusts the bias voltage based on ambient temperature sensor data, with a compensation coefficient of -0.2 millivolts per degree Celsius.

[0147] The differential level adjustment circuit utilizes a digitally controlled variable gain amplifier, with the gain control word stored in electrically erasable programmable read-only memory. The common-mode voltage compensation circuit generates a reference voltage based on a digital-to-analog converter with 12-bit accuracy. The industrial-grade RJ45 jack features a gold plating thickness greater than 50 microinches, and a guaranteed plug-in / plug-out lifespan of 1000 cycles. The transmission delay compensation value is measured by sending a short test frame and measuring the time difference between transmit enable and receive interrupt. This is repeated 100 times and the average value is taken.

[0148] The arbitration mechanism for the point-to-point direct data bus is implemented through hardware signal interlocking. The receiving physical layer chip outputs a request-to-send signal, and the transmitting physical layer chip returns a clear-to-send signal. Bus transmission protocol: 4 bits of data are transmitted per clock cycle, accompanied by data valid and byte enable signals. The watchdog monitoring period is 50 nanoseconds, with a timeout threshold of 1 microsecond. Error log storage format: Contains a timestamp (32 bits), frame length (16 bits), and error code (8 bits), stored in a circular buffer.

[0149] Parallel processing for frame validity checking: The length checker, media access control address matcher, and virtual local area network (VLAN) verifier operate simultaneously. The length checker uses a 16-bit comparator with a lower limit of 64 and an upper limit of 1526. The media access control address matcher is a content-addressable memory (CAM) that stores eight 64-bit address templates. The VLAN verifier uses a 4-bit range comparator with a lower limit of 4096 and an upper limit of 4100. The phase error detector in the clock and data recovery circuit uses a Hogge structure and a sampling clock frequency of 200 MHz.

[0150] Data transmission path bit error rate monitoring: Test patterns are inserted between frame transmissions, and the receiving end performs bit error statistics. A channel performance alarm is triggered when the bit error rate exceeds 10 to the power of -9 per second. Transparent channel electrical isolation: This is achieved using a pulse transformer with a primary and secondary insulation withstand voltage of 4000 volts AC. Transmission path length matching: The trace length difference between the receiving end and the transmitting end is controlled within 0.1 mm, and the delay difference is less than 1 picosecond. Impedance continuity is guaranteed: The characteristic impedance of the printed circuit board trace is maintained at 50 ohms, with a deviation of no more than ±5%.

[0151] Transmitter status indicator: Green LED illuminates during transmission, blue LED illuminates during reception, and red LED flashes during errors. Channel self-test: Automatically transmits a 512-byte pseudo-random code upon power-up, and the receiving end performs cyclic redundancy check verification. Maintenance interface: Access the error statistics register via the Joint Test Action Group interface. Hot-swap protection: The interface circuit integrates transient voltage suppression diodes with a response time of less than 1 nanosecond. Electrostatic discharge protection meets the 8 kV contact discharge standard.

[0152] Data bus interlock signal timeout handling: When the request-to-send signal remains valid for more than 5 microseconds, the transmit physical layer chip is forced to reset. The watchdog reset action includes disabling the transmit driver for 500 nanoseconds and clearing all status registers. The shield of the industrial-grade RJ45 jack is grounded at a single point via a 1 megohm resistor to suppress common-mode interference. A cyclic redundancy check calculation unit is located in parallel with the transparent transmission channel for self-testing without affecting the data transmission path.

[0153] Real-time monitoring indicators of transparent transmission performance: Statistics of the number of successfully transmitted frames per second, maximum frame delay, and minimum frame interval. Performance data is output to the maintenance terminal through an independent serial port. Channel fault switching strategy: When three consecutive frames fail to transmit, it automatically switches to the backup physical port (port number + 1). The initialization time of the backup port is controlled within 100 microseconds. All configuration parameters are stored in triple-module redundant storage units, with a single-particle upset tolerance of 10 to the power of -13. The operating temperature range of the transparent transmission channel is -40 degrees Celsius to 85 degrees Celsius. Temperature adaptation is achieved by adjusting the bias current in real time through on-chip sensors.

[0154] Monitors the absolute value of the instantaneous rate of change of the grid connection point voltage: This value is derived from the absolute value of the voltage difference between adjacent sampling points calculated in step S1 divided by the sampling interval, which is fixed at 100 microseconds (corresponding to a 10 kHz sampling rate). The monitoring process utilizes a sliding window mechanism with a window length of 10 sampling points, updating the rate of change value for each new sampling point. The hardware implementation consists of two parallel calculation units: Unit A calculates the absolute value of the difference between the current sampling point voltage and the previous one; Unit B divides the absolute value of this difference by the sampling interval of 100 microseconds. The output is expressed as the absolute value of the instantaneous rate of change per second. The output value is stored in a 32-bit floating-point register, with the update cycle strictly synchronized with the rising edge of the sampling clock. Data validity check: When the voltage value exceeds the rated voltage range by ±20%, the output is frozen and the invalid status bit is marked.

[0155] When the absolute value of the instantaneous rate of change continuously falls below a preset threshold for a preset duration, a cache restore instruction is generated. The preset threshold is set to 0.01 per second, determined by statistically analyzing the 95th percentile of the rate of change distribution during steady-state grid operation. The default preset duration is 1000 milliseconds and can be configured between 100 and 5000 milliseconds. The continuous determination logic is implemented by designing a 16-bit down-counter with an initial value equal to the preset duration / sampling interval (e.g., 1000 milliseconds / 100 microseconds = 10000). When the absolute value of the instantaneous rate of change falls below the preset threshold, the counter decrements by 1 during each sampling period. When the absolute value of the instantaneous rate of change rises above the threshold, the counter immediately resets to its initial value. When the counter reaches 0, a cache restore instruction is triggered, which is a high-level pulse with a width of 50 microseconds. Counter overflow protection: If the initial value exceeds 65535, the counter automatically switches to frequency division counting mode.

[0156] The protocol converter's data buffer write function is re-enabled using the cache restore instruction: This instruction accesses bit 0 (the write enable bit) of the protocol converter's control register. The specific operation process is as follows: 1) On the rising edge of the instruction, the data acquisition module's output enable register is unfrozen (the register value is set to 1); 2) The write pointer movement function is restored, and the write pointer increments from the frozen position; 3) The transmission channel from the first-in-first-out queue to the data buffer is activated. Timing control is enabled: The operation is executed with a delay of two sampling cycles after the rising edge of the instruction to avoid the synchronization cycle of the data acquisition module. Data redirection mechanism: Data temporarily stored in the first-in-first-out queue is transferred to the data buffer on a first-in-first-out basis, with the transfer rate consistent with the acquisition rate. Confirmation mechanism is enabled: When the write pointer is successfully moved, the operation completion status code 0x55 is returned.

[0157] The data cache mechanism of the protocol converter is restored to normal caching operation for device status information: Normal caching operation includes three parallel processes: 1) The three types of data, voltage RMS, current RMS, and active power, are written to the specified address segment of the cache at a fixed period (for example, the voltage value is updated every 10 milliseconds); 2) The write pointer automatically loops over, jumping to the base address 0x00000 when it reaches the end address 0xFFFFF of the cache; 3) The real-time calculation of the data checksum is reactivated, and the checksum is updated once every 256 bytes written. Cache recovery flag setting: Bit 7 in the cache management status register is set. This flag is queried by the subsequent data transmission module. Recovery completion verification: The write pointer movement status is continuously monitored for 10 sampling cycles. If it increases normally, a recovery success signal is output.

[0158] Dynamic adjustment strategy for preset thresholds: Automatically collect change rate data every 24 hours, recalculate the 95th percentile and update the threshold storage value. Temperature compensation for preset duration: Adjust the duration value according to the ambient temperature sensor reading, and reduce the duration by 5% for every 10 degrees Celsius increase in temperature. Initial value calculation unit of the down counter: Contains a 32-bit divider, the dividend is the preset duration in milliseconds multiplied by 1000 (converted to microseconds), the divisor is the sampling interval time of 100 microseconds, and the quotient is truncated and rounded. Transfer control of the first-in, first-out queue: Set a dedicated direct memory access channel, the channel burst transmission length is fixed at 16 bytes, and the bus occupancy priority is the highest.

[0159] Data buffer address management: The write pointer uses a 32-bit cyclic counter. The actual buffer size is 1 megabyte, with an address range of 0x00000 to 0xFFFFF. The checksum calculation algorithm uses a 32-bit cyclic redundancy check with the polynomial 0x04C11DB7. The electrical characteristics of the recovery success signal are: 3.3V high level, 10mA drive capability, and a duration of 100ms. The invalid status bit is automatically cleared when the voltage value returns to within ±10% of the rated range for 1ms. Sampling clock synchronization is guaranteed: A phase-locked loop is used to track the power grid frequency, with a synchronization error of less than 0.1 degrees.

[0160] Interlock logic of cache recovery instructions: When the real-time streaming transmission channel is in the activated state (step S6), the cache recovery instruction is automatically blocked. Emergency clearing mechanism of the first-in-first-out queue: If the queue storage data exceeds the preset length of 100 milliseconds without being processed, forced clearing is initiated. Boundary processing of write pointer loop jump: After writing to address 0xFFFFF, the next address is automatically reset to 0x00000 and the address wrap flag is set. Checksum update timing: The calculation is triggered when the write pointer moves to an integer multiple of 256 bytes. The temperature compensation coefficient is stored in the electrically erasable programmable read-only memory, and each byte corresponds to a compensation value of 1 degree Celsius.

[0161] Data filtering for dynamic threshold updates: Only data with grid load rate changes between 40% and 60% are selected for statistical analysis. Frequency division coefficient calculation for frequency division counting mode: The quotient of the initial value divided by 65535 is used as the pre-division value, and the remainder is used as the final count value. Control register bit 0 is set using a write-1 instruction, which requires two consecutive 0xA5 confirmation codes to prevent misoperation. Data redirection rate matching: The transmission channel clock frequency is co-sourced with the data acquisition clock, with a phase difference of less than 90 degrees. Automatic clearing of the address wrap flag: The flag is cleared immediately upon the next write pointer movement.

[0162] Abnormal monitoring during the recovery process: When five consecutive write operations fail, a write error interrupt is triggered and the system reverts to the frozen state. Invalid status flag propagation path: While the status register is set, a pause command is sent to the data acquisition module. Real-time stream channel status detection: This is determined by querying the media access control controller's send queue occupancy flag. Forced clear operation execution time: Clearing the queue of 10 groups of data takes no more than 20 microseconds. Dynamic threshold update effectiveness delay: The new threshold is automatically enabled at 0:00 the next day to avoid switching during operation.

[0163] Buffer Management Status Register Bit Definitions: Bit 0: Write Enable, Bit 1: Read Enable, Bit 7: Cache Recovery Flag. Write Error Interrupt Service Routine: Records the incorrect address and data type, attempts to write repeatedly three times, and then aborts. Sampling Clock Synchronization Fault Detection: Switches to the local crystal oscillator when out of sync for 100 consecutive cycles. Temperature Reading Cycle: Reads the temperature sensor value via the serial bus every 10 seconds. Compensation Value Lookup Method: Divides the temperature value by 10, rounded to the nearest integer, and uses it as the index address to read the corresponding compensation coefficient. Data Acquisition Pause Command Response Time: Takes effect at the start of the next acquisition cycle, with a delay of less than 100 microseconds.

[0164] Feedback path for the recovery success signal: connected to the driver circuit of the status indicator light and uploaded to the power grid dispatching system at the same time. Hardware acceleration of cyclic redundancy check calculation: uses a 32-bit linear feedback shift register to process 1 byte of data per clock cycle. Purpose of the address wrap flag: adds a special field to the data transmission protocol to identify the data block boundary. Write operation failure judgment standard: the write response signal times out for 1 microsecond and is not returned. Data storage area for dynamic threshold update: allocates an independent storage page, which is physically isolated from the operating threshold. Frequency division coefficient register width: 16 bits for pre-division value and 16 bits for final count value. Control register write protection: locks write operation permissions during the activation of the real-time streaming channel.

[0165] The calculations involved in the embodiments are all dimensionless numerical calculations, and the preset parameters and thresholds in the calculations are set by those skilled in the art according to actual conditions.

[0166] The above embodiments may be implemented in whole or in part through software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product.

[0167] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application of the technical solution and the invention constraints. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0168] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0169] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0170] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0171] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A data interaction adaptive method for a photovoltaic protocol converter, characterized in that: The steps include: S1. Real-time monitoring of the grid connection point voltage, calculation of the instantaneous rate of change of the grid connection point voltage and comparison with the preset threshold in real time; S2. When the instantaneous rate of change exceeds a preset threshold, synchronously collect the current phase of the grid connection point and generate the phase difference change direction between the grid connection point voltage and the grid connection point current phase; S3. Extract the high-frequency component of the grid connection point voltage, analyze the frequency band energy distribution of the high-frequency component through wavelet packet decomposition, and obtain the Shannon entropy value that represents the energy concentration; S4. When the phase difference change direction meets the preset grid short-circuit fault characteristics and the Shannon entropy value is lower than the preset entropy threshold, it is determined that the current event is a grid transient event; S5. When the current event is a transient power grid event, the data buffering mechanism of the protocol converter is immediately stopped, and the real-time streaming transmission channel is activated; S6. Forwarding the emergency control command issued by the grid dispatching system directly to the photovoltaic inverter through the real-time streaming transmission channel; S7. When the instantaneous change rate continues to be lower than the preset threshold for a preset time period, the data cache mechanism of the protocol converter is restored.

2. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: Real-time monitoring of the grid connection point voltage, calculation of the instantaneous rate of change of the grid connection point voltage and comparison with the preset threshold in real time, including: Continuously collect the instantaneous value of the grid connection point voltage; Calculate the instantaneous rate of change based on the difference between adjacent sampling points of the instantaneous value of the grid connection point voltage; Compare the instantaneous rate of change with the preset threshold in real time; When the absolute value of the instantaneous rate of change is continuously greater than a preset threshold value for more than a preset time, a flag signal for triggering synchronous acquisition of the grid connection point current phase is generated.

3. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: When the instantaneous rate of change exceeds a preset threshold, the current phase of the grid connection point is synchronously collected to generate the phase difference change direction between the grid connection point voltage and the grid connection point current phase, including: Based on the flag signal, the voltage phase sequence and the current phase sequence at the grid connection point are synchronously obtained within the first power frequency cycle after the fault occurs. Calculate the instantaneous phase difference between the grid connection point voltage phase and the grid connection point current phase at each sampling moment; Perform trend fitting on the instantaneous phase difference values ​​at multiple consecutive sampling moments; The slope value of the trend fitting result is used as the direction of phase difference change.

4. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: The high-frequency component of the grid connection point voltage is extracted, and the frequency band energy distribution of the high-frequency component is analyzed through wavelet packet decomposition to obtain the Shannon entropy value that represents the energy concentration, including: Intercepting the grid connection point voltage waveform within a preset time period after the fault determination moment as the signal to be analyzed; Perform wavelet packet decomposition on the signal to be analyzed to obtain multiple sub-band signals; Calculate the energy value of each sub-band signal; calculating frequency band energy distribution based on the energy values; The frequency band energy distribution is input into the Shannon entropy formula, and the Shannon entropy value representing the energy concentration is output.

5. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: When the phase difference change direction meets the preset grid short-circuit fault characteristics and the Shannon entropy value is lower than the preset entropy threshold, it is determined to be a grid transient event, including: Perform pattern matching on the phase difference change direction and the preset power grid short circuit fault feature library; At the same time, the Shannon entropy value is compared with the preset entropy threshold; When the phase difference change direction matches the preset power grid short circuit fault characteristics and the Shannon entropy value is less than the preset entropy threshold, a power grid transient event determination signal is generated.

6. The data interaction adaptive method of a photovoltaic protocol converter according to claim 5, characterized in that: The power grid transient event determination signal is used to trigger the termination of the data buffering mechanism of the protocol converter.

7. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: When a transient power grid event occurs, the protocol converter's data buffering mechanism is immediately suspended and the real-time streaming channel is activated, including: receiving a power grid transient event determination signal; Stop writing newly acquired device status information to the data buffer of the protocol converter; Clear the unsent data in the data buffer of the protocol converter; A real-time streaming transmission channel independent of a buffer mechanism is established at the communication link layer of the protocol converter.

8. The data interaction adaptive method of a photovoltaic protocol converter according to claim 7, characterized in that: The real-time streaming transmission channel is used to transmit emergency control instructions issued by the power grid dispatching system.

9. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: Directly forward emergency control commands issued by the grid dispatching system to the photovoltaic inverter via a real-time streaming channel, including: Receive the original data stream of emergency control instructions issued by the power grid dispatching system through the real-time streaming channel; Keep the protocol encapsulation format of the original data stream of the emergency control command unchanged; Transmit the original data stream of emergency control instructions to the communication interface of the photovoltaic inverter; No protocol parsing or data caching is performed during transparent transmission.

10. The data interaction adaptive method of a photovoltaic protocol converter according to claim 1, characterized in that: When the instantaneous rate of change remains below a preset threshold for a preset period of time, the data buffering mechanism of the protocol converter is restored, including: Monitor the absolute value of the instantaneous rate of change of the voltage at the grid connection point; When the absolute value of the instantaneous change rate is continuously lower than the preset threshold for a preset period of time, a cache recovery instruction is generated; Re-enable the data buffer write function of the protocol converter according to the buffer recovery instruction; Restore the normal caching operation of the data cache mechanism of the protocol converter for device status information.

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