TFET device and forming method thereof
By using a heterogeneous gate dielectric layer in the TFET device, the tunneling capability is enhanced and the bipolar effect is weakened, which solves the problems of low on-state current and large leakage current of the TFET device and achieves performance improvement.
Patent Information
- Application Number
- CN202410273837.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-11
- Publication Date
- 2025-09-12
AI Technical Summary
The on-state current of TFET devices is low and there is a bipolar effect, which limits their further development. Existing technologies make it difficult to effectively increase the on-state current and reduce the leakage current.
A heterogeneous gate dielectric layer is used, a high-k dielectric layer is used near the source to enhance the tunneling capability, and a high-k dielectric layer plus an oxide layer is used at the drain to weaken the bipolar effect, forming an asymmetric gate structure.
The on-state current of the TFET device is increased and the leakage current is reduced, weakening the bipolar effect, thereby improving the overall performance of the device.
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Figure CN120640706A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a TFET device and a method for forming the same. Background Art
[0002] For a long time, in pursuit of higher chip integration density and faster device operating speeds, the characteristic dimensions of MOSFETs have been continuously reduced to nanometer sizes. However, this continuous reduction in size has also led to defects such as short channel effects, which has led to deterioration in MOSFET performance. To meet the goals of continuously improving integrated circuit miniaturization, power consumption, and performance, a device that can replace MOSFETs is sought. Therefore, the unique current injection mechanism of tunneling field effect transistors (TFETs) makes them the most promising device for application in new integrated circuit designs.
[0003] However, TFETs have a low on-state current, and the bipolar effect severely limits their further development. TFETs are compatible with traditional CMOS processes, and their source and drain are completely symmetrical, so the device gate conducts even when a reverse voltage is applied. This is known as the bipolar effect. Therefore, increasing Ion (on-state current) inevitably increases Ioff (off-state current).
[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to increase the on-state current of TFET devices and reduce leakage current, weaken the bipolar effect of TFET, and thus improve device performance. Summary of the Invention
[0005] The present application provides a TFET device and a method for forming the same, which can increase the on-state current of the TFET device and reduce the leakage current, weaken the bipolar effect of the TFET, and thus improve the device performance.
[0006] One aspect of the present application provides a method for forming a TFET device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region; forming an oxide layer on a surface of the semiconductor substrate in the second region; sequentially forming an auxiliary layer and a high-k dielectric layer on the surfaces of the semiconductor substrate and the oxide layer; forming a barrier layer on the surface of the high-k dielectric layer; forming a gate layer on the surface of the barrier layer; etching the gate layer, barrier layer, high-k dielectric layer, auxiliary layer, and oxide layer to the surface of the semiconductor substrate to form a gate structure, the gate structure spanning the first region and the second region; and forming a source and a drain in the semiconductor substrate on both sides of the gate structure, respectively, wherein the source is located in the first region and the drain is located in the second region.
[0007] In some embodiments of the present application, the thickness of the oxide layer is 1.5 to 2.5 nanometers.
[0008] In some embodiments of the present application, the surface of the auxiliary layer in the second region is higher than the surface of the auxiliary layer in the first region; the surface of the high-k dielectric layer in the second region is higher than the surface of the high-k dielectric layer in the first region; and the surface of the barrier layer in the second region is higher than the surface of the barrier layer in the first region.
[0009] In some embodiments of the present application, the auxiliary layer thickness of the second region is the same as that of the first region; the high-k dielectric layer of the second region is the same as that of the first region; and the barrier layer surface of the second region is the same as that of the first region.
[0010] In some embodiments of the present application, surfaces of the gate layer in the second region are flush with surfaces of the gate layer in the first region.
[0011] Another aspect of the present application also provides a TFET device, comprising: a semiconductor substrate, the semiconductor substrate including a first region and a second region; a gate structure, located on the surface of the semiconductor substrate and spanning the first region and the second region, wherein the portion of the gate structure located in the first region includes an auxiliary layer, a high-k dielectric layer, a barrier layer and a gate layer located in sequence on the surface of the semiconductor substrate, and the portion of the gate structure located in the second region includes an oxide layer, an auxiliary layer, a high-k dielectric layer, a barrier layer and a gate layer located in sequence on the surface of the semiconductor substrate; a source and a drain, respectively located in the semiconductor substrate on both sides of the gate structure, wherein the source is located in the first region and the drain is located in the second region.
[0012] In some embodiments of the present application, the thickness of the oxide layer is 1.5 to 2.5 nanometers.
[0013] In some embodiments of the present application, the surface of the auxiliary layer in the second region is higher than the surface of the auxiliary layer in the first region; the surface of the high-k dielectric layer in the second region is higher than the surface of the high-k dielectric layer in the first region; and the surface of the barrier layer in the second region is higher than the surface of the barrier layer in the first region.
[0014] In some embodiments of the present application, the auxiliary layer thickness of the second region is the same as that of the first region; the high-k dielectric layer of the second region is the same as that of the first region; and the barrier layer surface of the second region is the same as that of the first region.
[0015] In some embodiments of the present application, surfaces of the gate layer in the second region are flush with surfaces of the gate layer in the first region.
[0016] The present application provides a TFET device and a method for forming the same, which can increase the on-state current of the TFET device and reduce the leakage current, weaken the bipolar effect of the TFET, and thus improve the device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0018] in:
[0019] Figures 1 to 7 Schematic diagram of the structure of each step in the method for forming a TFET device described in an embodiment of the present application. DETAILED DESCRIPTION
[0020] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.
[0021] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.
[0022] Figures 1 to 7 The following is a structural diagram of each step in the method for forming a TFET device according to an embodiment of the present application. The method for forming a TFET device according to an embodiment of the present application is described in detail with reference to the accompanying drawings.
[0023] refer to Figure 1 As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a first region 101 and a second region 102 .
[0024] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.
[0025] In some embodiments of the present application, the semiconductor substrate 100 also has structures such as a well region that are common in TFET devices, which are omitted here for the sake of brevity.
[0026] refer to Figure 2 As shown, an oxide layer 110 is formed on the surface of the semiconductor substrate 100 in the second region 102 .
[0027] In some embodiments of the present application, the material of the oxide layer 110 includes silicon oxide.
[0028] In some embodiments of the present application, the thickness of the oxide layer 110 is 1.5 to 2.5 nanometers, for example, 2 nanometers.
[0029] In some embodiments of the present application, the method of forming an oxide layer 110 on the surface of the semiconductor substrate 100 in the second region 102 includes: forming an oxide layer 110 on the surface of the semiconductor substrate 100; etching and removing the oxide layer 110 in the first region 101, and retaining the oxide layer 110 in the second region 102.
[0030] In other embodiments of the present application, the method for forming an oxide layer 110 on the surface of the semiconductor substrate 100 in the second region 102 includes: forming a mask layer on the surface of the semiconductor substrate 100 to expose the second region 102; forming an oxide layer 110 on the surface of the semiconductor substrate 100 in the second region 102 exposed by the mask layer 102 using a thermal oxidation process; and removing the mask layer.
[0031] refer to Figure 3 As shown, an auxiliary layer 120 and a high-k dielectric layer 130 are sequentially formed on the surfaces of the semiconductor substrate 100 and the oxide layer 110 .
[0032] In some embodiments of the present application, the surface of the auxiliary layer 120 in the second region 102 is higher than the surface of the auxiliary layer 120 in the first region 101 ; the surface of the high-k dielectric layer 130 in the second region 102 is higher than the surface of the high-k dielectric layer 130 in the first region 101 .
[0033] In some embodiments of the present application, the auxiliary layer 120 of the second region 102 and the first region 101 have the same thickness; the high-k dielectric layer 130 of the second region 102 and the high-k dielectric layer 130 of the first region 101 have the same thickness.
[0034] In some embodiments of the present application, the auxiliary layer 120 is made of silicon oxynitride. The thickness of the auxiliary layer 120 is 0.5 to 1.5 nanometers, for example, 1 nanometer. The auxiliary layer 120 is used to improve the interface state between the high-k dielectric layer 130 and the semiconductor substrate 100.
[0035] In some embodiments of the present application, the material of the high-k dielectric layer 130 includes a high dielectric constant material such as hafnium oxide. The thickness of the high-k dielectric layer 130 is 1 to 2 nanometers, for example, 1.5 nanometers.
[0036] In some embodiments of the present application, the high-k dielectric layer 130 may be a single-layer structure or a multi-layer stacked structure.
[0037] In some embodiments of the present application, a method for forming the auxiliary layer 120 and the high-k dielectric layer 130 includes a chemical vapor deposition process or a physical vapor deposition process.
[0038] refer to Figure 4 As shown, a barrier layer 140 is formed on the surface of the high-k dielectric layer 130 .
[0039] In some embodiments of the present application, the material of the barrier layer 140 includes titanium nitride. The thickness of the barrier layer 140 is 5 to 10 nanometers, for example, 6 nanometers or 8 nanometers. The function of the barrier layer 140 is to improve the gate polysilicon depletion effect.
[0040] In some embodiments of the present application, the surface of the barrier layer 140 in the second region 102 is higher than the surface of the barrier layer 140 in the first region 101 .
[0041] In some embodiments of the present application, the surface of the barrier layer 140 in the second region 102 has the same thickness as the barrier layer 140 in the first region 101 .
[0042] refer to Figure 5 As shown, a gate layer 150 is formed on the surface of the barrier layer 140 .
[0043] In some embodiments of the present application, the gate layer 150 is made of polysilicon and has a thickness of 30-80 nanometers.
[0044] In some embodiments of the present application, surfaces of the gate layer 150 in the second region 102 and the first region 101 are flush.
[0045] refer to Figure 6 As shown, the gate layer 150, the barrier layer 140, the high-k dielectric layer 130, the auxiliary layer 120, and the oxide layer 110 are etched to the surface of the semiconductor substrate 100 to form a gate structure 160. The gate structure 160 spans the first region 101 and the second region 102. The gate structure 160 includes the gate layer 150, the barrier layer 140, the high-k dielectric layer 130, the auxiliary layer 120, and the oxide layer 110.
[0046] The gate structure 160 of the technical solution of the present application is an asymmetric structure, wherein the portion of the gate structure 160 located in the first region 101 includes an auxiliary layer 120, a high-k dielectric layer 130, a barrier layer 140 and a gate layer 150 located in sequence on the surface of the semiconductor substrate, and the portion of the gate structure 160 located in the second region 102 includes an oxide layer 110, an auxiliary layer 120, a high-k dielectric layer 130, a barrier layer 140 and a gate layer 150 located in sequence on the surface of the semiconductor substrate 100.
[0047] refer to Figure 7 As shown, a source 170 and a drain 180 are respectively formed in the semiconductor substrate 100 on both sides of the gate structure 160 , wherein the source 170 is located in the first region 101 , and the drain 180 is located in the second region 102 .
[0048] In some embodiments of the present application, a method of forming the source 170 and the drain 180 in the semiconductor substrate 100 on both sides of the gate structure 160 , respectively, includes an ion implantation process.
[0049] In some embodiments of the present application, the ion implantation types of the source 170 and the drain 180 are opposite.
[0050] In some embodiments of the present application, the method for forming the TFET device further includes forming sidewalls (not shown) on the sidewalls of the gate structure 160. The sidewalls are also asymmetric; specifically, the sidewall thickness on the first region 101 side is less than the sidewall thickness on the second region 102 side.
[0051] In some embodiments of the present application, the sidewall spacer may be formed before the source and the drain, or after the source and the drain.
[0052] The use of high-k dielectric materials for the gate dielectric layer can increase the on-state current of TFET devices. However, due to the bipolar effect of TFETs, the bipolar effect current also increases, causing an increase in the leakage current Ioff. Therefore, in the technical solution of this application, a high-k dielectric layer 130 is used near the source 170 to enhance the tunneling capability and increase the on-state current; the drain 180 uses a high-k dielectric layer + oxide layer 110 to weaken the bipolar effect and reduce the leakage current.
[0053] The technical solution of the present application adopts a heterogeneous gate dielectric layer, and a high-k dielectric layer 130 is used near the source 170 to enhance the tunneling capability. The on-state current is determined by the source junction and the channel below the high-k dielectric layer 130, thereby increasing Ion; the drain 180 adopts a high-k dielectric layer + oxide layer 110 to weaken the bipolar effect.
[0054] The present application provides a method for forming a TFET device, which can increase the on-state current of the TFET device and reduce the leakage current, weaken the bipolar effect of the TFET, thereby improving the device performance.
[0055] The embodiment of the present application also provides a TFET device, referring to Figure 7 As shown, it includes: a semiconductor substrate 100, the semiconductor substrate 100 includes a first region 101 and a second region 102; a gate structure 160, located on the surface of the semiconductor substrate 100 and spanning the first region 101 and the second region 102, wherein the portion of the gate structure 160 located in the first region 101 includes an auxiliary layer 120, a high-k dielectric layer 130, a barrier layer 140 and a gate layer 150 sequentially located on the surface of the semiconductor substrate 100, and the portion of the gate structure 160 located in the second region 102 includes an oxide layer 110, an auxiliary layer 120, a high-k dielectric layer 130, a barrier layer 140 and a gate layer 150 sequentially located on the surface of the semiconductor substrate 100; a source 170 and a drain 180, respectively located in the semiconductor substrate 100 on both sides of the gate structure 160, wherein the source 170 is located in the first region 101, and the drain 180 is located in the second region 102.
[0056] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.
[0057] In some embodiments of the present application, the semiconductor substrate 100 also has structures such as a well region that are common in TFET devices, which are omitted here for the sake of brevity.
[0058] In some embodiments of the present application, the material of the oxide layer 110 includes silicon oxide.
[0059] In some embodiments of the present application, the thickness of the oxide layer 110 is 1.5 to 2.5 nanometers, for example, 2 nanometers.
[0060] In some embodiments of the present application, the auxiliary layer 120 is made of silicon oxynitride. The thickness of the auxiliary layer 120 is 0.5 to 1.5 nanometers, for example, 1 nanometer. The auxiliary layer 120 is used to improve the interface state between the high-k dielectric layer 130 and the semiconductor substrate 100.
[0061] In some embodiments of the present application, the material of the high-k dielectric layer 130 includes a high dielectric constant material such as hafnium oxide. The thickness of the high-k dielectric layer 130 is 1 to 2 nanometers, for example, 1.5 nanometers.
[0062] In some embodiments of the present application, the high-k dielectric layer 130 may be a single-layer structure or a multi-layer stacked structure.
[0063] In some embodiments of the present application, the material of the barrier layer 140 includes titanium nitride. The thickness of the barrier layer 140 is 5 to 10 nanometers, for example, 6 nanometers or 8 nanometers. The function of the barrier layer 140 is to improve the gate polysilicon depletion effect.
[0064] In some embodiments of the present application, the surface of the auxiliary layer 120 of the second region 102 is higher than the surface of the auxiliary layer 120 of the first region 101; the surface of the high-k dielectric layer 130 of the second region 102 is higher than the surface of the high-k dielectric layer 130 of the first region 101; the surface of the barrier layer 140 of the second region 102 is higher than the surface of the barrier layer 140 of the first region 101.
[0065] In some embodiments of the present application, the auxiliary layer 120 of the second region 102 and the first region 101 have the same thickness; the high-k dielectric layer 130 of the second region 102 and the high-k dielectric layer 130 of the first region 101 have the same thickness; the surface of the barrier layer 140 of the second region 102 and the barrier layer 140 of the first region 101 have the same thickness.
[0066] In some embodiments of the present application, the gate layer 150 is made of polysilicon and has a thickness of 30-80 nanometers.
[0067] In some embodiments of the present application, surfaces of the gate layer 150 in the second region 102 and the first region 101 are flush.
[0068] The gate structure 160 of the technical solution of the present application is an asymmetric structure, wherein the portion of the gate structure 160 located in the first region 101 includes an auxiliary layer 120, a high-k dielectric layer 130, a barrier layer 140 and a gate layer 150 located in sequence on the surface of the semiconductor substrate, and the portion of the gate structure 160 located in the second region 102 includes an oxide layer 110, an auxiliary layer 120, a high-k dielectric layer 130, a barrier layer 140 and a gate layer 150 located in sequence on the surface of the semiconductor substrate 100.
[0069] In some embodiments of the present application, the ion implantation types of the source 170 and the drain 180 are opposite.
[0070] In some embodiments of the present application, the TFET device further includes a sidewall spacer (not shown) located on the sidewall of the gate structure 160. The sidewall spacer also has an asymmetric structure. Specifically, the sidewall spacer on the first region 101 side is thinner than the sidewall spacer on the second region 102 side.
[0071] The use of high-k dielectric materials for the gate dielectric layer can increase the on-state current of TFET devices. However, due to the bipolar effect of TFETs, the bipolar effect current also increases, causing an increase in the leakage current Ioff. Therefore, in the technical solution of this application, a high-k dielectric layer 130 is used near the source 170 to enhance the tunneling capability and increase the on-state current; the drain 180 uses a high-k dielectric layer + oxide layer 110 to weaken the bipolar effect and reduce the leakage current.
[0072] The technical solution of the present application adopts a heterogeneous gate dielectric layer, and a high-k dielectric layer 130 is used near the source 170 to enhance the tunneling capability. The on-state current is determined by the source junction and the channel below the high-k dielectric layer 130, thereby increasing Ion; the drain 180 adopts a high-k dielectric layer + oxide layer 110 to weaken the bipolar effect.
[0073] The present application provides a TFET device and a method for forming the same, which can increase the on-state current of the TFET device and reduce the leakage current, weaken the bipolar effect of the TFET, and thus improve the device performance.
[0074] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.
[0075] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.
[0076] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0077] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.
[0078] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a TFET device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first region and a second region; forming an oxide layer on the surface of the semiconductor substrate in the second region; forming an auxiliary layer and a high-k dielectric layer in sequence on the surfaces of the semiconductor substrate and the oxide layer; forming a barrier layer on the surface of the high-k dielectric layer; forming a gate layer on the surface of the barrier layer; Etching the gate layer, the barrier layer, the high-k dielectric layer, the auxiliary layer, and the oxide layer to the surface of the semiconductor substrate to form a gate structure, wherein the gate structure spans the first region and the second region; A source electrode and a drain electrode are respectively formed in the semiconductor substrate on both sides of the gate structure, wherein the source electrode is located in the first region and the drain electrode is located in the second region.
2. The method for forming a TFET device according to claim 1, wherein: The thickness of the oxide layer is 1.5 to 2.5 nanometers.
3. The method for forming a TFET device according to claim 1, wherein: The auxiliary layer surface of the second region is higher than the auxiliary layer surface of the first region; the high-k dielectric layer surface of the second region is higher than the high-k dielectric layer surface of the first region; and the barrier layer surface of the second region is higher than the barrier layer surface of the first region.
4. The method for forming a TFET device according to claim 1, wherein: The auxiliary layer in the second region has the same thickness as that in the first region; the high-k dielectric layer in the second region has the same thickness as that in the first region; and the barrier layer surface in the second region has the same thickness as that in the first region.
5. The method for forming a TFET device according to claim 1, wherein: Surfaces of the gate layer in the second region are flush with surfaces of the gate layer in the first region.
6. A TFET device, characterized in that: include: a semiconductor substrate comprising a first region and a second region; a gate structure located on the surface of the semiconductor substrate and spanning the first region and the second region, wherein the portion of the gate structure located in the first region includes an auxiliary layer, a high-k dielectric layer, a barrier layer, and a gate layer sequentially located on the surface of the semiconductor substrate, and the portion of the gate structure located in the second region includes an oxide layer, an auxiliary layer, a high-k dielectric layer, a barrier layer, and a gate layer sequentially located on the surface of the semiconductor substrate; A source electrode and a drain electrode are respectively located in the semiconductor substrate on both sides of the gate structure, wherein the source electrode is located in the first region and the drain electrode is located in the second region.
7. The TFET device according to claim 6, wherein: The thickness of the oxide layer is 1.5 to 2.5 nanometers.
8. The TFET device according to claim 6, wherein: The auxiliary layer surface of the second region is higher than the auxiliary layer surface of the first region; the high-k dielectric layer surface of the second region is higher than the high-k dielectric layer surface of the first region; and the barrier layer surface of the second region is higher than the barrier layer surface of the first region.
9. The TFET device according to claim 6, wherein: The auxiliary layer in the second region has the same thickness as that in the first region; the high-k dielectric layer in the second region has the same thickness as that in the first region; and the barrier layer surface in the second region has the same thickness as that in the first region.
10. The TFET device according to claim 6, wherein: Surfaces of the gate layer in the second region are flush with surfaces of the gate layer in the first region.