SiC MOSFET terminal structure with low on-resistance and preparation process thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a low-on-resistance SiC MOSFET (metal oxide semiconductor field effect transistor) terminal structure, which consists of a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer, the semiconductor epitaxial layer sequentially comprises an N substrate layer, an N drift layer, a P well layer and an N well layer from bottom to top, P + layers are arranged on the two sides of the P well layer and the N well layer in a single MOS cell, a heavily doped N-layer is formed in the semiconductor epitaxial layer of the single MOS cell through ion implantation, and the heavily doped N-layer is located below the P well layer and is in contact with the P well layer. The heavily doped N-layer is additionally arranged below the P well layer to form a vertical low-resistance path, the uniformity of a grid electric field is destroyed in combination with the conduction P region, suppression of the grid on charge diffusion of a drain is weakened, the conduction resistance is greatly reduced compared with a traditional structure, and then the conduction current is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a SiC MOSFET terminal structure with low on-resistance and a preparation process thereof. Background Art

[0002] In order to meet the high voltage requirements, the traditional structure needs to thicken the drift layer or reduce its doping concentration, which leads to a significant increase in on-resistance. At the same time, the uniform electric field under the gate inhibits the diffusion of drain charge to the source (see Figure 6 The results of A in Figure 1 further limit current capability. Furthermore, electric field concentration in the terminal region can easily cause localized breakdown, forcing the design to compromise resistance performance to ensure voltage withstand reliability. Attempts to reduce resistance through JFET region implantation or epitaxial layer thinning have exacerbated voltage degradation, increased process complexity, and increased costs, making it difficult to achieve both high performance and mass production.

[0003] An existing patent discloses a low on-resistance SiC-based MOSFET device and its preparation method (publication number CN115117145A). The technology disclosed in this patent has the following problems: 1. The problem of gate electric field suppression is not solved: the drift region resistance is reduced only by segmented doping of the drift layer (highly doped nx layer + lowly doped n- layer), but no structure similar to the "conductive P region" is introduced under the gate, which cannot destroy the gate electric field uniformity (see Figure 6 A), resulting in the drain charge diffusion being suppressed and the on-current increase being limited.

[0004] 2. Passive issues in the terminal withstand voltage design: The electric field is optimized by relying on the coupling effect between the P well region and the low-doped drift layer (such as shielding the gate dielectric), but there is a lack of active lateral electric field control structure (such as side P regions and covering substrate layers). The edge electric field peak suppression capability is insufficient, and the risk of local breakdown is high. Summary of the Invention

[0005] In order to solve the existing technical problems, the present invention provides a low on-resistance SiC MOSFET terminal structure and its preparation process, which solves the problem that the uniform electric field under the gate inhibits the diffusion of drain charge to the source.

[0006] To solve the above technical problems, according to one aspect of the present invention, more specifically, a low on-resistance SiC MOSFET terminal structure is provided. The SiC MOSFET terminal structure is composed of a plurality of mutually parallel MOS cells, wherein the MOS cells include a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer. The semiconductor epitaxial layer includes, from bottom to top, an N substrate layer, an N drift layer, a P well layer, and an N well layer. P+ layers are provided on both sides of the P well layer and the N well layer in a single MOS cell. A heavily doped N- layer is formed in the semiconductor epitaxial layer of a single MOS cell by ion implantation. The heavily doped N- layer is located below and in contact with the P well layer. A conductive P region is provided below the gate, and the upper and lower ends of the conductive P region are only in contact with the gate and the N drift layer respectively.

[0007] Furthermore, the heavily doped N-layer is located inside the N drift layer.

[0008] Furthermore, the heavily doped N-layer further includes a connected N-layer, and the bottom end of the connected N-layer is in contact with the N substrate layer.

[0009] Furthermore, the conductive P region further includes two side P regions, and the two side P regions are both located in the region between the connected N-layers.

[0010] Furthermore, the N substrate layer also includes an intermediate substrate layer and a through substrate layer.

[0011] Furthermore, the top of the through-substrate layer contacts the P+ layer, the P-well layer, and the heavily doped N-layer, and the N-drift layer is located between the middle substrate layer and the gate.

[0012] Furthermore, the N substrate layer further includes a covering substrate layer, and the N drift layer further includes a central drift layer. The top of the covering substrate layer contacts the P+ layer, the P well layer, the heavily doped N- layer, and the central drift layer.

[0013] Furthermore, the central drift layer is located in a region between two adjacent heavily doped N-layers.

[0014] A process for preparing a low on-resistance SiC MOSFET terminal structure, specifically comprising: S1, epitaxially growing an N drift layer on the N substrate layer; S2. Forming a heavily doped N-layer in the N-drift layer by ion implantation, wherein the heavily doped N-layer is located below and in contact with the subsequent P-well layer; S3, forming a P-well layer above the heavily doped N-layer by ion implantation, and implanting P+ layers on both sides of the P-well layer; S4, implanting a conductive P region in the area below the gate so that its upper and lower ends only contact the gate and the N drift layer respectively; S5. Form a capping substrate layer by performing ion implantation on both sides of the N drift layer to make the ion concentration consistent with the ion concentration of the N substrate layer. The capping substrate layer is in contact with the P+ layer, the P well layer, and the heavily doped N- layer. S6, forming an N+ well layer in the P well layer by ion implantation; S7, growing a gate oxide layer on the surface of the semiconductor, and depositing metal on the conductive P region to form a gate; S8. Prepare a drain electrode on the back side of the device and a source electrode on the front side of the device, so that the source electrode contacts the P+ layer and the N+ well layer.

[0015] The present invention provides a low on-resistance SiC MOSFET terminal structure and its preparation process. Compared with the existing technology, this method achieves the following effects: 1. The present invention forms a vertical low-resistance path by adding a heavily doped N-layer below the P-well layer, and combines the conductive P region to destroy the gate electric field uniformity, weakening the gate's inhibition of drain charge diffusion. Compared with the traditional structure, the on-resistance is greatly reduced, and the on-current is greatly improved.

[0016] 2. The present invention isolates the electric field interference of adjacent cells through the side P region, and coordinates the terminal electric field regulation by the covering substrate layer and the central drift layer, thereby solving the contradiction between low resistance and high withstand voltage, thereby increasing the breakdown voltage, reducing the edge electric field peak, and avoiding the risk of local breakdown.

[0017] 3. The present invention uses ion implantation technology to precisely locate key areas such as the heavily doped N-layer and the conductive P region, minimizing doping concentration deviations. Furthermore, the entire process is compatible with standard SiC manufacturing processes, eliminating the need for additional photolithography steps, thereby significantly reducing production costs.

[0018] 4. The present invention shortens the substrate current path by penetrating the substrate layer, and reduces the contact resistance by making the source electrode double-contact the P+ layer and the N+ well layer; and the interface state density of the gate oxide layer can be reduced. Combined with the electric field modulation effect of the conductive P region, the switching speed is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic structural diagram of Example 1 of the present invention; Figure 2 This is a schematic structural diagram of Example 2 of the present invention; Figure 3 This is a schematic structural diagram of Example 3 of the present invention; Figure 4 This is a schematic structural diagram of Embodiment 4 of the present invention; Figure 5This is a structural diagram of Example 5 of the present invention; Figure 6 A in the figure is the electric field state diagram of the existing SiC MOSFET structure. Figure 6 B in FIG. 1 is an electric field state diagram of the structure in Example 1.

[0020] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Gate oxide layer; 5. N substrate layer; 6. N drift layer; 7. P+ layer; 8. N well layer; 9. P well layer; 10. Heavily doped N- layer; 11. Conductive P region; 51. Intermediate substrate layer; 52. Through substrate layer; 53. Covering substrate layer; 61. Centered drift layer; 101. Connected N- layer; 1101. Side P region. DETAILED DESCRIPTION

[0021] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The fabrication process for the low on-resistance SiC MOSFET terminal structure includes: Step 1: epitaxially grow an N drift layer 6 on the N substrate layer 5.

[0023] By precisely controlling epitaxial growth parameters (such as doping concentration and thickness), a uniform N drift layer 6 is formed, providing an ideal substrate for subsequent ion implantation. This ensures that the drift layer has both high withstand voltage and low resistance characteristics, laying the foundation for device performance.

[0024] Step 2: Form a heavily doped N-layer 10 in the N-drift layer 6 by ion implantation. The heavily doped N-layer 10 is located below and in contact with the subsequent P-well layer 9 .

[0025] A high-concentration doped region is formed directly below the P-well layer 9 to establish a vertical low-resistance path, significantly reducing the resistance of the drift layer (in traditional structures, current needs to flow through the high-resistance drift layer), while precisely positioning it to avoid affecting the device's voltage resistance.

[0026] Step 3: Form a P-well layer 9 on the heavily doped N-layer 10 by ion implantation, and form a P+ layer 7 on both sides of the P-well layer 9 by implantation.

[0027] The P-well layer 9 is in direct contact with the heavily doped N-layer 10, optimizing the carrier transmission path under the channel; the P+ layer 7 enhances the body contact, reduces the source contact resistance and suppresses the parasitic transistor effect, thereby improving device reliability.

[0028] Step 4: implant a conductive P region 11 in the area below the gate 3 so that its upper and lower ends only contact the gate 3 and the N drift layer 6 respectively.

[0029] By turning on the P region 11, the gate electric field uniformity is destroyed (see Figure 6In contrast, the gate's suppression of drain charge diffusion is weakened, the on-current is increased, and the independent design avoids the introduction of additional parasitic capacitance.

[0030] Step 5: Ion implantation is performed on both sides of the N drift layer 6 to make the ion concentration consistent with the ion concentration of the N substrate layer 5 to form a covering substrate layer 53. The covering substrate layer 53 contacts the P+ layer 7, the P well layer 9, and the heavily doped N- layer 10.

[0031] The high-concentration substrate is extended to the surface to reduce the resistance of the edge area, and at the same time connected to the P+ layer 7, the heavily doped N- layer 10, etc., to optimize the terminal electric field distribution and improve the withstand voltage reliability.

[0032] Step 6: Form an N+ well layer 8 in the P well layer 9 by ion implantation.

[0033] The N+ injection depth and concentration are precisely controlled to form a low-resistance source region, which together with the P-well layer 9 constitutes an efficient conductive channel, reduces the channel resistance, and cooperates with the P+ layer 7 to achieve dual-path contact with the source.

[0034] Step 7: growing a gate oxide layer 4 on the semiconductor surface, and depositing metal on the conductive P region 11 to form a gate 3.

[0035] The gate metal is deposited directly on the conductive P region 11, and its electric field modulation effect is used to enhance the gate control capability; the high-quality gate oxide layer 4 reduces the interface state density and improves the channel mobility and switching speed.

[0036] Step eight: prepare a drain electrode 1 on the back side of the device and a source electrode 2 on the front side of the device, so that the source electrode 2 contacts the P+ layer 7 and the N+ well layer 8.

[0037] Example 1 like Figure 1 、 6 As shown, according to one aspect of the present invention, a low on-resistance SiC MOSFET terminal structure is provided, wherein the SiC MOSFET terminal structure is composed of a plurality of mutually parallel MOS cells, wherein the MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer 4, wherein the semiconductor epitaxial layer includes, from bottom to top, an N substrate layer 5, an N drift layer 6, a P well layer 9, and an N well layer 8, wherein a P+ layer 7 is provided on both sides of the P well layer 9 and the N well layer 8 in a single MOS cell, and wherein: a heavily doped N- layer 10 is formed in the semiconductor epitaxial layer of the single MOS cell by ion implantation, wherein the heavily doped N- layer 10 is located below the P well layer 9 and in contact with the P well layer 9; A conductive P region 11 is provided below the gate 3. The upper and lower ends of the conductive P region 11 are only in contact with the gate 3 and the N drift layer 6 respectively. The conductive P region 11 is used to destroy the stable gate electric field. Since the gate electric field in traditional devices inhibits the diffusion speed of the charge in the drain 1 to the source 2, the conduction current between the drain and the source is reduced. Figure 6 As shown in A in FIG, the gate electric field is more uniform in direction at this time, so the effect will be greater. However, the addition of the conductive P region 11 can destroy the uniformity of the stable gate electric field, thereby significantly reducing the influence of the gate electric field. Figure 6 As shown in B.

[0038] By adding a conductive P region 11 below the gate 3, its upper and lower ends only contact the gate and the N drift layer 6. This structure destroys the stability of the gate electric field. Figure 6 The electric field distribution of A and B in the middle weakens the inhibitory effect of the gate electric field on the diffusion of drain 1 charges to source 2, thereby reducing the on-resistance and improving the current capability.

[0039] Example 2 like Figure 2 As shown, the heavily doped N-layer 10 is located inside the N drift layer 6. The heavily doped N-layer 10 further includes a connecting N-layer 101, the bottom end of which is in contact with the N substrate layer 5.

[0040] The bottom of the heavily doped N-layer 10 is extended to connect the N-layer 101, making it directly contact with the N substrate layer 5. This design forms a vertical low-resistance path from the substrate to the bottom of the P-well 9, utilizing the heavily doped characteristics to reduce the drift layer resistance and further reduce the overall on-resistance.

[0041] Example 3 like Figure 3 As shown, the heavily doped N-layer 10 is located inside the N-drift layer 6. The heavily doped N-layer 10 also includes a connected N-layer 101, the bottom end of which is in contact with the N substrate layer 5. The conductive P region 11 also includes two side P regions 1101, both of which are located in the area between the connected N-layer 101.

[0042] Two side P regions 1101 are added between the connected N-layers 101. The side P regions not only isolate the heavily doped N-layers of adjacent cells to avoid electric field interference, but also optimize the depletion layer expansion of the P-well 9, enhance the lateral withstand voltage capability, and maintain low on-resistance characteristics.

[0043] Example 4 like Figure 4 As shown, the N substrate layer 5 further includes an intermediate substrate layer 51 and a through substrate layer 52. The top of the through substrate layer 52 contacts the P+ layer 7, the P well layer 9, and the heavily doped N- layer 10, and the N drift layer 6 is located between the intermediate substrate layer 51 and the gate 3.

[0044] N-substrate layer 5 is divided into an intermediate substrate layer 51 and a through-substrate layer 52, the latter of which connects to P+ layer 7, P-well layer 9, and heavily doped N-layer 10. The through-substrate layer forms a longitudinal conductive channel, shortening the current path and reducing substrate resistance. The intermediate substrate layer supports the withstand voltage requirements of drift layer 6, balancing conduction and blocking performance.

[0045] Example 5 like Figure 5 As shown, the N substrate layer 5 further includes a covering substrate layer 53, and the N drift layer 6 further includes a central drift layer 61. The top of the covering substrate layer 53 contacts the P+ layer 7, the P well layer 9, the heavily doped N- layer 10, and the central drift layer 61. The central drift layer 61 is located in the region between two adjacent heavily doped N- layers 10.

[0046] Ion implantation forms a capping substrate layer 53 on both sides of the drift layer 6. Its top connects the P+ layer 7, P-well layer 9, heavily doped N- layer 10, and the central drift layer 61. The central drift layer 61, located between adjacent heavily doped regions, collaborates with the capping substrate layer to optimize the edge electric field distribution, improving the terminal withstand voltage reliability while maintaining low resistance characteristics.

[0047] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A low on-resistance SiC MOSFET terminal structure, the SiC MOSFET terminal structure comprising a plurality of mutually parallel MOS cells, the MOS cells comprising a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3) and a gate oxide layer (4), the semiconductor epitaxial layer comprising, from bottom to top, an N substrate layer (5), an N drift layer (6), a P well layer (9) and an N well layer (8), wherein P+ layers (7) are provided on both sides of the P well layer (9) and the N well layer (8) in a single MOS cell, and the characteristics are as follows: A heavily doped N-layer (10) is formed in the semiconductor epitaxial layer of a single MOS cell by ion implantation, and the heavily doped N-layer (10) is located below the P-well layer (9) and in contact with the P-well layer (9); A conductive P region (11) is provided below the gate (3), and the upper and lower ends of the conductive P region (11) are only in contact with the gate (3) and the N drift layer (6) respectively.

2. The low on-resistance SiC MOSFET terminal structure according to claim 1, characterized in that: The heavily doped N-layer (10) is located inside the N drift layer (6).

3. The low on-resistance SiC MOSFET terminal structure according to claim 2, characterized in that: The heavily doped N-layer (10) further includes a connected N-layer (101), the bottom end of the connected N-layer (101) being in contact with the N substrate layer (5).

4. The low on-resistance SiC MOSFET terminal structure according to claim 3, characterized in that: The conductive P region (11) further comprises two side P regions (1101), and the two side P regions (1101) are both located in the region between the connected N-layer (101).

5. The low on-resistance SiC MOSFET terminal structure according to claim 1, wherein: The N substrate layer (5) further includes an intermediate substrate layer (51) and a through substrate layer (52).

6. The low on-resistance SiC MOSFET terminal structure according to claim 5, characterized in that: The top of the through substrate layer (52) is in contact with the P+ layer (7), the P well layer (9), and the heavily doped N- layer (10), and the N drift layer (6) is located between the middle substrate layer (51) and the gate (3).

7. The low on-resistance SiC MOSFET terminal structure according to claim 1, wherein: The N substrate layer (5) further includes a covering substrate layer (53), and the N drift layer (6) further includes a central drift layer (61). The top of the covering substrate layer (53) contacts the P+ layer (7), the P well layer (9), the heavily doped N- layer (10), and the central drift layer (61).

8. The low on-resistance SiC MOSFET terminal structure according to claim 7, characterized in that: The central drift layer (61) is located in a region between two adjacent heavily doped N-layers (10).

9. A process for preparing a low on-resistance SiC MOSFET terminal structure, characterized in that: Applicable to the SiC MOSFET terminal structure according to any one of claims 7 or 8, the preparation process of the low on-resistance SiC MOSFET terminal structure specifically includes: S1, epitaxially growing an N drift layer (6) on the N substrate layer (5); S2, forming a heavily doped N-layer (10) in the N drift layer (6) by ion implantation, wherein the heavily doped N-layer (10) is located below and in contact with the subsequent P well layer (9); S3, forming a P-well layer (9) above the heavily doped N-layer (10) by ion implantation, and implanting P+ layers (7) on both sides of the P-well layer (9); S4, injecting into the area below the gate (3) to form a conductive P region (11), so that its upper and lower ends only contact the gate (3) and the N drift layer (6) respectively; S5. Forming a covering substrate layer (53) by performing ion implantation on both sides of the N drift layer (6) so that the ion concentration is consistent with the ion concentration of the N substrate layer (5), and the covering substrate layer (53) is in contact with the P+ layer (7), the P well layer (9), and the heavily doped N- layer (10); S6, forming an N+ well layer (8) in the P well layer (9) by ion implantation; S7, growing a gate oxide layer (4) on the surface of the semiconductor, and depositing metal on the conductive P region (11) to form a gate (3); S8. Prepare a drain electrode (1) on the back side of the device and prepare a source electrode (2) on the front side of the device, so that the source electrode (2) contacts the P+ layer (7) and the N+ well layer (8).

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