Low-channel resistance SiC VDMOSFET device and manufacturing method thereof

Abstract

The invention relates to a low-channel-resistance SiC VDMOSFET device and a manufacturing method thereof, a conducting channel of the low-channel-resistance SiC VDMOSFET device comprises a laminated channel region, the laminated channel region is composed of n groups of P-type channel layers and N-type channel layers which are sequentially laminated, and n is larger than or equal to 1. According to the structure, accurate regulation and control of channel doping concentration and distribution can be realized. Moreover, the effective conductive depth of the channel is obviously increased by the multilayer conductive channel formed by the laminated channel region structure. The characteristic effectively weakens the interference of coulomb scattering, surface roughness scattering and other main scattering mechanisms on the channel carrier transport process, and further significantly improves the mobility of the carriers in the channel. According to the invention, the on-resistance is effectively reduced while the low leakage current of the device is ensured, so that the conduction loss is reduced, and the energy conversion efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and more particularly to a low channel resistance SiCVD MOSFET device and a manufacturing method thereof. Background Art

[0002] MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a semiconductor device widely used for switching purposes and amplification of electronic signals in electronic devices.

[0003] Early semiconductor devices primarily used silicon substrates, but inherent properties of silicon, such as its narrow bandgap, significantly limited their high-temperature, high-voltage, and radiation-resistant performance. The rise and commercialization of wide-bandgap materials, such as silicon carbide (SiC) and gallium nitride (GaN), have successfully overcome the performance bottlenecks of silicon-based devices, significantly expanding their application. Currently, commonly used SiC MOSFETs fall into two main categories, based on their conduction paths: SiC VDMOSFETs (Vertical Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistors) and SiC LDMOSFETs (Lateral Diffused Metal Oxide Semiconductor Field-Effect Transistors). SiC VDMOSFETs are more widely used in discrete devices, such as inverters and electronic switches.

[0004] Existing SiC VDMOSFET structures such as Figure 1 As shown, it includes a SiC substrate 1, an N-type drift region 2, a P-type body region 3, a P-type heavily doped region 4, an N-type source region 5, a gate dielectric layer 6, a gate 7, a field passivation layer 8, a source electrode 9, and a drain electrode 10. The SiC substrate 1 is heavily N-type doped; the N-type drift region 2 is located within the epitaxial layer of the SiC substrate 1 and is lightly N-type doped; the P-type heavily doped region 4 is heavily P-type doped; the gate dielectric layer 6 is generally a silicon dioxide layer, and the gate 7 is generally polysilicon.

[0005] In actual applications, it was found that the carrier mobility in the conductive channel of SiC VDMOSFET devices is 10-70 cm² / (V·s), which is significantly lower than the mobility of 800-1000 cm² / (V·s) of SiC bulk material. This results in higher conduction losses and lower energy conversion efficiency of SiC VDMOSFET devices, which are significantly different from the theoretical values. Summary of the Invention

[0006] Research has shown that the carrier mobility of 10-70 cm² / (V·s) in the conductive channel region of the current mainstream SiC VDMOSFET devices is significantly lower than the mobility of 800-1000 cm² / (V·s) of the SiC bulk material. This phenomenon is mainly due to the poor quality of the SiC / SiO2 interface formed after high-temperature oxidation and further NO or N2O annealing treatment. The strong Coulomb scattering (such as fixed charge, interface traps) and surface roughness scattering cause the channel resistance Rch (Channel Resistance) to account for a large proportion, which has become a key bottleneck restricting SiC VDMOSFET from achieving lower conduction losses and higher energy conversion efficiency.

[0007] Based on this, it is necessary to provide a low channel resistance SiC VDMOSFET device and a manufacturing method thereof to address the above problems, so as to reduce conduction loss and improve energy conversion efficiency by optimizing the channel structure.

[0008] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0009] A low-channel-resistance SiC VDMOSFET device, wherein the conductive channel of the low-channel-resistance SiC VDMOSFET device comprises:

[0010] The stacked channel region is composed of n groups of P-type channel layers and N-type channel layers stacked in sequence, wherein n≥1.

[0011] In one embodiment, the stacked channel region is composed of 1-4 stacked groups of P-type channel layers and N-type channel layer groups.

[0012] In one embodiment, the P-type channel layer and the N-type channel layer group are sequentially composed of a P-type channel layer and an N-type channel layer along a first direction from the SiC / gate dielectric layer interface of the low channel resistance SiC VDMOSFET device.

[0013] In one embodiment, the P-type channel layer and the N-type channel layer group are sequentially composed of an N-type channel layer and a P-type channel layer along a first direction from the SiC / gate dielectric layer interface of the low channel resistance SiC VDMOSFET device.

[0014] In one embodiment, the doping range of the N-type channel layer and the P-type channel layer in the P-type channel layer and N-type channel layer group is 1×10 15 cm -3 ~4×10 18 cm -3 .

[0015] In one embodiment, the thickness of the P-type channel layer and the N-type channel layer in the P-type channel layer and the N-type channel layer group along the first direction is 0.05 μm to 0.25 μm.

[0016] In one embodiment, the depth of the stacked channel region from the SiC / gate dielectric layer interface of the low channel resistance SiC VDMOSFET device along the first direction is 0.2 μm to 1.2 μm, and the length of the stacked channel region along the second direction is 0.2 μm to 5 μm.

[0017] In one embodiment, the low channel resistance SiC VDMOSFET device is a planar gate device, a trench gate device, a fin gate device, a split gate device or a super junction device.

[0018] Another embodiment discloses a method for manufacturing a low-channel-resistance SiC VDMOSFET device. The method uses an ion implantation process to form a stacked channel region of the low-channel-resistance SiC VDMOSFET device.

[0019] Another embodiment discloses a method for manufacturing a low-channel-resistance SiC VDMOSFET device. The method uses an ion implantation process and an epitaxial growth process to form a stacked channel region of the low-channel-resistance SiC VDMOSFET device.

[0020] The conductive channel of the low channel resistance SiC VDMOSFET device disclosed in the present invention includes: a stacked channel region, wherein the stacked channel region is composed of n groups of P-type channel layers and N-type channel layer groups stacked in sequence, wherein n≥1. This structure can achieve precise control of the channel doping concentration and distribution. Moreover, the multi-layer conductive channel formed by the stacked channel region structure significantly increases the effective conductive depth of the channel. This feature effectively weakens the interference of major scattering mechanisms such as Coulomb scattering and surface roughness scattering on the channel carrier transport process, thereby significantly improving the carrier mobility in the channel. Therefore, the present invention effectively reduces the on-resistance while ensuring that the device maintains low leakage current, thereby reducing the conduction loss and improving the energy conversion efficiency, providing an effective and innovative technical approach to solving the bottleneck of SiC VDMOSFET channel performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1This is a schematic diagram of the structure of a conventional SiC VDMOSFET device (NMOS);

[0022] Figure 2 A schematic structural diagram of a SiC VDMOSFET device (NMOS) provided in one embodiment of the present invention;

[0023] Figure 3 A schematic diagram of the local structure of a stacked channel region (surface inversion channel) of a SiC VDMOSFET device provided in one embodiment of the present invention;

[0024] Figure 4 A schematic diagram of a partial structure of a stacked channel region (surface accumulation type channel) of another SiC VDMOSFET device provided by another embodiment of the present invention;

[0025] Figure 5 A schematic diagram of the partial structure of a stacked channel region of another SiC VDMOSFET device (composed of three groups of P-type channel layers and one group of N-type channel layers, being a surface accumulation-type channel) provided by another embodiment of the present invention;

[0026] Figure 6 A schematic diagram of the partial structure of a stacked channel region of another SiC VDMOSFET device (composed of three groups of P-type channel layers and an N-type channel layer group, with a surface inversion channel) provided by another embodiment of the present invention;

[0027] Figure 7 A cross-sectional view of a planar gate SiC VDMOSFET device (NMOS) provided in the first embodiment of the present invention taken along the A'-A'' section line;

[0028] Figure 8 A schematic structural diagram of a planar gate SiC VDMOSFET device (PMOS) provided in the second embodiment of the present invention;

[0029] Figure 9 A schematic diagram of the structure of a trench-gate SiC VDMOSFET device provided in Example 3 of the present invention;

[0030] Figure 10 A schematic diagram of the structure of a fin-gate SiC VDMOSFET device provided in the fourth embodiment of the present invention;

[0031] Figure 11 A top view of a strip cell design of a SiC VDMOSFET device provided in Example 5 of the present invention (with A'-A'' hatching);

[0032] Figure 12 A three-dimensional diagram of a strip cell design of a SiC VDMOSFET device provided in Example 5 of the present invention;

[0033] Figure 13 A top view of a hexagonal cell design of a SiC VDMOSFET device provided in Example 6 of the present invention (with hatching BA);

[0034] Figure 14 A three-dimensional diagram of a hexagonal cell design of a SiC VDMOSFET device provided in Example 6 of the present invention;

[0035] Figure 15 A cross-sectional view of a SiC VDMOSFET device provided in Example 6 of the present invention taken along the BA section line;

[0036] Figure 16 A schematic diagram of the steps for manufacturing a SiC VDMOSFET device according to the seventh embodiment of the present invention (using an ion implantation process to form a stacked channel region);

[0037] Figure 17 Schematic diagram of another SiC VDMOSFET device manufacturing step provided in the eighth embodiment of the present invention (using ion implantation and epitaxial growth processes to form a stacked channel region).

[0038] In the figure, 1, SiC substrate; 2, N-type drift region; 3, P-type body region; 4, P-type heavily doped region; 5, N-type source region; 2-1, P-type drift region; 3-1, N-type body region; 4-1, N-type heavily doped region; 5-1, P-type source region; 6, gate dielectric layer; 7, gate; 8, field passivation layer; 9, source electrode; 10, drain electrode; H1, stacked channel region; 31, first P-type channel layer; 32, second P-type channel layer; 33, third P-type channel layer; 3n, nth P-type channel layer; 61, first N-type channel layer; 62, second N-type channel layer; 63, third N-type channel layer; 6n, nth N-type channel layer; E1, first epitaxial layer; E2, second epitaxial layer; E3, third epitaxial layer. DETAILED DESCRIPTION

[0039] To facilitate understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments or embodiments and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of the related listed items, including any combination of any two related listed items, any more related listed items, or all related listed items.

[0041] One embodiment of the present invention discloses a low channel resistance SiC VDMOSFET device, such as Figure 2 As shown (taking NMOS as an example), the cell of the low channel resistance SiC VDMOSFET device includes: a SiC substrate 1 and an N-type drift region 2, a P-type body region 3, a P-type heavily doped region 4, an N-type source region 5, a gate dielectric layer 6, a gate 7, a field passivation layer 8, a source electrode 9 and a drain electrode 10 arranged on the SiC substrate 1.

[0042] like Figure 2 and Figure 3 As shown, the conductive channel of the low-channel resistance SiC VDMOSFET device includes a stacked channel region H1. The stacked channel region H1 is composed of n groups (n ≥ 1) of P-type channel layers and N-type channel layers stacked in sequence. The first group of P-type and N-type channel layers (connecting to the SiC / gate dielectric layer interface) consists of a first P-type channel layer 31 and a first N-type channel layer 61. The second group of P-type and N-type channel layers consists of a second P-type channel layer 32 and a second N-type channel layer 62. The third group of P-type and N-type channel layers consists of a third P-type channel layer 33 and a third N-type channel layer 63. Similarly, the nth group of P-type and N-type channel layers consists of the nth P-type channel layer 3n and the nth N-type channel layer 6n.

[0043] Taking a planar gate structured low channel resistance SiC VDMOSFET device as an example, the stacked channel region H1 is located inside the N-type source region 5 and on top of the P-type body region 3 .

[0044] It should be noted that in this embodiment, the doping depth of the P-type body region 3 is the deepest and surrounds the N-type source region 5. The stacked channel region H1 plays the role of the device conductive channel, so the doping depth of the N-type source region 5 is higher than that of the stacked channel region H1, but cannot be higher than the doping depth of the P-type body region 3.

[0045] The stacked channel region H1 replaces the inversion layer region at the top of the original P-type body region 3. In other words, the presence of the stacked channel region H1 transforms the original device's single conductive channel near the SiC / gate dielectric layer (typically SiC / SiO2) interface into multiple conductive channels located farther away from the SiC / gate dielectric layer interface. Ultimately, the device structure manifests itself as a stacked channel region H1 comprised of n (n ≥ 1) stacked groups of P-type and N-type channel layers, forming multiple conductive channels.

[0046] The present invention comprises a stacked channel region composed of a P-type channel layer and an N-type channel layer, which can achieve precise control of the channel doping concentration and distribution. Moreover, when the device is turned off, the multiple conductive channels formed by the overlapping P-type channel layer and the N-type channel layer will be depleted without forming a leakage path, so the device can maintain a low leakage current and remain normally off. When the device is turned on, the multiple conductive channels formed by the P-type channel layer and the N-type channel layer away from the SiC / SiO2 interface will be turned on, significantly increasing the effective conductive depth of the channel. The internal carriers are away from the Coulomb scattering center at the interface (such as interface charge) and are less scattered by surface roughness. That is, this characteristic effectively weakens the interference of the main scattering mechanisms such as Coulomb scattering and surface roughness scattering on the channel carrier transport process, thereby significantly improving the carrier mobility in the channel.

[0047] Therefore, the low channel resistance SiC VDMOSFET device disclosed in the present invention can effectively reduce the on-resistance while ensuring that the device maintains low leakage current, thereby reducing conduction losses and improving energy conversion efficiency, providing an effective and innovative technical approach to solving the bottleneck of SiCVDMOSFET channel performance.

[0048] In another embodiment, if Figure 3 As shown, the P-type channel layer and N-type channel layer group are sequentially arranged along the first direction from the SiC / gate dielectric layer interface. That is, sequentially arranged along the first direction from the SiC / gate dielectric layer interface are the first P-type channel layer and N-type channel layer group (first P-type channel layer 31 and first N-type channel layer 61), the second P-type channel layer and N-type channel layer group (second P-type channel layer 32 and second N-type channel layer 62), the third P-type channel layer and N-type channel layer group (third P-type channel layer 33 and third N-type channel layer 63), and so on, the nth P-type channel layer and N-type channel layer group (nth P-type channel layer 3n and nth N-type channel layer 6n). When the low-channel-resistance SiC VDMOSFET device is an NMOS device, its conductive channel is a surface inversion channel; when the low-channel-resistance SiC VDMOSFET device is a PMOS device, its conductive channel is a surface accumulation channel.

[0049] In another embodiment, if Figure 4 As shown, the P-type channel layer and N-type channel layer group are sequentially arranged along the first direction from the SiC / gate dielectric layer interface, namely, the first group of P-type channel layers and N-type channel layers (first N-type channel layer 61 and first P-type channel layer 31), the second group of P-type channel layers and N-type channel layers (second N-type channel layer 62 and second P-type channel layer 32), the third group of P-type channel layers and N-type channel layers (third N-type channel layer 63 and third P-type channel layer 33), and so on, the nth group of P-type channel layers and N-type channel layers (nth N-type channel layer 6n and nth P-type channel layer 3n). When the low-channel-resistance SiC VDMOSFET device is an NMOS device, its conductive channel is a surface accumulation channel; when the low-channel-resistance SiC VDMOSFET device is a PMOS device, its conductive channel is a surface inversion channel.

[0050] From the arrangement order of the P-type channel layer and the N-type channel layer in the above embodiment, it can be seen that although the present invention discloses the structure of the P-type channel layer and the N-type channel layer group, the P-type channel layer and the N-type channel layer group are only special structures named after the structural characteristics, which does not represent the arrangement order of the P-type channel layer and the N-type channel layer in the stacked channel region. Figure 3 As shown, the arrangement order of the P-type channel layer and the N-type channel layer in the stacked channel region is PNPNPN; it can also be as follows Figure 4 As shown, the arrangement order of the P-type channel layer and the N-type channel layer in the stacked channel region is NPNPNP, and the total number of channels is 2n.

[0051] In another embodiment, the stacked channel region is composed of 1 to 4 stacked groups of P-type channel layers and N-type channel layers.

[0052] Among them, the stacked channel region composed of three stacked groups of P-type channel layers and N-type channel layers is as follows: Figure 5 It should be noted that Figure 5 The stacked channel region is composed of three stacked groups of P-type channel layers and N-type channel layers. Each group of P-type channel layers and N-type channel layers is sequentially stacked with N-type channel layers and P-type channel layers along the first direction from the SiC / gate dielectric layer interface. That is, the stacked layers are the first N-type channel layer 61, the first P-type channel layer 31, the second N-type channel layer 62, the second P-type channel layer 32, the third N-type channel layer 63, and the third P-type channel layer 33. However, Figure 5While only three groups of P-type channel layers and N-type channel layers are shown, in practice, the P-type channel layer and N-type channel layer group may be stacked in the order of P-type channel layers and N-type channel layers along the first direction from the SiC / gate dielectric layer interface. Specifically, the stack may be a first P-type channel layer 31, a first N-type channel layer 61, a second P-type channel layer 32, a second N-type channel layer 62, a third P-type channel layer 33, and a third N-type channel layer 63.

[0053] In another embodiment, the doping range of the N-type channel layer and the P-type channel layer in the P-type channel layer and N-type channel layer group is 1×10 15 cm -3 ~4×10 18 cm -3 For example, the specific doping concentration of the N-type channel layer may be 1×10 15 cm -3 , 5×10 15 cm -3 , 1×10 16 cm -3 , 5×10 16 cm -3 The doping concentration of the P-type channel layer is 1×10 17 cm -3 , 4×10 17 cm -3 , 6×10 17 cm -3 , 1×10 18 cm -3 , 4×10 18 cm -3 etc., or a range consisting of any two of these values.

[0054] In specific applications, the low channel resistance SiC VDMOSFET device adopts a multi-layer channel design, which can adjust the doping concentration of each channel layer separately and perform a wide range of threshold voltage design V th (2V~4.5V). For example, for a low threshold voltage V th (2V~3.5V), the doping range of the P-type channel layer is 1×10 16 cm 3 ~4×10 17 cm -3 ; For high threshold voltage V th (3.5V~4.5V), the doping range of the P-type channel layer is 4×10 17 cm 3 ~4×10 18 cm -3 .

[0055] It should be noted that the doping concentrations of the N-type channel layer and the P-type channel layer may be the same or different.

[0056] In another embodiment, if Figure 6 As shown, the length L of the stacked channel region along the second direction is 0.2 μm to 5 μm, for example, 0.2 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc.

[0057] The depth S of the stacked channel region from the SiC / gate dielectric layer interface along the first direction is 0.2μm~1.2μm, for example, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.8μm, 1.2μm, etc., or a range consisting of any two of these values.

[0058] The P-type channel layer and the N-type channel layer in the P-type channel layer and N-type channel layer group ( Figure 6 (For example, the N-type channel layer has a thickness H along the second direction of 0.05 μm to 0.25 μm. For example, 0.05 μm, 0.08 μm, 0.1 μm, 0.12 μm, 0.15 μm, 0.18 μm, 0.2 μm, 0.23 μm, 0.25 μm, or a range consisting of any two of these values.)

[0059] The thicknesses of the N-type channel layer and the P-type channel layer are similar to their doping concentrations and can be the same or different. The specific thickness value depends on the thickness of the N-type channel layer depleted by the P-type channel layer. This ensures that when the device is turned off, the channel is completely depleted without generating leakage current, maintaining the low leakage current of the device. For example, the thickness of each channel layer (including P-type and N-type) is 0.1μm, 0.2μm, 0.11μm, and 0.09μm, respectively, starting from the SiC / gate dielectric layer interface. In specific applications, the doping concentration and thickness of the N-type channel layer and the P-type channel layer can be combined to control the on-resistance of each conductive channel. Due to the large number of possible combinations, they are not listed here one by one.

[0060] It should be noted that the first direction is perpendicular to the conductive channel of the low-channel-resistance SiC VDMOSFET device, and the second direction is parallel to the conductive channel of the low-channel-resistance SiC VDMOSFET device. For example, in a planar-gate structure and a fin-gate structure of a low-channel-resistance SiC VDMOSFET device, the first direction is perpendicular to the SiC substrate surface, and the second direction is parallel to the SiC substrate surface; in a trench-gate structure of a low-channel-resistance SiCVDMOSFET device (such as Figure 8 As shown), the first direction is parallel to the surface of the SiC substrate, and the second direction is perpendicular to the surface of the SiC substrate.

[0061] It should be noted that the depth S of the stacked channel region along the first direction is the distance from the SiC / gate dielectric layer interface to the stacked channel region / body region interface along the first direction. To reduce the number and types of ion implants, the number of process steps, and thus reduce costs, as a preferred solution, the doping concentrations of the N-type channel layer and the N-drift region can be the same, and the doping concentrations of the P-type channel layer and the P-type body region can also be the same. This further reduces process steps and lowers manufacturing costs.

[0062] However, since the doping concentrations of the P-type and N-type channel layers in the stacked channel region are related to the thickness of the PN junction depletion layer, which in turn affects the thickness of the individual P-type and N-type channel layers, as well as the thickness of the conductive channel, whether the doping concentration of the P-type or N-type channel layer is the same as that of the corresponding body or drift region depends on the device performance and manufacturing process requirements.

[0063] Another embodiment discloses a method for fabricating a low-channel-resistance SiC VDMOSFET device. This embodiment employs an ion implantation process to form the stacked channel region of the low-channel-resistance SiC VDMOSFET device. Specifically, multiple ion implantations are performed to form the N-type channel layer and the P-type channel layer.

[0064] Another embodiment discloses a method for fabricating a low-channel-resistance SiC VDMOSFET device. This embodiment employs a combination of ion implantation and epitaxial growth to form the stacked channel region of the low-channel-resistance SiC VDMOSFET device. Specifically, the N-type channel layer and the P-type channel layer are formed through epitaxial growth combined with ion implantation.

[0065] Hereinafter, the low channel resistance SiC VDMOSFET device and the manufacturing method thereof will be further described through specific embodiments.

[0066] Example 1

[0067] The first embodiment discloses a low channel resistance SiC VDMOSFET device, wherein the low channel resistance SiCVDMOSFET device is an NMOS device with a planar gate structure. Figure 7 As shown, the low channel resistance SiCVD MOSFET device cell disclosed in this embodiment includes:

[0068] SiC substrate 1, wherein the SiC substrate 1 is an N-type heavily doped substrate;

[0069] An N-type drift region 2, wherein the N-type drift region 2 is provided in the epitaxial layer of the SiC substrate 1 and is lightly N-type doped;

[0070] A P-type body region 3, which is P-type medium doped and located in the surface of the epitaxial layer below both sides of the gate 7;

[0071] P-type heavily doped region 4, the P-type heavily doped region 4 is P-type heavily doped, located in the epitaxial layer on both sides of the low channel resistance SiCVDMOSFET device cell, and connected to the P-type body region 3;

[0072] N-type source region 5, which is heavily N-type doped and located in the P-type body region 3 below both sides of the gate 7 and surrounded by the P-type body region 3 and the P-type heavily doped region 4;

[0073] A gate dielectric layer 6, which is a SiO2 layer and is located on the surface of the epitaxial layer of the SiC substrate 1 between the two N-type source regions 5;

[0074] a gate 7, the gate 7 being made of polysilicon and located on the surface of the gate dielectric layer 6;

[0075] a field passivation layer 8, the field passivation layer 8 covering the surface and side surfaces of the gate 7 and the gate dielectric layer 6;

[0076] a source electrode 9 , the source electrode 9 being located on the surfaces of the field passivation layer 8 , the N-type source region 5 , and the P-type heavily doped region 4 ;

[0077] The drain electrode 10 is located on the other side (back side) of the SiC substrate 1 .

[0078] The source electrode 9 and the drain electrode 10 are used to achieve electrical contact of the low channel resistance SiC VDMOSFET device;

[0079] The stacked channel region H1 is located in the primary conductive channel of the low-channel-resistance SiC VDMOSFET device. Specifically, the stacked channel region H1 is located inside the N-type source region 5 and above the P-type body region 3, and is composed of two stacked groups of P-type channel layers and N-type channel layers. The P-type channel layer of the stacked channel region H1 is in contact with the SiC / SiO2 interface.

[0080] The stacked channel region H1 of the low-channel resistance SiC VDMOSFET device disclosed in this embodiment is composed of two groups of P-type channel layers and N-type channel layers stacked in sequence, and contains four conductive channels. When the device is turned off, multiple conductive channels are depleted without forming a leakage path, and the device can maintain a low leakage current and remain normally off. When the device is turned on, multiple conductive channels will be turned on, maintaining a low leakage current while effectively reducing the on-resistance and thus reducing the conduction loss. Moreover, multiple channels can increase the effective channel depth, and the carriers inside them are away from the Coulomb scattering center at the interface (such as interface trapped charge) and are less scattered by surface roughness. That is, this feature effectively weakens the interference of major scattering mechanisms such as Coulomb scattering and surface roughness scattering on the channel carrier transport process, thereby significantly improving the carrier mobility in the channel.

[0081] Example 2

[0082] The second embodiment discloses a low channel resistance SiC VDMOSFET device. The difference from the first embodiment is that the low channel resistance SiC VDMOSFET device disclosed in the second embodiment is a PMOS device with a planar gate structure. Specifically, Figure 8 As shown, the low channel resistance SiC VDMOSFET device cell disclosed in this embodiment includes:

[0083] SiC substrate 1, wherein the SiC substrate 1 is a heavily P-type doped substrate;

[0084] A P-type drift region 2-1, which is provided in the epitaxial layer of the SiC substrate 1 and is lightly doped with P-type;

[0085] N-type body region 3 - 1 , which is N-type medium doped and located in the surface of the epitaxial layer below both sides of the gate 7 ;

[0086] N-type heavily doped regions 4-1, which are heavily N-doped and located in the epitaxial layer on both sides of the low channel resistance SiCVD MOSFET device cell and are connected to the N-type body region 3-1;

[0087] A P-type source region 5-1, which is heavily P-doped and located within the N-type body region 3-1 below both sides of the gate 7 and surrounded by the N-type body region 3-1 and the N-type heavily doped region 4-1;

[0088] A gate dielectric layer 6, which is a SiO2 layer and is located on the surface of the epitaxial layer of the SiC substrate 1 between the two P-type source regions 5-1;

[0089] a gate 7, the gate 7 being made of polysilicon and located on the surface of the gate dielectric layer 6;

[0090] a field passivation layer 8, the field passivation layer 8 covering the surface and side surfaces of the gate 7 and the gate dielectric layer 6;

[0091] a source electrode 9, the source electrode 9 being located on the surfaces of the field passivation layer 8, the P-type source region 5-1 and the N-type heavily doped region 4-1;

[0092] The drain electrode 10 is located on the other side (back side) of the SiC substrate 1 .

[0093] The source electrode 9 and the drain electrode 10 are used to achieve electrical contact of the low channel resistance SiC VDMOSFET device;

[0094] A stacked channel region H1 is located in the primary conductive channel of the low-channel-resistance SiC VDMOSFET device and is composed of two stacked groups of P-type channel layers and N-type channel layers. The N-type channel layer of the stacked channel region H1 is in contact with the SiC / SiO2 interface.

[0095] The low channel resistance SiC VDMOSFET device disclosed in this embodiment is a PMOS device, which is similar to the NMOS device disclosed in Example 1 in that when the device is turned off, multiple conductive channels are depleted and no leakage path is formed, and the device can maintain a low leakage current and remain normally off. When the device is turned on, multiple conductive channels will be turned on, maintaining low leakage current while effectively reducing the on-resistance and thus reducing conduction loss. Moreover, multiple channels can increase the effective channel depth, and the carriers inside them are away from the Coulomb scattering center at the interface (such as interface trapped charge) and are less scattered by surface roughness. That is, this feature effectively weakens the interference of major scattering mechanisms such as Coulomb scattering and surface roughness scattering on the channel carrier transport process, thereby significantly improving the carrier mobility in the channel. It can be seen that the stacked channel region disclosed in the present invention is also applicable to PMOS devices.

[0096] Example 3

[0097] Example 3 discloses another low channel resistance SiC VDMOSFET device. Figure 9 As shown, the low channel resistance SiC VDMOSFET device has a trench gate structure. Specifically, the gate 7 and gate dielectric layer 6 are both located in the trench between the two P-type body regions 3. The first direction of the stacked channel region H1 is parallel to the surface of the SiC substrate, and the second direction is perpendicular to the surface of the SiC substrate.

[0098] Example 4

[0099] The fourth embodiment discloses another low channel resistance SiC VDMOSFET device. Figure 10As shown, the low channel resistance SiC VDMOSFET device disclosed in this embodiment is an NMOS device with a fin gate structure. Specifically, part of the N-type drift region 2, the N-type source region 5, the P-type heavily doped region 4, the stacked channel region and the gate of the low channel resistance SiCVDMOSFET device all protrude from the surface of the SiC substrate to form a fin gate structure. The stacked channel region is composed of two groups of P-type channel layers and N-type channel layers stacked in sequence (surface inversion channel, first P-type channel layer 31, first N-type channel layer 61, second P-type channel layer 32, second N-type channel layer 62 in sequence), and the gate region is located above the channel (for easy observation, Figure 9 (The gate dielectric layer and gate structures are not shown). The first direction of the stacked channel region is perpendicular to the surface of the SiC substrate, and the second direction is parallel to the surface of the SiC substrate.

[0100] It should be noted that, in addition to the low-channel-resistance SiC VDMOSFET devices disclosed in Examples 1, 2, and 3, the low-channel-resistance SiC VDMOSFET devices may also have structures such as split-gate SGMOSFET and superjunction SJ-MOS (Superjunction MOSFET). The stacked channel region of the low-channel-resistance SiC VDMOSFET device is also suitable for lateral LD ​​MOSFETs (Lateral MOSFETs).

[0101] Example 5

[0102] Example 5 discloses a cell design of a low channel resistance SiC VDMOSFET device, based on two sets of stacked channel regions (surface inversion channel) low channel resistance SiC VDMOSFET devices made of strip cells. Figure 11 and Figure 12 As shown. Figure 11 The cross section formed by the A'-A'' section line is as follows Figure 7 shown.

[0103] Example 6

[0104] Example 6 discloses another cell design of a low channel resistance SiC VDMOSFET device, a low channel resistance SiC VDMOSFET device with two stacked channel regions (surface accumulation type channel) made of hexagonal cells. Figure 13 and Figure 14 As shown. Figure 13 The cross section formed by the B-A section line is as follows Figure 15 As shown, the doping concentration of the P-type channel layer in the surface accumulation type stacked channel region is 4×10 16 cm-3 ~6×10 17 cm -3 The improvement of the doping concentration range is due to the existence of a surface accumulation channel with a lower threshold voltage.

[0105] It should be noted that the design of the P-type heavily doped grounding cell can be diversified. Figures 11 to 14 While only the designs of the heavily P-type doped regions in stripe-shaped cells and hexagonal cells are shown, the shapes of the heavily P-type doped regions can be diverse. For example, in a stripe-shaped cell structure, the heavily P-type doped regions can be arranged in a quadrilateral, hexagonal, circular, quadrangular, triangular, or pentagonal shape, and are not specifically limited in this embodiment.

[0106] Example 7

[0107] The seventh embodiment discloses a method for manufacturing a low channel resistance SiC VDMOSFET device. The method disclosed in this embodiment uses an ion implantation process to form a stacked channel region of a low channel resistance SiC VDMOSFET device. Figure 16 The specific method is as follows:

[0108] Step S1: Prepare a silicon carbide epitaxial wafer, perform an N-type epitaxial growth to form a first epitaxial layer E1 (e.g. Figure 16 16a), the doping concentration is 8×10 15 cm -3 After the epitaxial layer growth is completed, RCA cleaning is performed to remove contamination and particles on the wafer surface.

[0109] Step S2: Perform the first mask growth etching, the oxide mask thickness is 2μm, photolithography, and perform the first stacked channel region implantation: the implantation type is P-type, Al ions are implanted, and the implantation energy is D1 (20kev-40kev) and D2 (40kev-200kev), forming the first P-type channel layer 31 (such as Figure 16 16b).

[0110] Step S3: Perform the second stacked channel region implantation: implant P-type, implant Al ions, implant energy D3 (200kev-300kev) and D4 (400kev-500kev), and form the second P-type channel layer 32 below the first P-type channel layer 31 (such as Figure 16 16c).

[0111] Step S4: P-type body region implantation: implantation is P-type, Al ions are implanted, and the implantation energy is D5 (500kev-600kev) and D6 (600kev-900kev), forming a P-type body region 3 below the stacked channel region (such as Figure 16 16d).

[0112] At this point, the doping of the stacked channel regions of two groups of P-type channel layers and N-type channel layers is completed. The doping of the first P-type channel layer 31 and the second P-type channel layer 32 is completed through steps S2 and S3. The N-type doped region between the first P-type channel layer 31 and the second P-type channel layer 32 is the first N-type channel layer 61; the N-type doped region between the second P-type channel layer 32 and the P-type body region 3 is the second N-type channel layer 62. The first P-type channel layer 31 and the first N-type channel layer 61 constitute a first group of P-type channel layers and N-type channel layers, and the second P-type channel layer 32 and the second N-type channel layer 62 constitute a second group of P-type channel layers and N-type channel layers.

[0113] It should be noted that although Figure 16 The colors of the first N-type channel layer 61 and the second N-type channel layer 62 are different from those of the first epitaxial layer E1. However, this difference is only to more clearly mark the positions of the first N-type channel layer 61 and the second N-type channel layer 62, and does not indicate a difference in doping type. In this embodiment, to reduce the number of implantations, additional N-type ions are not implanted to form the first N-type channel layer 61 and the second N-type channel layer 62. Instead, the first epitaxial layer E1 (which can also be considered an N-type drift region) is directly used as the N-type channel layer. This reduces costs and simplifies the process steps.

[0114] Step S5: Cleaning, performing the third mask growth, the oxide mask thickness is 1 μm, photolithography, N-type heavy source region implantation, the implantation type is N-type, and the doping concentration is 1×10 19 cm -3 , forming an N-type source region 5 (such as Figure 16 16e in );

[0115] Step S6: Cleaning, performing the fourth mask growth, the oxide mask thickness is 2μm, photolithography, P-type heavily doped region implantation, the implantation type is P-type, the doping concentration is 1×10 20 cm -3 , forming a P-type heavily doped region 4 (such as Figure 16 16f in );

[0116] Step S7: Perform activation annealing on all implants. The activation annealing temperature may be 1400° C.-1850° C., and the annealing time may be 30-60 minutes. Perform sacrificial oxidation and then clean the activated wafer.

[0117] Step S8: After cleaning, perform thermal oxidation growth on the wafer at an oxidation temperature between 1100°C and 1450°C to grow a gate dielectric layer 6 (SiO2 layer) with a thickness of 50±2nm. Perform N2O annealing on the gate dielectric layer 6 at an annealing temperature of 1200°C for 30 minutes (e.g. Figure 16 16g in it).

[0118] Step S9: deposit polysilicon and perform POCL3 annealing to dope P element into the polysilicon to form gate 7 (such as Figure 16 16h in the timer).

[0119] Step S10: Using low pressure chemical vapor deposition process, a field passivation layer 8 (such as Figure 16 16i in ).

[0120] Step S11: photolithography and etching to set polysilicon gate openings.

[0121] Step S12: Use magnetron sputtering process to sputter nickel metal, and anneal it in a rapid annealing device to complete the ohmic contact of the N-type source region, and then perform thick AL deposition on the front side to form the source electrode 9 (such as Figure 16 16j in the .

[0122] Step S13: Use magnetron sputtering process to sputter nickel on the back surface, perform laser annealing, and then perform thick metal TiNiAg deposition on the back surface to form the drain electrode 10 (such as Figure 16 16k in ).

[0123] Example 8

[0124] The eighth embodiment discloses another method for manufacturing a low channel resistance SiC VDMOSFET device. The method disclosed in this embodiment uses an ion implantation process and an epitaxial process to form a stacked channel region of a low channel resistance SiC VDMOSFET device. Figure 17 The specific method is as follows:

[0125] Step S1: Prepare a silicon carbide epitaxial wafer, grow a layer of N-type epitaxial, and form the first epitaxial layer E1 (such as Figure 17 17a), the doping concentration is 8×10 15 cm -3 , with a thickness of 9.6μm.

[0126] Step S2: Grow the second N-type epitaxial layer to form the second epitaxial layer E2 (such as Figure 17 17b), the doping concentration is 3×10 15 cm -3 , thickness 0.2μm.

[0127] Step S3: Grow the third N-type epitaxial layer to form the third epitaxial layer E3 (such as Figure 17 17c in the ), the doping concentration is 8×10 15 cm -3 After the epitaxial layer growth is completed, RCA cleaning is performed to remove contamination and particles on the wafer surface.

[0128] Step S4: Perform the first mask growth etching, the oxide mask thickness is 1μm, photolithography, and perform medium-doped P-type body region implantation, the implantation type is P-type, the implantation energy is C1 (energy range 20-40keV), C2 (energy range 40-200keV) and C3 (energy range 200-900keV), and control the formation of the first P-type channel layer 31 and the P-type body region 3.

[0129] like Figure 17 As shown in FIG17d , the first epitaxial layer above the first P-type channel layer 31 forms a first N-type channel layer 61; a portion of the P-type body region 3 below the second epitaxial layer forms a second P-type channel layer 32; and the second epitaxial layer is located between the first P-type channel layer 31 and the second P-type channel layer 32, forming a second N-type channel layer 62. That is, the first P-type channel layer 31 and the first N-type channel layer 61 constitute a first group of P-type and N-type channel layers, and the second P-type channel layer 32 and the second N-type channel layer 62 constitute a second group of P-type and N-type channel layers.

[0130] In this embodiment, in order to reduce the number of implantations and lower the cost, the second P-type channel layer 32 and the P-type body region 3 have the same doping concentration (actually an integrated structure).

[0131] It should be noted that in order to reduce the number and types of injections, Figure 17 In FIG17d , the second N-type channel layer 62 laterally penetrates the epitaxial layer of the SiC substrate. In fact, the second epitaxial layer E2 is directly selected as the N-type channel layer without the need for additional N-type ion injection, which can reduce costs and simplify process steps.

[0132] Step S5: Cleaning, performing the third mask growth, the oxide mask thickness is 1 μm, photolithography, N-type source region implantation, the implantation type is N-type, and the doping concentration is 1×10 19 cm -3 , forming an N-type source region 5 (such as Figure 17 17e in ).

[0133] Step S6: Cleaning, performing the fourth mask growth, the oxide mask thickness is 2μm, photolithography, P-type heavily doped region implantation, the implantation type is P-type, the doping concentration is 1×10 20 cm -3 , forming a P-type heavily doped region 4 (such as Figure 17 17f in ).

[0134] Step S7: Activation annealing is performed on all implants at a temperature of 1500° C. to 1850° C. for 30 to 60 minutes. The activated wafers are then sacrificially oxidized and cleaned.

[0135] Step S8: After cleaning, perform thermal oxidation growth on the wafer at an oxidation temperature between 1100°C and 1450°C to grow a gate dielectric layer 6 (SiO2 layer) with a thickness of 50±2nm. Perform N2O annealing on the gate dielectric layer 6 at an annealing temperature of 1200°C for 30 minutes (e.g. Figure 17 17g in it).

[0136] Step S9: deposit polysilicon and perform POCL3 annealing to dope P element into the polysilicon to form gate 7 (such as Figure 17 17h in the morning).

[0137] Step S10: Using low pressure chemical vapor deposition process, a field passivation layer 8 (such as Figure 17 17i in ).

[0138] Step S11: photolithography and etching to set polysilicon gate openings.

[0139] Step S12: Use magnetron sputtering process to sputter nickel metal, and anneal it in a rapid annealing device to complete the ohmic contact of the N-type source region, and then perform thick AL deposition on the front side to form the source electrode 9 (such as Figure 17 17j in ).

[0140] Step S13: Use magnetron sputtering process to sputter nickel on the back surface, perform laser annealing, and then perform thick metal TiNiAg deposition on the back surface to form the drain electrode 10 (such as Figure 17 17k in ).

[0141] It should be noted that the embodiments of the present invention are mainly described using an N-type low channel resistance SiC VDMOSFET device as an example, but the stacked channel region structure is not only applicable to N-type SiC VDMOSFET devices, but is also applicable to P-type SiCVDMOSFET devices (such as Example 2).

[0142] The technical features of the above-described embodiments may be combined in any manner. To simplify the description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as no contradiction exists between these combinations of technical features, they should be considered to be within the scope of this specification. The terms "first" and "second" are used for distinction only and do not limit the scope of the present invention.

[0143] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A low channel resistance SiC VDMOSFET device, characterized in that: The conductive channel of the low channel resistance SiC VDMOSFET device comprises: The stacked channel region is composed of n groups of P-type channel layers and N-type channel layers stacked in sequence, wherein n≥1.

2. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The stacked channel region is composed of 1 to 4 stacked groups of P-type channel layers and N-type channel layer groups.

3. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The P-type channel layer and the N-type channel layer group are sequentially formed into a P-type channel layer and an N-type channel layer along a first direction from the SiC / gate dielectric layer interface of the low channel resistance SiC VDMOSFET device.

4. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The P-type channel layer and the N-type channel layer group are sequentially composed of an N-type channel layer and a P-type channel layer along a first direction from the SiC / gate dielectric layer interface of the low channel resistance SiC VDMOSFET device.

5. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The doping range of the N-type channel layer and the P-type channel layer in the P-type channel layer and N-type channel layer group is 1×10 15 cm -3 ~4×10 18 cm -3 .

6. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The thickness of the P-type channel layer and the N-type channel layer in the P-type channel layer and the N-type channel layer group along the first direction is 0.05 μm to 0.25 μm.

7. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The depth of the stacked channel region from the SiC / gate dielectric layer interface of the low channel resistance SiC VDMOSFET device along the first direction is 0.2 μm to 1.2 μm, and the length of the stacked channel region along the second direction is 0.2 μm to 5 μm.

8. The low channel resistance SiC VDMOSFET device according to claim 1, characterized in that: The low channel resistance SiC VDMOSFET device is a planar gate device, a trench gate device, a fin gate device, a split gate device or a super junction device.

9. A method for manufacturing a low channel resistance SiC VDMOSFET device, characterized in that: The stacked channel region of the low channel resistance SiC VDMOSFET device is formed by ion implantation process.

10. A method for manufacturing a low channel resistance SiC VDMOSFET device, characterized in that: The stacked channel region of the low channel resistance SiC VDMOSFET device is formed by ion implantation and epitaxial growth.

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