Target power control scheme

Abstract

Various embodiments include systems and methods for controlling power in a computing device based on a number of frames per second (FPS) displayed on the computing device. A computing device may use a combination of power control and FPS control in a cascaded PID loop to enhance stability and / or performance of the device or software application. The cascaded PID loop may include a plurality of PID controllers that are hierarchically organized such that the output of one PID controller is used as the input (or setpoint) of a subsequent PID controller. This cascade configuration may improve control or performance by reducing variability, enhancing response to interference, and enabling more conservative tuning of external loops compared to a single loop control system.

Description

[0001] Related applications

[0002] This application is a continuation-in-part (CIP) of PCT international application No. PCT / CN2023 / 075371, filed on February 10, 2023, entitled “A Frames Per Second (FPS) Control Scheme”, the entire contents of which are hereby incorporated by reference for all purposes. Background Art

[0003] Resource-constrained computing devices such as smartphones are increasingly being used for video games or other animation applications. An important aspect of the user experience on these devices is the frames per second (FPS), which refers to the number of images (frames) displayed on the screen per second. A high FPS rate means that the game or animation runs smoothly, while a low FPS rate may result in a choppy or lagging experience. A stable FPS means that the rate at which frames are displayed on the screen is consistent and does not fluctuate frequently, which is important for providing a smooth and enjoyable gaming experience. For example, a game with a stable FPS rate of 60 will display 60 images on the screen per second. Summary of the Invention

[0004] Various aspects include a method of stabilizing a frames per second (FPS) displayed on a computing device, which may include applying a target FPS value and a current FPS value to a proportional-integral-derivative (PID) controller to generate a frequency adjustment value, and adjusting a processing frequency based on the frequency adjustment value.

[0005] Some aspects may include determining an updated current FPS value, determining whether the updated current FPS value is within a threshold range of a target FPS value; and repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to a PID controller to generate a frequency adjustment value, adjusting a processing frequency based on the frequency adjustment value, determining an updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value.

[0006] In some aspects, adjusting the processing frequency based on the frequency adjustment value may include setting a maximum frequency value and a minimum frequency value for the processing cluster. In some aspects, applying the target FPS value and the current FPS value to a PID controller to generate the frequency adjustment value may include determining an error value based on a difference between the current FPS value and the target FPS value, applying the error value to a proportional term, an integral term, and a derivative term to obtain an output control variable, and determining the frequency adjustment value based on the output control variable. In some aspects, determining the frequency adjustment value based on the output control variable may include determining a frequency adjustment value for each processing unit based on the output control variable and a load factor of each processing unit.

[0007] Some aspects may include determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value. Some aspects may also include repeatedly performing the following operations until the current FPS value is within a threshold range of the target FPS value: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0008] Other aspects include methods of controlling power in a computing device by controlling the number of frames per second (FPS) displayed on the computing device. In some aspects, the methods may include: applying a target power value and a current power value to a proportional-integral-derivative (PID) controller to generate a target FPS change (Δtarget FPS) value; adding the target FPS change (Δtarget FPS) value and the current target FPS value to generate an updated target FPS value as an input to an FPS controller that generates a current FPS as an output; and adjusting power based on the current FPS output by the FPS controller.

[0009] Some aspects may also include applying the updated target FPS and the current FPS value to a PID controller to generate a frequency adjustment value, and adjusting the processing frequency based on the frequency adjustment value.

[0010] Some aspects may also include: determining an updated current FPS value; determining whether the updated current FPS value is within a threshold range of a target FPS value; and repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to a PID controller to generate a frequency adjustment value, adjusting the processing frequency based on the frequency adjustment value, determining an updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value.

[0011] In some aspects, adjusting the processing frequency based on the frequency adjustment value may include setting a maximum frequency value and a minimum frequency value for the processing cluster.

[0012] In some aspects, applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value may include: determining an error value based on a difference between the current FPS value and the target FPS value; applying the error value to a proportional term, an integral term, and a derivative term to obtain an output control variable; and determining a frequency adjustment value for each processing unit based on the output control variable and a load factor of each processing unit.

[0013] Some aspects may further include determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0014] Some aspects may also include repeatedly performing the following operations until the current FPS value is within a threshold range of the target FPS value: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0015] Other aspects may include a computing device having a processor configured with processor-executable instructions for performing various operations corresponding to any of the methods described above.

[0016] Other aspects may include a non-transitory processor-readable storage medium having stored thereon processor-executable instructions configured to cause a processor to perform various operations corresponding to any of the methods described above.

[0017] Other aspects may include a computing device having means for performing functions corresponding to any of the methods described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the claims and, together with the general description and detailed description given, serve to explain the features herein.

[0019] Figures 1 to 3 is a component block diagram illustrating a computing system that may be configured to implement some embodiments.

[0020] Figure 4 is a process flow diagram illustrating an example proportional-integral-derivative (PID) method according to some embodiments.

[0021] Figure 5is a component block diagram illustrating a computing subsystem including a PID controller according to some embodiments.

[0022] Figure 6 is a component block diagram illustrating a computing subsystem including an enhanced PID controller including a frames per second (FPS) adjustment component that can be configured to stabilize FPS according to some embodiments.

[0023] Figures 7 to 12 is a process flow diagram illustrating a method of stabilizing an FPS according to some embodiments.

[0024] Figure 13 is a component block diagram illustrating an example computing device suitable for use with various embodiments.

[0025] Figure 14 is a component block diagram illustrating an example wireless communication device suitable for use with various embodiments.

[0026] Figure 15 An example wearable computing device in the form of smart glasses suitable for use with various embodiments is illustrated.

[0027] Figure 16A and Figure 16B is a component block diagram illustrating a computing subsystem including an enhanced PID controller and an FPS controller that may be configured to control power according to some embodiments.

[0028] Figures 17 to 20 is a process flow diagram illustrating a method of controlling power in a computing device based on an FPS displayed on the computing device according to some embodiments. DETAILED DESCRIPTION

[0029] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Reference to specific examples and specific implementations is for illustrative purposes and is not intended to limit the scope of protection of the claims.

[0030] In general, various embodiments include methods for stabilizing the frames per second (FPS) of video games or other animation applications operating on a computing device and computing devices configured to implement these methods. The computing device can be configured to determine a target FPS, determine a current FPS, and use a proportional integral derivative (PID) algorithm to determine a frequency adjustment value based on the target FPS and the current FPS. The computing device can use the frequency adjustment value to dynamically change their clock frequency or processing frequency based on the current workload and power consumption characteristics of one or more processors or resources in the device. The computing device can dynamically scale the processor frequency based on the difference between the target FPS and the current FPS so that the current FPS is within the target range without having a significant negative impact on the power consumption characteristics of the computing device.

[0031] In some embodiments, the computing device may be configured to determine an error value based on the difference between the target FPS value and the current FPS value, transmit the error value through the proportional term / gain, integral term / gain, and derivative term / gain of a PID controller to obtain an output control variable, and determine a frequency adjustment value based on the output control variable. The computing device may use the frequency adjustment value to adjust the maximum and minimum clock frequencies of processing units (e.g., a CPU cluster, etc.) in the computing device. In other words, the computing device may distribute the frequency adjustment value to various computing device subsystems (e.g., a cluster, etc.) based on the load rate.

[0032] According to various embodiments, allocating frequency adjustment values ​​and / or adjusting the maximum and minimum clock frequencies of processing units based on load ratios can improve the performance and functionality of a device by stabilizing FPS and balancing the tradeoff between performance and power consumption. Other improvements to the performance and functionality of computing devices will be apparent from the disclosure herein.

[0033] The term "computing device" may be used herein to refer to any or all of the following: a quantum computing device, an edge device, an Internet access gateway, a modem, a router, a network switch, a residential gateway, an access point, an integrated access device (IAD), a mobile convergence product, a networking adapter, a multiplexer, a personal computer, a laptop computer, a tablet computer, a user equipment (UE), a smartphone, a personal or mobile multimedia player, a personal data assistant (PDA), a handheld computer, a wireless email receiver, a multimedia Internet-enabled cellular telephone, a gaming system (e.g., a PlayStation 4), a gaming console, a tablet computer, a tablet computer, a 3.0-inch display, a 1.5-inch display, a 2.0-inch display, a 1.5-inch display, a 2.0-inch display, a 3 ... TM , Xbox TM 、Nintendo Switch TM etc.), wearable devices (e.g., smart glasses, head-mounted displays, fitness trackers, etc.), media players (e.g., DVD players, ROKU TM 、AppleTVTM etc.), digital video recorders (DVRs), automotive displays, portable projectors, 3D holographic displays, and other similar devices that include a display and a programmable processor that can be configured to provide the functionality of various embodiments.

[0034] The term "system on a chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip that includes multiple resources or independent processors integrated on a single substrate. A single SoC may include circuits for digital, analog, mixed-signal, and radio frequency functions. A single SoC may also include any number of general-purpose or specialized processors (e.g., network processors, digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.). For example, a SoC may include an application processor that operates as the main processor of the SoC, a central processing unit (CPU), a microprocessor unit (MPU), an arithmetic logic unit (ALU), etc. The SoC may also include software for controlling the integrated resources and processors and for controlling peripheral devices.

[0035] The term "system-in-package" (SIP) may be used herein to refer to a single module or package that contains multiple resources, computing units, cores, or processors on two or more IC chips, substrates, or SoCs. For example, a SIP may include a single substrate on which multiple IC chips or semiconductor dies are stacked in a vertical configuration. Similarly, a SIP may include one or more multi-chip modules (MCMs) on which multiple ICs or semiconductor dies are packaged into a unified substrate. A SIP may also include multiple independent SoCs coupled together via high-speed communication circuits and packaged in close proximity, such as on a single motherboard, in a single UE, or in a single CPU device. The proximity of the SoCs facilitates high-speed communication and the sharing of memory and resources.

[0036] The term "frames per second" (FPS) may be used herein to refer to the number of images (frames) displayed per second on an electronic screen of a computing device. FPS is an important feature of some software applications, such as gaming applications. For example, stable FPS can improve the overall gaming experience of many popular mobile games (e.g., Genshin Impact, etc.). Such applications may require heavy workloads, which may lead to thermal issues and unstable FPS. To ensure a smooth and enjoyable gaming experience, a computing device configured according to various embodiments can automatically adapt to the current workload and prevent thermal issues.

[0037] Various embodiments may be implemented on a variety of single-processor and multi-processor computer systems, including system-on-a-chip (SOC) or system-in-package (SIP). Figure 1An example computing system or SIP 100 architecture is illustrated that may be used in a mobile computing device implementing various embodiments.

[0038] Figure 1 The example SIP 100 illustrated in FIG includes two SOCs 102, 104, a clock 106, a voltage regulator 108, and a wireless transceiver 166. The first SOC 102 and the second SOC 104 can communicate via an interconnect / bus module 150. The various processors 110, 112, 114, 116, 118, 121, 122 can be interconnected to each other and to one or more memory elements 120, system components and resources 124, and a thermal management unit 132 via an interconnect / bus module 126. Similarly, the processor 152 can be interconnected to a power management unit 154, a millimeter wave transceiver 156, a memory 158, and various additional processors 160 via an interconnect / bus module 164. The interconnect / bus modules 126, 150, 164 can include arrays of reconfigurable logic gates and / or implement a bus architecture (e.g., CoreConnect, AMBA, etc.). Communications may be provided by advanced interconnects such as high-performance Network-on-Chip (NoC).

[0039] In some embodiments, the first SOC 102 can operate as a central processing unit (CPU) of a mobile computing device, which executes instructions of a software application by performing arithmetic, logic, control, and input / output (I / O) operations specified by the instructions. In some embodiments, the second SOC 104 can operate as a specialized processing unit. For example, the second SOC 104 can operate as a dedicated 5G processing unit responsible for managing high-capacity, high-speed (e.g., 5 Gbps, etc.) and / or ultra-high frequency short wavelength (e.g., 28 GHz millimeter wave spectrum, etc.) communications.

[0040] The first SOC 102 may include a digital signal processor (DSP) 110, a modem processor 112, a graphics processor 114, an application processor 116, one or more coprocessors 118 (e.g., vector coprocessors) connected to one or more of these processors, memory 120, a deep processing unit (DPU) 121, an artificial intelligence processor 122, system components and resources 124, an interconnect / bus module 126, one or more temperature sensors 130, a thermal management unit 132, and a thermal power envelope (TPE) component 134. The second SOC 104 may include a 5G modem processor 152, a power management unit 154, an interconnect / bus module 164, multiple mmWave transceivers 156, memory 158, and various additional processors 160, such as an application processor, a packet processor, and the like.

[0041] Each processor 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. For example, the first SOC 102 may include a processor that executes a first type of operating system (e.g., FreeBSD, LINUX, OS X, etc.) and a processor that executes a second type of operating system (e.g., MICROSOFT WINDOWS 10). In addition, any or all of the processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may be included as part of a processor cluster architecture (e.g., a synchronous processor cluster architecture, an asynchronous or heterogeneous processor cluster architecture, etc.).

[0042] Any or all of the processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may be operated as a CPU of a mobile computing device. In addition, any or all of the processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may be included in one or more CPU clusters as one or more nodes. A CPU cluster may be a group of interconnected nodes (e.g., processing cores, processors, SOCs, SIPs, computing devices, etc.) configured to work in a coordinated manner to perform computing tasks. Each node may run its own operating system and contain its own CPU, memory, and storage. Tasks assigned to a CPU cluster may be divided into smaller tasks that are distributed across the various nodes for processing. The nodes may work together to complete a task, with each node handling a portion of the computation. The results of the computations of each node may be combined to produce a final result. CPU clusters are particularly useful for tasks that can be parallelized and executed simultaneously. This allows a CPU cluster to complete tasks much faster than a single high-performance computer. Additionally, because CPU clusters are made up of multiple nodes, they are generally more reliable and less prone to failure than a single high-performance component.

[0043] In various embodiments, any or all of processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160 may be configured to stabilize frames per second (FPS) by repeatedly applying the target FPS value and the current FPS value to an enhanced PID controller to generate a frequency adjustment value, and using the frequency adjustment value to adjust or scale the processing frequency in SIP 100 until the current FPS value is within a threshold range of a target FPS value. Adjusting the processing frequency may include setting maximum and minimum frequency values ​​for any or all of the processors, nodes, or clusters discussed herein.

[0044] The first SOC 102 and the second SOC 104 may include various system components, resources, and custom circuits for managing sensor data, analog-to-digital conversion, wireless data transmission, and for performing other specialized operations, such as decoding data packets and processing encoded audio and video signals for presentation in a web browser. For example, the system components and resources 124 of the first SOC 102 may include power amplifiers, voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, memory controllers, system controllers, access ports, timers, and other similar components for supporting processors and software clients running on the mobile computing device. The system components and resources 124 may also include circuits for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, and the like.

[0045] The first SOC 102 and / or the second SOC 104 may also include an input / output module (not shown) for communicating with resources external to the SOC, such as a clock 106, a voltage regulator 108, and a wireless transceiver 166 (e.g., a cellular wireless transceiver, a Bluetooth transceiver, etc.). The resources external to the SOC (e.g., the clock 106, the voltage regulator 108, the wireless transceiver 166) may be shared by two or more of the internal SOC processors / cores.

[0046] In addition to the example SIP 100 discussed above, various embodiments may be implemented in a wide variety of computing systems that may include a single processor, multiple processors, multi-core processors, or any combination thereof.

[0047] Figure 2 An example SoC suitable for implementing various embodiments is illustrated. Figure 1 and Figure 2 , SoC200 (e.g., Figure 1The SoC 102, 104 in the embodiment may include various combinations of components, including any number and combination of processors 202 (e.g., application processor 116, graphics processor 114, etc.), L3 cache 216 (e.g., memory 120, etc.), system cache 218 (e.g., memory 120, etc.), and / or power controller 220.

[0048] Each processor 202 in the SOC 200 may include any number and combination of processing cores 204a, 204b, 204c, 206a, 206b, 206c, any or all of which may be included as one or more nodes in one or more CPU clusters. In addition, the processing cores 204a, 204b, 204c, 206a, 206b, 206c may be grouped together into processing core clusters 212, 214, any or all of which may be included as one or more nodes in one or more CPU clusters.

[0049] The processor 202 may include multiple homogeneous or heterogeneous processing cores 204a, 204b, 204c, 206a, 206b, 206c. A homogeneous multi-core processor may include multiple homogeneous processing cores. The processing cores 204a, 204b, 204c, 206a, 206b, 206c may be homogeneous in that the processing cores 204a, 204b, 204c, 206a, 206b, 206c of the multi-core processor 202 may be configured for the same purpose and have the same or similar performance characteristics (e.g., maximum and minimum frequency values, etc.). For example, the multi-core processor 202 may be a general-purpose processor, and the processing cores 204a, 204b, 204c, 206a, 206b, 206c may be homogeneous general-purpose processing cores. For another example, the multi-core processor 202 may be a graphics processor 112 or a DSP 110 , and the processing cores 204 a , 204 b , 204 c , 206 a , 206 b , and 206 c may be homogeneous graphics processing cores or digital signal processing cores, respectively.

[0050] A heterogeneous multi-core processor may include multiple heterogeneous processing cores. The processing cores 204a, 204b, 204c, 206a, 206b, 206c may be heterogeneous in that the processing cores 204a, 204b, 204c, 206a, 206b, 206c of the multi-core processor 202 may be configured for different purposes and / or have different performance characteristics. The heterogeneity of such heterogeneous processing cores may include different instruction set architectures, pipelines, operating frequencies, etc. An example of such heterogeneous processing cores may include a so-called "big.LITTLE" architecture, in which a slower, low-power processing core may be coupled with a more powerful and power-hungry processing core.

[0051] Generally speaking, processing core clusters 212, 214 may include homogeneous processing cores within each processing core cluster 212, 214. Processing core clusters 212, 214 may be homogeneous or heterogeneous with other processing core clusters 212, 214. For example, processing core clusters 212 and 214 may be homogeneous, having the same processing cores as each other. For another example, processing core clusters 212 and 214 may be heterogeneous, having different processing cores as each other.

[0052] The processor 202 may also include any number and combination of L2 caches 208a, 208b, 208c, 210a, 210b, 210c (e.g., Figure 1 100). For example, each processing core cluster 212, 214 and / or each processing core 204a, 204b, 204c, 206a, 206b, 206c may have a dedicated L2 cache 208a, 208b, 208c, 210a, 210b, 210c. Each L2 cache 208a, 208b, 208c, 210a, 210b, 210c may be designated for read and / or write access by a designated processing core cluster 212, 214 and / or processing core 204a, 204b, 204c, 206a, 206b, 206c. The L2 caches 208a, 208b, 208c, 210a, 210b, 210c may store data and / or instructions and make the stored data and / or instructions available to a designated processing core cluster 212, 214 and / or processing core 204a, 204b, 204c, 206a, 206b, 206c. The L2 caches 208a, 208b, 208c, 210a, 210b, 210c may include the L2 caches 208a, 208b, 208c, 210a, 210b, 210c as described herein. Figure 1 The memory 120 is described as a volatile memory.

[0053] The L3 cache 216 and the system cache 218 may be shared by the processing core clusters 212, 214 and / or the processing cores 204a, 204b, 204c, 206a, 206b, 206c and configured for read and / or write access by these processing core clusters and / or processing cores. The L3 cache 216 and the system cache 218 may store data and / or instructions and make the stored data and / or instructions available to the processing core clusters 212, 214 and / or the processing cores 204a, 204b, 204c, 206a, 206b, 206c. The L3 cache 216 and / or the system cache 218 may serve as a buffer for data and / or instructions input to and / or output from the processor 202. The L3 cache 216 and the system cache 218 may include a plurality of L3 caches as described herein. Figure 1 The memory 120 is described as a volatile memory.

[0054] Processor 202 may also include any number and combination of power controllers 220, such as one or more power management integrated circuits (PMICs). Power controllers 220 may be configured to control the amount of power provided to any number and combination of processing core clusters 212, 214 and / or processing cores 204a, 204b, 204c, 206a, 206b, 206c. The power provided to processing core clusters 212, 214 and / or processing cores 204a, 204b, 204c, 206a, 206b, 206c as controlled by power controllers 220 may be determined by the state of processing core clusters 212, 214 and / or processing cores 204a, 204b, 204c, 206a, 206b, 206c.

[0055] Figure 3 An example SoC suitable for implementing various embodiments is illustrated. Figures 1 to 3 , SoC 330 and / or CPU cluster 306 may include various components as described above (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 202, processing cores 204a, 204b, 204c, 206a, 206b, 206c, etc.). Some of these components and additional components may be subsystems of a computing device. SoC 330 may include various communication components that are configured to communicatively connect components in SoC 330 that can send, receive, and share data. The communication components may include a system hub 300, a protocol converter 308, and a system-on-chip network (NoC) 324. The communication components facilitate communication between subsystem components, such as between the processors in the CPU cluster 306 and various other subsystems (such as the camera subsystem 318, the video subsystem 320, the display subsystem 322, the application subsystem 332, the modem subsystem 334) and specialized processors (such as the graphics processor unit (GPU) 310, the image signal processor (ISP) 312, the accelerated processing unit (APU) 314 and other hardware accelerators).

[0056] ISP 312 may be a dedicated digital signal processor designed to process image data and produce high-quality images. APU 314 may be a single integrated chip that combines the functionality of a CPU and a GPU on a single die to improve performance and power efficiency. In some embodiments, any or all of GPU 310, modem ISP 312, and APU 314 may be included in one or more CPU clusters 306.

[0057] The communication components may facilitate communication between the subsystems 318, 320, 322, 332, 334 and the processing units 306, 310, 312, 314 and other components such as memory devices, including the system cache 302, random access memory (RAM) 328, and various memories included in the CPU cluster 306, such as the caches of the processors of the CPU cluster 306.

[0058] Various memory control devices, such as the system cache controller 304, the memory interface 316, and the memory controller 326, may be configured to control access to various memories (e.g., RAM 328) by the subsystems 318, 320, 322, 332, 334 and the processors 306, 310, 312, 314, and to implement operations on the various memories that may be requested by the subsystems 318, 320, 322, 332, 334 and the processors 306, 310, 312, 314.

[0059] The SoC 330 may be configured to repeatedly perform the following operations until the current FPS value is within a threshold range of the target FPS value: apply the target FPS value and the current FPS value to a PID controller to generate a frequency adjustment value, and use the frequency adjustment value to adjust or scale the processing frequency of any processing unit discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, etc.).

[0060] In this article Figure 3 The description of the SoC 330 and its various components illustrated in FIG is intended to be exemplary only and in no way limiting. Some of the components of the illustrated example SoC 330 may be variably configured, combined, and separated. Some of these components may be included in greater or fewer quantities in the SoC 330 and may be positioned and connected differently within the SoC, or separate from the SoC 330. Similarly, many other components (such as other memories, processors, subsystems, interfaces, and controllers) may be included in the SoC 330 and communicate with the system cache controller 304 to access the system cache 302.

[0061] Figure 4 A proportional-integral-derivative (PID) method 400 is illustrated that may be used in some embodiments. Figures 1 to 4, method 400 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600 and / or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing the functional method 400 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600 and / or components (e.g., PID controller 504, FPS adjustment component 602, etc.).

[0062] In block 402, the computing device may compare the current behavior of the system to the target behavior to generate an output proportional to the difference between the current state and the target state. The difference between the current state and the target state may be referred to as an "error." A proportionality constant (also referred to as a gain or gain factor "Kp") may be used to control how much the output will change for a given error.

[0063] In block 404, the computing device may accumulate the error value over time and generate an output proportional to the accumulated error value.The computing device may reduce the residual error by taking into account the accumulated past errors.

[0064] In block 406 , the computing device may anticipate future error values ​​based on the error value change rate and generate an output proportional to the error change rate. The computing device may reduce overshoot and oscillation by considering the error change rate.

[0065] In block 408 , the computing device may generate as output a weighted sum of the error value, the accumulated error value, and the expected future error values.

[0066] In some embodiments, a computing device may be equipped with an enhanced PID controller adapted to perform frequency control operations (e.g., adjusting the maximum and minimum clock frequencies of a processor) to stabilize the FPS. An important advantage of using a PID controller for frequency control is that it provides a closed-loop control system. Compared to an open-loop control system that only adjusts frequency without considering the current FPS state, the enhanced PID controller considers the current FPS during frequency adjustment. This can allow for a more accurate and responsive control system that maintains FPS stability and reduces power consumption.

[0067] Some embodiments can use a PID controller to introduce negative feedback into the system by repeatedly or continuously monitoring the current FPS state and adjusting the processor's clock frequency based on the current FPS state. If the FPS is too low, the clock frequency can be increased to improve performance. If the FPS is too high, the clock frequency can be reduced to reduce power consumption. Thus, embodiments can quickly and reliably return the FPS to the target FPS, maintain FPS stability, and improve the performance and power consumption characteristics of the computing device.

[0068] Figure 5 1 illustrates a computing subsystem 500 including a proportional-integral-derivative (PID) controller that can be configured to implement frequency control according to some embodiments. Figures 1 to 5 , the computing subsystem 500 may be included in a computing device and implemented by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.).

[0069] The computation subsystem 500 may include a summing component 502, a PID controller 504, and a plant / process component 506. The PID controller 504 may include a proportional term component 510, an integral term component 512, a derivative term component 514, and a PID controller output component 516.

[0070] The summing component 502 can be configured to add or sum the inverse of the setpoint (r(t)) and the feedback of the process variable (y(t)) output from the plant / process component 506 to generate an error value (e(t)=r(t)-y(t)) as an input to the PID controller 504. In some embodiments, the setpoint r(t) can be the target FPS and the process variable y(t) can be the current FPS.

[0071] The proportional term component 510 can be configured to compare the current FPS with the target FPS to generate an output proportional to the difference between the current FPS value and the target FPS value. The difference between the current FPS value and the target FPS value can be referred to as the error e(t). In some embodiments, a proportionality constant (also referred to as a gain) can be used to control how much the output will change for a given error.

[0072] The integral term component 512 can be configured to accumulate the error (the difference between the target FPS and the current FPS) over time. The integral term component 512 can reduce the residual error by taking into account the accumulated past error. The integral term component 512 can generate an output proportional to the error accumulated over time.

[0073] The derivative component 514 can be configured to predict future error values ​​based on the rate of change of the error. The derivative component 514 can reduce overshoot and oscillation by considering the rate of change of the error. The derivative component 514 can generate an output proportional to the rate of change of the error.

[0074] The PID controller output component 516 can be configured to generate a weighted sum of the outputs generated by the proportional term component 510, the integral term component 512, and the derivative term component 514 to generate a control variable u(t). In some embodiments, the control variable u(t) can be a frequency change value (Δfreq).

[0075] The plant / process component 506 can be configured to generate a process variable (PV) PV=y(t): e(t)=r(t)-y(t) based on the control variable u(t), which can be fed back as an input to the PID controller 504. Thus, the computing subsystem 500 can operate as a control loop mechanism that utilizes feedback to continuously adjust and control the processor clock frequency and current FPS. The computing subsystem 500 can continuously or repeatedly calculate an error value e(t) as the difference between the target set point SP=r(t) and the measured process variable PV=y(t): e(t)=r(t)-y(t), and apply corrections based on the proportional, integral, and derivative terms. The computing subsystem 500 can minimize the error over time by adjusting the control variable u(t) to a new value determined by the weighted sum of the outputs of the proportional, integral, and derivative terms.

[0076] Figure 6 FIGURE 6 illustrates a computing subsystem 600 including an enhanced PID controller including an FPS adjustment component that can be configured to implement frequency control according to some embodiments. Figures 1 to 6 , the computing subsystem 600 may be included in a computing device and implemented by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.).

[0077] System 600 may include a summation component 502, a PID controller 504, and an FPS adjustment component 602. The FPS adjustment component may include a load factor component 604, an FPS adjustment summation component 606, a CPU frequency component 608, and an FPS generator component 610. The set point r(t) may be a target FPS, the process variable y(t) may be a current FPS, the error value e(t) may be a difference (Δfps) between the target FPS and the current FPS, and the output control variable u(t) may be a frequency change (Δfreq).

[0078] The computing subsystem 600 may receive a target FPS value as input and generate a current FPS value as output. The target FPS value may represent the desired FPS under current application conditions or configurations. The current FPS value may represent the actual measured FPS of the application. The computing subsystem 600 may adjust the frequency of the processing unit associated with the application (e.g., game, video, animation, etc.) based on the difference (Δfps) between the target FPS and the current FPS.

[0079] The summation component 502 may receive a target FPS value and a current FPS value as inputs and generate an error signal value (e(t)) as output based on the difference (Δfps) between the target FPS value and the current FPS value. The PID controller 504 may receive an error signal value (e(t)=Δfps) as input and generate a control variable (u(t)) based on a frequency change (Δfreq).

[0080] The load rate component 604 can be configured to determine a load rate value (or current workload value) based on a current workload and capability of a processing unit (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.) in the computing system or associated with an application. In some embodiments, the load rate component 604 can determine the load rate value based on a CPU utilization and capacity ratio mapping information structure, a normalized capacity ratio mapping information structure, and / or a frequency-capacity ratio normalized mapping information structure.

[0081] The load factor component 604 can receive an output control variable (u(t))=Δfreq) as an input and generate an output based on the output control variable and the load factor value. The load factor component 604 can also transmit the output control variable (u(t))=Δfreq) to the processor / cluster. As a result, each processing unit can have a new updated frequency value (e.g., updated_freq[cluster_id]=Δfreq[cluster_id]+current_freq[cluster_id]).

[0082] The FPS adjustment summation component 606 can sum the output of the load rate component 604 with a performance value (e.g., a frequency adjustment value, etc.) determined based on the output control variable (u(t)). The FPS adjustment summation component 606 can output the summation result as an updated frequency value to the CPUFreq component 608.

[0083] The CPUFreq component 608 can be included in the kernel and configured to adjust the frequency of the processing unit based on the updated frequency value received from the FPS adjustment summation component 606. In some embodiments, the CPUFreq component 608 can be configured to adjust the frequency of each processing cluster or CPU cluster, rather than the frequency of each individual processor. For example, the CPUFreq component 608 can update the frequency of the processing core cluster 212, 214 or CPU cluster 306 by setting the maximum and minimum values ​​of updated_freq[cluster_id]. This can be particularly beneficial in homogeneous processing core clusters or in systems where processors or CPU groups share the same properties (e.g., frequency points).

[0084] As mentioned above, the CPUFreq component 608 can be configured to adjust the frequency of the processing unit. Such frequency changes can affect future or current FPS generation. Therefore, the CPUFreq component 608 can provide feedback 612 to the FPS adjustment summation component 606. The FPS adjustment summation component 606 can use the feedback 612 to repeatedly or continuously generate new updated frequency values, which are transmitted to the CPUFreq component 608. The CPUFreq component 608 can provide the performance value (frequency adjustment value) to the FPS generator component 610.

[0085] The FPS generator component 610 can receive as input the performance value from the CPUFreq component 608. The FPS generator component 610 can adjust the current FPS based on the received performance value.

[0086] The computing subsystem 600 can utilize negative feedback 614 to stabilize the FPS and quickly and smoothly return the FPS to the target FPS value in the event of a "stutter," or temporary glitches or interruptions in the smoothness of the video or animation, which would otherwise negatively impact the user experience. Stuttering can occur when the application's frame rate drops below its target value, causing a noticeable interruption in the smoothness of the motion. Stuttering can be caused by various factors or conditions, such as insufficient processing power or excessive system load.

[0087] Figure 7 Illustrated is a method 700 of adjusting a frame rate in a computing device according to some embodiments. Figures 1 to 7 , method 700 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600 and / or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing the functional method 700 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600 and / or components (e.g., PID controller 504, FPS adjustment component 602, etc.).

[0088] In block 702, the computing device may determine a target FPS (e.g., 90 fps). The target FPS value may represent the FPS required under current application conditions or configurations. The computing device may determine the target FPS based on any of a variety of factors, including application type, graphics quality, hardware specifications, and / or user preferences. Generally speaking, a target frame rate of 30 to 60 frames per second (fps) is considered stable and provides a smooth application (game, etc.) experience. However, modern mobile games (e.g., Genshin Impact, etc.) may require much higher frame rates (e.g., 80 to 100 fps, etc.).

[0089] In block 704, the computing device may determine a current FPS. Generally speaking, the number of individual images (frames) displayed per second, or the current FPS, may differ from the target FPS for a variety of reasons, including hardware performance, graphics settings, background processes, game or application design, and network lag. The computing device may determine the current FPS by measuring the time it takes to render each frame and / or measuring the number of frames actually displayed in one second.

[0090] In determination block 706, the computing device may determine whether the current FPS is within a target FPS range (e.g., 89.4 fps to 92 fps). For example, the computing device may determine whether the difference between the current FPS value and the target FPS value exceeds a threshold value (e.g., 0.5 fps, 1 fps, 2.6 fps, etc.). In some embodiments, the computing device may determine whether the current FPS is within the range by comparing the current FPS to a minimum FPS value and / or a maximum FPS value for an application (e.g., a gaming application, etc.).

[0091] In response to determining that the current FPS is within the range (i.e., determination block 706 = "Yes"), the computing device may disable the PID controller in block 708. For example, in some embodiments, the computing device may disable the PID controller 504 and the FPS adjustment component 602 in response to determining that the difference between the current FPS value and the target FPS value does not exceed a threshold value (or is within a target range, etc.).

[0092] In response to determining that the current FPS value is not within the range (i.e., determination block 706 = "No"), the computing device may enable the PID controller in block 710. For example, in some embodiments, the computing device may enable the PID controller 504 and the FPS adjustment component 602 in response to determining that the difference between the current FPS value and the target FPS value exceeds a threshold.

[0093] Figure 8 Illustrated is a method 800 of adjusting FPS in a computing device according to some embodiments. Figures 1 to 8, method 800 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600 and / or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing the functional method 800 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600 and / or components (e.g., PID controller 504, FPS adjustment component 602, etc.).

[0094] In blocks 702 and 704, the computing device may perform the operations described in the same numbered blocks of method 700. For example, the computing device may determine the target FPS in block 702 and the current FPS in block 704. In determination block 802, the computing device may determine whether the current FPS is stable. In some embodiments, the computing device may determine whether the current FPS is stable by determining whether the current FPS is within the target FPS range or by determining whether the difference between the current FPS value and the target FPS value exceeds a threshold. In some embodiments, the computing device may calculate a standard deviation value, which measures how much the current FPS differs from the average FPS over a period of time. In some embodiments, the computing device may determine whether the current FPS is stable based on the standard deviation value. For example, a low standard deviation value may indicate that the FPS is consistent and stable, while a high standard deviation value may indicate that the FPS is fluctuating and unstable. In some embodiments, the computing device may determine whether the current FPS is stable based on a combination of the standard deviation value and a threshold FPS value.

[0095] In response to determining that the current FPS is stable (ie, determination block 802 = "Yes"), the computing device may perform a negative frequency boost operation in block 804. The negative frequency boost operation may include lowering the frequency of the processing unit to reduce heat generation and / or improve energy consumption characteristics of the device.

[0096] In response to determining that the current FPS is unstable (i.e., determination block 802 = "No"), the computing device may update the PID output in block 806. For example, the PID controller 504 of the computing device may generate an output control variable based on a frequency change (Δfreq) or difference between the target FPS and the measured current FPS. As another example, the computing device may determine an error value based on the difference between the current FPS and the target FPS, apply the error value to a proportional term / gain, an integral term / gain, and a derivative term / gain to obtain an output control variable, determine a frequency adjustment value based on the output control variable, and use the frequency adjustment value to adjust or scale the processing frequency in the computing device to change the current FPS.

[0097] In block 808, the computing device may determine a cluster load factor and assign a frequency change value to the cluster. For example, the computing device may determine the processing unit workload and capacity (or a normalized frequency-to-capacity ratio mapping, etc.) and determine the cluster load factor based on the current workload and capacity. As another example, the computing device's load factor component 604 may receive an output control variable as input, generate a load factor value, and update the clock or operating frequency of the processing unit (e.g., CPU cluster 306, etc.) based on the load factor value. The computing device's FPS adjustment summation component 606 may sum the load factor value and the performance value (e.g., the frequency adjustment value) to generate an updated frequency value.

[0098] In block 810, the computing device may add the allocated frequency change to each processing unit in one or more clusters. For example, the CPUFreq component 608 of the computing device may transmit the updated frequency value to one or more CPU clusters in the CPU clusters 306, and each of the CPU clusters may use the allocated frequency change to adjust the operating frequency of any or all of its corresponding processing units (e.g., any or all of the processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, etc.).

[0099] In block 812, the computing device may update the frequency in the processor / cluster. For example, the CPUFreq component 608 may set new minimum and maximum processing unit frequency values ​​on the CPU cluster 306 based on the updated frequency value to adjust the frequency of the processing units. The computing device may continuously or repeatedly perform the operations in blocks 704 to 812 to maintain a stable FPS.

[0100] Figure 9 Illustrated is a method 900 of adjusting FPS in a computing device according to some embodiments. Figures 1 to 9, method 900 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing the functional method 900 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.). Although some of the examples below are discussed with reference to clusters (e.g., CPU clusters, etc.), it should be understood that the operations may be performed on any processing unit, subsystem, or component discussed in this application.

[0101] In blocks 702 and 704, the computing device may perform operations as described for the same numbered blocks of method 700. For example, the computing device may determine a target FPS in block 702 and a current FPS in block 704. In block 902, the computing device may determine whether the current FPS is greater than a threshold FPS. For example, the computing device may call a comparison function or determine whether the difference between the current FPS value and the threshold FPS is zero, a value greater than zero, etc.

[0102] In response to determining that the current FPS is not greater than the threshold FPS (i.e., determination block 902 = "No"), the computing device may determine the current FPS in block 704. For example, when a gaming application is loading, the FPS is typically very low, but frequency control should not be triggered. Therefore, if the current FPS is not greater than the threshold FPS in determination block 902, the system does not trigger frequency control. Instead, the computing device waits until the current FPS exceeds the threshold FPS before initiating frequency control.

[0103] In response to determining that the current FPS is greater than the threshold FPS (i.e., determination block 902 = "Yes"), the computing device may update the cluster utilization in block 904. For example, the computing device may monitor and collect information about the current use of resources in the CPU cluster (e.g., CPU utilization, memory utilization, network utilization, etc.), cluster performance, workload, capacity, resource allocation, and perform other operations to ensure that the cluster is running efficiently and / or avoid overloading or underutilizing any of its components. In some embodiments, as part of the operations in block 902, the computing device may generate a CPU utilization and capacity ratio map, a normalized capacity ratio map, and / or a frequency-capacity ratio normalized map.

[0104] In some embodiments, the computing device may perform the operations in blocks 906 to 912 in parallel with any or all of the other operations (e.g., blocks 920 to 934). In block 906, the computing device may determine a cluster load rate. For example, the load rate component 604 may determine the cluster load rate (e.g., a load rate value, etc.) based on the current workload and capabilities of the processors / clusters in the computing system. For another example, the load rate component 604 may determine the cluster load rate based on a CPU utilization and capacity ratio map, a normalized capacity ratio map, and / or a frequency-capacity ratio normalized map.

[0105] In block 908, the computing device may transmit or distribute the PID output to each processing unit. For example, in block 908, the computing device may distribute frequency adjustment values ​​to each processing unit (e.g., CPU cluster 306, etc.) based on the load ratio. By distributing frequency adjustment values ​​based on the load ratio, the computing device may allow the processing units to adjust the maximum and minimum processing frequencies to stabilize the FPS and balance the tradeoff between performance and power consumption.

[0106] In block 910 , the computing device may update the frequencies of the associated processing units. For example, the computing device may adjust the maximum and minimum processing frequencies of the processing units in each CPU cluster 306 to stabilize the FPS and balance the tradeoff between performance and power consumption.

[0107] In determination block 912 , the computing device may determine whether the current processing unit is the last cluster to be evaluated or updated. For example, the system may include multiple CPU clusters 306 , and the operations of method 900 may be performed for each CPU cluster 306 .

[0108] In response to determining that the current cluster is the last cluster to be evaluated or updated (i.e., determination block 912 = "Yes"), the computing device may determine the current FPS in block 704. The current FPS is the current frame rate of the application operating on the computing device. The computing device may determine the current FPS by measuring the number of frames rendered within a specific time interval (e.g., 1 second).

[0109] In response to determining that the current cluster is not the last cluster to be evaluated or updated (i.e., determination block 912 = "No"), the computing device may update the frequency in the next cluster in block 910. The computing device may perform the operations in blocks 910 and 912 until all clusters or processing units associated with the application in the system have been updated.

[0110] In block 920, the computing device may detect a target FPS. The target FPS value may represent the desired FPS under current application conditions or configurations. The computing device may determine the target FPS based on any of a variety of factors, including application type, graphics quality, hardware specifications, and / or user preferences.

[0111] In block 922, the computing device may determine a standard deviation value. For example, the computing device may calculate a standard deviation value that measures how much the current FPS varies from the average FPS over a period of time. The computing device may calculate the standard deviation value by calculating the difference between the current FPS value and the average FPS value over the period of time, summing the squares of these differences, dividing by the number of data points, and finding the square root to generate a value that represents the deviation from the average FPS value and indicates the degree of variation in the FPS readings.

[0112] In determination block 924, the computing device may determine whether the standard deviation value is greater than a threshold value. In some embodiments, the computing device may determine whether the current FPS value is stable based on whether the standard deviation value is greater than the threshold value. In some embodiments, the computing device may determine whether the current FPS value is stable by determining whether the current FPS value is within a range of a target FPS value or by determining whether the difference between the current FPS value and the target FPS value exceeds a threshold value. In some embodiments, the computing device may determine whether the current FPS value is stable based on a combination of the standard deviation value and a threshold FPS value.

[0113] In response to determining that the standard deviation value is greater than the threshold (i.e., determination block 924 = "Yes"), the computing device may determine the current FPS value in block 704. The computing device may determine the current FPS value by measuring the number of frames rendered within a particular time interval (e.g., 1 second).

[0114] In response to determining that the standard deviation value is greater than the threshold value (i.e., determination block 924 = "No"), the computing device may determine whether the current FPS value is within a threshold range in determination block 926. For example, the computing device may compare the current FPS value to a predefined threshold range to determine whether the current FPS value falls within the range. The computing device may determine the threshold range based on various factors, such as hardware specifications, target performance level, or user preferences.

[0115] In response to determining that the current FPS value is not within the threshold range (i.e., determination block 926 = "No"), the computing device may update the PID output in block 928 and then continue to perform operations in blocks 906 through 912. For example, the computing device may determine an error value based on the difference between the current FPS value and the target FPS value, apply the error value to the proportional term / gain, the integral term / gain, and the derivative term / gain to obtain an output control variable, determine a frequency adjustment value based on the output control variable, and use the frequency adjustment value to adjust or scale the processing frequency in the computing device to change the current FPS value.

[0116] In response to determining that the current FPS is within the threshold range (i.e., determination block 926 = "Yes"), the computing device may determine whether the average frequency is within the bottom of the current frequency range in determination block 930. For example, the computing device may calculate the average frequency over a period of time and compare the average frequency to a predetermined value that identifies the bottom of the current frequency range.

[0117] In response to determining that the average frequency is not within the bottom of the current frequency range (i.e., determination block 930 = "Yes"), the computing device may determine a current FPS value in block 704. The computing device may determine the current FPS value by measuring the number of frames rendered within a particular time interval (e.g., 1 second).

[0118] In response to determining that the average frequency is within the bottom of the current frequency range (ie, determination block 930 = "Yes"), the computing device may perform a negative frequency boost in block 932. The negative frequency boost operation may reduce the frequency of the processing unit to reduce power consumption.

[0119] In determination block 934 , the computing device may determine whether the current cluster is the last cluster to be evaluated or updated. For example, the system may include multiple CPU clusters 306 , and the operations of method 900 may be performed for each CPU cluster 306 .

[0120] In response to determining that the current cluster is the last cluster to be evaluated or updated (i.e., determination block 934 = "Yes"), the computing device may determine the current FPS value in block 704. The computing device may determine the current FPS value by measuring the number of frames rendered within a particular time interval (e.g., 1 second).

[0121] In response to determining that the current cluster is the last cluster to be evaluated or updated (i.e., determination block 934 = "Yes"), the computing device may determine the current FPS value in block 704. The computing device may determine the current FPS value by measuring the number of frames rendered within a particular time interval (e.g., 1 second).

[0122] In response to determining that the current cluster is not the last cluster to be evaluated or updated (i.e., determination block 934 = "No"), the computing device may perform the operations in blocks 930 through 934 until all clusters in the system within the bottom of the current frequency range have been subjected to a negative frequency boost. The negative frequency boost operation may reduce the operating frequency of the processing unit to save power.

[0123] Figure 10 Illustrated is a method 1000 for stabilizing the FPS displayed on a computing device according to some embodiments. Figures 1 to 10 , method 1000 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing functional method 1000 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.).

[0124] In block 1002, the computing device may apply the target FPS value and the current FPS value to a PID controller to generate a frequency adjustment value. In some embodiments, the computing device may generate the frequency adjustment value by determining an error value based on the difference between the current FPS value and the target FPS value, applying the error value to the proportional term component 510, the integral term component 512, and the derivative term component 514 to obtain an output control variable, and determining the frequency adjustment value based on the output control variable. In some embodiments, the computing device may be configured to generate the output control variable based on a weighted sum of the outputs generated by the proportional term component 510, the integral term component 512, and the derivative term component 514. In some embodiments, the output control variable may be a frequency change value (Δfreq).

[0125] In block 1004, the computing device may adjust the processing frequency based on the frequency adjustment value. In some embodiments, the computing device may determine the frequency adjustment value for each corresponding CPU cluster based on the output control variable and the load rate of each CPU cluster (e.g., CPU cluster 306, etc.). In some embodiments, the computing device may adjust the processing frequency based on the frequency adjustment value by setting maximum and minimum frequency values ​​of the processing units (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.).

[0126] Figure 11 Illustrated is a method 1100 for stabilizing the FPS displayed on a computing device according to some embodiments. Figures 1 to 11 , method 1100 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing the functional method 1100 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.).

[0127] In determination block 1102, the computing device may determine whether the current FPS value is within a threshold range of a target FPS value. For example, the computing device may compare the current FPS to a predefined threshold range value to determine whether the current FPS falls within the range. The computing device may determine the threshold range based on various factors, such as hardware specifications, target performance level, or user preferences.

[0128] In response to determining that the current FPS is not within the threshold range (i.e., determination block 1102 = "No"), the computing device may perform operations as described for the same numbered blocks of method 1000 in blocks 1002 and 1004. For example, the computing device may determine an error value based on the difference between the current FPS and the target FPS, apply the error value to the proportional term / gain, the integral term / gain, and the derivative term / gain to obtain an output control variable, determine a frequency adjustment value based on the output control variable, and use the frequency adjustment value to adjust or scale the processing frequency in the computing device to change the current FPS.

[0129] In response to determining that the current FPS is within the threshold range (i.e., determination block 1102 = "Yes") or after adjusting / scaling the processing frequency in the computing device to change the current FPS in block 1004, the computing device may determine or calculate an updated current FPS value that includes any changes to the FPS due to the adjustment or scaling of the processing frequency in block 1104. The computing device may repeatedly repeat the operations in blocks 1102, 1002, 1004, and 1104 to stabilize the FPS and ensure that the frame rate remains within a suitable range.

[0130] Figure 12 Illustrated is a method 1200 for stabilizing the FPS displayed on a computing device according to some embodiments. Figures 1 to 12 , method 1200 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.). The components for performing functional method 1200 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controller 504, FPS adjustment component 602, etc.).

[0131] In block 1002, the computing device may perform the operations of block 1002 of method 1000 as described. For example, the computing device may determine an error value based on a difference between a current FPS and a target FPS, apply the error value to a proportional term / gain, an integral term / gain, and a derivative term / gain to obtain an output control variable, and determine a frequency adjustment value based on the output control variable.

[0132] In block 1202, the computing device may determine an updated frequency adjustment value based on the output control variable, the frequency value of each CPU cluster, and the load rate of each CPU cluster. For example, the CPUFreq component 608 may adjust the frequency of the processing unit based on the frequency adjustment value, which may affect future or current FPS generation and / or the operation of other CPU clusters. The FPS adjustment summation component 606 may use feedback 612 from the CPUFreq component 608 to repeatedly or continuously generate new updated frequency values, which are transmitted to the CPUFreq component 608 for further updates on the same or different processing units or CPU clusters.

[0133] In block 1204, the computing device may adjust the processing frequency based on the updated frequency adjustment value. For example, the computing device may set the maximum and minimum frequency values ​​for CPU cluster 306 or any processing unit discussed herein (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, etc.). In some embodiments, the computing device may repeatedly perform the operations of determining the updated frequency adjustment value based on the output control variable, the frequency value of each CPU cluster, and the load rate of each CPU cluster in block 1202, and adjusting the processing frequency based on the updated frequency adjustment value in block 1204 until the current FPS value is within the threshold range of the target FPS value.

[0134] Various embodiments (including but not limited to the above reference Figures 1 to 12 The described embodiments) can be used in a variety of wireless devices and computing systems (including laptop computers 1300, an example of which is shown in FIG. Figure 13 Reference Figures 1 to 13, the laptop computer may include a processor 1302 coupled to a volatile memory 1304 and a disk drive 1306 of a large non-volatile memory such as flash memory. The processor 1302 may be any of the processing units discussed herein (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, SOC 102, SOC 104, etc.). The laptop computer 1300 may include a touchpad touch surface 1308 that serves as a pointing device for the computer and, therefore, may receive drag, scroll, and tap gestures. Additionally, the laptop computer 1300 may have one or more antennas 1310 for transmitting and receiving electromagnetic radiation, connectable to a wireless data link, and / or a cellular telephone transceiver 1312 coupled to the processor 1302. The computer 1300 may also include a BT transceiver 1314, a compact disk (CD) drive 1316, a keyboard 1318, and a display 1320 coupled to the processor 1302. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor (e.g., via a universal serial bus (USB) input), as is well known, which may also be used in conjunction with various embodiments.

[0135] Figure 14 is a component block diagram of a computing device 1400 suitable for use with various embodiments. Figures 1 to 14 , various embodiments may be implemented on a variety of computing devices 1400 (examples of which are Figure 14 The computing device 1400 may be implemented on a first SOC 102 coupled to a second SOC 104. The first and second SOCs 102, 104 may be coupled to an internal memory 1416, a display 1412, and a speaker 1414. The first and second SOCs 102, 104 may also be coupled to at least one subscriber identity module (SIM) 1440 and / or a SIM interface, which may store information supporting a first and second 5G NR subscription that supports services on a 5G non-standalone (NSA) network.

[0136] The computing device 1400 may include an antenna 1404 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless transceiver 166 coupled to one or more processors in the first SOC 102 and / or the second SOC 104. The computing device 1400 may also include a menu selection button or rocker switch 1420 for receiving user input.

[0137] The computing device 1400 also includes a sound coding / decoding (CODEC) circuit 1410 that digitizes the sound received from the microphone into data packets suitable for wireless transmission and decodes the received sound data packets to generate analog signals that are provided to the speaker to generate sound. In addition, one or more of the processor in the first circuit 102 and the second circuit 104, the wireless transceiver 166, and the CODEC 1410 may include a digital signal processor (DSP) circuit (not separately shown).

[0138] Various embodiments (including the above reference Figures 1 to 12 The embodiments discussed herein can be implemented in a variety of wearable devices (examples of which are Figure 15 (illustrated in the form of smart glasses 1500). Figures 1 to 15 , glasses 1500 can operate like conventional glasses, but with enhanced computer features and sensors, such as a built-in camera 1518 and a heads-up display or graphical features on or near the lenses 1516. Like any glasses, the smart glasses can include a frame 1502 coupled to temples 1504 that fit alongside the wearer's head and behind the ears. When nose pads 1506 on a nose bridge 1508 are placed on the wearer's nose, the frame 1502 can hold the lenses 1516 in place in front of the wearer's eyes.

[0139] In some embodiments, the glasses 1500 may include an image rendering device 1514 (e.g., an image projector) that may be embedded in one or both temples 1504 of the frame 1502 and configured to project an image onto an optical lens 1516. In some embodiments, the image rendering device 1514 may include a light emitting diode (LED) module, a light tunnel, a homogenizing lens, an optical display, a folding mirror, or other well-known projector or head-mounted display components. In some embodiments (e.g., those embodiments in which the image rendering device 1514 is not included or used), the optical lens 1516 may be or may include a perspective or partially perspective electronic display. In some embodiments, the optical lens 1516 includes an image generating element, such as a perspective organic light emitting diode (OLED) display element or a liquid crystal on silicon (LCOS) display element. In some embodiments, the optical lens 1516 may include independent left-eye and right-eye display elements. In some embodiments, the optical lens 1516 may include or operate as a light guide for delivering light from the display element to the wearer's eyes.

[0140] The glasses 1500 may include multiple external sensors that can be configured to obtain information about the wearer's movements and external conditions that can be used to sense images, sounds, muscle movements, and other phenomena that can be used to detect when the wearer interacts with the described virtual user interface. In some embodiments, the glasses 1500 may include a camera 1518 that is configured to image objects in front of the wearer in a still image or video stream that can be sent to another computing device for analysis. In some embodiments, the glasses 1500 may include a microphone 1510 that is positioned and configured to record sounds near the wearer. In some embodiments, multiple microphones may be positioned in different locations on the frame 1502, such as on the distal end of the temple 1504 near the chin to record the sound made when the user taps a selected object on their hand. In some embodiments, the glasses 1500 may include a pressure sensor (such as on the nose pad 1506) that is configured to sense facial movement to calibrate distance measurements.

[0141] The processing system 1512 may include any or all of the processing units discussed herein (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, etc.). The processing and communication SOCs 102, 104 may be coupled to internal sensors 1520, internal memory 1522, and communication circuitry 1524 coupled to one or more antennas 1526 for establishing a wireless data link with an external computing device (e.g., a remote server, etc.), such as via a Bluetooth or Wi-Fi link. The processing system 1512 may include a power source, such as a rechargeable battery 1530, coupled to the processing unit and external sensors on the frame 1502.

[0142] As discussed above, some embodiments may include methods and computing devices configured to stabilize the frames per second (FPS) characteristics of software applications on a computing device. These methods may include applying a target FPS value and a current FPS value to a proportional-integral-derivative (PID) controller to generate a frequency adjustment value, and adjusting a processing frequency based on the frequency adjustment value. In other words, these methods may include: determining a target FPS; determining a current FPS; finding a frequency adjustment value based on the target FPS and the current FPS using a proportional-integral-derivative (PID) control unit; and dynamically scaling a clock frequency or processing frequency of one or more processors or resources within the computing device based on the frequency adjustment value. By utilizing a PID component, these embodiments may ensure that the current FPS remains within a target range without significantly impacting the power consumption characteristics of the device.

[0143] Other embodiments may include methods and computing devices configured to control power in a computing device based on a stable FPS. These embodiments may include maintaining power within an appropriate range to extend device usage time, reduce heat, and / or improve the overall gaming experience. These embodiments may improve the power consumption characteristics of the device and / or further reduce FPS fluctuations with little or no user-perceivable impact on the performance of the device or software applications. Some embodiments may use a PID control component to automatically adjust the target FPS when the target power is high.

[0144] In some embodiments, the methods may include a processor obtaining a target power value (targetpower), determining a power difference value (Δpower) based on a difference between the target power value and a current power value, determining a target FPS change, generating an updated target FPS value based on the current target FPS and the target FPS change, determining a performance value, adjusting the current FPS based on the performance value, and adjusting the current power based on the current FPS. These operations may be performed repeatedly or continuously to stabilize or modulate the FPS and keep power consumption within acceptable thresholds while enhancing stability, power, and performance characteristics of the device or application.

[0145] Some embodiments may use a combination of power control and FPS control in a cascaded PID loop to further enhance the stability and / or performance of a device or software application. A cascaded PID loop may include multiple PID controllers organized hierarchically so that the output of one PID controller serves as the input (or set point) for a subsequent PID controller. Compared to a single-loop control system, this cascade configuration can improve control or performance by reducing variability, enhancing response to disturbances, and enabling more conservative tuning of the outer loop.

[0146] Figure 16A and Figure 16B 1 illustrates a power controller computing subsystem 1600 configured to control power using a cascaded PID loop according to some embodiments. Figures 1 to 16B , the power controller computing subsystem 1600 may be included in a computing device and implemented by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.).

[0147] exist Figure 16AIn the illustrated example, the power controller computation subsystem 1600 includes a PID controller 504a, an FPS stabilizer 1602, an FPS controller 1604, a device power 1606 component, a first setpoint summation component 1610, and a second setpoint summation component 1612. Figure 16B Components of the FPS controller 1604 are illustrated, and these components may include a summing component 502, a PID controller 504b, a load ratio (LR) component 604, an FPS adjustment summing component 606, a CPU frequency (CF) component 608, and an FPS generator (FG) component 610, any or all of which may be configured to perform the above-referenced Figure 5 and Figure 6 Any or all of the operations discussed. The device power 1606 component can be a power controller configured to stabilize power by adjusting the target FPS. The FPS controller 1604 can be configured to stabilize the FPS by adjusting the frequency. The PID controllers 504a and 504b can be combined into a cascaded PID control loop, where the FPS controller 1604 includes negative feedback 614 operating as an inner loop, and the power controller 1600 includes power feedback 1620 operating as an outer loop.

[0148] The computing subsystem 1600 may include cascaded proportional-integral-derivative (PID) control components that are particularly useful for software applications associated with heavy workloads, high power consumption, consistent or sustainable FPS, and / or power consumption limits. The cascaded PID control components may include two PID controllers 504a, 504b that are configured or arranged such that the output of a first PID controller 504a can be used as an input or set point for a second PID controller 504b.

[0149] The use of two PID controllers 504a, 504b cascaded according to the embodiment can provide several advantages, including reduced overall variability, more efficient response to disturbances, and more conservative outer loop tuning. Reduced overall variability can indicate that the faster inner loop (e.g., feedback 614) can react to disturbances faster or more quickly than the outer loop (e.g., feedback 1620), which can reduce the impact of disturbances and limit variability. In loops implementing a cascaded architecture, improved disturbance response can result in efficient response to disturbances. This is because the inner loop is not only faster than the outer loop, but also closer to the disturbance source, enabling more rapid correction of process disturbances. More cautious outer loop tuning can allow design engineers to fine-tune the outer loop to achieve more stable control.

[0150] exist Figure 16AIn the illustrated example, the first set point r(t) may be the target power, the first process variable y(t) may be the current power, the first error value e(t) may be the difference between the target power and the current power (Δpower), and the first output control variable u(t) may be the target FPS change (Δtarget FPS).

[0151] The PID controller 504a can receive an error signal value (e(t) = Δpower) as an input and generate an output control variable based on the target FPS change (Δtarget fps). The summing component 1608 can sum the output of the PID controller 504a (Δtarget FPS) and the output of the FPS stabilizer 1602 (current target FPS) to generate an updated target FPS value, which is input to the FPS controller 1604. The FPS controller 1604 can be configured to receive the updated target FPS value as an input and generate the current FPS as an output. The device power component 1606 can be configured to receive the current FPS as an input and adjust the power to generate a current power value (e.g., y(t)) as an output.

[0152] Thus, the computing subsystem 1600 may receive a target power value (e.g., r(t)) as input and generate a current power value (e.g., y(t)) as output. The target power value may represent the power required under current application conditions or configurations. The current power value may represent the actual measured power of the application. The computing subsystem 1600 may adjust the device power 1606 based on the current FPS.

[0153] refer to Figures 1 to 16B , the FPS controller 1604 can be configured to receive an updated target FPS value as input, determine the difference (Δfps) between the target FPS and the current FPS, and input the difference (Δfps) between the target FPS and the current FPS to the PID controller 504b. The PID controller 504b can determine the frequency change (Δfreq). The LR component 604 can receive the output (Δfreq) as input and generate an output based on the output of the PID controller 504b and the load factor value. The load factor component 604 can also transmit the output to the processor / cluster and / or perform the above referenced Figure 6 Any or all of the operations discussed.

[0154] The FPS adjustment summation component 606 can sum the output of the LR component 604 with a performance value (e.g., frequency adjustment value, etc.) determined based on the output (Δfreq). The FPS adjustment summation component 606 can output the summation result as an updated frequency value to the CF component 608. The CF component 608 can generate a performance value and / or perform the above-referenced Figure 6Any or all of the operations discussed above. The FPS generator component 610 may receive the performance value from the CF component 608 as input, adjust the current FPS based on the received performance value, and / or perform the operations described above with reference to Figure 6 Any or all of the operations discussed.

[0155] Figure 17 Illustrated is a method 1700 for adjusting power based on a current FPS in a computing device according to some embodiments. Figures 1 to 17 , method 1700 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controllers 504a, 504b, FPS adjustment component 602, FPS controller 1604, etc.). The components for performing functional method 1700 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controllers 504a, 504b, FPS adjustment component 602, FPS controller 1604, etc.).

[0156] In block 1702, the processor may obtain a target power value (target_power). In some embodiments, the target power value may identify a power level at which the computing device or software application is to operate. In some embodiments, the target power may be determined based on hardware capabilities, energy efficiency goals, performance requirements, etc. In some embodiments, the target power may be a predetermined value. In some embodiments, the target power may be identified or requested by a software application executing on the computing device. In some embodiments, the target power may be determined by the computing device as the power necessary to support the operating requirements of the software application executing on the computing device.

[0157] In block 1704, the processor may determine a power difference value (Δpower) based on the difference between the target power value and the current power value. The current power value may be a value representing the real-time power consumption of the device or application compared to the target power, which is the power level at which the computing device or software application should operate. Thus, the power difference value (Δpower) may identify how much the actual power usage of the computing device deviates from the expected or target power value. In some embodiments, the processor may determine the power difference value (Δpower) by subtracting the current power value from the obtained target power. A positive power difference value (Δpower) may indicate that the device is currently using less power than the target power and / or may indicate that there is room for performance improvement without exceeding the target power. A negative power difference value (Δpower) may indicate that the current power consumption exceeds the target power and / or that power reduction measures should be implemented to meet the set power target.

[0158] In block 1706, the processor may determine a target fps change (Δtarget fps). As discussed above, FPS is an important variable for software applications that quantifies the speed at which a computing device displays successive images or frames. A higher FPS is generally associated with smoother motion in the visual output, at the expense of higher power consumption. The target FPS value may be a frame rate that balances the tradeoff between performance and power consumption on the computing device. The processor may monitor the actual FPS over a specific period of time and compare the real-time actual FPS value with the target FPS to calculate a target fps change or difference (Δtarget FPS). Thus, the target fps value change (Δtarget FPS) may identify the difference between the target frame rate and the actual frame rate.

[0159] In block 1708, the processor may generate an updated target fps value based on the target fps value (Δtarget FPS) and the current target FPS (updated_targetFPS). As discussed above, the target fps value (Δtarget FPS) value may indicate the difference between the desired frame rate and the actual frame rate of the device or application. The current target FPS may be a predefined frame rate value that balances various trade-offs between performance and power consumption characteristics in a computing device. In some embodiments, the processor may calculate the current target FPS value (updated_target_FPS) to recalibrate the target FPS taking into account the real-time performance of the device or application. In some embodiments, the processor may determine whether the target fps value (Δtarget FPS) exceeds a threshold. The processor may determine that there is a significant difference between the actual FPS and the target FPS and / or may need to be adjusted in response to determining that the target fps value (Δtarget FPS) exceeds a threshold.

[0160] In blocks 802 through 812 , the processor may perform any or all of the operations of blocks 802 through 812 of method 800 as described.

[0161] In block 1710, the processor may use the performance value to adjust the current FPS (current_fps).For example, the processor may increase power consumption to improve performance or decrease power consumption to meet an energy efficiency target.

[0162] In block 1712, the processor may use the current FPS to adjust the current power (current_power). The processor may then repeat the operations in blocks 1704 through 1712 to stabilize or modulate the FPS, maintain power consumption within acceptable thresholds, and / or otherwise improve stability, power, and / or performance characteristics of the device or application.

[0163] Figure 18 A method 1800 is illustrated for managing FPS in a computing device to achieve stable performance while maintaining efficient power consumption. Figures 1 to 18 , method 1800 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controllers 504a, 504b, FPS adjustment component 602, FPS controller 1604, etc.). The components for performing functional method 1800 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controllers 504a, 504b, FPS adjustment component 602, FPS controller 1604, etc.).

[0164] In block 1804, the processor may obtain a current FPS or retrieve a current FPS value. The current FPS value may be the real-time frame rate at which the device or application is currently operating. The processor may determine the current FPS value by measuring the number of frames rendered within a specific time interval (e.g., 1 second).

[0165] In determination block 1806, the processor may determine whether the current FPS is greater than an FPS threshold. For example, the processor may compare the current FPS value to a predefined FPS threshold to determine whether the current FPS is greater than the FPS threshold. For another example, the computing device may invoke a comparison function or determine whether the difference between the current FPS value and the threshold FPS is zero, a value greater than zero, or the like.

[0166] In response to determining that the current FPS is not greater than the threshold (ie, determination block 1806 = "No"), the processor may return to block 1804 to determine an updated current FPS value.

[0167] In response to determining that the current FPS is greater than the threshold (i.e., determination block 1806 = "Yes"), the processor may update the cluster utilization in block 1808. That is, in block 1808, the processor may update the usage or utilization level of the processing cluster. In some embodiments, the processor may update the cluster utilization by monitoring and adjusting the distribution of computing tasks between different processing clusters within the computing device to more evenly balance the load, optimize power consumption, and / or maintain or improve system performance.

[0168] In block 1810, the processor may detect a target FPS. That is, the processor may identify a target FPS value, which may be a desired frame rate for balancing performance and power consumption characteristics on a device.

[0169] In block 1812, the processor may calculate the standard deviation of the FPS. For example, the processor may calculate the standard deviation of the FPS values ​​to assess the variability of the frame rate.

[0170] In determination block 1814, the processor may determine whether the standard deviation is greater than a predefined threshold. For example, the processor may compare the standard deviation calculated in block 1812 to a predefined threshold stored in memory.

[0171] In response to determining that the standard deviation is greater than the predefined threshold (determination block 1814 = "Yes"), the processor may obtain an updated current FPS in block 1804. In response to determining that the standard deviation is not greater than the predefined threshold (determination block 1814 = "No"), the processor may determine whether the current FPS is between a set of thresholds in determination block 1816. For example, in determination block 1816, the processor may check to determine whether the current FPS falls within a specific range defined by two thresholds.

[0172] In response to determining that the current FPS is between thresholds (e.g., determination box 1816 = "Yes"), the processor may update the PID output in box 1818, calculate the cluster load rate in box 1820, distribute the PID output over each cluster in box 1822, update the frequency in box 1824, and determine whether the current cluster is the last cluster in determination box 1826.

[0173] In response to determining that the current cluster is not the last cluster (i.e., determination block 1826 = "No"), the processor may update the frequency in block 1824. In response to determining that the current cluster is the last cluster (i.e., determination block 1826 = "Yes"), the processor may return to block 1804 to determine an updated current FPS value.

[0174] In response to determining that the current FPS is between the thresholds (eg, determination block 1816 =“No”), the processor may determine in determination block 1830 whether the cluster average frequency is at the bottom of the current range.

[0175] In response to determining that the cluster average frequency is not at the bottom of the current range (ie, determination block 1830 =“No”), the processor may determine an updated current FPS value in block 1804 .

[0176] In response to determining that the cluster average frequency is at the bottom of the current range (ie, determination block 1830 =“Yes”), the processor may perform a negative frequency boost in block 1832 .

[0177] In determination block 1834, the processor may determine whether the current cluster is the last cluster. In response to determining that the current cluster is not the last cluster (i.e., determination block 1834 = "No"), the processor may determine in determination block 1830 whether the cluster average frequency is at the bottom of the current range. The processor may perform the operations in blocks 1830 through 1834 until all clusters in the system that are within the bottom of the current frequency range have received a negative frequency boost. The negative frequency boost operation may reduce the operating frequency of the processing unit to save power.

[0178] In response to determining that the current cluster is the last cluster (ie, determination block 1834 = "Yes"), the processor may return to block 1804 to determine an updated current FPS value.

[0179] Figure 19 Another method 1900 for managing FPS in a computing device to achieve stable performance while maintaining efficient power consumption is illustrated. Figures 1 to 19, method 1900 may be performed in a computing device by any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controllers 504a, 504b, FPS adjustment component 602, FPS controller 1604, etc.). The components for performing functional method 1900 may include any or all of the processing units discussed in this application (e.g., processors 110, 112, 114, 116, 118, 121, 122, 121, 122, 152, 160, 306, 310, 312, 314, processing cores 204a, 204b, 204c, 206a, 206b, 206c, CPU cluster 306, etc.), computing subsystems 500, 600, or components (e.g., PID controllers 504a, 504b, FPS adjustment component 602, FPS controller 1604, etc.).

[0180] In block 1902, the processor may obtain or determine a current power value. The current power value may represent the actual measured power of the device or application.

[0181] In block 1804, the processor may obtain a current FPS or retrieve a current FPS value. The current FPS value may be the real-time frame rate at which the device or application is currently operating. The processor may determine the current FPS value by measuring the number of frames rendered within a specific time interval (e.g., 1 second).

[0182] In block 1906, the processor may evaluate the current target FPS. For example, the processor may retrieve the current target FPS value from memory or a register. This value may be set by the user or determined by the system based on hardware capabilities, performance requirements, or other factors. The processor may compare the current target FPS value with the actual or real-time FPS to determine whether the system is meeting its performance goals. The processor may also evaluate whether the current target FPS is achievable given the system's constraints. For example, the processor may evaluate the device's processing power, memory, graphics capabilities, and other factors that may affect FPS.

[0183] In determination block 1908 , the processor may determine whether the current power is less than the target power.

[0184] In response to determining that the current power is not less than the target power (i.e., determination block 1908 = "No"), the processor may update the PID output in block 1910. As discussed above, a PID controller is a control loop feedback mechanism widely used in control systems that calculates an error value as the difference between a desired set point and a measured process variable. A PID controller can reduce or minimize the error by adjusting the process control input.

[0185] In response to determining that the current power is not less than the target power (i.e., determination block 1908 = "Yes"), the processor may add a target fps value (Δtarget FPS) to the current target FPS (updated_target_FPS) in block 1912. As discussed above, the target fps value (Δtarget FPS) may indicate a difference between a desired frame rate and an actual frame rate for a device or application.

[0186] In blocks 1806 through 1834 , the processor may perform the operations of like numbered blocks of method 1800 as described.

[0187] Figure 20 Components, operations, and interactions in a system configured to manage FPS in a computing device to achieve stable performance while maintaining efficient power consumption are illustrated according to some embodiments. Figures 1 to 20 , in blocks 1902 through 1910 , a processor in the computing device may perform the operations of the like numbered blocks of method 1900 as described.

[0188] In block 1912, the processor may sum the output of the PID controller 504a (Δtarget FPS) and the output of the FPS stabilizer 1602 (current target FPS) to generate an updated target FPS value as input to the FPS controller 1604. In other words, in block 1912, the processor may add the target fps value (Δtarget FPS) to the current target FPS to generate an updated_target_FPS value.

[0189] The FPS controller 1604 may be configured to stabilize the FPS by adjusting the FPS frequency. The FPS controller 1604 may be configured to receive an updated target FPS value as input and generate a current FPS as output. The device power component 1606 may be configured to receive the current FPS as input and adjust the power to generate a current power value (e.g., y(t)) as output. As part of these operations, in block 2050, the processor may read the file node voltage_now_current_now. In block 2052, the processor may read or write to the file node and perform other similar operations.

[0190] The processor or processing unit discussed in this application can be any programmable microprocessor, microcomputer, or one or more multi-processor chips that can be configured to perform a variety of functions (including the functions of the various embodiments described) through software instructions (applications). In some computing devices, multiple processors may be provided, such as one processor dedicated to wireless communication functions within a first circuit and one processor dedicated to running other applications within a second circuit. Software applications can be stored in a memory and then accessed and loaded into the processor. The processor may include internal memory sufficient to store application software instructions.

[0191] Specific implementation examples are described in the following paragraphs. Although some of the following specific implementation examples are described in terms of example methods, further example implementations may include: the example methods discussed in the following paragraphs implemented by a computing device including a processor configured with processor-executable instructions for performing the operations of the methods of the following specific implementation examples; the example methods discussed in the following paragraphs implemented by a computing device including components for performing the functions of the methods of the following specific implementation examples; and the example methods discussed in the following paragraphs may be implemented on a non-transitory processor-readable storage medium having processor-executable instructions stored thereon, the processor-executable instructions being configured to cause the processor of the computing device to perform the operations of the methods of the following specific implementation examples.

[0192] Embodiment 1: A method for stabilizing the frames per second (FPS) displayed on a computing device, the method comprising: applying a target FPS value and a current FPS value to a proportional integral derivative (PID) controller to generate a frequency adjustment value, and adjusting a processing frequency based on the frequency adjustment value.

[0193] Example 2: According to the method described in Example 1, the method further includes: determining an updated current FPS value; determining whether the updated current FPS value is within a threshold range of the target FPS value; repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value, adjusting the processing frequency based on the frequency adjustment value, determining the updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value.

[0194] Embodiment 3: The method according to any one of embodiments 1 and 2, wherein adjusting the processing frequency based on the frequency adjustment value comprises: setting a maximum frequency value and a minimum frequency value of a processing cluster.

[0195] Example 4: A method according to any one of Examples 1 to 3, wherein applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value includes: determining an error value based on the difference between the current FPS value and the target FPS value; applying the error value to a proportional term, an integral term, and a differential term to obtain an output control variable; and determining the frequency adjustment value based on the output control variable.

[0196] Embodiment 5: The method according to embodiment 4, wherein determining the frequency adjustment value based on the output control variable comprises: determining the frequency adjustment value of each processing unit based on the output control variable and a load rate of each processing unit.

[0197] Example 6: According to the method described in any one of Examples 1 to 5, the method further includes: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0198] Example 7: According to the method described in any one of Example 6, the method further includes repeatedly performing the following operations until the current FPS value is within the threshold range of the target FPS value: determining the updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0199] Embodiment 8: A method for controlling power in a computing device based on the number of frames per second (FPS) displayed on the computing device, the method comprising: applying a target power value and a current power value to a proportional integral derivative (PID) controller to generate a target FPS change (Δtarget FPS) value; adding the target FPS change (Δtarget FPS) value and the current target FPS value to generate an updated target FPS value as an input to an FPS controller, the FPS controller generating a current FPS as an output; and adjusting the power based on the current FPS output by the FPS controller.

[0200] Embodiment 9: The method according to embodiment 8, further comprising: applying the updated target FPS and the current FPS value to the PID controller to generate a frequency adjustment value; and adjusting the processing frequency based on the frequency adjustment value.

[0201] Example 10: According to the method described in any one of Examples 8 or 9, the method further includes: determining an updated current FPS value; determining whether the updated current FPS value is within a threshold range of the target FPS value; and repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value, adjusting the processing frequency based on the frequency adjustment value, determining the updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value.

[0202] Embodiment 11: The method according to any one of embodiments 8 to 10, wherein adjusting the processing frequency based on the frequency adjustment value comprises: setting a maximum frequency value and a minimum frequency value of a processing cluster.

[0203] Example 12: A method according to any one of Examples 8 to 11, wherein applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value includes: determining an error value based on the difference between the current FPS value and the target FPS value; applying the error value to a proportional term, an integral term, and a differential term to obtain an output control variable; and determining the frequency adjustment value of each processing unit based on the output control variable and the load rate of each processing unit.

[0204] Example 13: According to the method described in any one of Examples 8 to 12, the method further includes: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0205] Example 14: According to the method described in any one of Examples 8 to 13, the method further includes repeatedly performing the following operations until the current FPS value is within the threshold range of the target FPS value: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

[0206] As used in this application, the terms "component", "module", "system", etc. are intended to include computer-related entities such as, but not limited to, hardware, firmware, a combination of hardware and software, software, or software being executed, which are configured to perform a specific operation or function. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, an execution thread, a program, and / or a computer. By way of example, both an application running on a computing device and a computing device can be referred to as a component. One or more components may reside within a process and / or execution thread, and a component may be located on a processor or core and / or distributed between two or more processors or cores. In addition, these components may be executed from various non-transitory computer-readable media having various instructions and / or data structures stored thereon. Components may communicate via local and / or remote processes, function or procedure calls, electronic signals, data packets, memory reads / writes, and other known network, computer, processor, and / or process-related communication methods.

[0207] The various embodiments illustrated and described are provided merely as examples illustrating various features of the claims. However, the features shown and described with respect to any given embodiment are not necessarily limited to that associated embodiment and may be used or combined with other embodiments shown and described. Furthermore, the claims are not intended to be limited to any one exemplary embodiment. For example, one or more operations of a method may be substituted for or combined with one or more operations of a method.

[0208] The foregoing method descriptions and process flow diagrams are provided as illustrative examples only and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of operations in the foregoing embodiments may be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of operations; these words are merely used to guide the reader in reading the description of the method. In addition, any reference to a claim element in the singular (e.g., a reference using the articles "a," "an," or "the") should not be construed as limiting the element to the singular.

[0209] The various illustrative logical blocks, modules, circuits, and algorithmic operations described in conjunction with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and operations have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Although a skilled person may implement the described functionality in different ways for each specific application, such specific implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0210] The hardware for implementing the various exemplary logics, logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Although a general-purpose processor may be a microprocessor, in an alternative embodiment, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuits specific to a given function.

[0211] In one or more embodiments, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions can be stored as one or more instructions or codes on a non-transient computer-readable medium or a non-transient processor-readable medium. The operation of the method or algorithm disclosed herein can be specifically embodied in a processor-executable software module, which can reside on a non-transient computer-readable or processor-readable storage medium. A non-transient computer-readable or processor-readable storage medium can be any storage medium that can be accessed by a computer or processor. By way of example and not limitation, such non-transient computer-readable or processor-readable media may include RAM, ROM, EEPROM, flash memory, CD-ROM or other optical disk storage, disk storage or other magnetic storage device, or any other medium that can be used to store target program code in the form of instructions or data structures and that can be accessed by a computer. Disks and optical disks as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and blue-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically with lasers. The above combinations are also included within the scope of non-transient computer-readable and processor-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and / or instructions on a non-transitory processor-readable medium and / or computer-readable medium, which may be incorporated into a computer program product.

[0212] The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments shown herein, but should be accorded the broadest scope consistent with the following claims and the principles and novel features disclosed herein.

Claims

1. A method of controlling power in a computing device based on frames per second (FPS) displayed on the computing device, the method comprising: Applying the target power value and the current power value to a proportional-integral-derivative (PID) controller to generate a target FPS change (Δtarget FPS) value; adding the target FPS change (Δtarget FPS) value to the current target FPS value to generate an updated target FPS value as input to an FPS controller, which generates the current FPS as output; as well as The power is adjusted based on the current FPS output by the FPS controller.

2. The method according to claim 1, further comprising: applying the updated target FPS value and the current FPS value to the PID controller to generate a frequency adjustment value; as well as The processing frequency is adjusted based on the frequency adjustment value.

3. The method according to claim 2, further comprising: Determine the updated current FPS value; determining whether the updated current FPS value is within a threshold range of the target FPS value; as well as Repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value, adjusting the processing frequency based on the frequency adjustment value, determining the updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value. The method of claim 2 , wherein adjusting the processing frequency based on the frequency adjustment value comprises setting a maximum frequency value and a minimum frequency value of a processing cluster.

5. The method of claim 2, wherein applying the updated target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value comprises: determining an error value based on a difference between the current FPS value and the updated target FPS value; applying the error value to a proportional term, an integral term, and a derivative term to obtain an output control variable; as well as The frequency adjustment value of each processing unit is determined based on the output control variable and the load rate of each processing unit.

6. The method according to claim 2, further comprising: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit; as well as The processing frequency is adjusted based on the updated frequency adjustment value.

7. The method according to claim 6 further includes repeatedly performing the following operations until the current FPS value is within a threshold range of the target FPS value: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

8. A power control module for use in a computing device having a display, the power control module comprising: a first proportional-integral-derivative (PID) controller configured to receive a target power value and a current power value as inputs and output a target frames per second (FPS) change (Δtarget FPS) value; and an adder circuit coupled to the PID controller and configured to add the target FPS change (Δtarget FPS) value to a current target FPS value to generate an updated target FPS value; an FPS controller coupled to the summer circuit and configured to generate as output a current FPS for the display of the computing device; and A device power controller is coupled to the FPS controller and is configured to adjust power in the computing device based on the current FPS output by the FPS controller.

9. The power control module according to claim 8, wherein: the FPS controller comprising a second PID controller configured to generate a frequency adjustment value based on the updated target FPS value and a current FPS value; and The FPS controller is further configured to adjust a processing frequency based on the frequency adjustment value.

10. The power control module of claim 9, wherein the FPS controller is further configured to: Determine the updated current FPS value; determining whether the updated current FPS value is within a threshold range of the target FPS value; and Repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value, adjusting the processing frequency based on the frequency adjustment value, determining the updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value. 11 . The power control module of claim 9 , wherein the FPS controller is further configured to adjust the processing frequency based on the frequency adjustment value by setting a maximum frequency value and a minimum frequency value of a processing cluster.

12. The power control module of claim 9 , wherein the second PID controller is configured to apply the updated target FPS value and the current FPS value to generate the frequency adjustment value by: determining an error value based on a difference between the current FPS value and the updated target FPS value; applying the error value to a proportional term, an integral term, and a derivative term to obtain an output control variable; as well as The frequency adjustment value of each processing unit is determined based on the output control variable and the load rate of each processing unit.

13. The power control module of claim 9, wherein the FPS controller is further configured to: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit; and The processing frequency is adjusted based on the updated frequency adjustment value.

14. The power control module according to claim 13, wherein the FPS controller is further configured to repeatedly perform the following operations until the current FPS value is within a threshold range of the target FPS value: determining the updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

15. A computing device, comprising: A processor configured to: applying the target power value and the current power value to a proportional-integral-derivative (PID) controller to generate a target frames per second (FPS) change (Δtarget FPS); adding the target FPS change (Δtarget FPS) value to the current target FPS value to generate an updated target FPS value as input to an FPS controller, which generates the current FPS as output; as well as Power in the computing device is adjusted based on the current FPS output by the FPS controller.

16. The computing device of claim 15, wherein the processor is further configured to: applying the updated target FPS value and the current FPS value to the PID controller to generate a frequency adjustment value; and The processing frequency is adjusted based on the frequency adjustment value.

17. The computing device of claim 16, wherein the processor is further configured to: Determine the updated current FPS value; determining whether the updated current FPS value is within a threshold range of the target FPS value; and Repeating the following operations until the current FPS value is within the threshold range of the target FPS value: applying the target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value, adjusting the processing frequency based on the frequency adjustment value, determining the updated current FPS value, and determining whether the updated current FPS value is within the threshold range of the target FPS value. 18 . The computing device of claim 16 , wherein the processor is configured to adjust the processing frequency based on the frequency adjustment value by setting a maximum frequency value and a minimum frequency value of a processing cluster.

19. The computing device of claim 16, wherein the processor is configured to apply the updated target FPS value and the current FPS value to the PID controller to generate the frequency adjustment value by: determining an error value based on a difference between the current FPS value and the updated target FPS value; applying the error value to a proportional term, an integral term, and a derivative term to obtain an output control variable; as well as The frequency adjustment value of each processing unit is determined based on the output control variable and the load rate of each processing unit.

20. The computing device of claim 16, wherein the processor is further configured to: determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit; and The processing frequency is adjusted based on the updated frequency adjustment value.

21. The computing device of claim 20 , wherein the processor is further configured to repeatedly perform the following operations until the current FPS value is within a threshold range of the target FPS value: determining the updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit, and adjusting the processing frequency based on the updated frequency adjustment value.

22. A computing device, comprising: means for generating a target frames per second (FPS) change (Δtarget FPS) value using the target power value and the current power value; means for adding the target FPS change (Δtarget FPS) value to the current target FPS value to generate an updated target FPS value; means for generating a current FPS using the updated target FPS value; and means for adjusting power in the computing device based on the current FPS.

23. The computing device of claim 22, further comprising: means for generating a frequency adjustment value using the updated target FPS value and the current FPS value; and Means for adjusting a processing frequency based on the frequency adjustment value.

24. The computing device of claim 23, further comprising: A component for determining the updated current FPS value; means for determining whether the updated current FPS value is within a threshold range of the target FPS value; and a component for generating the frequency adjustment value using the target FPS value and the current FPS value, a component for adjusting the processing frequency based on the frequency adjustment value, a component for determining the updated current FPS value, and a component for determining whether the updated current FPS value is within the threshold range of the target FPS value, repeating the operations of the following components until the current FPS value is within the threshold range of the target FPS value.

25. The computing device of claim 23, wherein the means for adjusting the processing frequency based on the frequency adjustment value comprises: This component is used to set the maximum and minimum frequency values ​​of the processing cluster.

26. The computing device of claim 23, wherein the means for generating the frequency adjustment value using the updated target FPS value and the current FPS value comprises: means for determining an error value based on a difference between the current FPS value and the updated target FPS value.

27. The computing device of claim 26, wherein the means for generating the frequency adjustment value using the updated target FPS value and the current FPS value further comprises: Means for applying the error value to proportional, integral and derivative terms to obtain an output controlled variable.

28. The computing device of claim 27, wherein the means for generating the frequency adjustment value using the updated target FPS value and the current FPS value further comprises: means for determining the frequency adjustment value of each processing unit based on the output control variable and the load rate of each processing unit.

29. The computing device of claim 23, further comprising: means for determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit, and the load rate of each processing unit; and Means for adjusting the processing frequency based on the updated frequency adjustment value.

30. The computing device according to claim 29 further includes a component for repeatedly performing operations of the following components until the current FPS value is within a threshold range of the target FPS value: a component for determining an updated frequency adjustment value based on the output control variable, the frequency value of each processing unit and the load rate of each processing unit, and a component for adjusting the processing frequency based on the updated frequency adjustment value.

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