Efficient implementation of floating point exponential functions in processor

Abstract

A processor includes an instruction decoder configured to provide at least a floating point instruction control signal; performing floating point calculation on a data path; a floating point custom instruction control logic block coupled to the floating point compute data path; a control and status register coupled to the floating point computational data path and the floating point custom instruction control logic block; a first multiplexer configured to provide a floating-point instruction control signal or a custom instruction control signal to the floating-point computational data path based on a state of a selection control signal; and a second multiplexer configured to provide a floating point operand or a custom operand to the floating point computing data path based on a state of the selection control signal. The floating point custom instruction control logic block asserts a select signal while directing the floating point computational data path to assist it in executing custom instructions. The custom instruction may be a floating point exponential function.

Description

Technical Field

[0001] Various illustrative embodiments disclosed herein relate to a processor microarchitecture for hardware support for execution of floating-point instructions for exponential calculations. Background Art

[0002] Transcendental functions are functions that cannot be expressed as a finite combination of the algebraic operations of addition, subtraction, multiplication, division, exponentiation, and root extraction. Examples of transcendental functions include log x, sin x, cos x, e^x, and functions containing any of the foregoing.

[0003] Transcendental functions, such as the exponential function (e^x), are used in nonlinear arithmetic operations performed by a processor. It would be desirable to have a processor that can efficiently implement the ability to perform exponential calculations. Summary of the Invention

[0004] A summary of various illustrative embodiments is presented below.

[0005] Various illustrative embodiments relate to electronic products, such as processors having floating-point units. In one illustrative embodiment, a processor includes a floating-point unit comprising a floating-point calculation datapath, a floating-point calculation datapath control logic block coupled to the floating-point calculation datapath, and a floating-point custom instruction control logic block coupled to the floating-point calculation datapath; and a control and status register coupled to the floating-point calculation datapath, the floating-point calculation datapath control logic block, and the floating-point custom instruction control logic block.

[0006] In some embodiments, the processor further includes an instruction decode unit configured to generate a floating-point instruction control signal based at least in part on a first floating-point instruction set and further configured to generate a start signal activating execution of a floating-point custom instruction.

[0007] In some embodiments, the floating point computation data path, in conjunction with the floating point computation data path control logic block, is configured to execute a first floating point instruction set.

[0008] In some embodiments, the floating-point calculation data path, in conjunction with the floating-point calculation data path control logic block and the floating-point custom instruction control logic block, is configured to execute a first floating-point instruction set and at least one custom instruction.

[0009] In some embodiments, the first floating-point instruction set is a floating-point instruction set specified by the RISC-V instruction set architecture.

[0010] In another illustrative embodiment, a processor includes: an instruction decoder configured to provide at least a floating-point instruction control signal; a floating-point computation datapath; a floating-point custom instruction control logic block coupled to the floating-point computation datapath; a control and status register coupled to the floating-point computation datapath and the floating-point custom instruction control logic block; a first multiplexer configured to provide the floating-point instruction control signal or the custom instruction control signal to the floating-point computation datapath based on a state of a select control signal; and a second multiplexer configured to provide a floating-point operand or the custom operand to the floating-point computation datapath based on the state of the select control signal.

[0011] In some embodiments, the processor additionally includes a third multiplexer configured to provide the first rounding control information or the custom rounding control information to the floating point calculation data path based on a state of a select control signal.

[0012] In some embodiments, the third multiplexer is coupled to receive the first rounding control information from the control and status register and is further coupled to receive the custom rounding control information from the floating point custom instruction control logic block.

[0013] In some embodiments, the floating-point custom instruction control logic block includes at least one lookup table.

[0014] In some embodiments, the processor further includes an instruction output data bus driver coupled to receive an instruction output result from the floating point computation data path when the select signal is de-asserted.

[0015] In some embodiments, the instruction decoder is configured to determine whether a custom instruction has been received.

[0016] In some embodiments, the instruction decoder is configured to assert a start signal in response to determining that a custom instruction has been received.

[0017] In some embodiments, the floating-point custom instruction control logic block is configured to initiate a sequence of actions performed by both the floating-point custom control logic block and the floating-point computation datapath in response to a start signal.

[0018] In some embodiments, the instruction decoder is configured to determine whether a floating point exponent instruction has been received.

[0019] In some embodiments, the floating-point custom instruction control logic is configured to control execution of floating-point exponentiation instructions.

[0020] In another illustrative embodiment, a method includes: asserting, by an instruction decoder, a start signal in response to decoding a floating-point custom instruction; initiating, by a floating-point custom instruction control logic block, a sequence of actions performed by both the floating-point custom instruction control logic block and a floating-point computation datapath in response to the start signal; asserting, by the floating-point custom instruction control logic block, a select control signal; selecting, by the floating-point custom instruction control logic block, a custom instruction control signal in response to the select control signal, and providing the custom instruction control signal to the floating-point computation datapath; and selecting, by the select control signal, a custom instruction operand, and providing the custom instruction operand to the floating-point computation datapath.

[0021] In some embodiments, the method further includes accessing, by the custom instruction control logic block, one or more lookup tables.

[0022] In some embodiments, the method additionally includes selecting custom rounding control information in response to a select control signal and providing the custom rounding control information to a floating point calculation data path.

[0023] In some embodiments, the method further includes disabling writeback of instruction execution results when the select signal is asserted.

[0024] In some embodiments, the method further includes deasserting the select control signal after executing the custom floating-point instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To facilitate a better understanding of the various illustrative embodiments, reference is made to the accompanying drawings, in which:

[0026] Figure 1 is a high-level block diagram of a portion of a processor in which a floating-point unit is integrated.

[0027] Figure 2 Shows a format for representing 32-bit single-precision floating-point numbers according to the IEEE 754-2008 standard.

[0028] Figure 3 A format for encoding 32-bit single-precision floating-point computation instructions according to the "F" extension of the RISC-V instruction set architecture is shown.

[0029] Figure 4 is a simplified high-level block diagram of a portion of the floating-point unit used to execute floating-point instructions.

[0030] Figure 5 is a simplified high-level block diagram of a portion of a floating-point unit for executing floating-point instructions of the RISC-V "F" extension and for executing custom floating-point exponential function instructions according to the present disclosure.

[0031] Figure 6is a high-level block diagram of a portion of a floating-point unit for executing floating-point instructions according to the "F" extension of the RISC-V instruction set architecture.

[0032] Figure 7 A high-level block diagram of a portion of a floating-point unit for executing floating-point instructions of the RISC-V "F" extension, with added logic for executing custom floating-point exponential function instructions according to the present disclosure.

[0033] Figure 8 is a diagram illustrating the order in which “F” extended floating-point instructions are executed under the guidance of a custom instruction control logic block in combination with the computational functionality of the custom instruction control logic block to perform functions allowed but not supported by RISC-VISA according to the present disclosure.

[0034] Figure 9 is a flow chart of a method according to the present disclosure.

[0035] To facilitate understanding, the same reference numerals have been used in some places to designate elements having substantially the same or similar structure and / or substantially the same or similar function. DETAILED DESCRIPTION

[0036] Many real-world problems require calculations using transcendental functions in order to find solutions. In some cases, processors such as, but not limited to, microprocessors have been implemented with dedicated hardware to support calculations using transcendental functions. Other processors, such as those that conform to the RISC-V instruction set architecture, do not provide specific hardware support for calculating floating-point transcendental functions in the RISC-V base or extended instruction set. However, the RISC-V instruction set architecture allows processor designers to add custom instructions visible to programmers, i.e., custom instructions become part of the instruction set architecture. However, the hardware design that serves as the basis for custom instructions is not specified by the RISC-V instruction set architecture, and processor designers need to develop hardware design or microarchitecture to support the functionality of custom instructions.

[0037] Various embodiments of the present disclosure provide apparatus and methods for computing at least one estimate of an exponential function (eg, e^x). Some embodiments of the present disclosure provide efficient implementation of processor hardware for executing floating-point exponentiation instructions.

[0038] Calculations involving the exponential function e^x (where e is the base of the natural logarithm) can be performed using, for example, but not limited to, the computing resources of a computer. Furthermore, these calculations can be performed by executing various floating-point instructions. Computers typically include dedicated hardware within their processors for executing floating-point instructions, and such dedicated hardware can be organized as a floating-point unit (FPU). That is, an FPU is specialized hardware designed to perform arithmetic operations on floating-point numbers.

[0039] Figure 1 is a high-level block diagram of a portion of a simplified example processor 102 with an integrated FPU. The processor 102 includes an instruction fetch and decode unit 104, a bus 106, an integer unit 108 including a set of integer registers and an integer arithmetic logic unit (ALU), and an FPU 110 including floating point registers and a floating point ALU. Those skilled in the art will recognize that the instructions in the example of FIG. Figure 1 The portions of the example processor shown in FIG. 5 may differ, and an actual processor may have many other functional blocks and features. Figure 1 A scenario is shown where the processor is configured to receive and decode instructions and then direct integer unit 108 or FPU 110 to perform the desired operation as specified by the decoded instructions.

[0040] Floating-point numbers are a way of representing real numbers in calculations, including rational and irrational numbers, with a decimal part. Compared to integers, which represent numbers without decimal places (whole numbers), floating-point numbers allow for the representation of a wider range of values, such as very small and very large numbers. Generally, a floating-point number has three parts: a sign, a decimal, and an exponent. The sign indicates whether the floating-point number is positive or negative. The decimal, which can also be called a mantissa or significant digit, provides the number of significant digits of the floating-point number, including the decimal part. The exponent represents the power of the floating-point number's base. In other words, the general form of a floating-point number is:

[0041] ±decimal x base 指数 .

[0042] While there are many ways that floating point numbers can be represented in computer systems, one of those ways is according to the IEEE 754-2008 specification. Figure 2 The format of a 32-bit single-precision floating-point number according to the IEEE 754-2008 specification is shown. In this representation of a 32-bit single-precision floating-point number, as shown in FIG. Figure 2 As shown in , bits 0 to 22 represent 23-bit fractional data, bits 23 to 30 represent 8-bit exponent data, and bit 31 represents one bit indicating the sign of the floating-point number (ie, whether the floating-point number is positive or negative).

[0043] In the field of computer design, particularly as it relates to processor design, an instruction set architecture (ISA) specification may have many different possible hardware implementations, and those implementations may be referred to as microarchitectures. Typically, processor designers are free to implement the ISA using the hardware and / or firmware of their choice, as long as the implementation meets the ISA specification.

[0044] Some ISA specifications provide a base instruction set to be implemented, and additionally provide one or more optional instruction sets, called "extensions," that are added to implementations of the base instruction set by processor designers.

[0045] RISC-V is an example of an ISA specification that provides processor designers with instructions to add to the base ISA for implementation in a microarchitecture. Some of RISC-V's instruction set extensions can be referred to as "standard" extensions, i.e., instruction set extensions predefined by the RISC-V ISA specification. RISC-V ISA specifies multiple standard extensions, including, for example, an "M" extension for integer multiplication and division, an "F" extension for single-precision floating point, and an "D" extension for double-precision floating point. The "F" standard extension includes several classes of single-precision floating-point instructions, namely, load and store instructions, calculation instructions, conversion and move instructions, comparison instructions, and sort instructions.

[0046] RISC-V also provides for adding one or more custom instructions, i.e., instructions that are not defined by the RISC-V ISA but are implemented by the processor designer.

[0047] Referring again to the RISC-V "F" extension, this standard instruction set extension for single-precision floating-point adds single-precision floating-point calculation instructions that comply with the IEEE 754-2008 arithmetic standard (ANSI / IEEE Std 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008). The IEEE 754-2008 standard single-precision floating-point format requires 23 fractional bits F, 8 exponent bits E, and a sign bit S, for a total of 32 bits per word. F is the mantissa of a positive binary fraction in 2's complement represented from bits 0 to 22 of a 32-bit single-precision floating-point number (see Figure 2 IEEE 754-2008 single-precision floating-point format).

[0048] The RISC-V "F" extension also defines a floating-point instruction set. Figure 3 Figure 2 shows the 32-bit format of the "F" extended floating-point calculation instruction. Figure 3 As shown in , bits 0-6 contain a 7-bit opcode, bits 7-11 contain a 5-bit destination register address, bits 12-14 contain a 3-bit field that specifies which rounding method to use, bits 15-19 contain a 5-bit first source register address, bits 20-24 contain a 5-bit second source register address, bits 25-26 contain a 2-bit field that specifies the instruction format (00 indicates single-precision floating-point operation), and bits 27-31 contain a 5-bit field that specifies a specific type of single-precision floating-point computation operation.

[0049] It should be noted that the principles of this disclosure can be used with RISC-V floating-point instructions other than single-precision floating-point calculation instructions. As an example and not a limitation, the principles of this disclosure can be used with RISC-V "D" extension double-precision floating-point calculation instructions or "Q" extension quadruple-precision calculation instructions. It should also be noted that the principles disclosed herein can be applied to floating-point units in non-RISC-V architectures, including but not limited to ARM, PowerPC, etc.

[0050] Although the standard RISC-V instruction encoding scheme is designed to support ISA extensions with variable-length instructions, the base RISC-V ISA has fixed-length 32-bit instructions that must be naturally aligned on 32-bit boundaries. The various illustrative embodiments described herein use fixed-length 32-bit instructions, however, embodiments of the present disclosure are not limited to fixed-length 32-bit instruction formats. As an example and not a limitation, various embodiments of the present disclosure may be implemented for RISC-V's variable-length instructions, where each instruction may be any number of 16-bit instruction packets (wherein the packets are aligned on 16-bit boundaries).

[0051] It should be noted that the name "RISC-V" refers to the fifth major reduced instruction set computer (RISC) instruction set architecture (ISA) from the University of California at Berkeley. See, for example, "The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213," edited by Andrew Waterman and Krste Asanovic, RISC-V Foundation, December 2019; and "The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203," edited by Andrew Waterman, Krste Asanovic, and John Hauser, RISC-V International Foundation, December 2021.

[0052] Various aspects of the present disclosure are more fully described herein with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to any specific structure or function presented throughout the present disclosure. In fact, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings herein, those skilled in the art will appreciate that the scope of the present disclosure is intended to encompass any aspect of the present disclosure disclosed herein, regardless of whether the aspect is implemented independently of any other aspect of the present disclosure or implemented in combination with any other aspect of the present invention. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to encompass such devices or methods that are practiced using other structures, functionality, or structure and functionality other than the various aspects of the present disclosure set forth herein or that are different from the various aspects of the present disclosure set forth herein. It should be understood that any aspect of the present disclosure can be embodied by one or more elements of the claims.

[0053] As described in more detail below, some embodiments according to the present disclosure may implement custom instructions by adding control circuitry to an FPU compliant with the RISC-V "F" extension, such that the added control circuitry redirects the "F" extension FPU hardware to participate in the execution of the custom instructions. It should be noted that the various embodiments are not limited to the RISC-V ISA, nor to RISC-V floating-point implementations. That is, embodiments according to the present disclosure may also be implemented in non-RISC-V processors.

[0054] Nonlinear arithmetic operations in processors require transcendental functions, such as the exponential function (e^x). Exponential functions have some mathematically interesting and unique characteristics. For example, exponential functions are unique because the derivative of an exponential function of a real variable is proportional to the value of the function. That is, given an exponential function f(x) = e^x, the derivative of f(x) is f'(x) = (e^x)(ln e), which is equal to e^x because ln e is equal to 1 (where e is the base of the natural logarithm, x is a real number, and ln is the natural logarithm).

[0055] Some conventional methods for calculating estimates of the exponential function (e^x) have used lookup table storage circuits that are not memory efficient. Such conventional methods may also have significant errors from the true value or reference value and may additionally have instruction delays that reduce computational efficiency.

[0056] Various embodiments of the present disclosure implement hardware support for executing floating-point exponential function instructions in a processor with an FPU. Some embodiments implement hardware support for executing custom floating-point exponential function instructions in a RISC-V processor that includes an "F" extension for single-precision floating-point instructions.

[0057] Figure 4 and 5 A block diagram illustrating a simplified FPU is used to introduce the concept of adding or inserting additional control logic into an FPU design to execute custom instructions through a series of actions, including but not limited to directing the FPU to execute instructions that have not been received and decoded from the processor's instruction stream.

[0058] Figure 4 4 is a high-level block diagram of a simplified FPU 400. The FPU 400 is integrated into a processor (not shown) and includes a control and status register (CSR) 402, an instruction decoder 404, a floating-point calculation datapath control logic block 406, a floating-point calculation datapath 408, and an instruction result output data bus driver 410. The CSR 402 is coupled to the floating-point calculation datapath control logic block 406 and the floating-point calculation datapath 408. The instruction decoder 404 is coupled to the floating-point calculation datapath control logic block 406, which is coupled to the floating-point calculation datapath 408. The floating-point calculation datapath 408 is coupled to the instruction result output data bus driver 410.

[0059] Those skilled in the art will understand that a "floating-point computation datapath" refers to a physical implementation, typically logic circuitry, that receives various operands and control signals and processes these operands to produce results according to specified logic rules.

[0060] Figure 5 is a high-level block diagram of a simplified FPU 500 integrated into a processor (not shown). In this illustrative example, the FPU 500 complies with the RISC-V "F" extension and further includes a control logic block for implementing a floating-point exponential function according to the present disclosure. The FPU 500 includes a control and status register (CSR) 502, an instruction decoder 504, a floating-point custom instruction control logic block 505, a floating-point calculation datapath control logic block 506, a floating-point calculation datapath 508, and an instruction output data bus driver 510. In this illustrative embodiment, the floating-point custom instruction control logic block 505 provides floating-point exponential function control logic. The CSR 502 is coupled to the floating-point custom instruction control logic block 505, the floating-point calculation datapath control logic block 506, and the floating-point calculation datapath 508. The instruction decoder 504 is coupled to the floating-point custom instruction control logic block 505 and to the floating-point calculation datapath control logic block 506. The floating-point custom instruction control logic block 505 is coupled to the floating-point calculation data path control logic block 506 and to the floating-point calculation data path 508. The floating-point calculation data path control logic block 506 is coupled to the floating-point calculation data path 508. The floating-point calculation data path 508 is coupled to the instruction output data bus driver 510.

[0061] Still refer to Figure 5 , the floating-point computation datapath control logic block 506 and the floating-point computation datapath 508 operate to execute 32-bit single-precision floating-point instructions specified by the RISC-V "F" extension. In some embodiments, decoding of a custom instruction, such as decoding of a custom floating-point exponent instruction (FEXP(x)) by the instruction decoder 504, initiates a series of actions controlled by the floating-point custom instruction control logic block 505. During the course of this series of actions, the floating-point custom instruction control logic block 505 may, in particular, direct the floating-point computation datapath 508 to execute one or more RISC-V "F" extension instructions without receiving such instructions from the instruction stream fetched by the processor.

[0062] Figure 6 and 7 is a high-level block diagram illustrating a simplified FPU compliant with the RISC-V “F” extension and integrated within a corresponding processor (not shown). Figure 7 Shown with Figure 6 Compared to the additional control logic block, where the additional control circuitry implements the functionality of custom floating-point instructions not found in the RISC-V "F" extension. Figure 6 and 7 The processors mentioned may be scalar or superscalar. Likewise, the processors may be single-core or multi-core implementations.

[0063] Figure 6 6 is a high-level block diagram of a portion of a floating-point unit 600 for executing floating-point instructions according to the "F" extension of the RISC-V instruction set architecture. In this illustrative example, the FPU 600 includes a floating-point control and status register (FCSR) 602, an instruction decode unit 604, a floating-point computation data path 606, and an instruction output data bus driver 608. Figure 6 As indicated in , control information from the instruction decode unit 604 is provided to a floating-point data path 606, which also receives floating-point operands from elsewhere in the processor, such as from one or more registers that can temporarily store these operands. After execution of the floating-point instruction is completed, the result can be transferred from the floating-point computation data path 606 to the instruction output data bus driver 608. The instruction output data bus driver 608 can transfer the result to an appropriate destination, such as a destination register, via write-back.

[0064] Figure 7This is a high-level block diagram of a portion of a floating-point unit 700 for executing floating-point instructions of the RISC-V "F" extension, with added logic for executing custom floating-point exponential function instructions according to the present disclosure. The FPU 700 includes a floating-point control and status register (FCSR) 702, an instruction decode unit 704, a floating-point custom instruction control logic block 706, a floating-point calculation data path 708, a first multiplexer (mux) 710, a second mux 712, a third mux 714, a fourth mux 716, and an instruction output data bus driver 718. In this illustrative embodiment, the floating-point custom instruction control logic block 706 is used to implement a custom instruction for calculating an exponential function and includes at least one lookup table (LUT). In this illustrative embodiment, the first mux 710, the second mux 712, the third mux 714, and the fourth mux 716 are each 2:1 muxes. In this illustrative embodiment, muxes 710 , 712 , and 714 allow floating-point custom instruction control logic block 706 to take over control of floating-point computation datapath 708 to assist in the execution of FEXP instructions.

[0065] The floating-point calculation data path 708 is configured to receive instruction control information from the first mux 710, receive floating-point operands from the mux 712, and receive rounding control information from the third mux 714. The floating-point calculation data path 708 is configured to execute floating-point instructions of the RISC-V "F" extension. The floating-point calculation data path 708 is further configured to provide information to the FCSR 702 and provide the results of the instruction execution to the fourth mux 716.

[0066] Still refer to Figure 7 The first mux 710 is coupled to receive floating-point instruction control information from the instruction decode unit 704 at a first of its data inputs. The first mux 710 is coupled to receive floating-point exponent instruction control information from the floating-point custom instruction control logic block 706 at a second of its data inputs. The first mux 710 is coupled to receive a select control signal (fexp_ongoing) from the floating-point custom instruction control logic block 706 at a select input thereof. The first mux 710 provides floating-point instruction control information from the instruction decode unit 704 at its output when fexp_ongoing is deasserted, and provides floating-point exponent (FEXP) instruction control information at its output when fexp_ongoing is asserted.

[0067] The second mux 712 is coupled to receive a floating-point operand at a first of its data inputs. The second mux 712 is coupled to receive a FEXP operand at a second of its data inputs. The second mux 712 is coupled to receive fexp_ongoing from the floating-point custom instruction control logic block 706 at its select input. The second mux 712 provides a floating-point operand at its output when fexp_ongoing is deasserted and provides a FEXP operand at its output when fexp_ongoing is asserted.

[0068] The third mux 714 is coupled to receive CSR rounding control information from the FCSR 702 at a first of its data inputs. The third mux 714 is coupled to receive FEXP rounding control information from the floating-point custom instruction control logic block 706 at a second of its data inputs. The third mux 714 is coupled to receive fexp_ongoing at its select input from the floating-point custom instruction control logic block 706. The third mux 714 provides CSR rounding control information at its output when fexp_ongoing is deasserted, and provides FEXP rounding control information at its output when fexp_ongoing is asserted.

[0069] The fourth mux 716 is coupled to receive an instruction result from the floating-point calculation data path 708 at a first of its data inputs. The fourth mux 716 is coupled to receive a writeback invalid signal at a second of its data inputs. The fourth mux 716 is coupled to receive fexp_ongoing from the floating-point custom instruction control logic block 706 at its select input. The fourth mux 716 provides the instruction result from the floating-point calculation data path 708 at its output when fexp_ongoing is deasserted, and provides a writeback invalid signal at its output when fexp_ongoing is asserted. The writeback invalid signal indicates to the instruction output data bus driver 718 that a valid instruction result is not available while execution of the custom FEXP instruction is in progress.

[0070] As noted above, various embodiments of the present disclosure provide hardware support typically implemented in a processor for efficiently computing exponential functions using floating-point computing hardware. Still other embodiments provide methods for operating floating-point computing hardware to implement the task of computing exponential functions.

[0071] As described in more detail below, various embodiments may combine the functionality of floating-point computation hardware that implements functionality defined by the RISC-V ISA with the functionality of floating-point computation hardware that implements custom instructions according to the present disclosure.

[0072] According to the present disclosure, some embodiments may utilize the functionality of at least a subset of the RISC-V "F" standard extension for single-precision floating-point in combination with hardware support for implementing custom instructions to allow efficient calculation of exponential functions. It should be noted that in the RISC-V "F" extension, floating-point arithmetic instructions with one or two source operands use an R-type format with an OP-FP major opcode (see "The RISC-V Instruction Set Manual, Volume 1: User-Level ISA, Document Version 20191213"). In some embodiments, processor hardware for implementing the "F" extension floating-point instructions FMUL, FCVT.WS, FCVT.SW, FNMSUB, and FMADD, combined with control logic for implementing one or more custom instructions according to the present disclosure, may be used to perform calculations of exponential functions.

[0073] FMUL.S performs a single-precision floating-point multiplication between rs1 and rs2 and writes the result to rd.

[0074] FCVT stands for single-precision floating-point conversion. RISC-V floating-point to integer and integer to floating-point conversion instructions are encoded in the OP-FP major opcode space. FCVT.WS converts the floating-point number in floating-point register rs1 to a signed 32-bit integer in integer register rd. FCVT.SW converts the 32-bit signed integer in integer register rs1 to a floating-point number in floating-point register rd. All floating-point to integer and integer to floating-point conversion instructions round according to the instruction's rm field.

[0075] FNMSUB is a fused multiply-accumulate single-precision floating-point instruction that specifies three source registers (rs1, rs2, and rs3) and a destination register rd. The execution of FNMSUB calculates -rs1 x rs2 + rs3 and writes the result to rd.

[0076] FMADD is a fused multiply-add single-precision floating-point instruction that specifies three source registers (rs1, rs2, and rs3) and a destination register rd. The execution of FMADD calculates rs1 x rs2 + rs3 and writes the result to rd.

[0077] In various embodiments, control logic for a custom FEXP instruction according to the present disclosure operates in conjunction with floating-point circuitry for implementing the RISC-V standard "F" extension. The following mathematical properties may be used in some embodiments implementing a processor for performing floating-point exponent calculations:

[0078] e^(x + y) = (e^x)(e^y) (Equation 1)

[0079] e^(xln2) = e^(ln2^x) = 2^x (Equation 2)

[0080] In some embodiments, the instruction decoding unit determines a custom FEXP instruction to be executed and asserts the signal FEXP_start. The FEXP instruction control block responds to the assertion of the FEXP_start signal by initiating an FEXP_execution_sequence to compute the exponential function, where the FEXP_execution_sequence is a sequence of actions performed by both the FEXP instruction control block and the floating-point computation data path. In this illustrative embodiment, the FEXP instruction control block has a pre-computed value of 1 / ln2 stored therein. In this way, the division (i.e., 1 / ln2) in the hardware implementation can be avoided by replacing it with a multiplication by the pre-computed constant (1 / ln2). In this illustrative example, the constant 1 / ln2 can be represented as 32'h3FB8AA3B.

[0081] After initiating the FEXP_execution_sequence, e^x is considered as e^(I*ln2 + F), where I is an integer and the fraction F is the remainder of the equation (0 <= F < ln2). Also, after initiating the FEXP_execution_sequence, the FEXP instruction control block switches the selection inputs of one or more multiplexers such that the floating-point instruction control signals from the instruction decoding unit are skipped, and the FEXP instruction control block supplies the FEXP instruction control signals to the floating-point computation data path.

[0082] Reference Figure 8 , in the first operation 802, the floating-point custom instruction control block directs the floating-point computation data path to perform a floating-point multiplication (FMUL) such that a = x * 1 / ln2, where the pre-computed value of 1 / ln2 is supplied by the floating-point custom instruction control block to the floating-point computation data path.

[0083] In the second operation 804, a is separated into an integer part (I) and a fractional part (F). To achieve this separation, the floating-point custom instruction control block directs the floating-point computation data path to perform a floating-point to integer conversion (FCVT.W.S(a) = I) on the value a, where the rounding mode is set to round down (towards -∞).

[0084] In the third operation 806, I is converted to floating-point form. To achieve this, the floating-point custom instruction control block directs the floating-point computation data path to perform an integer to floating-point conversion (FCVT.S.W(I)).

[0085] In the fourth operation 808, F is determined by calculating x - float(I)*ln2. To achieve this, the floating-point custom instruction control logic block guides the floating-point calculation data path to perform a fused multiply-subtract (FNMSUB).

[0086] As noted above, e^x is regarded as e^(I*ln2 + F), where I is an integer and the fraction F is the remainder of the equation (0 <= F < ln2). Using the property of equation (1) above, it can be seen that e^(I*ln2 + F) can also be expressed as e^(I*ln2)*e^(F). And, using the property of equation (2) above, it can be seen that:

[0087] e^(I*ln2)*e^(F) = e^(ln2^I)*(e^F) = (2^I)*(e^F)

[0088] It should be noted that F in single-precision floating-point representation has 23 bits, i.e., bits 0 to 22 of a 32-bit single-precision floating-point number, and the first argument given above is reduced to 0 <= F < ln2. Therefore:

[0089] (2^I)*(e^F) = (2^I)*(e^(.b22b21b20…b1b0))

[0090] A table-based method can be used to further reduce the argument range to 0 <= F < ln2 / 128. The FEXP instruction control logic block is configured to use the fractional part to look up e^x (LUT16) for the first four bits (0 to 0.1111), and concurrently look up e^x (LUT8) for the subsequent three bits, efficiently looking up the table of entries with e^x having 0 to 0.0000111.

[0091] To obtain the first 7 upper bits of F, the fifth operation 810 and the sixth operation 812 are performed. In the fifth operation 810, the floating-point custom instruction control logic block guides the floating-point calculation data path to perform a floating-point to integer conversion on F to calculate the upper 7 bits of the fraction (FCVT.W.S(F) = C). And in the sixth operation 812, the floating-point custom instruction control logic block guides the floating-point calculation data path to perform an integer to floating-point conversion (FCVT.S.W(upper 7 bits of C)) to obtain the upper 7 bits of C in floating-point format.

[0092] Therefore, e^x = (2^I)*(e^(.b22b21b20……b1b0)) =

[0093] (2^I)*(e^(.b22b21b20b19 +.0000b18b17b16 +.0000000b15b14……b1

[0094] b0)). And,

[0095] e^x =

[0096] (2^I)*(e^(.b22b21b20b19 +.0000b18b17b16 +.0000000b15b14……b1

[0097] b0)) =

[0098] (2^I)*(e^(.b22b21b20b19)*e^(0000b18b17b16)*e^(.0000000b15b14…

[0099] …b1b0)). And, (2^I)*lut16*lut8*e^(.0000000b15b14……b1b0)). It should be noted that.0000000b15b14……b1b0 is within the range of 0 to ln2 / 128 because 0 < F < ln2. Now, since F' is between 0 and ln2 / 128, the power series of e^x converges very well to 1 + F' + (F'^2) / 2 (only up to the 3rd order). Therefore, e^x =

[0100] 2^I*lut16*lut8*e^(.0000000b15b14……b1b0)) =

[0101] 2^I*lut16*lut,8*(1 + F' + (F'^2) / 2), where F' is.0000000b15b14……b1b0. Let n = (lut16*lut8), where n >> I, then e^x = n + n*(F' + (F'^2) / 2). It should be noted that n = FEXP LUT (the upper 7 bits of C), that is, the FEXP instruction control logic block accesses the contents of lut16 and lut8 based on the upper 7 bits of C.

[0102] In the seventh operation 814, the floating - point custom instruction control logic block including the lookup table provides the value from the lookup table, that is, the operand, so that a single - loop floating - point multiplication (FMUL) can obtain n = (lut16*lut8), where n >> I.

[0103] In the eighth operation 816, the floating - point custom instruction control logic block guides the floating - point calculation data path to execute a fused multiply - add instruction (FMADD) to obtain F' + (F'^2) / 2 in floating - point format.

[0104] In a ninth operation 818 , the floating-point custom instruction control logic block directs the floating-point computation data path to execute a fused multiply-add instruction (FMADD) to obtain (n+n*(F′+(F′^2) / 2) in a floating-point format.

[0105] refer to Figure 9 , an illustrative method 900 according to the present disclosure is shown. Method 900 includes asserting 902 a start signal by an instruction decoder in response to decoding a floating-point custom instruction, and initiating 904 a sequence of actions by both the floating-point custom instruction control logic block and the floating-point computation datapath in response to the start signal by the floating-point custom instruction control logic block. Method 900 further includes asserting 906 a select control signal by the floating-point custom instruction control logic block. Method 900 continues by selecting 908 a custom instruction control signal in response to the select control signal and providing the custom instruction control signal to the floating-point computation datapath, and selecting 910 a custom instruction operand in response to the select control signal and providing the custom instruction operand to the floating-point computation datapath. In some embodiments, the floating-point custom instruction is a floating-point exponent instruction, and the floating-point custom instruction control logic block is a floating-point exponent instruction control logic block configured to direct the floating-point computation datapath to support the floating-point exponent instruction control logic block when executing the floating-point exponent instruction.

[0106] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the aspects to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the various aspects.

[0107] Unless otherwise stated, terms such as "first," "second," etc., are used to arbitrarily distinguish between the elements such terms describe. Therefore, these terms are not necessarily intended to indicate temporal or other priority of such elements.

[0108] It should be readily understood that the meaning of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and that “over,” and “over” mean not only “over something” or “over something,” but also includes the meaning of “over something” or “over something” (i.e., directly on something) without intervening features or layers therebetween.

[0109] In addition, spatially relative terms, such as "below," "beneath," "below," "above," and the like, may be used herein to describe the relationship of one element or feature to another or other elements or features shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0110] As used herein, the term "vertical / vertically" refers to nominally normal to the surface of the object of reference.

[0111] As used herein, the term "nominal" refers to a desired or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances.

[0112] As used herein, the term "about" indicates that the value of a given quantity may vary from its nominal value based on, for example, various manufacturing tolerances. As an example and not limitation, the term "about" may indicate that the referenced value of a given quantity may vary, for example, within 1-30% of that value (e.g., ±0.5%, ±1%, ±5%, ±10%, ±20%, or ±30% of that value). Specific ranges are provided herein where necessary.

[0113] Those skilled in the art will appreciate that any block diagrams herein represent conceptual views of illustrative hardware embodying the principles of various aspects.

[0114] While each of the embodiments is described above in terms of its structural arrangement, it should be understood that the aspects also encompass the associated methods of using the above-described embodiments.

[0115] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the aspects to the precise forms disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be acquired from practice of the various aspects.

[0116] Even if a particular combination of features is recited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various aspects. In fact, many of these features can be combined in a manner not specifically recited in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of the various aspects includes each dependent claim in combination with each other claim in the claim set. A phrase referring to "at least one" in a list of items refers to any combination of those items, including single members. As an example, "at least one of the following: a, b or c" is intended to cover a, b, c, ab, ac, bc and abc, as well as any combination of multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc and ccc, or any other ordering of a, b and c).

[0117] Unless so clearly described, the elements, actions or instructions used herein should not be interpreted as critical or necessary. Moreover, as used herein, the articles "a" and "an" are intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the terms "set" and "group" are intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.), and can be used interchangeably with "one or more". In the case of only one item, the phrase "only one" or similar language is used. Moreover, as used herein, the terms "has", "have", "having" etc. are intended to be open terms. In addition, unless otherwise explicitly stated, the phrase "based on" is intended to mean "based at least in part on".

[0118] Although various exemplary embodiments have been described in detail with particular reference to specific exemplary aspects of the various exemplary embodiments, it will be understood that the invention is capable of other embodiments and that the details of the invention may be modified in various obvious respects. As will be readily apparent to those skilled in the art, variations and modifications may be made while remaining within the spirit and scope of the invention. Accordingly, the foregoing disclosure, description, and figures are for illustrative purposes only and do not in any way limit the invention, which is defined solely by the appended claims.

Claims

1. A processor, characterized in that: include: A floating-point unit, which includes: Floating-point calculation data path; a floating-point calculation data path control logic block coupled to the floating-point calculation data path; a floating-point custom instruction control logic block coupled to the floating-point calculation data path; and A control and status register is coupled to the floating-point calculation data path, the floating-point calculation data path control logic block, and the floating-point custom instruction control logic block.

2. The processor according to claim 1, wherein: Additionally included is an instruction decode unit configured to generate a floating-point instruction control signal based at least in part on the first floating-point instruction set and further configured to generate a start signal activating execution of a floating-point custom instruction.

3. The processor according to claim 2, wherein: The floating-point calculation data path, in conjunction with the floating-point calculation data path control logic block, is configured to execute a first floating-point instruction set.

4. The processor according to claim 2, wherein: The floating-point calculation data path, in conjunction with the floating-point calculation data path control logic block and the floating-point custom instruction control logic block, is configured to execute a first floating-point instruction set and at least one custom instruction.

5. The processor according to claim 4, wherein: The first floating-point instruction set is a floating-point instruction specified by the RISC-V instruction set architecture.

6. A processor, characterized in that: include: an instruction decoder configured to provide at least floating-point instruction control signals; Floating-point calculation data path; a floating-point custom instruction control logic block coupled to the floating-point calculation data path; a control and status register coupled to the floating-point calculation data path and the floating-point custom instruction control logic block; a first multiplexer configured to provide a floating-point instruction control signal or a custom instruction control signal to the floating-point calculation data path based on a state of a selection control signal; as well as A second multiplexer is configured to provide a floating point operand or a custom operand to the floating point calculation data path based on a state of the selection control signal.

7. The processor according to claim 6, wherein: Also includes: A third multiplexer is configured to provide first rounding control information or custom rounding control information to the floating-point calculation data path based on a state of the selection control signal.

8. The processor according to claim 7, wherein: The third multiplexer is coupled to receive the first rounding control information from a control and status register and is further coupled to receive the custom rounding control information from the floating-point custom instruction control logic block.

9. The processor according to claim 6, wherein: Additionally included is an instruction output data bus driver coupled to receive an instruction output result from the floating-point computation data path when a select signal is de-asserted.

10. A method, characterized in that include: asserting a start signal by the instruction decoder in response to decoding a floating-point custom instruction; Initiating, by the floating-point custom instruction control logic block in response to the start signal, a sequence of actions performed by both the floating-point custom instruction control logic block and the floating-point calculation data path; The floating-point custom instruction control logic block asserts a selection control signal; selecting a custom instruction control signal in response to the selection control signal, and providing the custom instruction control signal to the floating-point calculation data path; as well as A custom instruction operand is selected in response to the selection control signal and provided to the floating-point calculation data path.

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