Coding method and system based on matrix optimization and storage and calculation integrated accelerator, and medium

Abstract

The invention discloses a coding method and system based on matrix optimization and a storage and calculation integrated accelerator and a medium, and relates to the technical field of communication, and the method comprises the steps: constructing the storage and calculation integrated accelerator which comprises an input buffer area, a dynamic reconstruction storage and calculation array and a result processing module; m * n sub-matrixes obtained by splitting the check matrix H are respectively stored in corresponding storage and calculation integrated cores of the dynamic reconstruction storage and calculation array; the total code c is divided into n segments through an input buffer area and then multiply-accumulate with the corresponding column of sub-matrixes, a calculation result of the dynamic reconstruction storage array is input into a result processing module for result processing, and a final coding result is obtained; according to the coding method, the coding system and the medium, the dynamic adaptability and the calculation efficiency are broken through, and a high-reliability and low-delay LDPC coding solution is provided for tape storage.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an encoding method, system and medium based on matrix optimization and storage-computing integrated accelerator. Background Art

[0002] The challenges of LDPC coding in tape storage scenarios stem from the following: the fixed structure of the traditional LDPC parity check matrix H prevents flexible redundancy adjustments in dynamic channel environments (such as noise fluctuations caused by tape temperature and physical deformation, and media fatigue caused by repeated reading and writing). Furthermore, the parity check matrix H is large, requiring significant physical space to store. Direct operations on such a large matrix significantly increase coding latency. Furthermore, in the traditional von Neumann architecture, the majority of LDPC iterative decoding time is consumed by matrix data transfer. However, the integrated storage and computing architecture integrates storage and computing, eliminating data transfer latency, making integrated storage and computing technology a promising solution.

[0003] The paper Zhang Jing-lin, Liu Rong-ke, Zhao Ling. Optimized Decoder Design and Implement for High Rate LDPC Codes [J]. Journal of Electronics & Information Technology, 2009, 31(1): 83-86. doi: 10.3724 / SP.J.1146.2007.01072 proposes dynamic resource optimization based on matrix splitting. By splitting the check matrix H of the LDPC code (e.g., into two parts), the decoder operation flow is reconstructed. After the split, the hardware resource consumption is significantly reduced (logic resources are reduced by 41%, and memory resources are simultaneously optimized). At the same time, the loss in decoding rate is compensated by increasing the clock frequency (the rate is reduced to 2 / 3 of the original solution, but the clock performance is improved). This solution adopts a partially parallel design, balancing the computational complexity of CNU (check node update) and VNU (variable node update), optimizing module utilization (CNU increased from 50% to 100%, VNU increased from 50% to 67%) and storage density. It is particularly suitable for high-rate scenarios (such as 7 / 8-rate LDPC codes), providing high-reliability, low-latency error correction coding support for tape storage.

[0004] Patent CN115173867A, "A Method for Reconstructing an LDPC Sparse Check Matrix Under High Bit Error Rates," discloses a method for reconstructing an LDPC matrix under high bit error rates. This method constructs a square matrix by randomly extracting LDPC codeword bits and performs Gaussian elimination to obtain suspected check vectors, which are then judged based on statistical characteristics and the minimum error decision criterion. Through iterative extraction and verification, the proportion of error-free code groups is increased by "eliminating erroneous codewords" or "flipping the least unreliable bits," ultimately achieving check matrix reconstruction. Compared with existing technologies, this method has stronger fault tolerance and lower computational complexity, making it suitable for rapid reconstruction under high bit error rate environments.

[0005] There are two main problems with the technologies related to LDPC coding optimization in tapes:

[0006] (1) Existing solutions lack dynamic adaptability. Fixed sparsity and predefined bit rates make it difficult to cope with dynamic channel environments (such as temperature fluctuations and noise changes caused by medium fatigue). For example, the high bit error rate reconstruction method in patent CN115173867A relies on repeated iterative codeword extraction, which lacks real-time performance and cannot quickly respond to channel changes, resulting in a difficult balance between error correction efficiency and storage capacity.

[0007] (2) In traditional computing architectures, direct computation of large-scale parity check matrices requires a long time to move data. For example, in the aforementioned literature, after matrix splitting, the clock frequency still needs to be increased to compensate for the rate loss, and the degree of parallelization is limited, resulting in significant coding delay. Summary of the Invention

[0008] Based on the technical problems existing in the background technology, the present invention proposes an encoding method, system and medium based on matrix optimization and storage-computing integrated accelerator, which achieves breakthroughs in dynamic adaptability and computing efficiency, and provides a highly reliable and low-latency LDPC encoding solution for tape storage.

[0009] The encoding method based on matrix optimization and storage-computation integrated accelerator proposed in the present invention includes:

[0010] Constructing a storage-computing integrated accelerator, the storage-computing integrated accelerator including an input buffer, a dynamically reconfigurable storage-computing array, and a result processing module;

[0011] The m×n sub-matrices obtained by splitting the check matrix H are stored in the corresponding storage-computation integrated cores of the dynamically reconstructed storage-computation array respectively;

[0012] The total code c is divided into n segments through the input buffer and then multiplied and accumulated with the corresponding column sub-matrices respectively. The calculation results of the dynamically reconstructed storage array are input into the result processing module for result processing to obtain the final coding result.

[0013] Furthermore, the total code c is divided into n segments through the input buffer and then multiplied and accumulated with the corresponding column sub-matrices respectively, specifically:

[0014] The total code c is split into n segments in the input buffer, and each segment is judged to see if it is a zero vector. If it is a zero vector, the multiplication and accumulation process with the sub-matrix is ​​skipped directly.

[0015] The i-th segment code is multiplied and concatenated with each submatrix in the i-th column in sequence to obtain the i-th intermediate result. The storage and calculation array is dynamically reconstructed to finally obtain n intermediate results.

[0016] Furthermore, the calculation result of the dynamically reconstructed storage and calculation array is input into the result processing module for result processing to obtain the final coding result. Specifically, the result processing module adds n intermediate results and then performs binary domain calculation to obtain the final coding result;

[0017] Furthermore, the final coding result is subjected to zero vector judgment to determine whether the LDPC coding is wrong, specifically:

[0018] Determine whether the final encoding result is a zero vector;

[0019] If so, there is no error in the LDPC code;

[0020] If not, there is an error in the LDPC code.

[0021] Furthermore, the sub-matrices are stored in the corresponding storage-computation integrated cores of the dynamically reconfigurable storage-computation array, and the dynamic reconstruction algorithm is used to support the storage of sub-matrices of different sizes in the corresponding storage-computation integrated cores, specifically:

[0022] Ideally, the check matrix H is split into k×k sub-matrices of the same size, and each storage-computation core stores one k×k sub-matrix.

[0023] In actual conditions, the size of the split sub-matrix is ​​uncertain. The actual size of the split sub-matrix is ​​rounded up to a multiple of k×k, and the rounded value is used as the number of required storage-computation integrated cores. The combined storage-computation integrated cores are used as the storage resources of the actual sub-matrix.

[0024] Furthermore, each storage-computation core includes an 8T SRAM array, a multiplier, an adder tree, and a shift accumulator;

[0025] A sub-matrix is ​​stored in each storage-computation core, and the sub-matrix is ​​multiplied by the corresponding segment code through a multiplier;

[0026] The multiplied results are added through the adder tree and stored in the shift accumulator.

[0027] The encoding system based on matrix optimization and storage-computation integrated accelerator includes a check matrix splitting module and a storage-computation integrated accelerator, wherein the storage-computation integrated accelerator includes an input buffer, a dynamically reconstructed storage-computation array, and a result processing module;

[0028] The check matrix splitting module is used to split the check matrix H into m×n sub-matrices;

[0029] The input buffer is used to divide the total code c into n segments and transmit them to the dynamic reconstruction storage array;

[0030] The dynamically reconstructed storage and calculation array is used to store the sub-matrices and perform the multiplication and accumulation operation of each segment of code and the corresponding sub-matrix, and input the calculation results to the result processing module;

[0031] The result processing module processes the received calculation results to obtain the final encoding result.

[0032] Furthermore, the input buffer is specifically used for:

[0033] The total code c is split into n segments in the input buffer, and each segment is judged to see whether it is a zero vector. If it is a zero vector, the multiplication and accumulation process with the sub-matrix is ​​directly skipped.

[0034] Furthermore, the dynamic reconstruction of the storage and computing array is specifically used for:

[0035] Dynamically allocate computing and storage resources according to the size of the stored submatrix. Multiply and concatenate the i-th segment code with each submatrix in the i-th column in sequence to obtain the i-th intermediate result. Dynamically reconstruct the storage and computing array to finally obtain n intermediate results.

[0036] All intermediate results are sent to the result processing module as calculation results.

[0037] A computer-readable storage medium stores a plurality of classification programs, wherein the plurality of classification programs are used to be called by a processor and execute the encoding method described above.

[0038] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk, etc. Various media that can store program codes.

[0039] The advantages of the encoding method, system and medium based on matrix optimization and storage-computation integrated accelerator provided by the present invention are: 1. Matrix operations are optimized by matrix splitting, and at the same time, matrix calculation acceleration is performed using a storage-computation integrated accelerator to optimize the calculation of encoding (such as LDPC encoding). In terms of computational optimization, the split sub-matrices are stored in the storage-computation integrated core, and multiplication and addition operations are completed directly in the storage unit, eliminating the data handling overhead of the traditional von Neumann architecture; through full parallelization design and dynamic allocation of hardware resources, the rate loss caused by splitting is avoided. Therefore, this embodiment intends to achieve a breakthrough in dynamic adaptability and computational efficiency, and provides a highly reliable, low-latency LDPC encoding solution for tape storage. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of the present invention;

[0041] Figure 2 Schematic diagram of parity check matrix splitting;

[0042] Figure 3 This is a schematic diagram of the storage-computing integrated accelerator architecture;

[0043] Figure 4 Schematic diagram of dynamically reconstructed storage and computing array. DETAILED DESCRIPTION

[0044] The technical solutions of the present invention are described in detail below through specific embodiments. Numerous specific details are set forth in the following description to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0045] like Figures 1 to 4 As shown, the encoding method based on matrix optimization and storage-computing integrated accelerator proposed in the present invention includes the following steps:

[0046] Step 1: Build a storage-computing integrated accelerator, which includes an input buffer, a dynamically reconfigurable storage-computing array, and a result processing module;

[0047] Step 2: The m×n sub-matrices obtained by splitting the a×b check matrix H are stored in the corresponding integrated storage and computation cores of the dynamically reconfigurable storage and computation array, where m and n are two integers, representing the number of sub-matrices obtained by splitting the a×b check matrix H into integers, and a and b are the number of rows and columns of the check matrix H, respectively. That is, the check matrix H is split into m×n parts, and the corresponding LDPC code is split into n parts;

[0048] Step 3: The total code c is divided into n segments through the input buffer and then multiplied and accumulated with the corresponding column sub-matrices respectively. The calculation results of the dynamically reconstructed storage array are input into the result processing module for result processing to obtain the final coding result.

[0049] This embodiment optimizes matrix operations by matrix splitting, and uses a storage-computing accelerator to accelerate matrix calculations to optimize coding (such as LDPC coding). In terms of computational optimization, the split sub-matrices are stored in the storage-computing core, and multiplication and addition operations are performed directly in the storage unit, eliminating the data handling overhead of the traditional von Neumann architecture; through full parallelization design and dynamic allocation of hardware resources, the rate loss caused by splitting is avoided. Therefore, this embodiment intends to achieve breakthroughs in dynamic adaptability and computational efficiency, providing a highly reliable, low-latency LDPC coding solution for tape storage.

[0050] The encoding method of this embodiment can be used in all application scenarios that require matrix calculation. This embodiment uses the matrix calculation in LDPC encoding as an example for explanation, and the encoding method is still applicable in other application scenarios.

[0051] LDPC coding, as an error-correcting code, operates in channel coding and decoding. Channel coding adds parity bits and error-correcting bits to the output of the source code, enabling data to self-detect and self-correct, thereby increasing communication reliability. LDPC coding has related decoding algorithms, such as bit-flipping and belief propagation. However, all decoding algorithms require a parity check matrix H. The parity check matrix H must satisfy the following two formulas:

[0052] H*c T =0;(1)

[0053] G*H T =0;(2)

[0054] Wherein, c is the LDPC code, G is the generator matrix, the generator matrix G satisfies c=s*G, and s is the original code.

[0055] This embodiment is based on the above two matrix calculation formulas (1) and (2) related to the check matrix, simplifies the calculation process through dynamic matrix splitting, and improves the calculation efficiency through the storage and calculation integrated accelerator. This embodiment is aimed at the matrix calculation related to the check matrix H in LDPC coding, and optimizes it through three aspects: new matrix splitting, dynamic reconstruction, and storage and calculation integrated accelerator. The specific solution is as follows:

[0056] 1. Matrix splitting;

[0057] (1-1) Matrix analysis;

[0058] First, let's analyze formulas (1) and (2) in detail. Since the matrix multiplication is 0, the transpose of the matrix multiplication is also 0, so formula (2) can be transformed as follows:

[0059] G*H T =(G*H T ) T =H*G T =0;(3)

[0060] Formula (1) can be transformed as follows:

[0061] H*c T =H*(s*G) T =H*G T *s T =0;(4)

[0062] It can be found that as long as formula (2) holds, G*H T =H*G T =0, then both formulas (1) and (2) will be satisfied. From this perspective, formulas (1) and (2) are equivalent.

[0063] The check matrix H and the generator matrix G always satisfy G*H T = 0, then when LDPC code c is error-free, equations (1) and (2) always equal 0. In fact, there are two points that require attention: 1) The check matrix H and the generator matrix G are in one-to-one correspondence, which means that when discussing LDPC code c, only one of the matrices can be discussed. This embodiment focuses on optimizing the check matrix H. 2) In actual calculations, LDPC code c is prone to errors due to interference. Therefore, when equation (2) holds true, it does not necessarily mean that equation (1) holds true. Therefore, equation (1) still needs to be calculated. This embodiment focuses on accelerating the calculation of equation (1).

[0064] (1-2) Matrix optimization;

[0065] The check matrix H is optimized from the perspective of matrix splitting, and a dynamic matrix splitting scheme is designed for the check matrix H to realize parallel matrix calculation and improve computational efficiency.

[0066] like Figure 1 As shown, for a parity check matrix H of size a×b, the corresponding LDPC code c has a length of n. The parity check matrix H and LDPC code c are split separately. Figure 2Taking the example of a matrix split into 12 sub-matrices (i.e., m = 3, n = 4), the LDPC code c is split into four parts, i.e., four code segments, and only corresponding elements are multiplied. For example, the first code segment is multiplied only by the sub-matrix in the leftmost column of the parity check matrix after the split, and the results are then concatenated. That is, the i-th code segment is multiplied with each sub-matrix in the i-th column in sequence and concatenated to produce the i-th intermediate result.

[0067] In addition, for each code segment, as long as the element is 0, the multiplication result is 0. At this time, the multiplication calculation is redundant. Therefore, it is necessary to check the zero element in advance to avoid redundant calculation. After splicing, 4 vectors are obtained. Then, these 4 vectors are added together to get the same value as H*c T Equivalent calculation results. In LDPC coding, it is usually necessary to perform calculations in the binary domain (mod2), so H*c T The calculated result needs to be modulo 2 to obtain the final encoding result. Finally, the final encoding result is checked to see if it is a zero vector. If it is a zero vector, then the LDPC encoding is error-free. If it is a non-zero vector, then the LDPC encoding is error-free, and decoding algorithms such as bit flipping algorithms and belief propagation algorithms are needed to correct the errors.

[0068] The core of the matrix splitting solution in this embodiment is to split the calculation of multiplying a large matrix and a vector into many small matrices and small vectors (segmented encoding) that can be multiplied in parallel. In these small matrices and small vectors that are multiplied in parallel, it is necessary to check in advance for zero elements in each small vector (segmented encoding). If it is a zero element, the multiplication calculation will be completely skipped and no computing resources will be occupied. This splitting solution is compatible with the subsequent storage and computing integrated accelerator architecture.

[0069] By analyzing the parity check matrix and LDPC code in advance and employing a dynamic splitting scheme with multiple matrix splitting options, the appropriate matrix splitting method can be selected based on the matrix characteristics, and the LDPC code is split accordingly. The split matrices and vectors can then be calculated in full parallelization, achieving extremely high computational efficiency.

[0070] 2. Integrated storage and calculation accelerator;

[0071] The design and parity matrix splitting scheme are compatible with the storage and computing accelerator architecture. The overall architecture is shown in the figure below. Figure 3 As shown, it includes modules such as input buffer, control unit, clock generator, test module, dynamic reconfiguration storage array, result processing module, and global buffer. The focus of this architecture is the input buffer and dynamic reconfiguration storage array.

[0072] The dynamically reconfigurable storage and computing array consists of multiple storage and computing cores. Each storage and computing core contains an 8T SRAM array, a multiplier, an adder tree, and a shift accumulator. The original check matrix H is split into small matrices H 11 、H 12 ,...,H 1n ;H 21 、H 22 ,...,H 2n ;...;H n1 、H n2 ,...,H nn , is stored in such a storage-computing integrated core, the LDPC code c will be input through the input buffer and will be correspondingly split into c1, c2, ..., c n , entering the dynamically reconstructed storage and computation array and multiplying the corresponding submatrices to achieve parallel computation of multiple matrices. Specifically, the computation proceeds as follows: a submatrix is ​​stored in each integrated storage and computation core, multiplied by the corresponding segmented code via a multiplier, and the multiplied results are added through an adder tree and stored in a shift accumulator. After the computation is complete, the result processing module integrates these results, divides by 2, and obtains the final result. It then determines whether the result is a zero vector. If so, the LDPC code is error-free; otherwise, the LDPC code is error-free.

[0073] 3. Dynamic reconstruction;

[0074] This embodiment introduces the idea of ​​dynamic reconstruction, which makes it possible to support matrix calculation more flexibly. Figure 4 As shown in the figure, under ideal conditions, an a×b check matrix H is split into small matrices of the same size k×k. Correspondingly, the SRAM array in each storage-computing core only stores one k×k sub-matrix. This is of course the most ideal and simplest splitting and calculation scheme.

[0075] However, in actual calculations, the storage capacity of the SRAM array is fixed, and the check matrix H is generally also statically fixed. However, the size of the split small matrix is ​​not fixed, so the actual size of the sub-matrix is ​​rounded up according to a multiple of k×k, and the rounded value is used as the number of required storage-computing cores, and the combined storage-computing cores are used as the storage resource of the actual sub-matrix. For example, if the size of the small matrix is ​​(2k)×(2k), then it needs to be stored in the SRAM array of four storage-computing cores, and the calculation also requires four storage-computing cores to calculate together. Therefore, this embodiment is designed as follows Figure 4The dynamically reconfigurable storage and computation array shown can allocate storage and computation resources based on the size of the small matrix to be stored, using the instruction control module and shift-accumulator to complete the multiplication and accumulation calculations of multiple storage-computation cores. For example, if the size of the small matrix to be stored occupies four storage-computation cores, the instruction control module will control these four storage-computation cores to perform storage and computation, and the shift-accumulator will then complete the multiplication and accumulation of the calculation results of these four storage-computation cores.

[0076] This embodiment designs a storage-and-computation accelerator architecture for dynamic matrix splitting. The split sub-matrices can be stored in multiple storage-and-computation cores and computed simultaneously. This integrated storage and computation architecture significantly reduces data handling and further improves computational efficiency. Furthermore, the architecture's instruction control module and multiple shift accumulators also support the dynamic matrix reconfiguration computations of this embodiment, enhancing computational flexibility.

[0077] 4. Combining matrix splitting, dynamic reconstruction, and storage-computing integrated accelerator, the overall process of this embodiment is as follows:

[0078] 1) Analyze the check matrix H and LDPC code c required for calculation, and split the check matrix H into appropriate sub-matrices;

[0079] 2) The submatrix is ​​stored in the dynamically reconstructed storage array, and its storage resources are allocated according to the size of the submatrix. At the same time, the LDPC code c enters the input buffer for segmentation;

[0080] 3) In the dynamically reconstructed storage array, the corresponding sub-matrix and segmented encoding are multiplied and accumulated, and the shift accumulator is used as needed; 4) The calculation result of the dynamically reconstructed storage array enters the result accumulation module of the result processing module for further processing to obtain the calculation result; 5) Finally, the calculation result needs to be divided by 2 to obtain the remainder, that is, the calculation result mod 2, and check whether it is a zero vector to determine H*c T Whether it is a zero vector, that is, whether the LDPC encoding is correct.

[0081] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. The encoding method based on matrix optimization and storage-computation integrated accelerator is characterized by: include: Constructing a storage-computing integrated accelerator, the storage-computing integrated accelerator including an input buffer, a dynamically reconfigurable storage-computing array, and a result processing module; The m×n sub-matrices obtained by splitting the check matrix H are stored in the corresponding storage-computation integrated cores of the dynamically reconstructed storage-computation array respectively; The total code c is divided into n segments through the input buffer and then multiplied and accumulated with the corresponding column sub-matrices respectively. The calculation results of the dynamically reconstructed storage array are input into the result processing module for result processing to obtain the final coding result.

2. The encoding method based on matrix optimization and storage-computation integrated accelerator according to claim 1, characterized in that: The total code c is divided into n segments through the input buffer and then multiplied and accumulated with the corresponding column sub-matrices respectively, specifically: The total code c is split into n segments in the input buffer, and each segment is judged to see if it is a zero vector. If it is a zero vector, the multiplication and accumulation process with the sub-matrix is ​​skipped directly. The i-th segment code is multiplied and concatenated with each submatrix in the i-th column in sequence to obtain the i-th intermediate result. The storage and calculation array is dynamically reconstructed to finally obtain n intermediate results.

3. The encoding method based on matrix optimization and storage-computation integrated accelerator according to claim 2, characterized in that: The calculation result of the dynamically reconstructed storage and calculation array is input into the result processing module for result processing to obtain the final coding result. Specifically, the result processing module adds n intermediate results and then performs binary domain calculation to obtain the final coding result.

4. The encoding method based on matrix optimization and storage-computation integrated accelerator according to claim 3, characterized in that: By performing zero vector judgment on the final coding result, it is determined whether the LDPC coding is wrong. Specifically: Determine whether the final encoding result is a zero vector; If so, there is no error in the LDPC code; If not, there is an error in the LDPC code.

5. The encoding method based on matrix optimization and storage-computation integrated accelerator according to claim 1, characterized in that: The sub-matrices are stored in the corresponding storage-computation integrated cores of the dynamically reconstructed storage-computation array. The dynamic reconstruction algorithm supports the storage of sub-matrices of different sizes in the corresponding storage-computation integrated cores. Specifically: Ideally, the check matrix H is split into k×k sub-matrices of the same size, and each storage-computation core stores one k×k sub-matrix. In actual conditions, the size of the split sub-matrix is ​​uncertain. The actual size of the split sub-matrix is ​​rounded up to a multiple of k×k, and the rounded value is used as the number of required storage-computation integrated cores. The combined storage-computation integrated cores are used as the storage resources of the actual sub-matrix.

6. The encoding method based on matrix optimization and storage-computation integrated accelerator according to claim 2, characterized in that: Each storage-computing core includes an 8T SRAM array, a multiplier, an adder tree, and a shift accumulator. A sub-matrix is ​​stored in each storage-computation core, and the sub-matrix is ​​multiplied by the corresponding segment code through a multiplier; The multiplication results are added through the adder tree and stored in the shift accumulator.

7. The coding system based on matrix optimization and storage-computation integrated accelerator is characterized by: It includes a check matrix splitting module and a storage-computation integrated accelerator, wherein the storage-computation integrated accelerator includes an input buffer, a dynamically reconstructed storage-computation array, and a result processing module; The check matrix splitting module is used to split the check matrix H into m×n sub-matrices; The input buffer is used to divide the total code c into n segments and transmit them to the dynamic reconstruction storage array; The dynamically reconstructed storage and calculation array is used to store the sub-matrices and perform the multiplication and accumulation operation of each segment of code and the corresponding sub-matrix, and input the calculation results to the result processing module; The result processing module processes the received calculation results to obtain the final encoding result.

8. The encoding system based on matrix optimization and storage-computation integrated accelerator according to claim 7, characterized in that: The input buffer is specifically used for: The total code c is split into n segments in the input buffer, and each segment is judged to see whether it is a zero vector. If it is a zero vector, the multiplication and accumulation process with the sub-matrix is ​​directly skipped.

9. The encoding system based on matrix optimization and storage-computation integrated accelerator according to claim 7, characterized in that: Dynamically reconstructing the storage and computing array is specifically used for: Dynamically allocate computing and storage resources according to the size of the stored submatrix. Multiply and concatenate the i-th segment code with each submatrix in the i-th column in sequence to obtain the i-th intermediate result. Dynamically reconstruct the storage and computing array to finally obtain n intermediate results. All intermediate results are sent to the result processing module as calculation results.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a plurality of classification programs, which are used to be called by a processor and execute any one of the encoding methods 1 to 6.

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