Memory controller, memory device, and operation method of memory controller

Abstract

The invention provides a memory controller, a memory device, and an operation method of the memory controller. The memory controller may store data in the non-volatile memory device or read data from the non-volatile memory device based on an external request; and schedule a processing performance of a processing operation for the external request and an internal management operation of the nonvolatile memory device based on an occurrence frequency of the logical address included in the external request.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0037109, filed on March 18, 2024, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor integrated device, and more particularly, to a memory controller, a memory device including the memory controller, and an operating method of the memory controller. Background Art

[0004] The storage device is electrically connected to an external device and performs data input and output operations based on a request from the external device. The storage device can use various storage media to store data, and a non-volatile memory device such as a flash memory can be used as the storage medium.

[0005] Flash memory cannot be rewritten or updated in place, and the read / write unit and erase unit in flash memory are different from each other. Therefore, in order to process the read / write request from the external device, the flash memory must map the logical address provided by the external device to the physical address.

[0006] Mapping information between the logical address and the physical address is stored in the non-volatile memory device and can be loaded into the buffer memory device for use.

[0007] The buffer memory devices may include volatile memory devices and require refreshing in order to prevent data loss. Summary of the Invention

[0008] In an embodiment of the present disclosure, a memory controller can store data in a non-volatile memory device or read data from a non-volatile memory device based on an external request; and schedule processing performance of processing operations for external requests and internal management operations of the non-volatile memory device based on the frequency of occurrence of logical addresses included in the external requests.

[0009] In an embodiment of the present disclosure, a storage device may include: a non-volatile memory device; a volatile memory device configured to store mapping data, the mapping data including mapping information between logical addresses and physical addresses corresponding to data stored in the non-volatile memory device; and a memory controller configured to schedule processing operations for external requests and processing performance of internal management operations of the non-volatile memory device based on information about a location in the volatile memory device where the mapping data associated with the external request is stored.

[0010] In an embodiment of the present disclosure, a method for operating a memory controller that controls a storage medium may include: when an external request is received, determining, by the memory controller, the frequency of occurrence of a logical address included in the external request; and scheduling, by the memory controller, processing performance of processing operations for the external request and internal management operations of the storage medium based on the determination result.

[0011] Embodiments of the present disclosure may provide a memory controller, a memory device including the memory controller, and an operating method of the memory controller, which may prevent concentrated access to a buffer memory device.

[0012] According to an embodiment of the present disclosure, when external requests that centrally access a specific area of ​​a cache memory device are detected, attacks against the cache memory device can be prevented by processing internal management operations with priority over external requests. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a configuration of a data processing system according to an embodiment of the present disclosure.

[0014] Figure 2 is a diagram illustrating a configuration of a memory controller according to an embodiment of the present disclosure.

[0015] Figure 3 is a diagram illustrating a configuration of a buffer memory device according to an embodiment of the present disclosure.

[0016] Figure 4 is a diagram illustrating a configuration of a memory cell array included in a buffer memory device according to an embodiment of the present disclosure.

[0017] Figure 5 is a diagram illustrating a configuration of a processor according to an embodiment of the present disclosure.

[0018] Figure 6 is a diagram illustrating a configuration of a row hammer prevention circuit according to an embodiment of the present disclosure.

[0019] Figure 7 is a flowchart describing an operating method of a memory controller according to an embodiment of the present disclosure.

[0020] Figure 8 is a diagram illustrating a configuration of a data processing system according to an embodiment of the present disclosure.

[0021] Figure 9 is a diagram illustrating a configuration of a network system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a diagram showing the configuration of a data processing system 10 according to an embodiment of the present disclosure.

[0024] Reference Figure 1 , the data processing system 10 may include an external device (ie, a host device) 100 and a storage device 200 .

[0025] The external device 100 may include at least one processor. The external device 100 itself may be a processor, or may be an electronic device or system including a processor.

[0026] The memory device 200 may include a memory controller 210, a buffer memory device 220, and a storage medium 260. The storage medium 260 may include at least a plurality of nonvolatile memory devices 230, 240, and 250.

[0027] The external device 100 may send a write request including a write command WT, an address ADD, and write data DATA to the memory device 200 to write data. In response, the memory device 200 may operate so that the write data is programmed into the storage medium 260.

[0028] The external device 100 may send a read request including a read command RD and an address ADD to the memory device 200 to read data. The memory device 200 may read the requested data DATA from the storage medium 260 and send the data DATA to the external device 100.

[0029] In addition to read operations or write operations for reading data from or writing data to the storage medium 260 in response to a read or write request from the external device 100, the storage device 200 may also perform internal management operations for managing the storage medium 260. The internal management operations may include internal management operations (e.g., garbage collection operations, wear leveling operations, or read reclaim operations) that are performed independently of a request from the external device 100 in order to efficiently use the storage space of the storage medium 260 or ensure the reliability of data stored in the storage medium 260.

[0030] The storage medium 260 may be electrically coupled to the memory controller 210 via one or more channels CH1 to CHn, and may include one or more non-volatile memory devices NVM1 and NVM2 to NVMn. In embodiments, the non-volatile memory devices NVM1 and NVM2 to NVMn may include at least one of various non-volatile memory devices, such as NAND flash memory, NOR flash memory, ferroelectric RAM (FRAM) using ferroelectric capacitors, magnetic RAM (MRAM) using tunnel magnetoresistive (TMR) thin films, phase change memory (PRAM) using chalcogenide alloys, and resistive random access memory (RERAM) using transition metal oxides.

[0031] Each of the nonvolatile memory devices NVM1 and NVM2 to NVMn may include a plurality of memory cells. Each memory cell may operate as a single-level cell (SLC) capable of storing 1 bit of data or a multi-level cell (MLC) capable of storing 2 or more bits of data.

[0032] Each of the nonvolatile memory devices NVM1 and NVM2 to NVMn can operate as an SLC memory device or as an MLC memory device. Alternatively, some of the nonvolatile memory devices NVM1 and NVM2 to NVMn can each be configured to operate as an SLC memory device, and some of the nonvolatile memory devices NVM1 and NVM2 to NVMn can each be configured to operate as an MLC memory device.

[0033] After a write or read operation begins, the buffer memory device 220 can temporarily store data transmitted and received between the external device 100 and the storage device 200. The buffer memory device 220 can also temporarily store mapping data. The mapping data can be mapping information between addresses (e.g., physical addresses) constituting the physical storage space of the storage medium 260 and logical addresses assigned to the storage medium 260 by the external device.

[0034] The mapping data may be stored in the storage medium 260. The memory controller 210 may use the mapping data by loading the buffer memory device 220, at least in part, the mapping data required for the operation of the memory device 200.

[0035] Figure 2 is a diagram illustrating a configuration of the memory controller 210 according to an embodiment of the present disclosure.

[0036] Reference Figure 2 , the memory controller 210 may include a processor 211 , an external device interface 213 , an operating memory (or working memory) 215 , and a storage interface 217 .

[0037] The processor 211 can operate by running firmware or software provided for various operations of the memory controller 210 on the hardware of the memory controller 210. The processor 211 can be implemented in the form of a combination of hardware and firmware or software running on the hardware. In an embodiment, the processor 211 can perform functions for managing the flash translation layer (FTL) of the storage device 200, such as address mapping, block management, garbage collection, or wear leveling.

[0038] The external device interface 213 may receive commands and clock signals from the external device 100 under the control of the processor 211 and may provide a communication channel for controlling data input and output. Specifically, the external device interface 213 may provide a physical connection between the external device 100 and the storage device 200.

[0039] In an embodiment, the external device interface 213 can communicate with the external device 100 based on an interface using at least one of various communication standards or interfaces such as: Universal Serial Bus (USB) protocol, MultiMediaCard (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI-Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA) protocol, Parallel ATA (PATA) protocol, Small Computer System Interface (SCSI) protocol, Enhanced MiniDisk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, proprietary protocol, System Management Bus (SMBus) protocol, Inter-Integrated Circuit (I2C) protocol, and Improved Inter-Integrated Circuit (I3C) protocol.

[0040] The external device interface 213 may store write data provided by the external device 100 in the buffer memory device 220 under the control of the processor 211. In addition, the external device interface 213 may provide the external device 100 with read data read from the storage medium 260 and stored in the buffer memory device 220.

[0041] The operating memory 215 may include a random access memory device (RAM), such as a dynamic random access memory (DRAM) or a static random access memory (SRAM). The operating memory 215 may store firmware driven by the processor 211. In addition, the operating memory 215 may store data required to drive the firmware, such as metadata.

[0042] The operation memory 215 may operate as a buffer memory, and stores write data provided by the external device 100 , read data read from the storage medium 260 , or map data.

[0043] The storage interface 217 can provide a communication channel for signal transmission and reception between the memory controller 210 and the storage medium 260. The storage interface 217 can write data temporarily stored in the buffer memory device 220 to the storage medium 260 under the control of the processor 211. In addition, the storage interface 217 can temporarily store read data read from the storage medium 260 by transmitting the read data to the buffer memory device 220 under the control of the processor 211.

[0044] Figure 3 is a diagram illustrating a configuration of a buffer memory device 2200 according to an embodiment of the present disclosure.

[0045] Figure 3 The buffer memory device 2200 may be configured as Figure 1 The buffer memory device 220 shown in Figure 2 The operating memory 215 is shown in FIG.

[0046] Reference Figure 3 The buffer memory device 2200 may include a memory cell array 2210 , a row decoder 2220 , a sense amplifier 2230 , a column decoder 2240 , a refresh control circuit 2250 , a command decoder 2260 , an address buffer 2270 , and a data input / output circuit 2280 .

[0047] The memory cell array 2210 may include a plurality of memory cells arranged in row and column directions. The plurality of memory cells may include main cells for storing data and redundant cells for replacing memory cells in which errors occur.

[0048] Figure 4 2 is a diagram illustrating a configuration of a memory cell array 2210 included in a buffer memory device 2200 according to an embodiment of the present disclosure.

[0049] Figure 4 A memory cell array 2210 comprising DRAM cells is shown.

[0050] Reference Figure 4 , the memory cell array 2210 may include memory cells MC arranged between a plurality of word lines WL1 , WL2 , . . . and a plurality of bit lines BL1 , BL2 , BL3 , . . .

[0051] Each memory cell MC may include a select element SE and a capacity element CE. The select element SE may operate based on the voltage of a corresponding word line among word lines WL1, WL2, ... When a corresponding word line among word lines WL1, WL2, ... is activated, the select element SE may be turned on and may electrically couple the capacity element CE to a corresponding bit line among bit lines BL1, BL2, BL3, ... When a corresponding word line among word lines WL1, WL2, ... is deactivated, the select element SE may be turned off and may electrically separate the capacity element CE from the corresponding bit line among bit lines BL1, BL2, BL3, ...

[0052] The capacitance element CE may be electrically coupled between the selection element SE and a common node to which a common voltage VC is applied. The capacitance element CE may include a capacitor. The capacitance element CE may store data bits by storing charge according to a voltage transmitted by the selection element SE from a corresponding bit line among the bit lines BL1, BL2, BL3, ...

[0053] Return to reference Figure 3 The command decoder 2260 can internally generate a decoded control signal (e.g., an activation signal, a read signal, a write signal, or a refresh signal) by receiving and decoding a command CMD1 applied by control logic (not shown). The refresh control circuit 2250 can receive the refresh signal from the command decoder 2260 and output a row address of a word line for refreshing the memory cell array 2210 to the row decoder 2220.

[0054] The control logic may send an address ADD1 and a command CMD1 to the buffer memory device 2200. The address ADD1 specifies a memory cell to read / write data. The address buffer 2270 may generate a row / column address by receiving the address ADD1 from the control logic.

[0055] The row decoder 2220 can decode the row address output by the refresh control circuit 2250 or the address buffer 2270 to specify a word line of the memory cell array 2210. That is, after a write / read operation begins, the row decoder 2220 can enable the word line electrically coupled to the memory cell to which data is to be written / read by decoding the row address output by the address buffer 2270. Furthermore, the row decoder 2220 can refresh the corresponding word line based on the row address generated by the refresh control circuit 2250.

[0056] The sense amplifier 2230 can sense and amplify data of a memory cell electrically connected to a word line specified by the row decoder 2220 and can store the data of the memory cell. In addition, the column decoder 2240 can decode the column address output by the address buffer 2270 to specify a bit line electrically connected to a memory cell that inputs or outputs data.

[0057] The data input / output circuit 2280 can output data from a memory cell specified by the address ADD1 in the memory cell array 2210, or input data to the corresponding memory cell. Data input through the data input / output circuit 2280 can be written to the memory cell array 2210 based on the address ADD1, or data read from the memory cell array 2210 based on the address ADD1 can be output to the control logic through the data input / output circuit 2280.

[0058] When a specific word line is activated and data is written or read, a voltage change may occur in a capacity element of a memory cell electrically coupled to the activated word line.

[0059] Voltage variations in the capacitance elements of memory cells electrically coupled to an activated word line can cause coupling-induced voltage variations in capacitance elements of memory cells included in subsequent word lines. These coupling-induced voltage variations can induce stress in the memory cells and potentially lead to data bit errors.

[0060] When specific word lines are activated intensively, a row hammer phenomenon may occur, in which data is distorted due to increased stress applied to memory cells of consecutive word lines.

[0061] To prevent data loss due to row hammering, a known approach is to frequently refresh consecutive word lines while the corresponding word lines are being accessed. Frequent refreshes can degrade memory system performance because excessive power is consumed because voltage must be applied to the word lines being refreshed and the memory cells being refreshed cannot be accessed while the refresh is being performed.

[0062] In the data processing system 10 or the storage device 200 storing mapping data in the buffer memory device 2200 , row hammering may occur when a specific logical address or a specific logical address range is frequently accessed.

[0063] Figure 5 is a diagram illustrating a configuration of the processor 211 according to an embodiment of the present disclosure.

[0064] Reference Figure 5 , the processor 211 may include a write processing circuit 310 , a read processing circuit 320 , a mapping management circuit 330 , an internal operation processing circuit 340 , and a row hammering prevention circuit 350 .

[0065] The write processing circuit 310 may control the storage medium 260 to program write data. The write data may be data provided by the external device 100 along with a write request of the external device 100 or data associated with an internal management operation of the storage device 200.

[0066] The read processing circuit 320 can control the storage medium 260 to read data in a specific physical area from the storage medium 260. The read operation can be performed based on a read request and a logical address from the external device 100, or can be performed in association with an internal management operation of the storage device 200. The data read from the storage medium 200 based on the read request from the external device 100 can be provided to the external device 100.

[0067] The mapping management circuit 330 may control the nonvolatile memory device 260 and the buffer memory device 220 to perform operations related to the mapping data. The operations related to the mapping data may include mapping cache operations and mapping update operations.

[0068] When the external device 100 provides a write request, a logical address to be written, and write data, the processor 211 can perform a mapping update operation, that is, by driving the mapping management circuit 330, store in the buffer memory device 220 mapping data in which the physical address where the write data is to be stored is mapped to the logical address to be written, and update the address mapping table stored in the storage medium 260 based on the mapping data stored in the buffer memory device 220.

[0069] In addition, the processor 211 may perform a mapping cache operation, ie, cache mapping data corresponding to logical addresses frequently or recently requested to be read by the external device 100 in the buffer memory device 220 by driving the mapping management circuit 330 .

[0070] The internal operation processing circuit 340 can perform internal management operations on the storage medium 260 regardless of the request from the external device 100. If the operation performed in response to the request from the external device 100 is a foreground operation, the internal management operation autonomously processed by the processor 211 can be represented as a background operation. In an embodiment, the internal management operation can be at least one of a wear leveling operation, a garbage collection operation, and a read reclaim operation.

[0071] The row hammer prevention circuit 350 may schedule processing performance for processing operations for external requests and internal management operations of the storage medium 260 based on the frequency of occurrence of a logical address included in an external request of the external device 100 .

[0072] From another perspective, the row hammering prevention circuit 350 may schedule processing performance of processing operations for external requests and internal management operations based on access frequency to the buffer memory device 220 in order to read mapping data corresponding to a logical address included in the external request.

[0073] To schedule processing performance, the row hammering prevention circuit 350 may use various scheduling methods, such as adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity allocation ratio, and a priority level.

[0074] In an embodiment, when the number of read requests for a specific logical address or a specific logical address range repeatedly received within a set time reaches above a set threshold, the row hammer prevention circuit 350 can determine that row hammering has occurred and schedule the processing performance of internal management operations so that the processing performance of internal management operations is higher than the processing performance of processing operations for external requests.

[0075] In an embodiment, when it is determined that row hammering will occur, the row hammering prevention circuit 350 may utilize various scheduling methods, such as allocating more credits, allocating more resources, providing greater processing opportunities, or assigning higher priorities to internal management operations compared to processing operations for external requests.

[0076] Figure 6 is a diagram illustrating a configuration of a row hammer prevention circuit 350 according to an embodiment of the present disclosure.

[0077] Reference Figure 6 The row hammering prevention circuit 350 may include an external request monitoring circuit 351 , an attack sensing circuit 353 , and a scheduler 355 .

[0078] The external request monitoring circuit 351 may count the number of occurrences of a logical address by receiving the logical address included in a read request from the external device 100. In an embodiment, the read request may include a specific logical address or a specific logical address range. The external request monitoring circuit 351 may count the number of occurrences of each logical address or each logical address range.

[0079] The attack sensing circuit 353 may determine the row hammering possibility based on the number of occurrences (ie, frequency) of a specific logical address range or a specific logical address counted within a set time.

[0080] To read data stored in the storage medium 260, the mapping management circuit 330 can obtain a physical address corresponding to the logical address included in the read request by accessing the mapping data of the buffer memory device 220. When read requests for a specific logical address range or a specific logical address repeatedly occur within a set time, the attack sensing circuit 353 can predict that a row hammer attack will occur in the memory area of ​​the buffer memory device 220 that caches the mapping data associated with the read request.

[0081] When the row hammer possibility is predicted, the scheduler 355 may schedule processing performance of processing operations for external requests from the external device 100 and internal management operations.

[0082] To schedule processing performance, the scheduler 355 may utilize various scheduling methods, such as adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity allocation ratio, and a priority.

[0083] In an embodiment, when row hammering is predicted, the scheduler 355 may allocate more credits, allocate more resources, provide greater processing opportunities, or assign a higher priority to internal management operations than to processing operations for external requests.

[0084] Figure 7 is a flowchart for describing an operating method of a memory controller according to an embodiment of the present disclosure.

[0085] When the memory device 200 operates, the memory controller 210 may count the number of occurrences of each specific logical address or logical address range by monitoring the logical addresses included in a read request of the external device 100 ( S101 ).

[0086] The memory controller 210 may determine the likelihood of row hammering based on the number of occurrences of a specific logical address range or a specific logical address counted within a set time (S103). Specifically, if read requests for the specific logical address repeatedly occur within a set time and exceed a set threshold, the memory controller 210 may predict that a row hammer attack will occur in the row line of the buffer memory device 220 that stores the mapping data associated with the read request.

[0087] When the row hammer possibility is predicted (YES in S103 ), the memory controller 210 may schedule processing performance of a processing operation for an external request from the external device 100 and an internal management operation ( S105 ).

[0088] In an embodiment, the memory controller 210 may utilize various scheduling methods, such as allocating more credits, allocating more resources, providing greater processing opportunities, or assigning higher priorities to internal management operations than to processing operations for external requests.

[0089] When the row hammer possibility is not predicted (No in S103 ), the memory controller 210 may continue to monitor the external request ( S101 ).

[0090] Figure 8 4000 is a diagram illustrating a configuration of a data processing system 4000 according to an embodiment of the present disclosure.

[0091] Reference Figure 8 , the data processing system 4000 may include a host device 4100 and a memory system 4200 .

[0092] The host device 4100 may be constructed in the form of a circuit board, such as a printed circuit board. Although not shown, the host device 4100 may further include a background function block that performs host device functions.

[0093] The memory system 4200 may be constructed in the form of a surface mount package and may be mounted on the host device 4100 via solder balls 4250. The memory system 4200 may include a controller 4210, a buffer memory device 4220, and a nonvolatile memory device 4230.

[0094] The controller 4210 may control the overall operation of the memory system 4200. The controller 4210 may include Figure 5 and Figure 6 Row hammer prevention circuit 350 is shown.

[0095] The buffer memory device 4220 may temporarily store data to be stored in the nonvolatile memory device 4230 or data read from the nonvolatile memory device 4230. In addition, the buffer memory device 4220 may store mapping data, that is, address mapping between a logical address of an external device and a physical address of the nonvolatile memory device 4230.

[0096] The nonvolatile memory device 4230 may be used as a storage medium of the memory system 4200 .

[0097] Since the controller 4210 includes the row hammer prevention circuit 350 , stress applied to the buffer memory device 4220 may be reduced by detecting malicious repeated read operations for a specific logical address.

[0098] Figure 9 5 is a diagram illustrating a configuration of a network system 5000 according to an embodiment of the present disclosure.

[0099] Reference Figure 9 , the network system 5000 may include a plurality of client systems 5410 to 5430 , which are electrically connected to the server system 5300 via a network 5500 .

[0100] The server system 5300 may provide data based on requests from the plurality of client systems 5410 to 5430. For example, the server system 5300 may store data provided by the plurality of client systems 5410 to 5430. For another example, the server system 5300 may provide data to the plurality of client systems 5410 to 5430.

[0101] The server system 5300 may include a host device 5100 and a memory system 5200. The memory system 5200 may include Figure 1 The storage device 200 or Figure 8 The memory system 4200 includes a row hammering prevention circuit 350.

[0102] As described above, it will be understood by those skilled in the art that the embodiments of the present disclosure can be implemented in various other forms without departing from the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the above embodiments are described from various aspects and are not restrictive. The scope of the present disclosure is defined by the appended claims rather than the detailed description, and all modifications or changes derived from the meaning and scope of the claims and their equivalents should be understood to be included within the scope of the present disclosure. In addition, the embodiments can be combined to form other embodiments.

Claims

1. A memory controller for controlling a nonvolatile memory device, the memory controller: storing data in the nonvolatile memory device or reading data from the nonvolatile memory device based on an external request; and Based on the frequency of occurrence of the logical address included in the external request, processing performance of a processing operation for the external request and an internal management operation of the nonvolatile memory device is scheduled.

2. The memory controller according to claim 1, wherein: The memory controller determines the occurrence frequency based on a specific logical address range or a specific logical address.

3. The memory controller according to claim 1, wherein: The memory controller schedules the processing performance by adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity allocation ratio, and a priority level.

4. The memory controller according to claim 1 , wherein: The external request comprises a read request; and When the number of read requests for a specific logical address range or a specific logical address repeatedly received within a set time reaches or exceeds a set threshold, the memory controller increases the processing performance of the internal management operation to a higher level than the processing performance of the external request processing operation.

5. The memory controller according to claim 1, wherein: The internal management operation includes at least one of a garbage collection operation, a wear leveling operation, and a read reclaim operation.

6. A storage device comprising: non-volatile memory devices; a volatile memory device storing mapping data including mapping information between logical addresses and physical addresses corresponding to data stored in the nonvolatile memory device; as well as A memory controller schedules processing performance of a processing operation for the external request and an internal management operation of the nonvolatile memory device based on information about a location in the volatile memory device where mapping data associated with the external request is stored.

7. The storage device according to claim 6, wherein: The external request includes a logical address; and The memory controller schedules the processing performance based on an access frequency of the volatile memory device to read mapping data corresponding to the logical address. The storage device according to claim 6 , wherein: The memory controller schedules the processing performance by adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity allocation ratio, and a priority level.

9. The storage device according to claim 6, wherein: The external request comprises a read request; and When the number of read requests for a specific logical address range or a specific logical address repeatedly received within a set time reaches or exceeds a set threshold, the memory controller increases the processing performance of the internal management operation to a higher level than the processing performance of the external request processing operation.

10. The storage device according to claim 6, wherein: The internal management operation includes at least one of a garbage collection operation, a wear leveling operation, and a read reclaim operation.

11. A method for operating a memory controller, wherein the memory controller controls a storage medium, the method comprising: When an external request is received, determining, by the memory controller, an occurrence frequency of a logical address included in the external request; as well as By the memory controller, processing performance for a processing operation for the external request and an internal management operation of the storage medium is scheduled based on the determination result.

12. The operating method according to claim 11, wherein: Determining the occurrence frequency includes determining the occurrence frequency based on a specific logical address range or a specific logical address.

13. The operating method according to claim 11, wherein: Scheduling the processing performance includes scheduling the processing performance by adjusting at least one of a credit allocation ratio, a computer resource allocation ratio, a processing opportunity allocation ratio, and a priority.

14. The operating method according to claim 11, wherein: The external request includes a read request; Determining the occurrence frequency includes determining whether the number of read requests for a specific logical address range or a specific logical address repeatedly received within a set time exceeds a set threshold; and Scheduling the processing performance includes increasing the processing performance of the internal management operation to be higher than the processing performance of the processing operation for the external request.

15. The operating method according to claim 11, wherein: The internal management operation includes at least one of a garbage collection operation, a wear leveling operation, and a read reclaim operation.

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