Instruction buffer circuit, instruction buffer method, chip, and electronic device

Abstract

The invention discloses an instruction buffer circuit, an instruction buffer method, a chip and electronic equipment, and relates to the technical field of integrated circuits. The circuit comprises a cycle detection circuit, a write-in circuit and a buffer. The cycle detection circuit is used for acquiring the type of the instruction and sending the type of the instruction to the write-in circuit; the writing circuit is used for writing the instruction into the buffer or transmitting the instruction to the instruction execution circuit on the basis of the acquired instruction number, the instruction number stored in the buffer and the instruction number required by the instruction execution circuit under the condition that the type of the instruction indicates that the instruction is a universal instruction; when the type of the instruction indicates that the instruction is an instruction of a loop body, writing the instruction into a buffer; and the buffer is used for sharing the storage space by the general instruction and the instruction of the loop body. According to the scheme, it can be avoided that ibuf and lbuf are designed respectively, the chip area is saved, and the timeliness of instruction execution is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular to an instruction buffer circuit, an instruction buffer method, a chip, and an electronic device. Background Art

[0002] A processor typically includes an instruction buffer (ibuf) and a loop buffer (lbuf). The ibuf is used to cache instructions fetched by the instruction fetch unit if the subsequent stages of the instruction fetch unit are blocked, allowing the instruction fetch unit to continue fetching instructions. The lbuf is used to cache loop body instructions. When loop body instructions need to be executed, the loop body instructions can be directly read from the lbuf, without repeatedly accessing the instruction cache (icache) used to store all instructions. This improves the efficiency of fetching loop body instructions and reduces the power consumption caused by accessing the icache. Summary of the Invention

[0003] This application provides an instruction buffer circuit, instruction buffer method, chip, and electronic device for implementing the overall design of ibuf and lbuf. The technical solution includes the following contents.

[0004] On the one hand, an instruction buffer circuit is provided, which includes a loop detection circuit, a write circuit and a buffer. The write circuit is respectively connected to the loop detection circuit, the buffer and an instruction execution circuit located outside the instruction buffer circuit, and the buffer is also connected to the instruction execution circuit; the loop detection circuit is used to obtain the type of instruction and send the type of instruction to the write circuit; the write circuit is used to write the instruction into the buffer or transfer the instruction to the instruction execution circuit based on the number of instructions obtained, the number of instructions stored in the buffer and the number of instructions required by the instruction execution circuit when the type of instruction indicates that the instruction is a general instruction; the write circuit is also used to write the instruction into the buffer when the type of instruction indicates that the instruction is an instruction of a loop body; the buffer is used for general instructions and loop body instructions to share storage space.

[0005] In one possible implementation, the loop detection circuit includes an end recording circuit and an end matching circuit, wherein the end matching circuit is connected to the end recording circuit and the writing circuit, respectively; the end recording circuit is used to obtain an instruction stream within a first time period, and when the instruction stream within the first time period includes a target conditional branch instruction, record the address of the next instruction to be executed of the target conditional branch instruction, the target conditional branch instruction being a conditional branch instruction whose branch prediction result is a jump and whose jump offset is negative; the end recording circuit is also used to obtain an instruction stream within a second time period, and when the instruction stream within the second time period includes the target conditional branch instruction, transmit the address of the next instruction to be executed of the target conditional branch instruction and the recorded address of the instruction to be executed to the end matching circuit, wherein the second time period is later than the first time period; the end matching circuit is used to determine that the instructions to be executed to the target conditional branch instruction are all loop body instructions based on the address of the next instruction to be executed of the target conditional branch instruction being the same as the address of the recorded instruction to be executed; determine that the instructions to be executed to the target conditional branch instruction are all general instructions based on the address of the next instruction to be executed of the target conditional branch instruction being different from the address of the recorded instruction to be executed; and send the determined instruction type to the writing circuit.

[0006] In one possible implementation, the loop detection circuit also includes a backfill completion judgment circuit, which is connected to the end matching circuit and the write circuit respectively; the end matching circuit is also used to send the instructions of the loop body to the backfill completion judgment circuit; the backfill completion judgment circuit is used to determine whether the last instruction of the instructions of the loop body is written into the buffer by the write circuit based on the instructions of the acquired loop body; the backfill completion judgment circuit is also used to send a record instruction to the write circuit when it is determined that the last instruction of the instructions of the loop body is written into the buffer by the write circuit, and the record instruction is used to instruct the write circuit to record the storage location of the instructions of the loop body in the buffer.

[0007] In one possible implementation, the instruction buffer circuit also includes a reading circuit, which is connected to the buffer and the instruction execution circuit respectively; the reading circuit is used to read instructions from the buffer based on the number of instructions required by the instruction execution circuit and the number of instructions stored in the buffer; and transmit the read instructions to the instruction execution circuit.

[0008] In one possible implementation, the instruction buffer circuit also includes an end detection circuit, which is connected to the write circuit and the read circuit respectively; the read circuit is also used to transmit the read instruction to the end detection circuit; the end detection circuit is used to predict the jump result of the conditional branch instruction when the read instruction includes a conditional branch instruction; based on the jump result being no jump or jump and the jump offset being positive, the loop is determined to be over, and a clear instruction is sent to the write circuit to instruct the write circuit to clear the storage location of the recorded loop body instructions in the buffer.

[0009] On the other hand, an instruction buffering method is provided, which is executed by an instruction buffer circuit, wherein the instruction buffer circuit includes a loop detection circuit, a write circuit and a buffer, wherein the write circuit is respectively connected to the loop detection circuit, the buffer and an instruction execution circuit located outside the instruction buffer circuit, and the buffer is also connected to the instruction execution circuit; the method includes: obtaining the type of instruction through the loop detection circuit, and sending the type of instruction to the write circuit; when the type of instruction indicates that the instruction is a general instruction, the write circuit writes the instruction into the buffer or transmits the instruction to the instruction execution circuit based on the number of instructions obtained, the number of instructions stored in the buffer and the number of instructions required by the instruction execution circuit; when the type of instruction indicates that the instruction is an instruction of a loop body, the write circuit writes the instruction into the buffer, and the general instruction and the instructions of the loop body share the storage space of the buffer.

[0010] In one possible implementation, the loop detection circuit includes an end recording circuit and an end matching circuit, wherein the end matching circuit is connected to the end recording circuit and the writing circuit, respectively. Acquiring the instruction type through the loop detection circuit and sending the instruction type to the writing circuit includes:

[0011] Obtaining an instruction stream within a first time period through an epilogue recording circuit, and recording an address of a next instruction to be executed after the target conditional branch instruction when the instruction stream within the first time period includes a target conditional branch instruction, wherein the target conditional branch instruction is a conditional branch instruction whose branch prediction result is a jump and whose jump offset is negative;

[0012] obtaining an instruction stream within a second time period through an epilogue recording circuit, and transmitting an address of an instruction to be executed next to the target conditional branch instruction and the recorded address of the instruction to be executed to an epilogue matching circuit when the instruction stream within the second time period includes a target conditional branch instruction, wherein the second time period is later than the first time period;

[0013] Through the end matching circuit, based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is the same as the address of the recorded instruction to be executed, it is determined that the instructions to be executed to the target conditional branch instruction are all instructions of the loop body; based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is different from the address of the recorded instruction to be executed, it is determined that the instructions to be executed to the target conditional branch instruction are all general instructions; and the determined instruction type is sent to the write circuit.

[0014] In one possible implementation, the loop detection circuit also includes a backfill completion judgment circuit, which is connected to the end matching circuit and the write circuit respectively; the method also includes: sending the instructions of the loop body to the backfill completion judgment circuit through the end matching circuit; determining through the backfill completion judgment circuit based on the instructions of the loop body obtained, whether the last instruction in the instructions of the loop body is written into the buffer by the write circuit; and sending a record instruction to the write circuit when the backfill completion judgment circuit determines that the last instruction is written into the buffer by the write circuit, the record instruction being used to instruct the write circuit to record the storage location of the instructions of the loop body in the buffer.

[0015] In one possible implementation, the instruction buffer circuit also includes a reading circuit, which is connected to the buffer and the instruction execution circuit respectively; the method also includes: reading instructions from the buffer through the reading circuit based on the number of instructions required by the instruction execution circuit and the number of instructions stored in the buffer; and transmitting the read instructions to the instruction execution circuit.

[0016] In one possible implementation, the instruction buffer circuit also includes an end detection circuit, which is connected to the write circuit and the read circuit respectively; the method also includes: transmitting the read instruction to the end detection circuit through the read circuit; predicting the jump result of the conditional branch instruction through the end detection circuit when the read instruction includes a conditional branch instruction; determining the end of the loop based on the jump result being no jump or jump and the jump offset being positive, and sending a clear instruction to the write circuit to instruct the write circuit to clear the storage location of the recorded loop body instructions in the buffer.

[0017] On the other hand, a chip is provided, which includes any of the above-mentioned instruction buffer circuits.

[0018] On the other hand, an electronic device is provided, which includes the above chip.

[0019] The technical solution provided by this application brings at least the following beneficial effects:

[0020] In the technical solution provided by the present application, the type of instruction acquired by the writing circuit is determined. If the instruction type indicates that the instruction is a general instruction, the instruction is written into the buffer or transmitted to the instruction execution circuit based on the number of instructions acquired, the number of instructions stored in the buffer, and the number of instructions required by the instruction execution circuit. If the instruction type indicates that the instruction is a loop body instruction, the instruction is written into the buffer. The general instructions and the loop body instructions share storage space in the buffer.

[0021] Thus, this technical solution can realize the functions of ibuf and lbuf with a single buffer, realizing the integrated design of ibuf and lbuf. Therefore, this technical solution can avoid the separate design of ibuf and lbuf, saving chip area and improving the timeliness of instruction execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 is a schematic diagram of an instruction buffer circuit provided in an embodiment of the present application;

[0024] Figure 2 1 is a schematic diagram of an end recording circuit provided in an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of another instruction buffer circuit provided in an embodiment of the present application;

[0026] Figure 4 This is a flow chart of an instruction buffering method provided by an embodiment of the present application;

[0027] Figure 5 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0028] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0030] It should be noted that the terms "first," "second," and the like in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0031] The instruction buffer (ibuf) and loop buffer (lbuf) are common structures in processor design. Typically, ibufs are used to cache instructions in the fetch unit pipeline when the fetch unit is blocked, reducing the impact of factors such as fetch bandwidth and cache misses on instruction fetch efficiency.

[0032] Lbuf is used to identify the instructions of the loop body in the instruction stream and store the instructions of the loop body in lbuf. In the case where the processor is a RISC-V processor, the number of instructions included in the loop body is relatively small, and the loop body is also called a short loop body. When the instructions of the loop body are stored in lbuf, the instructions of the loop body can be directly extracted from lbuf without repeatedly accessing the instruction cache (instruction cache, icache) that stores all instructions, thereby improving the efficiency of instruction fetching and reducing the power consumption caused by accessing icache.

[0033] In processors, ibuf and lbuf are typically designed separately, resulting in a larger chip area. Furthermore, when ibuf and lbuf are designed separately, the instructions to be executed must be selected from both ibuf and lbuf. This logic increases the overall execution time, resulting in lower execution efficiency. Therefore, an instruction buffer circuit is needed to achieve an integrated design of ibuf and lbuf, thereby saving chip area and improving instruction execution efficiency.

[0034] An embodiment of the present application provides an instruction buffer circuit that can identify the type of instruction. When the instruction type indicates that the instruction is a loop body instruction, the loop body instructions are sequentially written into a buffer included in the instruction buffer circuit. When the instruction type indicates that the instruction is a general instruction, the instruction is written into the buffer or transmitted to the circuit that executes the instruction based on the number of instructions obtained, the number of instructions stored in the buffer, and the number of instructions required by the circuit that executes the instruction. Thus, the buffer can achieve compatible caching of general instructions and loop body instructions.

[0035] Illustratively, the instruction buffer circuit provided in the embodiment of the present application is implemented by a pure hardware circuit, so that when the instruction buffer circuit is implemented by a pure hardware circuit, the operation reliability and efficiency of the instruction buffer circuit are relatively high.

[0036] like Figure 1 As shown, the instruction buffer circuit includes a loop detection circuit 10, a write circuit 20 and a buffer 30. The write circuit 20 is respectively connected to the loop detection circuit 10, the buffer 30 and the instruction execution circuit located outside the instruction buffer circuit. The buffer 30 is also connected to the instruction execution circuit.

[0037] The loop detection circuit 10 is used to obtain the type of instruction and send the type of instruction to the write circuit; the write circuit 20 is used to write the instruction into the buffer 30 or transfer the instruction to the instruction execution circuit based on the number of instructions obtained, the number of instructions stored in the buffer 30 and the number of instructions required by the instruction execution circuit when the type of instruction indicates that the instruction is a general instruction; the write circuit 20 is also used to write the instruction into the buffer 30 when the type of instruction indicates that the instruction is an instruction of a loop body; the buffer 30 is used for general instructions and loop body instructions to share storage space.

[0038] Thus, the instruction buffer circuit provided in the embodiment of the present application can implement the functions of ibuf and lbuf with a single buffer 30, achieving an integrated design of ibuf and lbuf. Therefore, this instruction buffer circuit can avoid the need to design ibuf and lbuf separately, saving chip area and improving the timeliness of instruction execution.

[0039] In the embodiment of the present application, the storage space of buffer 30 is shared by general instructions and loop body instructions. This means that a block of storage space in buffer 30 can be used to cache both loop body instructions and general instructions. In other words, in buffer 30, there is no distinction between storage space dedicated to caching general instructions and storage space dedicated to caching loop body instructions.

[0040] In a possible implementation, the loop detection circuit 10 includes an end recording circuit 101 and an end matching circuit 102 , and the end matching circuit 102 is connected to the end recording circuit 101 and the writing circuit 20 , respectively.

[0041] The end recording circuit 101 is used to obtain the instruction stream within the first time period. When the instruction stream within the first time period includes the target conditional branch instruction, the address of the next instruction to be executed of the target conditional branch instruction is recorded. The target conditional branch instruction is a conditional branch instruction whose branch prediction result is a jump and the jump offset is negative. The end recording circuit 101 is also used to obtain the instruction stream within the second time period. When the instruction stream within the second time period includes the target conditional branch instruction, the address of the next instruction to be executed of the target conditional branch instruction and the recorded address of the instruction to be executed are transmitted to the end matching circuit. The second time period is later than the first time period.

[0042] The end matching circuit 102 is used to determine that the instructions to be executed to the target conditional branch instruction are all loop body instructions based on the address of the next instruction to be executed of the target conditional branch instruction being the same as the address of the recorded instruction to be executed; determine that the instructions to be executed to the target conditional branch instruction are all general instructions based on the address of the next instruction to be executed of the target conditional branch instruction being different from the address of the recorded instruction to be executed; and send the determined instruction type to the write circuit 20.

[0043] That is, the end matching circuit 102 is used to compare the address of the next instruction to be executed after the target conditional branch instruction is obtained and the address of the previously recorded instruction to be executed is the same. If the two are the same, it means that the instructions to be executed to the target conditional branch instruction are instructions that need to be executed repeatedly, and the instructions to be executed to the target conditional branch instruction constitute a loop body, and thus it is determined that the instructions to be executed to the target conditional branch instruction are all instructions of the loop body. If the two are different, it means that the instructions to be executed to the target conditional branch instruction are not instructions that need to be executed repeatedly, and the instructions to be executed to the target conditional branch instruction do not constitute a loop body, and thus it is determined that the instructions to be executed to the target conditional branch instruction are all general instructions.

[0044] In some embodiments, for any instruction in the instruction stream, the address of the next instruction to be executed is recorded in the program counter (PC) corresponding to the instruction. Therefore, the epilogue recording circuit 101 can record the value of the PC corresponding to the target conditional branch instruction to achieve the address of the next instruction to be executed after the target conditional branch instruction.

[0045] Exemplarily, the instruction buffer circuit is driven by a clock with high-low level switching, and the clock has periodicity. The length of the first time period and the second time period is equal to one time cycle, and the second time period is a time cycle adjacent to and later than the first time period. For example, one time cycle is called a beat, the first time period is called a first beat, and the second time period is called a second beat adjacent to and later than the first beat. The instruction stream in the first time period includes the instructions to be executed obtained in the first time period, and the instruction stream in the second time period includes the instructions to be executed obtained in the second time period.

[0046] In a possible implementation, the end recording circuit 101 includes: a pre-decoding circuit, a conditional branch checking circuit, a branch prediction circuit, an offset detection circuit, an instruction judgment circuit and a recording circuit. Figure 2 As shown, the conditional branch check circuit is respectively connected to the pre-decoding circuit, the branch prediction circuit and the offset detection circuit, the instruction judgment circuit is respectively connected to the branch prediction circuit, the offset detection circuit, the recording circuit and the end matching circuit, and the recording circuit is also connected to the end matching circuit.

[0047] The pre-decoding circuit is configured to pre-decode the acquired instruction stream and transmit the pre-decoded instruction stream to the conditional branch checking circuit. The conditional branch checking circuit is configured to check whether the pre-decoded instruction stream includes a conditional branch instruction; if the pre-decoded instruction stream includes a conditional branch instruction, the pre-decoded instruction stream is transmitted to the branch prediction circuit and the offset detection circuit, respectively.

[0048] The branch prediction circuit is used to obtain a branch prediction result for a conditional branch instruction based on the pre-decoded instruction stream and transmit the conditional branch instruction and the branch prediction result to the instruction decision circuit. For example, the branch prediction result may include a jump or no jump.

[0049] The offset detection circuit is configured to obtain a jump offset for a conditional branch instruction based on a pre-decoded instruction stream, and transmit the conditional branch instruction and the jump offset to the instruction determination circuit. For example, the jump offset may include whether the jump offset is positive or negative. The jump offset may also include a specific numerical value of the offset. For example, an obtained jump offset of -5 indicates that the jump offset is negative and has a value of 5 instructions.

[0050] The instruction determination circuit is configured to determine whether the conditional branch instruction is a target branch conditional instruction based on the conditional branch instruction, the branch prediction result, and the jump offset. For example, if the branch prediction result of the conditional branch instruction is a jump and the jump offset is negative, the conditional branch instruction is determined to be the target conditional branch instruction. If the branch prediction result of the conditional branch instruction is a jump and the jump offset is positive, the conditional branch instruction is determined not to be the target conditional branch instruction. If the branch prediction result of the conditional branch instruction is not a jump, the conditional branch instruction is determined not to be the target conditional branch instruction.

[0051] The instruction judgment circuit is further configured to, when the conditional branch instruction is a target branch conditional instruction, write the address of the next instruction to be executed after the target conditional branch instruction into the recording circuit, and transmit the address of the next instruction to be executed after the target conditional branch instruction to the end matching circuit. Exemplarily, the recording circuit includes a register configured to store the address of the next instruction to be executed after the target conditional branch instruction.

[0052] The instruction judgment circuit may proactively transmit the address of the next instruction to be executed after the target conditional branch instruction to the end matching circuit once during each time period. Alternatively, the instruction judgment circuit may receive a first acquisition request transmitted by the end matching circuit during each time period, the first acquisition request being used to request the address of the next instruction to be executed after the target conditional branch instruction. Based on the first acquisition request, the instruction judgment circuit transmits the address of the next instruction to be executed after the target conditional branch instruction to the end matching circuit.

[0053] The recording circuit is configured to transmit the recorded address of the instruction to be executed to the end matching circuit once during each time period. For example, the recording circuit proactively transmits the recorded address of the instruction to be executed to the end matching circuit once during each time period. Alternatively, the recording circuit receives a second acquisition request transmitted by the end matching circuit during each time period, the second acquisition request being used to request the address of the recorded instruction to be executed. The recording circuit transmits the recorded address of the instruction to be executed to the end matching circuit based on the second acquisition request.

[0054] The specific circuit structures of the above-mentioned pre-decoding circuit, conditional branch checking circuit, branch prediction circuit, offset detection circuit, instruction judgment circuit and recording circuit can refer to the contents in the relevant technology, and are not limited in the embodiments of the present application.

[0055] In some embodiments, the loop detection circuit further includes a backfill completion judgment circuit 40 , which is connected to the end matching circuit 102 and the write circuit 20 .

[0056] The end matching circuit 102 is further configured to send the loop body instructions to the backfill completion determination circuit 40. The backfill completion determination circuit 40 is configured to determine, based on the acquired loop body instructions, whether the last instruction in the loop body instructions has been written into the buffer 30 by the write circuit 20. The backfill completion determination circuit 40 is further configured to, if it is determined that the last instruction in the loop body instructions has been written into the buffer 30 by the write circuit 20, send a record instruction to the write circuit 20, the record instruction being used to instruct the write circuit 20 to record the storage location of the loop body instructions in the buffer 30.

[0057] Exemplarily, the end matching circuit 102 simultaneously sends the loop body instructions to the backfill completion determination circuit 40 and the write circuit. The backfill completion determination circuit 40 compares the obtained loop body instructions with the target conditional branch instruction to see if they are identical. If the obtained loop body instructions are identical to the target conditional branch instruction, it is determined that the last instruction of the loop body has been obtained, and the last instruction of the loop body is written into the buffer 30 by the write circuit 20.

[0058] When the last instruction in the instruction of the loop body is written into buffer 30, it means that the instruction of the loop body has all been written into buffer 30. Thus, write circuit 20 can record the storage location of the instruction of the loop body in buffer 30, and subsequently, when it is necessary to repeatedly read the instruction of the loop body, the instruction of the loop body can be directly read based on the storage location recorded by write circuit 20, and the efficiency of reading the instruction of the loop body is higher. Moreover, when it is necessary to repeatedly read the instruction of the loop body, by reading the instruction of the loop body from buffer 30, without having to repeatedly read the instruction of the loop body from icache storing all instructions, the power consumption caused by the operation of accessing icache is lower.

[0059] Exemplarily, the storage locations of the instructions of the loop body in the buffer 30 are continuous. In this case, the write circuit 20 records the first storage location of the first instruction of the loop body in the buffer 30, and the second storage location of the last instruction of the loop body in the buffer 30. Since the storage locations of the instructions of the loop body in the buffer 30 are continuous, the instructions at the storage locations between the first storage location and the second storage location all belong to the instructions of the loop body. Compared to the storage location method of recording the storage locations of all instructions of the loop body in the buffer 30, the storage space occupied by the storage location method of recording the storage locations of the instructions of the loop body in the buffer 30 is less.

[0060] In some embodiments, the write circuit 20 includes a quantity detection circuit and a write control circuit, and the write control circuit is connected to the quantity detection circuit, the buffer 30, the cycle detection circuit 10, and the instruction execution circuit respectively.

[0061] The quantity detection circuit is configured to retrieve instructions, determine the number of retrieved instructions, and transmit the retrieved instructions and the number of retrieved instructions to the write control circuit. The write control circuit is configured to receive the instructions transmitted by the quantity detection circuit and the number of retrieved instructions, determine the number of instructions stored in the buffer 30, and determine the number of instructions required by the instruction execution circuit.

[0062] If no instructions are stored in the buffer 30, the write control circuit transmits the instructions to the instruction execution circuit based on the number of instructions required by the instruction execution circuit. Specifically, if the number of instructions acquired is less than or equal to the number of instructions required by the instruction execution circuit, the write control circuit transmits all acquired instructions to the instruction execution circuit. If the number of instructions acquired is greater than the number of instructions required by the instruction execution circuit, the write control circuit transmits the instructions to the instruction execution circuit according to the number required by the instruction execution circuit, and writes the instructions not transferred to the instruction execution circuit into the buffer 30.

[0063] When instructions are stored in the buffer 30 and the number of instructions stored is less than the number of instructions required by the instruction execution circuit, the write control circuit transmits instructions to the instruction execution circuit according to the difference between the number required by the instruction execution circuit and the number of instructions stored in the buffer 30; and writes the instructions that are not transmitted to the instruction execution circuit into the buffer 30.

[0064] When the buffer 30 stores instructions and the number of stored instructions is greater than or equal to the number of instructions required by the instruction execution circuit, the write control circuit writes the acquired instructions into the buffer 30 .

[0065] If the number of instructions that can be stored in the buffer 30 is less than the number of instructions transmitted by the number detection circuit, the write control circuit writes the acquired instructions into the buffer 30 according to the number of instructions that can be stored in the buffer 30. Furthermore, the write control circuit instructs the loop detection circuit and the number detection circuit to pause to avoid instruction loss until the number of instructions that have been received by the write control circuit but not written into the buffer 30 is less than or equal to the number of instructions that can be stored in the buffer 30.

[0066] The above description of the write control circuit is based solely on the relationship between the number of instructions. The write control circuit is also configured to obtain the type of instruction. If the instruction type indicates that the instruction is a general instruction, the write control circuit writes the instruction into buffer 30 based on the relationship between the number of instructions. If the instruction type indicates that the instruction is a loop body instruction, the write control circuit writes the instruction into buffer 30 regardless of whether the instruction has been transmitted to the instruction execution circuit.

[0067] In some embodiments, the instruction buffer circuit also includes a reading circuit, which is connected to the buffer 30 and the instruction execution circuit respectively; the reading circuit is used to read instructions from the buffer 30 based on the number of instructions required by the instruction execution circuit and the number of instructions stored in the buffer 30; and transmit the read instructions to the instruction execution circuit.

[0068] Exemplarily, the instruction buffer circuit also includes an end detection circuit, which is connected to the write circuit 20 and the read circuit respectively; the read circuit is also used to transmit the read instruction to the end detection circuit; the end detection circuit is used to predict the jump result of the conditional branch instruction when the read instruction includes a conditional branch instruction; based on the jump result being no jump or jump and the jump offset being positive, the loop is determined to be over, and a clear instruction is sent to the write circuit 20 to instruct the write circuit 20 to clear the storage location of the recorded loop body instructions in the buffer.

[0069] The manner in which the end detection circuit predicts the jump result of the conditional branch instruction is described in the related art and is not limited in the present embodiment. By sending a clear instruction to the write circuit 20 upon the end of the loop, instructing the write circuit 20 to clear the location of the recorded loop body instructions in the buffer 30, storage resources can be saved.

[0070] Figure 3 This is a schematic diagram of another instruction buffer circuit provided by an embodiment of the present application. The connection relationship between the above-mentioned end recording circuit, end matching circuit, backfill completion judgment circuit, quantity detection circuit, write control circuit, buffer, read circuit, end detection circuit and instruction execution circuit can be as follows: Figure 3 The functions of each circuit are described in the previous section and will not be repeated here.

[0071] An embodiment of the present application also provides an instruction buffering method, which is executed by an instruction buffer circuit. The instruction buffer circuit includes a loop detection circuit, a write circuit and a buffer. The write circuit is respectively connected to the loop detection circuit, the buffer and an instruction execution circuit located outside the instruction buffer circuit. The buffer is also connected to the instruction execution circuit. Figure 4 This is a flow chart of an instruction buffering method provided by an embodiment of the present application. Figure 4 , the method includes but is not limited to steps 401 to 403.

[0072] Step 401: Obtain the type of instruction through the loop detection circuit, and send the type of instruction to the writing circuit.

[0073] In one possible implementation, the loop detection circuit includes an end recording circuit and an end matching circuit, wherein the end matching circuit is connected to the end recording circuit and the writing circuit, respectively. Acquiring the instruction type through the loop detection circuit and sending the instruction type to the writing circuit includes:

[0074] Obtaining an instruction stream within a first time period through an epilogue recording circuit, and recording an address of a next instruction to be executed after the target conditional branch instruction when the instruction stream within the first time period includes a target conditional branch instruction, wherein the target conditional branch instruction is a conditional branch instruction whose branch prediction result is a jump and whose jump offset is negative;

[0075] obtaining an instruction stream within a second time period through an epilogue recording circuit, and transmitting an address of an instruction to be executed next to the target conditional branch instruction and the recorded address of the instruction to be executed to an epilogue matching circuit when the instruction stream within the second time period includes a target conditional branch instruction, wherein the second time period is later than the first time period;

[0076] Through the end matching circuit, based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is the same as the address of the recorded instruction to be executed, it is determined that the instructions to be executed to the target conditional branch instruction are all instructions of the loop body; based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is different from the address of the recorded instruction to be executed, it is determined that the instructions to be executed to the target conditional branch instruction are all general instructions; and the determined instruction type is sent to the write circuit.

[0077] Step 402 , when the instruction type indicates that the instruction is a general instruction, the writing circuit writes the instruction into the buffer or transmits the instruction to the instruction execution circuit based on the number of instructions acquired, the number of instructions stored in the buffer, and the number of instructions required by the instruction execution circuit.

[0078] Step 403 : When the instruction type indicates that the instruction is a loop body instruction, the writing circuit writes the instruction into the buffer. The general instructions and the loop body instructions share the storage space of the buffer.

[0079] In one possible implementation, the loop detection circuit also includes a backfill completion judgment circuit, which is connected to the end matching circuit and the write circuit respectively; the method also includes: sending the instructions of the loop body to the backfill completion judgment circuit through the end matching circuit; determining through the backfill completion judgment circuit based on the instructions of the loop body obtained, whether the last instruction in the instructions of the loop body is written into the buffer by the write circuit; and sending a record instruction to the write circuit when the backfill completion judgment circuit determines that the last instruction is written into the buffer by the write circuit, the record instruction being used to instruct the write circuit to record the storage location of the instructions of the loop body in the buffer.

[0080] In one possible implementation, the instruction buffer circuit also includes a reading circuit, which is connected to the buffer and the instruction execution circuit respectively; the method also includes: reading instructions from the buffer through the reading circuit based on the number of instructions required by the instruction execution circuit and the number of instructions stored in the buffer; and transmitting the read instructions to the instruction execution circuit.

[0081] In one possible implementation, the instruction buffer circuit also includes an end detection circuit, which is connected to the write circuit and the read circuit respectively; the method also includes: transmitting the read instruction to the end detection circuit through the read circuit; predicting the jump result of the conditional branch instruction through the end detection circuit when the read instruction includes a conditional branch instruction; determining the end of the loop based on the jump result being no jump or jump and the jump offset being positive, and sending a clear instruction to the write circuit to instruct the write circuit to clear the storage location of the recorded loop body instructions in the buffer.

[0082] In the method provided in an embodiment of the present application, the type of instruction acquired by the writing circuit is determined. If the instruction type indicates that the instruction is a general instruction, the instruction is written to the buffer or transmitted to the instruction execution circuit based on the number of instructions acquired, the number of instructions stored in the buffer, and the number of instructions required by the instruction execution circuit. If the instruction type indicates that the instruction is a loop body instruction, the instruction is written to the buffer. The general instructions and the loop body instructions share storage space in the buffer.

[0083] Therefore, this method can implement the functions of ibuf and lbuf with a single buffer, achieving an integrated design of ibuf and lbuf. Therefore, this method can avoid designing ibuf and lbuf separately, saving chip area and improving the timeliness of instruction execution.

[0084] It should be understood that the above method embodiment and the instruction buffer circuit described above belong to the same concept, and the specific implementation process is detailed in the embodiment of the instruction buffer circuit, which will not be repeated here.

[0085] In an exemplary embodiment, a chip is also provided, such as Figure 5 As shown, the chip 500 includes the instruction buffer circuit mentioned above, and the instruction buffer circuit is used to execute the instruction buffer method mentioned above.

[0086] In an exemplary embodiment, an electronic device is also provided, such as Figure 6 As shown, the electronic device 600 includes the chip 500 mentioned above.

[0087] It should be understood that the term "plurality" used herein refers to two or more. "And / or" describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates an "or" relationship between the associated objects.

[0088] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0089] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An instruction buffer circuit, characterized in that: The instruction buffer circuit includes a loop detection circuit, a write circuit and a buffer, wherein the write circuit is respectively connected to the loop detection circuit, the buffer and an instruction execution circuit located outside the instruction buffer circuit, and the buffer is also connected to the instruction execution circuit; The cycle detection circuit is used to obtain the type of instruction and send the type of instruction to the writing circuit; the writing circuit is configured to, when the type of the instruction indicates that the instruction is a general instruction, write the instruction into the buffer or transmit the instruction to the instruction execution circuit based on the number of instructions acquired, the number of instructions stored in the buffer, and the number of instructions required by the instruction execution circuit; The writing circuit is further configured to write the instruction into the buffer when the type of the instruction indicates that the instruction is a loop body instruction; The buffer is used for the general instructions and the instructions of the loop body to share storage space.

2. The instruction buffer circuit according to claim 1, wherein: The loop detection circuit includes an end recording circuit and an end matching circuit, and the end matching circuit is connected to the end recording circuit and the writing circuit respectively; The epilogue recording circuit is configured to obtain an instruction stream within a first time period, and if the instruction stream within the first time period includes a target conditional branch instruction, record an address of an instruction to be executed next to the target conditional branch instruction, wherein the target conditional branch instruction is a conditional branch instruction whose branch prediction result is a jump and whose jump offset is negative; The end recording circuit is further configured to obtain an instruction stream within a second time period, and, if the instruction stream within the second time period includes the target conditional branch instruction, transmit an address of an instruction to be executed next to the target conditional branch instruction and the address of the recorded instruction to be executed to the end matching circuit, wherein the second time period is later than the first time period; The end matching circuit is configured to determine that the instructions to be executed and the target conditional branch instruction are all loop body instructions based on the address of the next instruction to be executed of the target conditional branch instruction being the same as the address of the recorded instruction to be executed; Based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is different from the address of the recorded instruction to be executed, it is determined that the instructions to be executed to the target conditional branch instruction are all general instructions; and the determined instruction type is sent to the write circuit.

3. The instruction buffer circuit according to claim 2, wherein: The loop detection circuit further includes a backfill completion judgment circuit, and the backfill completion judgment circuit is connected to the end matching circuit and the write circuit respectively; The end matching circuit is further configured to send an instruction of the loop body to the backfill completion judgment circuit; The backfill completion judgment circuit is used to determine whether the last instruction in the instructions of the loop body is written into the buffer by the writing circuit based on the instructions of the loop body obtained; The backfill completion judgment circuit is also used to send a record instruction to the write circuit when it is determined that the last instruction is written into the buffer by the write circuit. The record instruction is used to instruct the write circuit to record the storage location of the instruction of the loop body in the buffer.

4. The instruction buffer circuit according to any one of claims 1 to 3, characterized in that: The instruction buffer circuit further includes a reading circuit, wherein the reading circuit is connected to the buffer and the instruction execution circuit respectively; The reading circuit is used to read instructions from the buffer based on the number of instructions required by the instruction execution circuit and the number of instructions stored in the buffer; and transmit the read instructions to the instruction execution circuit.

5. The instruction buffer circuit according to claim 4, wherein: The instruction buffer circuit further includes an end detection circuit, wherein the end detection circuit is connected to the write circuit and the read circuit respectively; The reading circuit is further configured to transmit the read instruction to the end detection circuit; The end detection circuit is used to predict the jump result of the conditional branch instruction when the read instruction includes a conditional branch instruction; determine the end of the loop based on whether the jump result is no jump or jump and the jump offset is positive, and send a clear instruction to the write circuit to instruct the write circuit to clear the storage location of the recorded instructions of the loop body in the buffer.

6. A command buffering method, characterized in that: The method is performed by an instruction buffer circuit, the instruction buffer circuit including a loop detection circuit, a write circuit, and a buffer, the write circuit being connected to the loop detection circuit, the buffer, and an instruction execution circuit located outside the instruction buffer circuit, respectively, and the buffer being further connected to the instruction execution circuit; the method comprising: acquiring the type of instruction through the cycle detection circuit, and sending the type of instruction to the writing circuit; writing the instruction into the buffer or transmitting the instruction to the instruction execution circuit by the writing circuit based on the number of instructions acquired, the number of instructions stored in the buffer, and the number of instructions required by the instruction execution circuit when the type of the instruction indicates that the instruction is a general instruction; When the type of the instruction indicates that the instruction is a loop body instruction, the writing circuit writes the instruction into the buffer, and the general instruction and the loop body instruction share storage space in the buffer.

7. The method according to claim 6, characterized in that The loop detection circuit includes an end recording circuit and an end matching circuit, and the end matching circuit is connected to the end recording circuit and the writing circuit respectively; The acquiring the type of instruction by the loop detection circuit and sending the type of instruction to the write circuit includes: Acquiring an instruction stream within a first time period through the epilogue recording circuit, and recording an address of a next instruction to be executed after the target conditional branch instruction if the instruction stream within the first time period includes a target conditional branch instruction, wherein the target conditional branch instruction is a conditional branch instruction whose branch prediction result is a jump and whose jump offset is negative; acquiring an instruction stream within a second time period through the epilogue recording circuit, and transmitting an address of an instruction to be executed next to the target conditional branch instruction and the recorded address of the instruction to be executed to the epilogue matching circuit when the instruction stream within the second time period includes the target conditional branch instruction, wherein the second time period is later than the first time period; The end matching circuit determines that the instructions to be executed to the target conditional branch instruction are all loop body instructions based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is the same as the address of the recorded instruction to be executed; determines that the instructions to be executed to the target conditional branch instruction are all general instructions based on the fact that the address of the next instruction to be executed of the target conditional branch instruction is different from the address of the recorded instruction to be executed; and sends the determined instruction type to the write circuit.

8. The method according to claim 7, characterized in that The loop detection circuit further includes a backfill completion judgment circuit, and the backfill completion judgment circuit is connected to the end matching circuit and the write circuit respectively; the method further includes: Sending the loop body instruction to the backfill completion judgment circuit through the end matching circuit; determining, by the backfill completion judgment circuit based on the acquired instructions of the loop body, whether the last instruction in the instructions of the loop body is written into the buffer by the writing circuit; When the backfill completion judgment circuit determines that the last instruction is written into the buffer by the write circuit, a record instruction is sent to the write circuit, where the record instruction is used to instruct the write circuit to record the storage location of the instructions of the loop body in the buffer.

9. A chip, characterized in that: The chip includes the instruction buffer circuit according to any one of claims 1 to 5.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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