JFMQL-based aviation airborne information processing board card

Abstract

The invention discloses a JFMQL-based aviation airborne information processing board card, which comprises a JFMQL series PSoC chip, a DDR3 memory, a PCIe bridge chip and an external connector, the PL end of the JFMQL series PSoC chip is provided with a PCIe core, and the PCIe bridge chip is electrically connected with the PCIe core at the PL end of the JFMQL series PSoC chip and is electrically connected with the external connector; the DDR3 memory is electrically connected with the PSoC chip of the JFMQL series; and the PCIe core packages data to be interacted on the DDR3 memory into PCIe data according to a PCIe protocol, and the PCIe data are output to two external NVMe hard disks by the external connector through two paths of PCIe * 4 ports expanded by the PCIe bridge chip. According to the invention, the airborne communication rate can be effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of data transmission and storage, and in particular relates to an aviation airborne information processing board based on JFMQL. Background Art

[0002] In avionics systems, airborne communication and data exchange are crucial components. With the development and advancement of avionics technology, higher requirements are being placed on the bandwidth and quality of onboard data exchange buses. Aviation data bus architectures are gradually evolving from low-speed buses (such as GJB289A) to TSN buses. However, traditional airborne data transmission solutions often rely on foreign chips, which not only limits the mastery of core technologies but also introduces technical risks and security concerns. Furthermore, the uncertainty of chip supply increases product development risks. To address these challenges, several domestic companies have released independently developed chips and solutions. These solutions are awaiting further verification and application, aiming to reduce reliance on external technologies and enhance the autonomous and controllable capabilities of avionics systems. Summary of the Invention

[0003] The object of the present invention is to provide an aviation airborne information processing board based on JFMQL, which can effectively improve the airborne communication rate and realize the controllability of the technical solution.

[0004] The object of the present invention is achieved through the following technical solutions:

[0005] A JFMQL-based aviation airborne information processing board, comprising a JFMQL series PSoC chip, DDR3 memory, a PCIe bridge chip, and external connectors;

[0006] The PL side of the JFMQL series PSoC chip is equipped with a PCIe core. The PCIe bridge chip is electrically connected to the PCIe core on the PL side of the JFMQL series PSoC chip and is also electrically connected to an external connector. The DDR3 memory is electrically connected to the JFMQL series PSoC chip.

[0007] The PCIe core packages the data to be interacted with on the DDR3 memory into PCIe data according to the PCIe protocol, and outputs it to two external NVMe hard drives through the external connector via the two PCIe×4 ports expanded by the PCIe bridge chip.

[0008] Preferably, the aviation onboard information processing board further comprises an SGMII channel and a protection circuit;

[0009] The PL side of the JFMQL series PSoC chip is provided with an SGMII core. The SGMII channel and protection circuit are electrically connected to the SGMII core of the PL side of the JFMQL series PSoC chip and are electrically connected to the external connector.

[0010] The high-speed SGMII data required for interaction enters the information processing board through the external connector, and then enters the JFMQL series PSoC chip through the SGMII channel and protection circuit. The SGMII core inside the JFMQL series PSoC chip parses the message according to the SGMII interface protocol, and stores the parsed data from the PL end of the JFMQL series PSoC chip into the DDR3 memory. The PCIe core on the PL end then packages the data into PCIe data according to the PCIe protocol, and the two PCIe×4 ports expanded by the PCIe bridge chip are output from the external connector to two external NVMe hard drives.

[0011] Preferably, the aviation onboard information processing board further comprises a TSN channel and a protection circuit;

[0012] The JFMQL series PSoC chip has a TSN core on the PL side. The TSN channel and protection circuit are electrically connected to the TSN core on the PL side of the JFMQL series PSoC chip and are also electrically connected to the external connector.

[0013] The high-speed TSN data required for interaction enters the information processing board through the external connector, and enters the JFMQL series PSoC chip through the TSN channel and protection circuit. The TSN core inside the JFMQL series PSoC chip parses the data according to the TSN protocol, and stores the parsed data from the PL end of the JFMQL series PSoC chip into the DDR3 memory. The PCIe core on the PL end then packages the data into PCIe data according to the PCIe protocol, and the two PCIe×4 ports expanded by the PCIe bridge chip are output to the external NVMe hard drive through the external connector.

[0014] Preferably, the aviation airborne information processing board further comprises a 1553 bus protocol chip;

[0015] The PL-IO core is provided on the PL side of the JFMQL series PSoC chip; the 1553 bus protocol chip is electrically connected to the PL-IO core on the PL side of the JFMQL series PSoC chip and is electrically connected to the external connector;

[0016] The 1553 bus data required for interaction enters the 1553 bus protocol chip through the external connector. After the 1553 bus protocol chip parses the data, the parsed data is sent to the JFMQL series PSoC chip through the LOCALBUS bus, and then sent to the PCIe core through the on-chip bus inside the PL-IO core. The PCIe core packages it into PCIe data according to the PCIe protocol, and the data is expanded into two PCIe×4 ports through the PCIe bridge chip, and then output to the external NVMe hard drive through the external connector.

[0017] Preferably, the aviation onboard information processing board further comprises a first Ethernet PHY6 and a second Ethernet PHY7;

[0018] The PS side of the JFMQL series PSoC chip includes two ETH cores; the first Ethernet PHY and the second Ethernet PHY are electrically connected to the two ETH cores of the PS side of the JFMQL series PSoC chip in sequence, and the first Ethernet PHY1 and the second Ethernet PHY2 are electrically connected to the external connector via the network transformer using RGMII;

[0019] The Ethernet data required for interaction enters the JFMQL series PSoC chip through the external connector via the first Ethernet PHY1 and the second Ethernet PHY2. A network transformer is used between the electrical paths where the external Ethernet signal enters the Ethernet PHY chip to provide overvoltage protection against electrostatic discharge, pulses, and transient voltages. The PS-side ETH core then parses the data and sends it to the PCIe core via the on-chip bus. The PCIe core packages the data into PCIe data according to the PCIe protocol, and the data is expanded into two PCIe×4 ports via the PCIe bridge chip, and then output to the external NVMe hard drive via the external connector.

[0020] Preferably, the aviation airborne information processing board further comprises a FLASH chip, which is electrically connected to the PS end of the JFMQL series PSoC chip using a Queued SPI method to store an operating system boot loader.

[0021] Preferably, the aviation airborne information processing board further includes an NVRAM chip, which is electrically connected to the PS end of the JFMQL series PSoC chip to record board self-test data and abnormal error data.

[0022] Preferably, the aviation airborne information processing board further comprises a JTAG plug, which is electrically connected to a dedicated JTAG pin port on the PL side of the JFMQL series PSoC chip for burning system files and online debugging.

[0023] Preferably, the aviation airborne information processing board further includes an input and output discrete quantity protection circuit, which is electrically connected to the PL-IO core of the PL end of the JFMQL series PSoC chip and is electrically connected to the external connector.

[0024] Preferably, the aviation airborne information processing board card further comprises an input power conversion circuit, which is electrically connected to the external connector and converts the input DC power into the voltage required by the board card.

[0025] Preferably, there are 4 pieces of DDR3 memory, 2 of which are electrically connected to the PS end of the JFMQL series PSoC chip using a FLY-BY topology to form a 32-bit DDR for system cache, and the other 2 pieces are independently electrically connected to the PL end of the FPGA SOC chip to flexibly serve as data cache for high-speed signals.

[0026] The beneficial effects of the present invention are:

[0027] The present invention utilizes the high-speed IO port on the PL side of PSoC to implement communications from SGMII and TSN, and utilizes the ordinary IO port on the PL side to package the data obtained from 1553 communication and Ethernet communication on the PS side into disk data through the PCIe2.0 protocol. The data flow is clear and the rate is as high as 5Gbps. In addition, the present invention uses domestically produced devices with high autonomy, controllability and security, meeting the product needs of special industries. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The figure is a schematic diagram of the structure of an aviation airborne information processing board based on JFMQL. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0030] See also Figure 1 As shown, the JFMQL-based aviation airborne information processing board shown in this embodiment includes a JFMQL series PSoC chip 1, a FLASH chip 2, an NVRAM chip 3, a DDR3 memory 4, a JTAG plug-in 5, a first Ethernet PHY 6, a second Ethernet PHY 7, a PCIe bridge chip 8, an SGMII channel and protection circuit 9, a TSN channel and protection circuit 10, a 1553 bus protocol chip 11, an input and output discrete quantity protection circuit 12, an input power conversion circuit 13 and an external connector 14, etc.

[0031] By way of example, in this embodiment, the JFMQL series PSoC chip model is JFMQL100T900, the FLASH chip model is EFM25QL256-E16, the DDR3 memory model is SM41J256M16M, the JTAG plug model is LMA-110-02-GDA, the first and second Ethernet PHY models are B88E1111MB, the PCIe bridge chip model is SM8619, and the 1553 bus protocol chip model is SM2130. The SGMII channel and protection circuitry, the TSN channel and protection circuitry, the input and output discrete value protection circuitry, and the input power conversion circuitry are comprised of common components such as resistors, capacitors, and TVS diodes.

[0032] The JFMQL series PSoC chip consists of a PS side and a PL side. The PS side is used for system initialization, system status monitoring, and Ethernet communication, and includes two ETH cores. The PL side is used for PCIe, SGMII, TSN, 1553 communication, and I / O port control, and includes a PCIe core, SGMII core, TSN core, and PL-IO core.

[0033] The first Ethernet PHY and the second Ethernet PHY are electrically connected to the two ETH cores of the PS end of the JFMQL series PSoC chip in sequence, and the first Ethernet PHY1 and the second Ethernet PHY2 are electrically connected to the external connector via the network transformer using RGMII to realize the physical layer of the board Ethernet.

[0034] The PCIe bridge chip is electrically connected to the PCIe core on the PL side of the JFMQL series PSoC chip and is electrically connected to the external connector.

[0035] The SGMII channel and protection circuit are electrically connected to the SGMII core at the PL end of the JFMQL series PSoC chip and are electrically connected to the external connector.

[0036] The TSN channel and protection circuit are electrically connected to the TSN core on the PL side of the JFMQL series PSoC chip and are electrically connected to the external connector.

[0037] The 1553 bus protocol chip and the input and output discrete quantity protection circuit are electrically connected to the PL-IO core of the PL end of the JFMQL series PSoC chip, and are electrically connected to the external connector.

[0038] The input power conversion circuit is electrically connected to the external connector and converts the input +12V DC power to the voltages required by the board. In some exemplary embodiments, the input +12V DC power is converted to power signals such as 3.3V, 2.5V, 2.0V, 1.8V, 1.5V, and 1.0V, thereby providing the voltages required by the board and the operating voltage of the NVMe electronic disk.

[0039] The FLASH chip, NVRAM chip, DDR3 memory, and JTAG plug-in are electrically connected to the JFMQL series PSoC chip.

[0040] The FLASH chip is electrically connected to the PS end of the JFMQL series PSoC chip using Queued SPI to store the operating system boot loader;

[0041] The NVRAM chip is electrically connected to the PS terminal of the JFMQL series PSoC chip to record the board self-test data and abnormal error data;

[0042] There are four DDR3 memory chips in total. Two chips are electrically connected to the PS end of the JFMQL series PSoC chip using a FLY-BY topology to form a 32-bit DDR for system cache. The other two chips are independently electrically connected to the PL end of the FPGA SOC chip to flexibly serve as data cache for high-speed signals.

[0043] The JTAG plug-in is electrically connected to the dedicated JTAG pin port on the PL side of the JFMQL series PSoC chip for burning system files and online debugging.

[0044] The board driver design has two working states: system working state and monitoring working state. The two working states share the same operating system image file. After the board is powered on, the operating system image file is started. The operating system selects to execute different applications according to the state of the external switch discrete signal. The system working state executes the upper-level product application software and related drivers. The monitoring working state does not execute the upper-level application software and related drivers, but only initializes the operating system, which is convenient for board-level debugging and verification of the airborne information processing board.

[0045] Based on the above information processing board, the information processing method is as follows:

[0046] The required high-speed SGMII data for interaction enters the information processing board through the external connector, then passes through the SGMII channel and protection circuitry to the JFMQL series PSoC chip. The SGMII core within the JFMQL series PSoC chip parses the message according to the SGMII interface protocol and stores the parsed data into DDR3 memory from the JFMQL series PSoC chip's PL side. The PL-side PCIe core then packages the data into PCIe data according to the PCIe protocol. The data is then output through the external connector to two external NVMe hard drives via the two PCIe x4 ports expanded by the PCIe bridge chip. The board driver completes the PCIe bus configuration, enabling the connection of two NVMe electronic hard drives and other external devices, thus completing the NVMe function.

[0047] The required high-speed TSN data for interaction enters the information processing board through an external connector, then passes through the TSN channel and protection circuitry to the JFMQL series PSoC chip. The TSN core within the JFMQL series PSoC parses the data according to the TSN protocol and stores the parsed data in DDR3 memory from the JFMQL series PSoC's PL side. The PCIe core on the PL side then packages the data into PCIe data according to the PCIe protocol. The data is then output to an external NVMe drive through the external connector via two PCIe x4 ports expanded into a PCIe bridge chip. The TSN network provides dual-redundancy communication, meaning a failure in one channel does not affect the normal communication function of the other. The TSN network also supports configurable single-node communication bandwidth of 1 / 10 Gbps. As the primary data transmission method for the information processing board, the TSN communication network handles the primary communication between the board and external devices. It also receives relevant data communication commands, bit self-tests, or status query commands.

[0048] The required 1553 bus data for interaction enters the 1553 bus protocol chip via the external connector. The 1553 bus protocol chip parses the data and sends it to the JFMQL series PSoC chip via the LOCALBUS bus. It then sends the data to the PCIe core via the on-chip bus. The PCIe core packages the data into PCIe data according to the PCIe protocol. The data is then expanded into two PCIe x4 ports on the PCIe bridge chip and output via the external connector to the external NVMe hard drive. The GJB289A bus interface driver software must complete the initialization interface function to configure the four-channel 1553 bus protocol chip, set up the bus communication function, implement the BM refresh and BM read functions, and implement interrupt management and interrupt service functions.

[0049] The Ethernet data required for interaction enters the JFMQL series PSoC chip through the external connector via the first Ethernet PHY1 and the second Ethernet PHY2. A low-capacitance TVS array should be used between the electrical paths where the external Ethernet signal enters the Ethernet PHY chip to provide overvoltage protection against electrostatic discharge, pulses, and transient voltages. The PS-side ETH core then parses the data and sends it to the PCIe core via the on-chip bus. The PCIe core packages the data into PCIe data according to the PCIe protocol, and the data is then expanded through the two PCIe×4 ports formed by the PCIe bridge chip and output to the external NVMe hard drive via the external connector.

[0050] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of the present invention, and all these changes or substitutions should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A JFMQL-based aviation airborne information processing board, comprising a JFMQL series PSoC chip, DDR3 memory, a PCIe bridge chip, and an external connector, characterized by: The PL side of the JFMQL series PSoC chip is provided with a PCIe core. The PCIe bridge chip is electrically connected to the PCIe core of the PL side of the JFMQL series PSoC chip and is also electrically connected to an external connector. DDR3 memory is electrically connected to the JFMQL series PSoC chip; The PCIe core packages the data to be interacted with on the DDR3 memory into PCIe data according to the PCIe protocol, and outputs it to two external NVMe hard drives through the external connector via the two PCIe×4 ports expanded by the PCIe bridge chip.

2. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes SGMII channels and protection circuits; The PL side of the JFMQL series PSoC chip is provided with an SGMII core. The SGMII channel and protection circuit are electrically connected to the SGMII core of the PL side of the JFMQL series PSoC chip and are electrically connected to the external connector. The high-speed SGMII data required for interaction enters the information processing board through the external connector, and then enters the JFMQL series PSoC chip through the SGMII channel and protection circuit. The SGMII core inside the JFMQL series PSoC chip parses the message according to the SGMII interface protocol, and stores the parsed data from the PL end of the JFMQL series PSoC chip into the DDR3 memory. The PCIe core on the PL end then packages the data into PCIe data according to the PCIe protocol, and the two PCIe×4 ports expanded by the PCIe bridge chip are output from the external connector to two external NVMe hard drives.

3. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes TSN channels and protection circuits; The JFMQL series PSoC chip has a TSN core on the PL side. The TSN channel and protection circuit are electrically connected to the TSN core on the PL side of the JFMQL series PSoC chip and are also electrically connected to the external connector. The high-speed TSN data required for interaction enters the information processing board through the external connector, and enters the JFMQL series PSoC chip through the TSN channel and protection circuit. The TSN core inside the JFMQL series PSoC chip parses the data according to the TSN protocol, and stores the parsed data from the PL end of the JFMQL series PSoC chip into the DDR3 memory. The PCIe core on the PL end then packages the data into PCIe data according to the PCIe protocol, and the two PCIe×4 ports expanded by the PCIe bridge chip are output to the external NVMe hard drive through the external connector.

4. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes a 1553 bus protocol chip; The PL-IO core is provided on the PL side of the JFMQL series PSoC chip; the 1553 bus protocol chip is electrically connected to the PL-IO core on the PL side of the JFMQL series PSoC chip and is electrically connected to the external connector; The 1553 bus data required for interaction enters the 1553 bus protocol chip through the external connector. After the 1553 bus protocol chip parses the data, the parsed data is sent to the JFMQL series PSoC chip through the LOCALBUS bus, and then sent to the PCIe core through the on-chip bus inside the PL-IO core. The PCIe core packages it into PCIe data according to the PCIe protocol, and the data is expanded into two PCIe×4 ports through the PCIe bridge chip, and then output to the external NVMe hard drive through the external connector.

5. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that Also includes a first Ethernet PHY6 and a second Ethernet PHY7; The PS side of the JFMQL series PSoC chip includes two ETH cores; the first Ethernet PHY and the second Ethernet PHY are electrically connected to the two ETH cores of the PS side of the JFMQL series PSoC chip in sequence, and the first Ethernet PHY1 and the second Ethernet PHY2 are electrically connected to the external connector via the network transformer using RGMII; The Ethernet data required for interaction enters the JFMQL series PSoC chip through the external connector via the first Ethernet PHY1 and the second Ethernet PHY2. A network transformer is used between the electrical paths where the external Ethernet signal enters the Ethernet PHY chip to provide overvoltage protection against electrostatic discharge, pulses, and transient voltages. The PS-side ETH core then parses the data and sends it to the PCIe core via the on-chip bus. The PCIe core packages the data into PCIe data according to the PCIe protocol, and the data is expanded into two PCIe×4 ports via the PCIe bridge chip, and then output to the external NVMe hard drive via the external connector.

6. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes a FLASH chip, which is electrically connected to the PS end of the JFMQL series PSoC chip using Queued SPI to store the operating system boot loader.

7. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes an NVRAM chip, which is electrically connected to the PS end of the JFMQL series PSoC chip to record board self-test data and abnormal error data.

8. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes a JTAG plug-in component, which is electrically connected to the dedicated JTAG pin port on the PL side of the JFMQL series PSoC chip for burning system files and online debugging.

9. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that It also includes an input and output discrete quantity protection circuit, which is electrically connected to the PL-IO core of the PL end of the JFMQL series PSoC chip and is electrically connected to the external connector.

10. The JFMQL-based aviation airborne information processing board according to claim 1, characterized in that There are four DDR3 memory chips in total, two of which are electrically connected to the PS end of the JFMQL series PSoC chip using a FLY-BY topology to form a 32-bit DDR for system cache, and the other two chips are independently electrically connected to the PL end of the FPGA SOC chip to flexibly serve as data cache for high-speed signals.

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