Triple-modular redundancy data synchronization method and device based on FPGA

Abstract

The invention relates to the technical field of data processing, in particular to a triple modular redundancy data synchronization method and device based on an FPGA. The method comprises the following steps: performing three-mode synchronization based on a periodic synchronization signal generated by an FPGA (Field Programmable Gate Array); when data interaction needs to be carried out among the three modes, non-periodic data handshake is carried out among the three modes by adopting an FPGA (Field Programmable Gate Array); and after the data handshake succeeds, performing data interaction among the three modes by adopting the FPGA. According to the invention, on the basis of triple-modular redundancy periodic synchronization, a data handshake function is added before data interaction among the three moduli at any moment is executed, synchronization errors caused by hardware of a triple-modular redundancy system or other reasons are reduced, and triple-modular redundancy synchronization is realized more accurately. Meanwhile, periodic synchronization, data handshake and data interaction are realized by adopting an FPGA (Field Programmable Gate Array), and the time delay is further reduced on the basis of triple modular redundancy architecture synchronization, so that the synchronization precision of the synchronization method reaches + / -20ns.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a triple-module redundant data synchronization method and device based on FPGA. Background Art

[0002] Triple-module redundancy is a common fault-tolerant design technology used in aerospace equipment. Three modules run the same software and perform the same operations, with the majority of identical outputs representing the correct output. As long as no two identical errors occur simultaneously in the three modules, the faulty module's error is masked, ensuring correct system output. Because the three modules are independent, the probability of two modules failing simultaneously is extremely low, significantly improving system reliability. This technology is widely used in aerospace and other environments requiring high reliability.

[0003] Currently, to ensure consistent operation of the three redundant computers in a triple-module redundant system, most systems use periodic synchronization, synchronizing the computers at preset intervals. However, due to differences in hardware design and crystal oscillators between the three modules, as well as other factors, synchronization errors between the modules accumulate over time. Therefore, periodic synchronization cannot meet the requirements of certain devices with high synchronization requirements, such as rockets. Summary of the Invention

[0004] In view of this, the present invention provides a triple-mode redundant data synchronization method and device based on FPGA to solve the problem that periodic synchronization cannot meet the triple-mode data synchronization requirements.

[0005] In the first aspect, the present invention provides a FPGA-based triple-mode redundant data synchronization method, including: synchronizing the three modes based on a periodic synchronization signal generated by the FPGA; when any mode determines to interact with other modes for data, using the FPGA to perform non-periodic data handshakes between the three modes; when the data handshake is successful, using the FPGA to interact with the three modes.

[0006] This invention builds on the triple-module redundant periodic synchronization by adding a data handshake function before any data exchange between the three modules. This reduces synchronization errors caused by hardware or other issues in the three-module computers, and more accurately achieves synchronization within the triple-module redundant architecture. Furthermore, by using an FPGA to implement periodic synchronization, data handshake, and data exchange, this method further reduces latency, achieving a synchronization accuracy of ±20ns, based on the triple-module redundant architecture.

[0007] In an optional embodiment, when any module determines to interact with other modules for data, an FPGA is used to perform non-periodic data handshakes between the three modules, including: when any module determines to interact with other modules for data, a handshake request signal is sent to the FPGA; the FPGA is used to send the handshake request signal to the FPGAs of the other two modules, and the handshake request signals of the other two modules are received; and whether the data handshake is successful is determined based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high level.

[0008] In an optional embodiment, whether the data handshake is successful is judged based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modes and whether the three handshake request signals are high levels, including: when the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modes is within the allowed time, and the three handshake request signals are all high levels, it is judged that the data handshake between the module sending the handshake request signal and the other two modules is successful; otherwise, it is judged that the data handshake has failed.

[0009] In an optional implementation, the method further includes: when the data handshake fails, not performing data interaction with the modules where the data handshake fails; and performing data voting based on the modules where the data handshake succeeds.

[0010] In the second aspect, the present invention provides a three-module redundant data synchronization device based on FPGA, including: a periodic signal synchronization module, which is used to send the periodic synchronization signal generated by the FPGA of each module to the FPGA of the other two modules to synchronize the three modules; a data handshake module, which is used to receive a handshake request signal sent when any module determines to interact with other modules for data, and perform data handshake between the three modules according to the handshake request signal, and determine whether the handshake is successful; a data interaction module, which is used to interact data between the modules after the data handshake is successful.

[0011] In an optional embodiment, the data handshake module includes: a handshake request sending module, which is used to receive a handshake request signal sent when any module determines to interact with other modules for data, and send the handshake request signal to the other two modules; a handshake request signal receiving module, which is used to receive the handshake request signals of the other two modules; and a verification module, which is used to determine whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high level.

[0012] In an optional embodiment, the verification module is specifically used to: when the time difference between sending a handshake request signal and receiving the handshake request signals of the other two modules is within the allowed time, and the three handshake request signals are all high level, determine that the data handshake between the module sending the handshake request signal and the other two modules is successful; otherwise, determine that the data handshake fails.

[0013] In an optional implementation, the data interaction module is specifically configured to: when the data handshake succeeds, receive the data to be interacted with, and send the data to the module where the data handshake succeeds.

[0014] In the present invention, the functions of the above-mentioned modules are implemented through FPGA, which can avoid the built-in synchronization logic in the three modules and reduce hardware complexity and cost. At the same time, the clock independence and gate circuit delay controllability of FPGA are utilized to achieve ±20ns level synchronization. In addition, through the handshake failure mechanism, abnormal modules in the three modules are identified in real time to prevent the spread of data errors.

[0015] In a third aspect, the present invention provides a three-module redundant system, wherein each module of the three-module redundant system includes an FPGA and a CPU, and the three FPGAs are connected by IO ports; the FPGA is used to generate a periodic synchronization signal and send it to two external modules; the three modules are used to synchronize according to the periodic synchronization signal; when any module determines to exchange data with other modules, the FPGA is also used to perform non-periodic data handshakes between the three modules, and after the data handshake is successful, send a data handshake success signal to the CPUs of the three modules; the three CPUs are also used to exchange data according to the data handshake success signal.

[0016] In an optional embodiment, when any module determines to interact with other modules for data, the module sends a handshake request signal to the FPGA; the FPGA sends the handshake request signal to the FPGAs of the other two modules, and receives the handshake request signals from the other two modules. It is determined whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high levels. When the data handshake is successful, a data handshake success signal is sent to the CPU where the data handshake is successful. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 1 is a flow chart of a triple-module redundant data synchronization method based on FPGA according to an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of the accumulated error of the synchronization signal during the synchronization period according to an embodiment of the present invention;

[0020] Figure 3 1 is a block diagram of a triple-module redundant data synchronization device based on FPGA according to an embodiment of the present invention;

[0021] Figure 4 2 is a schematic diagram of the working process of a triple modular redundancy system according to an embodiment of the present invention;

[0022] Figure 5 is a schematic diagram of three-mode handshake synchronization according to an embodiment of the present invention;

[0023] Figure 6 2 is a schematic diagram of a data handshake timing sequence according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0026] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components; wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0027] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0028] According to an embodiment of the present invention, an embodiment of a triple-module redundant data synchronization method based on FPGA is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0029] In this embodiment, a triple-module redundant data synchronization method based on FPGA is provided and implemented using FPGA. Figure 1 FIG. 1 is a flow chart of a triple-module redundant data synchronization method based on FPGA according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0030] Step S101, synchronization between the three modules is performed based on the periodic synchronization signal generated by the FPGA. Specifically, rocket flight control involves extreme environments (such as vibration, radiation, high temperature) and complex tasks (such as multi-orbit adaptation and reuse), which places extremely high demands on the reliability and synchronization accuracy of the control system. Therefore, this embodiment constructs a three-module redundant system in the rocket control system by deploying three sets of independent modules in parallel, namely three modules (respectively as module A, module B and module C). For each module, it contains structures such as module, memory and bus, among which the module is used for data scheduling and fault decision-making. In addition, in the related art, synchronization between the three modules is mostly achieved based on the module. However, the module-based synchronization process mostly requires software processing, which may take a long time.

[0031] Based on this, this embodiment further provides an FPGA that generates a periodic synchronization signal and sends it to the two external modules through the IO port to achieve three-module synchronization. Specifically, the FPGA can periodically send synchronization signals to achieve synchronization between the three modules. The specific synchronization method can be implemented with reference to related technologies and will not be described in detail here. Among them, the FPGA has an independent high-precision clock source (such as a crystal oscillator), which is decoupled from the clocks of the three modules, and can avoid timing errors caused by clock drift between modules.

[0032] In step S102, when any module determines to exchange data with another module, an FPGA is used to perform a non-periodic data handshake between the three modules. Specifically, according to related art, when only periodic synchronization is used, synchronization errors between the three modules can accumulate over time due to differences in hardware design and crystal oscillators, or other factors. Therefore, unacceptable synchronization errors may exist between the three modules during data exchange.

[0033] Among them, there is only periodic synchronization between the three modes. Figure 2As shown in the figure, the three modes are called A, B, and C. Assuming that the hardware delay of mode B is greater than that of mode A, and that the hardware delay of mode C is greater than that of mode B, at synchronization time N, the three-mode synchronization signals are aligned after synchronization is completed. At time t1, the three-mode signals become misaligned due to hardware delay or other factors. At time t4, the misalignment further increases until the misalignment error caused by hardware delay or other factors reaches its maximum before the arrival of synchronization time N+1. After reaching synchronization time N+1, the misalignment is temporarily eliminated, and the three modes are aligned again. For example, if data packet A needs to be sent at time t1, then if only periodic synchronization is used, the data from mode A, mode B, and mode C will be sent at times t1, t2, and t3, respectively. Furthermore, if data exchange between the three modes is transmitted in a misaligned state, the arrival time of the data from the three modes at the actuator will also vary, resulting in inconsistent actuator operation.

[0034] Based on this, this embodiment further provides a data handshake synchronization method based on periodic synchronization. Specifically, at any time between two periodic synchronizations, before the CPU has a data exchange request, the CPU starts the data handshake function, that is, notifies the FPGA to perform the data handshake function between the modules. Among them, the FPGA implements the "hard coding" of the handshake logic through a hardware description language (such as Verilog / VHDL), thereby controlling the delay to the nanosecond level while ensuring synchronization. In addition, whether data exchange is to be performed can be determined by the module. That is, when a module in any module determines that data exchange is required, the FPGA is controlled to perform data handshakes between the three modules.

[0035] Step S103, when the data handshake is successful, FPGA is used to perform data exchange between modules. Specifically, when the data handshake is successful, data exchange between modules is performed. Among them, when performing data exchange, this embodiment also uses FPGA to implement. For example, if it is determined that module A needs to exchange data, then after the three-module handshake is successful, FPGA notifies module A through the IO port that "data can be sent" and establishes a temporary data transmission channel between module A and module B / C (such as through FPGA cache or direct forwarding). The CPU of module A sends the data to the FPGA of module A through the bus, and then the FPGA of module A forwards it to the FPGA of module B / C.

[0036] This invention builds on the triple-module redundant periodic synchronization by adding a data handshake function before any data exchange between the three modules. This reduces synchronization errors caused by hardware or other issues in the three-module computers, and more accurately achieves synchronization within the triple-module redundant architecture. Furthermore, by using an FPGA to implement periodic synchronization, data handshake, and data exchange, this method further reduces latency, achieving a synchronization accuracy of ±20ns, based on the triple-module redundant architecture.

[0037] In this embodiment, a triple-module redundant data synchronization method based on FPGA is provided, which includes the following steps:

[0038] Step S201: Synchronize the three modules based on the periodic synchronization signal generated by the FPGA. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0039] Step S202: When any module determines to exchange data with other modules, FPGA is used to perform non-periodic data handshake between the three modules.

[0040] Specifically, the above step S202 includes:

[0041] Step S2021: When any module determines to exchange data with another module, it sends a handshake request signal to the FPGA. Specifically, when the CPU of a module (such as module A) determines that it needs to exchange data with another module, it sends a handshake request signal to the FPGA of the module via the internal bus.

[0042] In step S2022, the FPGA is used to send a handshake request signal to the FPGAs of the other two modules, and to receive the handshake request signals sent by the FPGAs of the other two modules. Specifically, after the FPGA of module A receives the handshake request signal from the CPU of module A, it sends a handshake request signal (such as an electrical signal pulse) to the hardware interfaces of modules B and C through the IO port. In addition, the FPGAs of modules B and C also send handshake request signals to the FPGA of module A. When the FPGA of module A sends signals to modules B and C and receives handshake request signals from modules B and C, direct transmission via physical lines can be used to improve response speed.

[0043] Step S2023 determines whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules, and whether the three handshake request signals are at a high level. Specifically, if the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules is within the allowed time, and all three handshake request signals are at a high level, the data handshake between the module sending the handshake request signal and the other two modules is determined to be successful; otherwise, the data handshake is determined to have failed.

[0044] Among them, the FPGA can use its internal timer to determine whether the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modes is within the allowed time. Specifically, when the handshake request signal is sent by mode A, it is necessary to separately determine whether the time difference between sending the handshake request signal and receiving the handshake request signal of mode B, and the time difference between sending the handshake request signal and receiving the handshake request signal of mode C are within the allowed time respectively.

[0045] At the same time, it is also necessary to determine whether the three handshake request signals are high-level signals. Only when the signals are high-level are they judged as valid signals. By using high-level signals as valid signals, the signal's anti-interference ability can be improved. Therefore, based on the above content, the data handshake is judged to be successful only when the time difference is within the allowed time and the three handshake request signals are high-level signals. Specifically, when the handshake request signal is sent by module A, the time difference between sending the handshake request signal and receiving the handshake request signal by module B is within the allowed time, and the handshake request signal is a high-level signal, the data handshake between module A and module B is determined to be successful. If any one of them does not meet the requirements, such as a large time difference or a low-level signal, the data handshake is judged to have failed. Similarly, the same method is used to determine whether the handshake between module A and module C is successful.

[0046] Step S203: After the data handshake succeeds, FPGA is used to perform data exchange between the three modules.

[0047] Step S204: When the data handshake fails, data exchange is not performed with the module where the data handshake fails.

[0048] Step S205: Data voting is performed based on the model of successful data handshake.

[0049] Specifically, after the data handshake between the three modules is completed, data exchange occurs only between the modules that successfully completed the handshake. For example, according to step S2023, if the data handshake between modules A and B is successful, but the handshake between modules A and C fails, the CPU in module A will send the data to module B via the FPGA. Furthermore, during the next step of voting on the data among the three modules, the data from module C is discarded, and only the data from modules A and B is processed. A failed handshake indicates that the module was unable to interact in a timely manner, possibly due to hardware failure, communication interruption, or other reasons. Therefore, the module is discarded during voting, thus achieving fault isolation.

[0050] In this embodiment, a triple-module redundant data synchronization device based on FPGA is provided. Figure 3 As shown, the device includes:

[0051] The periodic signal synchronization module 31 is used to send the periodic synchronization signal generated by the FPGA of each module to the FPGAs of the other two modules to synchronize the three modules;

[0052] The data handshake module 32 is configured to receive a handshake request signal sent by any module when it determines to exchange data with other modules, perform a data handshake between the three modules according to the handshake request signal, and determine whether the handshake is successful;

[0053] The data interaction module 33 is used to perform data interaction between the three modes after the data handshake is successful.

[0054] In an optional implementation, the data handshake module includes:

[0055] A handshake request sending module is used to send a handshake request signal when any module determines to exchange data with other modules, and send the handshake request signal to the other two modules;

[0056] A handshake request receiving module is used to receive handshake request signals sent by the other two modules;

[0057] The verification module is used to determine whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high level.

[0058] In an optional implementation, the verification module is specifically configured to:

[0059] When the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules is within the allowed time, and the three handshake request signals are all high, it is judged that the data handshake between the module sending the handshake request signal and the other two modules is successful; otherwise, it is judged that the data handshake fails.

[0060] In an optional implementation, the data interaction module is specifically configured to:

[0061] When the data handshake succeeds, the data to be exchanged is received and sent to the module where the data handshake succeeds.

[0062] It should be noted that each module in the above-mentioned device can be implemented by the hardware structure in the FPGA. For example, the FPGA includes a clock source, a hardware gate circuit, and an IO interface (connecting a handshake line or a data line, etc.). Specifically, when using FPGA to implement functions such as cycle synchronization, data handshake, and data interaction, it can be mapped to the gate-level circuit (such as a trigger, a multiplexer, a comparator) inside the FPGA through language descriptions such as Verilog / VHDL to achieve hardware solidification. The parallel processing characteristics of the hardware circuit ensure nanosecond response (such as ±20ns synchronization accuracy), which far exceeds the timing control capability of the software program (microsecond level).

[0063] In the present invention, the functions of the above-mentioned modules are implemented through FPGA, which can avoid the built-in synchronization logic in the three modules and reduce hardware complexity and cost. At the same time, the clock independence and gate circuit delay controllability of FPGA are utilized to achieve ±20ns level synchronization. In addition, through the handshake failure mechanism, abnormal modules in the three modules are identified in real time to prevent the spread of data errors.

[0064] In this embodiment, a triple-module redundant system is provided. Each module of the triple-module redundant system includes an FPGA and a CPU, and the three FPGAs are connected via IO ports. The FPGA is used to generate a periodic synchronization signal and send it to the other two modules. The three modules are used to synchronize according to the periodic synchronization signal. When any module determines to exchange data with the other modules, the FPGA is also used to perform a non-periodic data handshake between the three modules and send a data handshake success signal to the CPUs of the three modules after the data handshake is successful. The three modules are also used to exchange data according to the data handshake success signal.

[0065] In an optional embodiment, when any module determines to exchange data with other modules, the module sends a handshake request signal to the FPGA; the FPGA sends the handshake request signal to the other two modules and receives the handshake request signals of the other two modules. It determines whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high level. When the data handshake is successful, a data handshake success signal is sent to the computer where the data handshake is successful.

[0066] In an optional embodiment, as Figure 4 As shown, the triple-module redundant system can specifically work in the following process:

[0067] An FPGA is used to generate a high-precision periodic synchronization signal between the three modes, such as a 10ms periodic synchronization signal. This synchronization signal is sent to the three modes for synchronization. The CPU schedules all messages based on the periodic synchronization on the FPGA side. Between two periodic synchronization signals, a handshake request signal is added when data exchange between the three modes is required. For example, when mode A needs to exchange data between the three modes, the FPGA side is first commanded to perform a non-periodic handshake, that is, a start handshake request signal (handshake request signal) is sent to the FPGA. After the handshake is successful, a handshake success signal is sent to the CPU. The CPU then sends the exchange data between the three modes through the FPGA. If the handshake fails, the CPU is notified of the handshake failure and the CPU initiates the handshake failure process. Periodic synchronization, data handshake, and data exchange between the three modes are all implemented through the FPGA's IO port.

[0068] Among them, the data handshake method is as follows Figure 5 As shown in the figure, each module A, B and C sends a handshake request signal to the other two modules and receives the handshake request signals from the other two modules at the same time. When the handshake request signals of the module and the other two modules are all high level within the specified handshake time, the handshake is successful. Figure 6As shown, taking module A as an example, data transmission between the three modules is required at time t7. All three modules initiate a data handshake. Module A initiates a handshake request signal at time t7, module B transmits its handshake request signal to module A at time t8, and module C transmits its handshake request signal to module A at time t9. According to the aforementioned handshake rules, if t9-t7 is less than or equal to the handshake time allowed, module A completes the data handshake at time t9 and sends the data to modules B and C. If t9-t7 is greater than the handshake time allowed, then only module B succeeds in the handshake within module A, while module C fails. This indicates that module C's delay is too large. In this case, module A will not send data to module C, but only to module B. Therefore, module C does not receive the data from module A and will proceed to the next step during the three-module data voting process, such as discarding the data from module C and processing only the data from modules A and B.

[0069] Although exemplary embodiments and their advantages have been described in detail, those skilled in the art may make various changes, substitutions, and modifications to these embodiments without departing from the spirit of the present invention and the scope of protection defined by the appended claims. Such modifications and variations fall within the scope defined by the appended claims. For other examples, those skilled in the art will readily appreciate that the order of the process steps may be varied while remaining within the scope of protection of the present invention.

[0070] Furthermore, the scope of application of the present invention is not limited to the processes, mechanisms, manufactures, compositions of matter, means, methods, and steps of the specific embodiments described in the specification. From the disclosure of the present invention, a person of ordinary skill in the art will readily understand that any currently existing or later developed processes, mechanisms, manufactures, compositions of matter, means, methods, or steps that perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein may be applied in accordance with the present invention. Therefore, the claims appended hereto are intended to include within their scope such processes, mechanisms, manufactures, compositions of matter, means, methods, or steps.

Claims

1. A triple-module redundant data synchronization method based on FPGA, characterized in that: include: Synchronize the three modes based on the periodic synchronization signal generated by FPGA; When any of the three modules decides to exchange data with other modules, FPGA is used to perform non-periodic data handshake between the three modules. When the data handshake is successful, FPGA is used to perform data interaction between the three modules.

2. The method according to claim 1, characterized in that When any module decides to exchange data with other modules, the FPGA is used to perform a non-periodic data handshake between the three modules, including: When any module determines to exchange data with other modules, it sends a handshake request signal to the FPGA; Use FPGA to send handshake request signals to the FPGAs of the other two modules, and receive handshake request signals sent by the FPGAs of the other two modules; Whether the data handshake is successful is determined based on the time difference between sending the handshake request signal and receiving the two external two-module handshake request signals and whether the three handshake request signals are high level.

3. The method according to claim 2, characterized in that The success of the data handshake is determined based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high, including: When the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules is within the allowed time, and the three handshake request signals are all high, it is determined that the data handshake between the module sending the handshake request signal and the other two modules is successful; Otherwise, it is determined that the data handshake fails.

4. The method according to claim 1, wherein The method further comprises: When the data handshake fails, no data interaction is performed with the module where the data handshake fails. Data voting is performed based on the model of successful data handshake.

5. A triple-module redundant data synchronization device based on FPGA, characterized in that: include: The periodic signal synchronization module is used to send the periodic synchronization signal generated by the FPGA of each module to the FPGA of the other two modules to synchronize the three modules; The data handshake module is used to receive a handshake request signal sent by any module when it determines to exchange data with other modules, perform data handshake between the three modules according to the handshake request signal, and determine whether the handshake is successful; The data interaction module is used to perform data interaction between the three modes after the data handshake is successful.

6. The device according to claim 5, characterized in that The data handshake module includes: A handshake request sending module is used to receive a handshake request signal sent when any module determines to exchange data with other modules, and send the handshake request signal to the other two modules; A handshake request receiving module is used to receive handshake request signals sent by the other two modules; The verification module is used to determine whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high level.

7. The device according to claim 6, characterized in that The verification module is specifically used for: When the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules is within the allowed time, and the handshake request signal and the handshake request signals of the other two modules are both high, it is determined that the data handshake between the module sending the handshake request signal and the other two modules is successful; Otherwise, it is determined that the data handshake fails.

8. The device according to claim 5, characterized in that The data interaction module is specifically used for: When the data handshake succeeds, the data to be exchanged is received and sent to the module where the data handshake succeeds.

9. A triple-module redundancy system, characterized in that: Each module of the triple-module redundant system includes an FPGA and a CPU, and the three FPGAs are connected by IO ports; The FPGA is used to generate a periodic synchronization signal and send it to the other two modules; The three modes are used for synchronization according to the periodic synchronization signal; When any module determines to exchange data with other modules, the FPGA is further used to perform non-periodic data handshake between the three modules, and send a data handshake success signal to the CPUs of the three modules after the data handshake is successful; The three CPUs are further configured to perform data exchange according to a data handshake success signal.

10. The system according to claim 9, characterized in that: When any module determines to exchange data with another module, the module sends a handshake request signal to the FPGA; The FPGA sends a handshake request signal to the FPGAs of the other two modules and receives the handshake request signals of the other two modules. It determines whether the data handshake is successful based on the time difference between sending the handshake request signal and receiving the handshake request signals of the other two modules and whether the three handshake request signals are high level. When the data handshake is successful, it sends a data handshake success signal to the CPU where the data handshake is successful.

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