Intelligent calibration multi-channel clock chip system and control method

Abstract

The invention belongs to the technical field of clock chips, and discloses an intelligent calibration multi-channel clock chip system and a control method, the system comprises a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the clock output branch comprises a numerical control circuit and a frequency divider which are connected with each other; the initial phase-locked loop is used for receiving an input clock signal, performing frequency multiplication on the input clock signal to obtain a reference clock signal, and sending the reference clock signal to the numerical control circuit of the at least one clock output branch through the selector; and the numerical control circuit is used for eliminating the distributed transmission delay difference in the reference clock signal by adopting a digital compensation algorithm, generating a target clock signal according to the reference clock signal after the delay difference is eliminated, and sending the target clock signal to the corresponding frequency divider. According to the invention, the absolute synchronization error of each clock output branch can be reduced, and the application scene diversity and flexibility of the clock chip are improved.

Description

Technical Field

[0001] The present application relates to the technical field of clock chips, and in particular to an intelligently calibrated multi-channel clock chip system and a control method. Background Art

[0002] As more and more functional modules are integrated into modern electronic systems, each module may require clock signals of different frequencies and phases. Therefore, the functional requirements of clock generators are also increasing. Clock generators with more channels can flexibly provide appropriate clock signals for new modules or functions through programming without replacing hardware, making it easier to upgrade and expand the system. For example, a multi-channel clock generator first uses a crystal oscillator with a fixed frequency as the reference clock of the internal clock, and then multiplies the reference clock through multiple dividers to generate multiple independently adjustable clocks.

[0003] However, in current clock generators, the initial reference clock signal generated by the phase-locked loop is transmitted to each divider through a distributed wiring network. The transmission path lengths and parasitic parameters of different channels are different, which not only causes differences in the time it takes for the clock signal to reach each divider, resulting in clock deviation, but the internal circuit noise of the main phase-locked loop (such as thermal noise, 1 / f noise, etc.) will also be amplified or accumulated during the long transmission process, resulting in synchronization errors in the clocks output by each channel. Summary of the Invention

[0004] The present application provides an intelligently calibrated multi-channel clock chip system and control method, which can reduce the absolute synchronization error of each clock output branch and improve the diversity and flexibility of application scenarios of the clock chip.

[0005] In a first aspect, an embodiment of the present application provides a multi-channel clock chip system with intelligent calibration, comprising a coprocessor, an initial phase-locked loop, a selector, and a plurality of clock output branches; the initial phase-locked loop and the selector are connected; The clock output branch includes a digital control circuit and a frequency divider connected to each other; Each digital control circuit is connected to the selector respectively; each frequency divider is connected to the coprocessor respectively; The initial phase-locked loop is used to receive an input clock signal, multiply the input clock signal, obtain a reference clock signal and send it to a digital control circuit of at least one clock output branch through a selector; The digital control circuit is used to eliminate the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generate a target clock signal according to the reference clock signal after the delay difference is eliminated, and send it to the corresponding frequency divider; The coprocessor is used to receive clock mode information, determine clock control parameters according to the clock mode information, and control each frequency divider to adjust the target clock signal and output it according to the clock control parameters.

[0006] Furthermore, the coprocessor is specifically configured to receive clock mode information through a digital pin level combination, and use a clock frequency parameter corresponding to the clock mode information as a clock control parameter; or receive the clock control parameter through an I2C interface or an SPI interface.

[0007] Furthermore, the clock mode information includes 5G base station mode and vehicle system mode.

[0008] Furthermore, the lines between the initial phase-locked loop and each digital control circuit use differential spiral wiring, with the upper half covered with an electromagnetic shielding layer; the differential spiral wiring has a pitch of 1.5 microns and a line width of 3 microns; The electromagnetic shielding layer is made of tantalum-based composite material.

[0009] Furthermore, FBAR filters are embedded on the packaging substrates of the initial phase-locked loop and each digital control circuit; Each FBAR filter is connected to a coprocessor; The coprocessor is used to send the suppressed frequency band to each FBAR filter; The FBAR filter is used to suppress interference according to the received suppression frequency band.

[0010] Furthermore, the digital control circuit includes a time-to-digital conversion module, a processing module, and a digital control oscillation module connected in sequence; The time-to-digital conversion module is connected to the selector and is used to receive the reference clock signal, detect the phase difference between the local clock signal and the reference clock signal, and send the phase difference and the reference clock signal to the processing module; The processing module is used to adjust the phase of the digital control oscillation module according to the phase difference and the digital compensation algorithm, and send the reference clock signal to the digital control oscillation module after the adjustment; The digital controlled oscillator module is connected to the frequency divider and is used for receiving a reference clock signal, adjusting the frequency or phase of the reference clock signal, generating a target clock signal and sending the target clock signal to the frequency divider.

[0011] Furthermore, the processing module is also connected to the processing module in the adjacent clock output branch; The processing module is further configured to send the received phase difference as an adjacent phase difference to an adjacent processing module; And, receiving at least one adjacent phase difference, updating the received phase difference according to the adjacent phase difference; and adjusting the frequency or phase of the digitally controlled oscillation module according to the updated phase difference and the digital compensation algorithm.

[0012] Furthermore, the processing module is also used to obtain the temperature voltage compensation table and the control voltage of the digital control oscillation module; If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to a temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold; And, after adjusting the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, adjusting the frequency of the digitally controlled oscillation module according to the first compensation frequency value.

[0013] Furthermore, the system also includes a temperature sensing module; The temperature sensing module is used to collect the junction temperature data of each clock output branch and send it to the corresponding processing module; The processing module is also used to obtain the semiconductor carrier mobility temperature coefficient and the thermal expansion coefficient of the packaging material of the clock output branch; calculate the temperature delay change based on the junction temperature data, the semiconductor carrier mobility temperature coefficient, the thermal expansion coefficient and the preset calibration temperature; obtain the temperature compensation frequency value in the temperature voltage compensation table based on the temperature delay change, and adjust the frequency of the numerical control oscillation module based on the temperature compensation frequency value and the first compensation frequency value.

[0014] Furthermore, the system also includes a voltage sensing module; the voltage sensing module is used to measure the power supply voltage of each clock output branch and send it to the corresponding processing module; The processing module is used to calculate the voltage delay change based on the power supply voltage, the preset nominal voltage and the preset delay reference value, obtain the second compensation frequency value in the temperature voltage compensation table according to the voltage delay change, and adjust the frequency of the numerical control oscillation module according to the first compensation frequency value, the second compensation frequency value and the temperature compensation frequency value.

[0015] Furthermore, the digitally controlled oscillation module is specifically configured to divide the frequency control word by a power of 2 and then multiply the result by the frequency of the reference clock signal to obtain the frequency of the target clock signal; wherein the power is the bit width of the phase accumulator of the digitally controlled oscillation module.

[0016] Furthermore, the processing module is also used to calculate the average delay change based on multiple temperature delay changes and multiple voltage delay changes within a preset period; obtain the running time of the numerical control oscillation module; obtain the aging factor of the clock output branch based on the average delay change and the running time; and issue an aging warning when the aging factor is greater than a preset aging threshold.

[0017] Furthermore, the processing module is also used to obtain the historical frequency error of each clock output branch; construct an error probability density function based on each historical delay error, extract the fixed offset of the preset frequency point based on the error probability density function, and use it as a systematic deviation component; update the network parameters of the first linear model and the second linear model based on the systematic deviation component and recursive least squares method.

[0018] Furthermore, the system also includes a compensation adaptive module; The compensation adaptive module is respectively connected to the initial phase-locked loop and each time-to-digital conversion module; The compensation adaptive module is used to control the initial phase-locked loop to generate a frequency sweep signal and send it to each time-to-digital conversion module; obtain the transmission delay data of different frequency points recorded by each time-to-digital conversion module; generate a compensation coefficient matrix corresponding to each clock output branch based on the transmission delay data; and update the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix and send it to the processing module of the clock output branch.

[0019] In a second aspect, an embodiment of the present application provides a multi-channel clock chip control method with intelligent calibration, which is applied to a multi-channel clock chip control system. The multi-channel clock chip control system includes a coprocessor, an initial phase-locked loop, a selector, and multiple clock output branches; the clock output branches include interconnected digital control circuits and frequency dividers; the control method includes: The initial phase-locked loop receives an input clock signal, multiplies the input clock signal, obtains a reference clock signal and sends it to a digital control circuit of at least one clock output branch through a selector; The digital control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal based on the reference clock signal after the delay difference is eliminated, and sends it to the corresponding divider; The coprocessor receives the clock mode information, determines the clock control parameters according to the clock mode information, and controls each frequency divider according to the clock control parameters to adjust the target clock signal and then output it.

[0020] Furthermore, the method further comprises: The coprocessor receives clock mode information through a combination of digital pin levels; Alternatively, the coprocessor receives the clock control parameters via an I2C interface or an SPI interface.

[0021] Furthermore, the digital control circuit includes a time-to-digital conversion module, a processing module, and a digital control oscillation module connected in sequence; The digital control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal based on the reference clock signal after the delay difference is eliminated, and sends it to the corresponding frequency divider, including: The time-to-digital conversion module receives a reference clock signal, detects a phase difference between the local clock signal and the reference clock signal, and sends the phase difference and the reference clock signal to the processing module; The processing module adjusts the phase of the digital control oscillation module according to the phase difference and the digital compensation algorithm, and sends the reference clock signal to the digital control oscillation module after the adjustment; The digital controlled oscillator module receives a reference clock signal, adjusts the frequency or phase of the reference clock signal, generates a target clock signal and sends it to the frequency divider.

[0022] Furthermore, the processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, including: The processing module sends the received phase difference as an adjacent phase difference to the processing module of the adjacent clock output branch; The processing module receives at least one adjacent phase difference, updates the received phase difference according to the adjacent phase difference, and adjusts the frequency or phase of the digital control oscillation module according to the updated phase difference and the digital compensation algorithm.

[0023] Furthermore, the method further comprises: The processing module is also used to obtain the temperature voltage compensation table and the control voltage of the digital control oscillation module; If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to a temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold; The frequency of the digital controlled oscillation module is adjusted according to the first compensation frequency value.

[0024] Furthermore, the method further comprises: The compensation adaptive module controls the initial phase-locked loop to generate a frequency sweep signal and sends it to each time-to-digital conversion module; obtains the transmission delay data of different frequency points recorded by each time-to-digital conversion module; generates a compensation coefficient matrix corresponding to each clock output branch based on the transmission delay data; and updates the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix and sends it to the processing module of the clock output branch.

[0025] In summary, compared with the prior art, the technical solutions provided by the embodiments of the present application have at least the following beneficial effects: An embodiment of the present application provides an intelligently calibrated multi-channel clock chip system. First, in a distributed transmission architecture, a digital control circuit is added to each clock output branch, which is used to use a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal before the reference clock signal reaches the divider, and then generate a target clock signal based on the reference clock signal after eliminating the delay difference, thereby reducing the absolute synchronization error of each clock output branch; secondly, a coprocessor is added to control the divider of each clock output branch, so that the divider's multiplication operation of the target clock signal can be flexibly adjusted according to the usage scenario, so that the multi-channel clock chip of the present application can adapt to the clock requirements of different scenarios and even new scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A structural diagram of an intelligently calibrated multi-channel clock chip system provided in one embodiment of the present application.

[0027] Figure 2 This is a diagram of the internal structure of a numerical control circuit provided in one embodiment of the present application.

[0028] Figure 3 A flowchart of a multi-channel clock chip control method for intelligent calibration provided by one embodiment of the present application.

[0029] Figure 4 A flowchart of the target clock signal generation steps provided in one embodiment of the present application.

[0030] Figure 5 Flowchart of the temperature voltage compensation table update steps provided for one embodiment of the present application DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0032] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative work shall fall within the scope of protection of this application.

[0033] See Figure 1 An embodiment of the present application provides an intelligently calibrated multi-channel clock chip system, including a coprocessor, an initial phase-locked loop, a selector, and multiple clock output branches; the initial phase-locked loop and the selector are connected.

[0034] The clock output branch includes a digital control circuit and a frequency divider connected to each other.

[0035] Each numerical control circuit is connected to the selector respectively; each frequency divider is connected to the coprocessor respectively.

[0036] The initial phase-locked loop is used to receive an input clock signal, multiply the input clock signal, obtain a reference clock signal, and send the reference clock signal to a digital control circuit of at least one clock output branch through a selector.

[0037] The digital control circuit is used to eliminate the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generate a target clock signal according to the reference clock signal after the delay difference is eliminated, and send it to the corresponding divider.

[0038] The coprocessor is used to receive clock mode information, determine clock control parameters according to the clock mode information, and control each frequency divider to adjust the target clock signal and output it according to the clock control parameters.

[0039] Specifically, the clock chip architecture of this application is as follows: Figure 1 As shown, the overall distributed hybrid PLL architecture is adopted. The initial phase-locked loop multiplies the clock signal input by the input stage circuit to generate a high-precision reference clock, which is transmitted to the digital control circuit of each clock output branch through a low-noise distributed wiring network. The digital control circuit configured for each clock output branch supports 0.1ps level phase fine-tuning, and adopts a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock, so as to achieve an absolute synchronization error of less than 5ps for each clock output branch; at the same time, a micro coprocessor is integrated and connected to each divider; the coprocessor is used to receive clock mode information and control the frequency or phase parameters of each divider according to the clock control parameters corresponding to the clock mode information, so that the divider outputs a clock signal that meets the requirements of the clock mode information.

[0040] In specific implementations, clock mode information may include 5G base station mode and vehicle system mode. The coprocessor is specifically used to receive clock mode information through digital pin level combinations, such as 01 for 5G base station mode and 00 for vehicle system mode. The coprocessor also pre-stores the required clock frequency parameters for each clock mode information and uses the clock frequency parameters corresponding to the clock mode information as clock control parameters. Alternatively, the coprocessor receives the clock control parameters through an I2C interface or an SPI interface. A transfer learning algorithm can also be added to the coprocessor to enable the clock chip to adapt to the clock requirements of new scenarios.

[0041] The above embodiment provides an intelligently calibrated multi-channel clock chip system. First, in a distributed transmission architecture, a digital control circuit is added to each clock output branch, which is used to use a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal before the reference clock signal reaches the divider, and then generate a target clock signal based on the reference clock signal after eliminating the delay difference, thereby reducing the absolute synchronization error of each clock output branch; secondly, a coprocessor is added to control the divider of each clock output branch, so that the divider's multiplication operation of the target clock signal can be flexibly adjusted according to the usage scenario, so that the multi-channel clock chip of the present application can adapt to the clock requirements of different scenarios and even new scenarios.

[0042] In some embodiments, the lines between the initial phase-locked loop and each digital control circuit use differential spiral wiring, with the upper half covered with an electromagnetic shielding layer; the differential spiral wiring has a pitch of 1.5 microns and a line width of 3 microns.

[0043] The above differential spiral wiring scheme can reduce the crosstalk between the lines of the clock chip by about 30%.

[0044] Furthermore, the power supply line of the entire chip can adopt a honeycomb power supply network to reduce power supply noise coupling.

[0045] The electromagnetic shielding layer is made of tantalum-based composite material, and its shielding effectiveness can be greater than 45dB@10GHz.

[0046] In some embodiments, FBAR filters are embedded on the packaging substrates of the initial phase-locked loop and each digital control circuit.

[0047] Each FBAR filter is connected to a coprocessor respectively.

[0048] The coprocessor is used to send the suppression frequency band to each FBAR filter.

[0049] The FBAR filter is used to suppress interference according to the received suppression frequency band.

[0050] Among them, the FBAR filter is a thin film bulk acoustic resonator, whose core function is to achieve precise management of signals in different frequency bands in wireless communication equipment through frequency selection, noise suppression and signal processing.

[0051] The FBAR filter uses the inverse piezoelectric effect of piezoelectric film to convert electrical energy into acoustic wave resonance. It filters and enhances signals through resonance at a specific frequency, effectively isolating interference signals and ensuring that the device only receives signals in the target frequency band.

[0052] Moreover, the FBAR filter manufactured using MEMS technology is only 1 / 3 to 1 / 2 the size of a traditional ceramic filter and can withstand higher power, meeting the requirements of multi-channel clock chips for small area and multiple application scenarios.

[0053] Specifically, the coprocessor can be programmed to control the FBAR filter to suppress frequency bands such as 2.4 GHz and 5.8 GHz that are likely to interfere with the clock signal. Different FBAR filters may suppress different frequency bands.

[0054] Please attend Figure 2 In some embodiments, the digital control circuit includes a time-to-digital conversion module, a processing module, and a digital control oscillation module connected in sequence. The time-to-digital conversion module is connected to the selector and is configured to receive a reference clock signal, detect a phase difference between the local clock signal and the reference clock signal, and transmit the phase difference and the reference clock signal to the processing module.

[0055] Specifically, the time-to-digital conversion module detects the phase difference periodically, and the detection period can be within 1ms~1s. The phase difference detected in each period will be sent to the processing module, and the reference clock signal is sent to the processing module in real time.

[0056] The processing module is used to adjust the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, and send the reference clock signal to the digitally controlled oscillation module after the adjustment.

[0057] Specifically, the processing module adjusts the phase of the digital control oscillation module based on the latest received phase difference.

[0058] It should be noted that the digitally controlled oscillator (DCO) module is a digitally controlled oscillator. Its core function is to generate a controllable, high-precision digital signal based on digital control instructions (frequency control word or phase offset word). The phase of the DCO module being adjusted here is the DCO's phase offset word.

[0059] In the specific implementation process, the digital compensation algorithm can be a PID control algorithm: in, It represents the control parameter output by the discrete PID controller at the nth moment. This control parameter is usually used to control the controlled object. In the clock chip system used in this application, this control parameter is the phase offset word that controls the numerical control oscillation module so that the numerical control oscillation module can achieve phase adjustment of the reference clock signal.

[0060] is the proportional coefficient, which determines the instantaneous response of the PID controller to the error. The larger it is, the stronger the PID controller responds to the current error, the larger the output control parameter is, and the faster the error can be reduced.

[0061] is the integral coefficient, which is mainly used to eliminate the steady-state error of the system. It accumulates and sums the errors in the past period of time. The larger it is, the stronger the integral effect is, which can gradually eliminate the constant deviation in the system.

[0062] It is the differential coefficient, which is related to the rate of change of the error. It is used to predict the changing trend of the error and adjust the system in advance to improve the dynamic performance of the system. The larger it is, the more sensitive it is to the error change and the more effective it is in suppressing the overshoot of the system.

[0063] , represents the phase difference at the nth moment, which reflects the current deviation of the corresponding clock output branch and is the basis for the PID controller to make adjustments; Indicates the phase difference from the start time to the nth time The cumulative sum reflects the influence of the phase difference at all past moments on the current control action, and the steady-state error is eliminated through the integral action; The difference between the phase difference at time n and the phase difference at time n−1 is used to calculate the rate of change of the phase difference between two adjacent detection cycles, reflecting the changing trend of the phase difference. The differential link predicts the direction of the phase difference based on this difference, thereby adjusting the control output in advance and enabling the target clock signal to reach a stable state more quickly.

[0064] The digital controlled oscillator module is connected to the frequency divider and is used for receiving a reference clock signal, adjusting the frequency or phase of the reference clock signal, generating a target clock signal and sending the target clock signal to the frequency divider.

[0065] Specifically, the digitally controlled oscillation module adjusts the frequency of the reference clock signal according to the frequency control word, adjusts the initial phase of the reference clock signal according to the phase offset word, and sends the adjusted signal as the target clock signal to the frequency divider.

[0066] In the above embodiment, the time-to-digital conversion module, the processing module and the digitally controlled oscillation module work together to make the target clock signal more accurate and stable than the reference clock signal, thereby reducing the absolute synchronization error between the various clock output branches.

[0067] In some embodiments, the processing module is further connected to a processing module in an adjacent clock output branch.

[0068] The processing module is also used to send the received phase difference as an adjacent phase difference to an adjacent processing module; and receive at least one adjacent phase difference, update the received phase difference according to the adjacent phase difference; and adjust the frequency or phase of the digitally controlled oscillation module according to the updated phase difference and the digital compensation algorithm.

[0069] Specifically, the processing module may average the adjacent phase differences and the phase difference received by itself as the updated phase difference.

[0070] In clock chips, relying solely on phase difference measurement within a single channel is equivalent to first-order negative feedback, requiring a very narrow loop bandwidth to suppress noise. Weighting the phase difference of adjacent channels effectively introduces a second-order or even multi-order component, spreading the error energy more quickly across adjacent nodes. This can shorten lock time by 30%–50% and reduce output period jitter (RJ). Furthermore, on-chip wiring, temperature gradients, and power supply noise often cause directional phase difference skew. Using only local error, the adjustment direction may consistently conflict with the true gradient. Incorporating information from adjacent channels smooths the phase difference surface, allowing the adjustment direction to naturally follow the gradient downward, further reducing residual skew.

[0071] In summary, when the present application compensates for the reference clock signal based on the phase difference control numerical control oscillation module, the phase difference of the present application is updated according to the phase difference of the adjacent channels, which is equivalent to turning the "single point" adjustment of a single channel into a small distributed collaborative adjustment, which can further reduce the error between different clock output branches and has better robustness.

[0072] In some embodiments, the processing module is also used to obtain the control voltage of the temperature-voltage compensation table and the numerically controlled oscillation module; if the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold; and, after adjusting the phase of the numerically controlled oscillation module according to the phase difference and the digital compensation algorithm, the frequency of the numerically controlled oscillation module is adjusted according to the first compensation frequency value.

[0073] Among them, the temperature and voltage compensation table is summarized based on historical experience values ​​and records the frequency deviation that is easily caused by the clock chip circuit transmitting at different ambient temperatures and different voltages.

[0074] The control voltage of the digitally controlled oscillator module is the voltage of the control signal when the processing module sends a frequency / phase control signal to the digitally controlled oscillator module to adjust its frequency control word or phase offset word. Adjusting the frequency of the digitally controlled oscillator module based on the first compensation frequency value specifically involves adding the first compensation frequency value to the original frequency control word in the digitally controlled oscillator module, so that the digitally controlled oscillator module adjusts the frequency of the reference clock signal based on the updated frequency control word.

[0075] Specifically, if the control voltage is less than the first preset voltage threshold, the first linear model is used: in, is the first compensation frequency value, is the control voltage of the numerically controlled oscillation module. It is the variable input into the linear model and is used to control the working state of the numerically controlled oscillation module. Its size determines the frequency value that ultimately needs to be compensated.

[0076] If the control voltage is greater than or equal to the first preset voltage threshold and less than the second preset voltage threshold, the second linear model is used: in, 、 、 、 、 These are coefficients in different linear models. These coefficients are determined by certain methods based on the characteristics of the CNC oscillation module and specific compensation requirements. They are used to calculate the compensation frequency values ​​under different voltage ranges. They determine the specific functional relationship between the compensation frequency and the control voltage.

[0077] If the control voltage is greater than the second preset voltage threshold, then , that is, according to the preset temperature voltage compensation table LUT The corresponding first compensation frequency value.

[0078] This application adopts differentiated compensation methods in different control voltage ranges of the numerically controlled oscillation module, that is, linear model compensation is used in the low voltage area to ensure frequency compensation accuracy, and a lookup table method is used in the high voltage area to save computing resources.

[0079] Furthermore, the processing module is also used to obtain the historical frequency error of each clock output branch; construct an error probability density function based on each historical delay error, extract the fixed offset of the preset frequency point based on the error probability density function, and use it as a systematic deviation component; update the network parameters of the first linear model and the second linear model based on the systematic deviation component and recursive least squares method.

[0080] Specifically, during the long-term operation of the clock chip, the transmission delay may change due to device aging or other external factors. Therefore, this application adds a self-learning mechanism in the processing module to extract the frequency offset characteristics in the historical data, and then updates the network parameters of the first linear model and the second linear model based on the recursive least squares method (i.e. 、 、 、 、 ) to ensure the synchronization accuracy of the processing module or the entire multi-channel clock chip system during long-term operation.

[0081] In some embodiments, the system further includes a temperature sensing module.

[0082] The temperature sensing module is used to collect the junction temperature data of each clock output branch and send it to the corresponding processing module.

[0083] The processing module is also used to obtain the semiconductor carrier mobility temperature coefficient and the thermal expansion coefficient of the packaging material of the clock output branch; calculate the temperature delay change based on the junction temperature data, the semiconductor carrier mobility temperature coefficient, the thermal expansion coefficient and the preset calibration temperature; obtain the temperature compensation frequency value in the temperature voltage compensation table based on the temperature delay change, and adjust the frequency of the numerical control oscillation module based on the temperature compensation frequency value and the first compensation frequency value.

[0084] Specifically, the temperature sensing module collects the junction temperature data of each clock output branch with an acquisition accuracy of ±0.5°C and sends it to the corresponding processing module. The processing module uses this to build a temperature compensation model: in, The temperature delay variation of the ith clock output branch due to temperature change is used to measure the impact of temperature on channel transmission delay. The temperature compensation frequency value is obtained by looking up the table based on the temperature delay variation.

[0085] The thermal expansion coefficient of the packaging material reflects the property of the packaging material to expand or contract with temperature changes. The larger the coefficient, the more obvious the dimensional change of the packaging material caused by temperature, and the greater the impact on transmission delay.

[0086] It is the temperature coefficient of semiconductor carrier mobility, which reflects the relationship between the carrier mobility in the semiconductor and the temperature. The carrier mobility will affect the transmission speed of electrons in the semiconductor, thereby affecting the transmission delay of the channel.

[0087] The junction temperature data of the ith clock output branch actually measured by the temperature sensing module, in °C.

[0088] The preset calibration temperature is a reference temperature value, usually the temperature set when calibrating a multi-channel clock chip, and serves as a benchmark for calculating the impact of temperature changes on transmission delay.

[0089] After obtaining the temperature compensated frequency value, the processing module adds the temperature compensated frequency value and the first compensated frequency value and then adds the sum to the original frequency control word of the digital controlled oscillation module to update the frequency of the digital controlled oscillation module.

[0090] The above embodiment collects junction temperature data of the clock output branches through the temperature sensing module, and compensates for the delay variation of the reference clock signal transmission caused by the ambient temperature based on the junction temperature data, thereby further ensuring the synchronization of each clock output branch.

[0091] In some embodiments, the system further includes a voltage sensing module.

[0092] The voltage sensing module is used to measure the power supply voltage of each clock output branch and send it to the corresponding processing module.

[0093] The processing module is used to calculate the voltage delay change based on the power supply voltage, the preset nominal voltage and the preset delay reference value, obtain the second compensation frequency value in the temperature voltage compensation table according to the voltage delay change, and adjust the frequency of the numerical control oscillation module according to the first compensation frequency value, the second compensation frequency value and the temperature compensation frequency value.

[0094] Specifically, the voltage sensing module monitors power supply fluctuations at a sampling rate of 10MS / s, obtains the power supply voltage of each clock output branch, and sends it to the corresponding processing module. The processing module builds a voltage compensation model based on the received power supply voltage: Among them, VDD is the measured power supply voltage; The preset nominal voltage is the normal operating voltage value specified when the chip is designed, and serves as a benchmark for measuring whether the actual power supply voltage deviates from the normal state.

[0095] Preset nominal voltage The preset delay reference value of the channel transmission under CMOS is a reference value determined during the chip design or calibration process, which represents the ideal transmission delay of the channel under normal voltage.

[0096] It is a coefficient related to the chip circuit characteristics, and its value range is usually between 0.8 and 1.2. It is used to describe the degree of nonlinear relationship between supply voltage and transmission delay.

[0097] After obtaining the second compensation frequency value, the processing module adds the temperature compensation frequency value, the second compensation frequency value and the first compensation frequency value and then adds the sum to the original frequency control word of the numerically controlled oscillation module to update the frequency of the numerically controlled oscillation module.

[0098] It should be noted here that the supply voltage and the control voltage are different, and the objects of compensation are also different; the control voltage of the CNC oscillation module is generated when the processing module adjusts and controls it, while the supply voltage is generated by the power supply of the clock chip. The control voltage only exists when the processing module controls the CNC oscillation module, and the supply voltage exists all the time while the chip is powered; the first compensation frequency value is used to compensate for the transmission delay caused by the transmission of the reference clock signal under different control voltages, and the second compensation frequency value is used to compensate for the transmission delay caused by changes in the supply voltage.

[0099] The above embodiment collects the supply voltage of the clock output branch through the voltage sensing module, thereby compensating for the delay variation of the reference clock signal transmission caused by the supply voltage variation, and further ensuring the synchronization of each clock output branch.

[0100] In some embodiments, the digitally controlled oscillation module is specifically configured to divide the frequency control word by a power of 2 and then multiply the power by the frequency of the reference clock signal to obtain the frequency of the target clock signal; wherein the power is the bit width of the phase accumulator of the digitally controlled oscillation module.

[0101] Specifically, the formula for the digital controlled oscillation module to adjust the reference clock signal according to the frequency control word is: Among them, FCW is the frequency control word after being updated by the processing module in the numerically controlled oscillation module; N is the bit width of the phase accumulator of the numerically controlled oscillation module, which is a known data determined during chip design and development.

[0102] is the frequency of the output target clock signal, is the frequency of the received reference clock signal.

[0103] In some embodiments, the processing module is also used to calculate an average delay change based on multiple temperature delay changes and multiple voltage delay changes within a preset period; obtain the operating time of the numerically controlled oscillation module; obtain the aging factor of the clock output branch based on the average delay change and the operating time; and issue an aging warning when the aging factor is greater than a preset aging threshold.

[0104] Specifically, the processing module averages the temperature delay changes and voltage delay changes calculated within a preset period, such as one week or one month, to obtain an average delay change. The aging factor is calculated based on the operating time of the numerically controlled oscillation module. The specific calculation formula is as follows: in, The aging factor, calculated using the above formula, measures the aging of the multi-channel clock chip system in this application. It takes into account other relevant parameters (such as operating time and average delay variation) to derive a quantitative value to assess the aging of the clock chip system. When this value exceeds a preset aging threshold, an alert is triggered, alerting personnel that the device or system may be experiencing aging issues and requires inspection, maintenance, or replacement.

[0105] is the average delay variation; The initial time delay refers to the time delay parameter corresponding to the numerical control oscillation module connected to the processing module when it starts running or is in the initial state; is the running time, that is, the time elapsed from the start of the digital control oscillation module of the current clock output branch to the current moment.

[0106] In the above embodiment, each processing module performs an aging assessment on its own clock output branch, so that when the device ages to the point where it is difficult to achieve clock signal synchronization by compensating for frequency or phase, the staff is reminded to repair or replace it as soon as possible.

[0107] In some embodiments, the system further includes a compensation adaptation module.

[0108] The compensation adaptive module is respectively connected to the initial phase-locked loop and each time-to-digital conversion module.

[0109] The compensation adaptive module is used to control the initial phase-locked loop to generate a frequency sweep signal and send it to each time-to-digital conversion module; obtain the transmission delay data of different frequency points recorded by each time-to-digital conversion module; generate a compensation coefficient matrix corresponding to each clock output branch based on the transmission delay data; and update the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix and send it to the processing module of the clock output branch.

[0110] The frequency range of the frequency sweep signal is 10 MHz to 2 GHz, with a step of 10 MHz.

[0111] Specifically, the compensation adaptive module controls the initial phase-locked loop to generate a frequency scanning signal, and injects it into the input end of the time-to-digital conversion module of each clock output branch through the multiplexer MUX in a time-sharing manner; for example, a 10MHz frequency scanning signal is sent to each channel for the first time, a 20MHz frequency scanning signal is sent to each channel for the second time... and so on.

[0112] The time-to-digital conversion module of each clock output branch records the transmission delay data of the channel at different frequencies and sends it to the compensation adaptive module so that the compensation adaptive module can build a delay-frequency model based on the transmission delay data: in, The transmission delay data generated by the i-th clock output branch when the frequency scanning signal with a frequency of f is transmitted is obtained by sampling the time-to-digital conversion module with a sampling rate of 1 GS / s.

[0113] is the quadratic coefficient caused by wiring parasitic capacitance, The first-order coefficient related to the transmission line characteristic impedance matching, Fixed wiring delay, the above three coefficients are based on multiple and Fitting obtained; is random noise; After constructing the delay-frequency model, the compensation coefficient matrix of the current clock chip system is obtained according to the model: in, is the compensation coefficient matrix of the i-th clock output branch, k=1...N frequency points, The maximum delay value of each clock output branch; The minimum phase adjustment step of the digital controlled oscillator module is usually 0.1 ps.

[0114] After obtaining the compensation coefficient matrix, the compensation coefficient matrix is ​​multiplied by the temperature-voltage compensation table summarized by historical experience to obtain a temperature-voltage compensation table suitable for the current clock chip system and written into the SRAM of each clock output branch.

[0115] It is worth noting that the traditional temperature and voltage compensation table is obtained based on historical experience, and the clock chip system is constantly iterating with the development of technology, and the internal components are also updated from generation to generation. Therefore, the historical temperature and voltage compensation table may not be fully applicable to the current version of the clock chip system. For this reason, after designing the hardware architecture of the clock chip system, this application constructs a compensation coefficient matrix through the transmission delay data obtained by the frequency scanning signal to update the traditional temperature and voltage compensation table so that the table is adapted to the hardware conditions of the current clock chip system, thereby achieving accurate error compensation.

[0116] In addition, the above embodiment adopts a pseudo-random frequency scanning sequence when measuring the transmission delay data of each channel of the clock chip system, which can enhance the robustness of the compensation coefficient matrix obtained by constructing the model.

[0117] See Figure 3 Another embodiment of the present application provides a multi-channel clock chip control method with intelligent calibration, which is applied to a multi-channel clock chip control system. The multi-channel clock chip control system includes a coprocessor, an initial phase-locked loop, a selector, and multiple clock output branches; the clock output branches include interconnected digital control circuits and frequency dividers; the control method includes: Step S1: an initial phase-locked loop receives an input clock signal, multiplies the input clock signal, obtains a reference clock signal, and sends the reference clock signal to a digital control circuit of at least one clock output branch through a selector.

[0118] In step S2, the digital control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal according to the reference clock signal after the delay difference is eliminated, and sends it to the corresponding frequency divider.

[0119] Step S3: The coprocessor receives the clock mode information, determines the clock control parameters according to the clock mode information, and controls each frequency divider according to the clock control parameters to adjust the target clock signal and then output it.

[0120] In some embodiments, the method further comprises: The coprocessor receives clock mode information through a combination of digital pin levels.

[0121] Alternatively, the coprocessor receives the clock control parameters via an I2C interface or an SPI interface.

[0122] In some embodiments, the digital control circuit includes a time-to-digital conversion module, a processing module, and a digital control oscillation module connected in sequence.

[0123] See Figure 4The digital control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal based on the reference clock signal after the delay difference is eliminated, and sends it to the corresponding frequency divider, including: Step S21 : The time-to-digital conversion module receives a reference clock signal, detects a phase difference between the local clock signal and the reference clock signal, and sends the phase difference and the reference clock signal to the processing module.

[0124] In step S22 , the processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, and sends the reference clock signal to the digitally controlled oscillation module after the adjustment.

[0125] In step S23 , the digital controlled oscillation module receives the reference clock signal, performs frequency adjustment or phase adjustment on the reference clock signal, generates a target clock signal, and sends the target clock signal to the frequency divider.

[0126] In one embodiment, the processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, including: The processing module sends the received phase difference as an adjacent phase difference to the processing module of the adjacent clock output branch.

[0127] The processing module receives at least one adjacent phase difference, updates the received phase difference according to the adjacent phase difference, and adjusts the frequency or phase of the digital control oscillation module according to the updated phase difference and the digital compensation algorithm.

[0128] In some embodiments, the method further comprises: In step S41 , the processing module is further configured to obtain a temperature voltage compensation table and a control voltage of the digital control oscillation module.

[0129] In step S42, if the control voltage is less than the first preset voltage threshold, a first compensation frequency value is obtained based on the first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than the second preset voltage threshold, a first compensation frequency value is obtained based on the second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold.

[0130] Step S43: adjusting the frequency of the digital controlled oscillation module according to the first compensation frequency value.

[0131] See Figure 5 In some embodiments, the method further comprises: Step S01: the compensation adaptive module controls the initial phase-locked loop to generate a frequency sweep signal and sends it to each time-to-digital conversion module; and obtains transmission delay data of different frequency points recorded by each time-to-digital conversion module.

[0132] Step S02 , generating a compensation coefficient matrix corresponding to each clock output branch according to the transmission delay data; updating the temperature and voltage compensation table of the corresponding clock output branch according to the compensation coefficient matrix, and sending it to the processing module of the clock output branch.

[0133] The specific limitations of the intelligently calibrated multi-channel clock chip control method provided in this embodiment can be found in the above embodiment of an intelligently calibrated multi-channel clock chip system, which will not be repeated here.

[0134] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. An intelligently calibrated multi-channel clock chip system, characterized in that: It includes a coprocessor, an initial phase-locked loop, a selector and a plurality of clock output branches; the initial phase-locked loop is connected to the selector; The clock output branch includes a digital control circuit and a frequency divider connected to each other; each digital control circuit is connected to the selector; each frequency divider is connected to the coprocessor; The initial phase-locked loop is used to receive an input clock signal, multiply the input clock signal, obtain a reference clock signal, and send it to the digital control circuit of at least one of the clock output branches through a selector; The digital control circuit is used to eliminate the distributed transmission delay difference in the reference clock signal by using a digital compensation algorithm, generate a target clock signal according to the reference clock signal after the delay difference is eliminated, and send it to the corresponding frequency divider; The coprocessor is used to receive clock mode information and determine clock control parameters according to the clock mode information; The frequency dividers are controlled according to the clock control parameters to adjust the target clock signal and then output it.

2. The intelligently calibrated multi-channel clock chip system according to claim 1, characterized in that: The coprocessor is specifically configured to receive the clock mode information through a digital pin level combination, and use the clock frequency parameter corresponding to the clock mode information as the clock control parameter; or receive the clock control parameter through an I2C interface or an SPI interface.

3. The intelligently calibrated multi-channel clock chip system according to claim 2, characterized in that: The clock mode information includes 5G base station mode and vehicle system mode.

4. The intelligently calibrated multi-channel clock chip system according to claim 1, characterized in that: The circuits between the initial phase-locked loop and each of the digital control circuits adopt differential spiral wiring, and the upper half is covered with an electromagnetic shielding layer; The differential spiral wiring has a pitch of 1.5 microns and a line width of 3 microns; The electromagnetic shielding layer is made of a tantalum-based composite material.

5. The intelligently calibrated multi-channel clock chip system according to claim 4, characterized in that: The initial phase-locked loop and the packaging substrate of each of the digital control circuits are both embedded with FBAR filters; Each of the FBAR filters is connected to the coprocessor respectively; The coprocessor is used to send the suppressed frequency band to each of the FBAR filters; The FBAR filter is used to perform interference suppression according to the received suppression frequency band.

6. The intelligently calibrated multi-channel clock chip system according to claim 1, characterized in that: The digital control circuit includes a time-to-digital conversion module, a processing module and a digital control oscillation module connected in sequence; The time-to-digital conversion module is connected to the selector, and is configured to receive the reference clock signal, detect a phase difference between the local clock signal and the reference clock signal, and send the phase difference and the reference clock signal to the processing module; The processing module is used to adjust the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, and send the reference clock signal to the digitally controlled oscillation module after the adjustment; The digitally controlled oscillation module is connected to the frequency divider, and is used to receive the reference clock signal, perform frequency adjustment or phase adjustment on the reference clock signal, generate the target clock signal, and send the target clock signal to the frequency divider.

7. The intelligently calibrated multi-channel clock chip system according to claim 6, characterized in that: The processing module is also connected to the processing module in the adjacent clock output branch; The processing module is further configured to send the received phase difference as an adjacent phase difference to an adjacent processing module; And, receiving at least one adjacent phase difference, updating the received phase difference according to the adjacent phase difference; and adjusting the frequency or phase of the digitally controlled oscillation module according to the updated phase difference and a digital compensation algorithm.

8. The intelligently calibrated multi-channel clock chip system according to claim 6, characterized in that: The processing module is further used to obtain a temperature voltage compensation table and a control voltage of the digital control oscillation module; If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold; And, after adjusting the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, adjusting the frequency of the digitally controlled oscillation module according to the first compensation frequency value.

9. The intelligently calibrated multi-channel clock chip system according to claim 8, characterized in that: It also includes a temperature sensing module; the temperature sensing module is used to collect the junction temperature data of each clock output branch and send it to the corresponding processing module; The processing module is also used to obtain the semiconductor carrier mobility temperature coefficient and the thermal expansion coefficient of the packaging material of the clock output branch; calculate the temperature delay change based on the junction temperature data, the semiconductor carrier mobility temperature coefficient, the thermal expansion coefficient and the preset calibration temperature; obtain the temperature compensation frequency value in the temperature voltage compensation table based on the temperature delay change, and adjust the frequency of the numerical control oscillation module according to the temperature compensation frequency value and the first compensation frequency value.

10. The intelligently calibrated multi-channel clock chip system according to claim 9, characterized in that: It also includes a voltage sensing module; the voltage sensing module is used to measure the power supply voltage of each clock output branch and send it to the corresponding processing module; The processing module is used to calculate the voltage delay variation based on the supply voltage, the preset nominal voltage and the preset delay reference value, obtain the second compensation frequency value in the temperature voltage compensation table based on the voltage delay variation, and adjust the frequency of the numerically controlled oscillation module based on the first compensation frequency value, the second compensation frequency value and the temperature compensation frequency value.

11. The intelligently calibrated multi-channel clock chip system according to claim 10, characterized in that: The digitally controlled oscillation module is specifically configured to divide the frequency control word by a power of 2 and then multiply the result by the frequency of the reference clock signal to obtain the frequency of the target clock signal; wherein the power is the bit width of the phase accumulator of the digitally controlled oscillation module.

12. The intelligently calibrated multi-channel clock chip system according to claim 10, characterized in that: The processing module is further configured to calculate an average delay variation based on a plurality of the temperature delay variations and a plurality of the voltage delay variations within a preset period; and obtain an operating time of the digitally controlled oscillation module; An aging factor of the clock output branch is obtained based on the average delay variation and the running time; and an aging warning is issued when the aging factor is greater than a preset aging threshold.

13. The intelligently calibrated multi-channel clock chip system according to claim 8, characterized in that: The processing module is also used to obtain the historical frequency error of each clock output branch; construct an error probability density function based on each of the historical delay errors, extract the fixed offset of the preset frequency point based on the error probability density function, and use it as a systematic deviation component; update the network parameters of the first linear model and the second linear model based on the systematic deviation component and the recursive least squares method.

14. The intelligently calibrated multi-channel clock chip system according to claim 8, characterized in that: It also includes a compensation adaptive module; the compensation adaptive module is respectively connected to the initial phase-locked loop and each of the time-to-digital conversion modules; The compensation adaptive module is used to control the initial phase-locked loop to generate a frequency scanning signal and send it to each of the time-to-digital conversion modules; obtain transmission delay data of different frequency points recorded by each of the time-to-digital conversion modules; generate a compensation coefficient matrix corresponding to each of the clock output branches based on the transmission delay data; and update the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix and send it to the processing module of the clock output branch.

15. A multi-channel clock chip control method with intelligent calibration, characterized in that: Applicable to a multi-channel clock chip control system, the multi-channel clock chip control system includes a coprocessor, an initial phase-locked loop, a selector and multiple clock output branches; The clock output branch includes a digital control circuit and a frequency divider connected to each other; the control method includes: The initial phase-locked loop receives an input clock signal, multiplies the input clock signal, obtains a reference clock signal, and sends the reference clock signal to the digital control circuit of at least one of the clock output branches through a selector; The digital control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal based on the reference clock signal after the delay difference is eliminated, and sends it to the corresponding frequency divider; The coprocessor receives clock mode information, determines clock control parameters according to the clock mode information, and controls each of the frequency dividers according to the clock control parameters to adjust the target clock signal and then output it.

16. The intelligent calibration multi-channel clock chip control method according to claim 15, characterized in that: Also includes: The coprocessor receives the clock mode information through a digital pin level combination; Alternatively, the coprocessor receives the clock control parameter via an I2C interface or an SPI interface.

17. The intelligent calibration multi-channel clock chip control method according to claim 15, characterized in that: The digital control circuit includes a time-to-digital conversion module, a processing module and a digital control oscillation module connected in sequence; The digital control circuit uses a digital compensation algorithm to eliminate the distributed transmission delay difference in the reference clock signal, generates a target clock signal according to the reference clock signal after the delay difference is eliminated, and sends it to the corresponding frequency divider, including: The time-to-digital conversion module receives the reference clock signal, detects a phase difference between the local clock signal and the reference clock signal, and sends the phase difference and the reference clock signal to the processing module; The processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, and sends the reference clock signal to the digitally controlled oscillation module after the adjustment; The digital controlled oscillation module receives the reference clock signal, performs frequency adjustment or phase adjustment on the reference clock signal, generates the target clock signal, and sends the target clock signal to the frequency divider.

18. The intelligent calibration multi-channel clock chip control method according to claim 17, characterized in that: The processing module adjusts the phase of the digitally controlled oscillation module according to the phase difference and the digital compensation algorithm, including: The processing module sends the received phase difference as an adjacent phase difference to the processing module of the adjacent clock output branch; The processing module receives at least one adjacent phase difference, updates the received phase difference according to the adjacent phase difference, and adjusts the frequency or phase of the digitally controlled oscillation module according to the updated phase difference and a digital compensation algorithm.

19. The intelligent calibration multi-channel clock chip control method according to claim 17, characterized in that: Also includes: The processing module is further used to obtain a temperature voltage compensation table and a control voltage of the digital control oscillation module; If the control voltage is less than a first preset voltage threshold, a first compensation frequency value is obtained based on a first linear model; if the control voltage is greater than or equal to the first preset voltage threshold and less than a second preset voltage threshold, a first compensation frequency value is obtained based on a second linear model; if the control voltage is greater than the second preset voltage threshold, a first compensation frequency value is obtained according to the temperature-voltage compensation table; wherein the second preset voltage threshold is greater than the first preset voltage threshold; The frequency of the digitally controlled oscillation module is adjusted according to the first compensation frequency value.

20. The intelligent calibration multi-channel clock chip control method according to claim 19, characterized in that: Also includes: The compensation adaptive module controls the initial phase-locked loop to generate a frequency sweep signal and sends it to each of the time-to-digital conversion modules; obtains transmission delay data of different frequency points recorded by each of the time-to-digital conversion modules; generates a compensation coefficient matrix corresponding to each of the clock output branches based on the transmission delay data; and updates the temperature and voltage compensation table of the corresponding clock output branch based on the compensation coefficient matrix and sends it to the processing module of the clock output branch.

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