Interrupt processing method, PCIe system and storage medium

Abstract

The invention provides an interrupt processing method, a PCIe system and a storage medium, and the method comprises the steps: a target EP in an EP set writes a message signal interrupt MSI interrupt number into a local address of the target EP, so that the MSI interrupt number enters a storage space corresponding to the target address based on a mapping relation between the local address and the target address of host equipment; and the RC reads the MSI interrupt number from the storage space corresponding to the target address, and executes an interrupt processing task corresponding to the MSI interrupt number. Based on the scheme, hardware resource occupation and design complexity of the EP and PCIe system are effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an interrupt processing method, a PCIe system, and a storage medium. Background Art

[0002] In the related art, the high-speed Peripheral Component Interconnect Express (PCIe) system consists of a host device (Host Device) and an endpoint device (EP). The host device contains a root complex (RC), which is responsible for managing the communication connection between the host device and the EP and handling data transmission and control tasks. When the EP needs to report the message signaled interrupt (MSI) interrupt number to the RC, it usually relies on the MSI data register provided by the PCIe intellectual property core (IP core) locally integrated in the EP. However, the existence of the MSI data register will increase the design complexity and hardware cost of the EP's PCIe IP core. Summary of the Invention

[0003] Embodiments of the present application provide an interrupt processing method, a PCIe system, and a storage medium.

[0004] A first aspect of an embodiment of the present application provides an interrupt handling method, which is applied to a Peripheral Component Interconnect Express (PCIe) system. The PCIe system includes a host device and a set of endpoint devices (EPs). The host device includes a root complex (RC). The RC is connected to each EP in the set of EPs based on a PCIe bus. The method includes:

[0005] The target EP in the EP set writes a message signal interrupt MSI interrupt number to the local address of the target EP, so that the MSI interrupt number enters the storage space corresponding to the target address based on the mapping relationship between the local address and the target address of the host device;

[0006] RC reads the MSI interrupt number from the storage space corresponding to the target address and executes the interrupt processing task corresponding to the MSI interrupt number.

[0007] In an optional embodiment of the present application, the target EP in the EP set writes a message signal interrupt MSI interrupt number to the local address of the target EP, so that the MSI interrupt number is based on the mapping relationship between the local address and the target address of the host device, before entering the storage space corresponding to the target address, it also includes: RC determines the target address from the host device; RC determines the target EP from the EP set, and the target EP has MSI capability; RC transmits the target address to the target EP; RC registers the interrupt callback function corresponding to the target address, and enables the MSI function of the target EP based on the registration status of the interrupt callback function; the target EP establishes a mapping relationship between the local address of the target EP and the target address based on the target address.

[0008] In an optional embodiment of the present application, the RC determines the target address from the host device, including: the RC determines a storage space for storing interrupt data from the host device; and the RC determines an address corresponding to the storage space for storing interrupt data as the target address.

[0009] In an optional embodiment of the present application, RC determines the target EP from the EP set, including: RC reads the configuration space of each EP separately to obtain the configuration space reading result of each EP; RC determines the target EP from the EP set based on the configuration space reading result of each EP, and the configuration space reading result of the target EP includes MSI capability information, and the MSI capability information indicates that the target EP has MSI capability.

[0010] In an optional embodiment of the present application, the RC transmits the target address to the target EP, including: the RC determines the MSI capability register group from the configuration space of the target EP; the RC determines the MSI address register from the MSI capability register group; and the RC writes the target address to the MSI address register.

[0011] In an optional embodiment of the present application, the target EP establishes a mapping relationship between the local address of the target EP and the target address based on the target address, including: the target EP reads the target address from the MSI address register; the target EP establishes a mapping relationship between the local address of the target EP and the target address based on a preset mapping method and the target address.

[0012] In an optional embodiment of the present application, the target EP establishes a mapping relationship between the local address of the target EP and the target address based on a preset mapping method and the target address, including: the target EP associates the local address of the target EP with the target address to generate an outbound mapping file; the target EP maps the association operation of the local address to the storage space corresponding to the target address based on the outbound mapping file to establish a mapping relationship between the local address and the target address.

[0013] In an optional embodiment of the present application, the target EP in the EP set writes a message signal interrupt MSI interrupt number to the local address of the target EP, so that the MSI interrupt number is based on the mapping relationship between the local address and the target address of the host device, before entering the storage space corresponding to the target address, it also includes: the target EP configures the MSI capability register group in the configuration space of the target EP, the MSI capability register group includes the MSI control register; the target EP writes MSI capability information to the MSI control register, and the MSI capability information indicates that the target EP has MSI capability.

[0014] A second aspect of an embodiment of the present application provides a PCIe system, the PCIe system including a host device and an endpoint device EP set, the host device including a root complex RC, the RC being connected to each EP in the EP set based on a PCIe bus;

[0015] The PCIe system is configured to perform the steps of any of the above methods.

[0016] According to a third aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program implements the steps of any of the above methods when executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A schematic diagram of the PCIe system architecture provided in one embodiment of the present application;

[0019] Figure 2 A flowchart of an interrupt handling method provided in one embodiment of the present application;

[0020] Figure 3 A flowchart of establishing a mapping relationship provided in one embodiment of the present application;

[0021] Figure 4 A flowchart for determining a target address provided in one embodiment of the present application;

[0022] Figure 5 A flowchart for determining a target EP is provided for one embodiment of the present application;

[0023] Figure 6 A flow chart of transmitting a target address provided in one embodiment of the present application;

[0024] Figure 7A flowchart of establishing a mapping relationship based on a preset mapping method provided in one embodiment of the present application;

[0025] Figure 8 A flowchart of establishing a mapping relationship based on an outbound mapping method provided in one embodiment of the present application;

[0026] Figure 9 A flowchart of the target EP's MSI reporting capability provided in one embodiment of the present application;

[0027] Figure 10 A schematic diagram of the interaction between the RC and the target EP provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will clearly and thoroughly describe the technical solutions in this application in conjunction with the accompanying drawings. In the description of the embodiments of this application, unless otherwise specified, " / " means or, for example, A / B can mean A or B: "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more than two.

[0029] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features.

[0030] See Figure 1 , Figure 1 A schematic diagram of the PCIe system architecture provided for one embodiment of the present application.

[0031] The PCIe system includes a host device and an EP set. The host device includes an RC, which is connected to each EP in the EP set based on the PCIe bus. Among them, RC refers to the component in the host device that is responsible for managing the communication connection with the EP and processing data transmission and control tasks; EP refers to the external device that exchanges data with the host device through PCIe; EP set refers to a set of one or more EPs connected to RC through PCIE. For example, the EP set may include Figure 1 The RC is connected to each EP in the EP set, EP (1) through EP (n), via the PCIe bus. This means that the RC establishes a communication link with each EP via the PCIe protocol to achieve data transmission and control. Based on the PCIe connection, the RC can receive and process data sent by the EP and send control instructions to the EP.

[0032] In related art, when an EP needs to report an MSI interrupt number to a RC, it typically relies on the MSI data registers provided by the EP's locally integrated PCIe IP core. Specifically, the EP's PCIe IP core in related art includes an MSI capability register set, which includes an MSI control register, an MSI address register, and an MSI data register. The MSI control register is used to configure the MSI interrupt enable state, the number of interrupt vectors, and the interrupt triggering method. The MSI address register is used to store the target address of the MSI interrupt message, i.e., the address at which the RC receives the interrupt message. The MSI data register is used to store the specific data of the MSI interrupt message, including the MSI interrupt number and other related information.

[0033] However, the presence of MSI data registers requires additional hardware resources to implement their functionality, increasing the design complexity of the PCIe IP core. Specifically, the MSI data registers require additional storage space and require dedicated registers and logic circuits to be allocated during hardware design, which increases chip area and power consumption. Furthermore, the presence of MSI data registers complicates verification and testing of the PCIe IP core, as it is necessary to ensure its correctness and stability in various scenarios. These factors can potentially increase the design complexity and hardware cost of the EP's PCIe IP core.

[0034] To address the above-mentioned issues, the solution provided by the embodiment of the present application mainly includes the following: first, the target EP writes the MSI interrupt number to the local address, and uses the mapping relationship between the local address and the target address of the host device to directly transfer the MSI interrupt number to the storage space corresponding to the target address, thereby avoiding the hardware resource overhead of relying on the MSI data register in the related art, thereby reducing the hardware design complexity of the EP. Secondly, the RC reads the MSI interrupt number from the storage space corresponding to the target address and executes the interrupt processing task corresponding to the MSI interrupt number, ensuring the accuracy and real-time performance of the interrupt processing. Through the above steps, while ensuring the integrity of the interrupt processing function, the hardware resource usage and design complexity of the EP and PCIe system are effectively reduced.

[0035] based on Figure 1 The system architecture shown in the figure is shown in the figure. Figure 2 - Figure 10 , the interrupt handling method provided in the embodiment of the present application is introduced in detail.

[0036] See Figure 2, is a flow chart of an interrupt handling method provided by one embodiment of the present application. The interrupt handling method is applied to a Peripheral Component Interconnect Express (PCIe) system, wherein the PCIe system includes a host device and an endpoint device (EP) set. The host device includes a root complex (RC), which is connected to each EP in the EP set based on a PCIe bus. Figure 2 As shown, the method of the embodiment of the present application may include the following steps S101-S103.

[0037] S101 , a target EP in an EP set writes a message signal interrupt MSI interrupt number to a local address of the target EP, so that the MSI interrupt number enters a storage space corresponding to the target address based on a mapping relationship between the local address and the target address of the host device.

[0038] Specifically, a target EP in an EP set is an EP with MSI capabilities, capable of generating and sending an MSI interrupt number to trigger the interrupt handling process. The local address of a target EP refers to a specific address within the target EP used to store the MSI interrupt number, but the local address does not point to the target EP's internal storage space. The MSI interrupt number is an interrupt identifier generated by the target EP to indicate a specific interrupt type or interrupt event. The MSI interrupt number is generated by the target EP based on preset interrupt rules.

[0039] The mapping relationship between the local address and the target address of the host device refers to the association between the local address of the target EP and the address of the storage space in the host device for storing interrupt data. It is understandable that this mapping relationship is pre-established and implemented through configuration and communication between the RC of the host device and the target EP.

[0040] When the target EP detects an event requiring an interrupt, it generates an MSI interrupt number based on pre-set interrupt rules and writes the MSI interrupt number to a local address. This write operation triggers the target EP's hardware logic or software module to transfer the MSI interrupt number to the host device's target address storage space based on a pre-established mapping between the local address and the host device's target address. This process eliminates the need for additional MSI data registers, reducing hardware resource usage and design complexity.

[0041] S102, the RC reads the MSI interrupt number from the storage space corresponding to the target address, and executes the interrupt processing task corresponding to the MSI interrupt number.

[0042] Specifically, the RC accesses the storage space corresponding to the target address through periodic polling or event-triggered access via hardware logic or software modules, and reads the MSI interrupt number from the storage space. After the read operation is completed, the RC executes the interrupt handling task corresponding to the MSI interrupt number. The interrupt handling task is used to trigger hardware operations, data read and write operations, error handling, or system status updates corresponding to the MSI interrupt number.

[0043] In some possible implementations, the RC can pass the MSI interrupt number to the operating system's interrupt handling module, triggering the operating system's interrupt handling module to search for the interrupt callback function associated with the MSI interrupt number and call that interrupt callback function to execute the interrupt handling logic. During the execution of the interrupt callback function, the operating system's interrupt handling module can implement hardware operations, data read and write operations, error handling, or system status updates corresponding to the MSI interrupt number.

[0044] An operating system is a software system running on a host device that manages and schedules hardware resources, handles interrupts, and executes applications. The interrupt handling module in an operating system is a specific functional module responsible for managing and handling interrupts. It receives the MSI interrupt number, searches for and calls the corresponding interrupt callback function, and executes the interrupt handling logic.

[0045] In this embodiment, the target EP first writes the MSI interrupt number to a local address. Leveraging the mapping between the local address and the host device's target address, the MSI interrupt number is directly transferred to the storage space corresponding to the target address. This avoids the hardware resource overhead associated with relying on message signal interrupt data registers in related technologies, thereby reducing the EP's hardware design complexity. Secondly, the RC reads the MSI interrupt number from the storage space corresponding to the target address and executes the interrupt handling task associated with the MSI interrupt number, ensuring accurate and real-time interrupt processing. These steps effectively reduce the hardware resource usage and design complexity of the EP and PCIe system while ensuring the integrity of the interrupt handling functionality.

[0046] See Figure 3 , which is a flow chart of establishing a mapping relationship provided by an embodiment of the present application, such as Figure 3 As shown, the method of the embodiment of the present application may include the following steps S201-S205, and steps S201-S205 may be performed in Figure 2 In the illustrated embodiment, step S101 is performed before the step S101.

[0047] S201, RC determines the target address from the host device;

[0048] S202: The RC determines a target EP from the EP set. The target EP has MSI capability.

[0049] S203, RC transmits the target address to the target EP;

[0050] S204, the RC registers an interrupt callback function corresponding to the target address, and enables the MSI function of the target EP based on the registration status of the interrupt callback function;

[0051] S205: The target EP establishes a mapping relationship between the local address of the target EP and the target address based on the target address.

[0052] Specifically, the RC first selects a specific address from the host device's memory space as the target address for storing the message signal interrupt (MSI) number subsequently sent by the target EP. In some possible implementations, the RC selects an unoccupied address as the target address based on the host device's memory space allocation policy, or selects a specific address as the target address based on preconfigured address mapping rules. It will be appreciated that determining the target address ensures smooth storage and processing of the subsequent MSI number.

[0053] Next, the RC selects MSI-capable EPs from the EP set as target EPs. In some possible implementations, the RC obtains each EP's configuration information by reading its configuration space. Based on the MSI capability flag in the configuration information, the RC determines whether each EP is MSI-capable. Based on the determination, the RC selects one or more MSI-capable EPs from the EP set as target EPs. It is understood that determining the target EP provides the hardware foundation for subsequent MSI interrupt processing.

[0054] After determining the target EP, the RC transmits the determined target address to the target EP. In some possible implementations, the RC writes the target address to a specific register in the target EP's configuration space via a configuration write operation within the PCIe protocol. It will be appreciated that transmitting the target address ensures that the target EP knows the specific address in the host device used to store the MSI interrupt number, providing address information for subsequent MSI interrupt number transmission.

[0055] Subsequently, the RC registers an interrupt callback function associated with the target address in the operating system of the host device, and enables the MSI function of the target EP based on the registration status of the interrupt callback function. In some possible implementations, the RC assigns an interrupt vector to the target address in the interrupt management module of the operating system, and associates the interrupt vector with a specific interrupt callback function. The registration of the interrupt callback function ensures that the correct interrupt handling process can be triggered after the MSI interrupt number is received in the storage space corresponding to the target address. It can be understood that the RC enables the MSI function of the target EP by configuring the write operation based on the registration status of the interrupt callback function, ensuring that the target EP can generate and send the MSI interrupt number.

[0056] Finally, the target EP establishes a mapping relationship between its local address and the target address based on the received target address, thereby associating the local specific address with the target address. In some possible implementations, the target EP reads the target address from a specific register in the configuration space and associates the local specific address with the target address based on a preset mapping rule. It will be appreciated that establishing this mapping relationship ensures that when the target EP writes the MSI interrupt number to the local address, it can transmit the MSI interrupt number to the storage space corresponding to the target address of the host device based on the mapping relationship.

[0057] In some possible implementations, the RC registers an MSI interrupt callback function with the host device's system software through the host device's device driver software, and enables the target EP's MSI functionality based on the registration status of the interrupt callback function. Specifically, the host device's device driver software refers to a specific software module running on the host device for managing and controlling the target EP. It is responsible for interacting with the target EP's hardware and processing interrupt requests generated by the target EP. The host device's system software refers to the host device's operating system kernel or interrupt management module, which is responsible for managing and scheduling the host device's interrupt handling process. The RC registers an interrupt callback function corresponding to the target address with the host device's system software by calling an interface provided by the host device's device driver software. The interrupt callback function refers to a specific processing function called by the host device's system software after receiving the MSI interrupt number in the storage space corresponding to the target address. It is used to execute the interrupt handling logic associated with the MSI interrupt number. After successfully registering the interrupt callback function, the RC writes an enable bit to the MSI control register in the target EP's configuration space through a configuration write operation to enable the target EP's MSI functionality. It can be understood that RC registers the MSI interrupt callback function to the system software of the host device through the device driver software of the host device, and enables the MSI function of the target EP based on the registration status of the interrupt callback function, ensuring that after receiving the MSI interrupt number in the storage space corresponding to the target address, the correct interrupt processing process can be triggered, and at the same time ensuring that the MSI function of the target EP can be enabled normally.

[0058] In some possible implementations, the EP set is determined by scanning by the host device. Specifically, during startup or operation, the host device scans the PCIe bus through RC to discover and identify all connected EPs, thereby forming an EP set.

[0059] In this embodiment, the RC first determines the target address from the host device, determines the target EP from the EP set, and then transmits the target address to the target EP, ensuring that the target EP can know the specific address in the host device for storing the MSI interrupt number. Next, the RC registers the interrupt callback function corresponding to the target address, and enables the MSI function of the target EP based on the registration status of the interrupt callback function, ensuring that after receiving the MSI interrupt number in the storage space corresponding to the target address, the correct interrupt processing flow can be triggered. Finally, the target EP establishes a mapping relationship between the local address of the target EP and the target address based on the target address, ensuring that when the target EP writes the MSI interrupt number to the local address, it can transmit the MSI interrupt number to the storage space corresponding to the target address of the host device based on the mapping relationship. In this way, while ensuring the integrity of the interrupt processing function, the hardware resource usage and design complexity of the EP and PCIe system are effectively reduced.

[0060] See Figure 4 , is a flow chart of determining a target address provided by an embodiment of the present application, such as Figure 4 As shown, the method of the embodiment of the present application may include the following steps S301-S302, and steps S301-S302 may be used as Figure 3 The detailed steps of step S201 of the embodiment are shown.

[0061] S301, the RC determines a storage space for storing interrupt data from the host device;

[0062] S302 , the RC determines an address corresponding to a storage space for storing interrupt data as a target address.

[0063] Specifically, the storage space for storing interrupt data refers to a specific area in the host device's memory or cache used to store interrupt data. Interrupt data may include one or more pieces of information, such as the interrupt vector, interrupt status information, interrupt priority information, and the MSI interrupt number. The RC allocates or selects the storage space for storing interrupt data from the host device's memory or cache through hardware logic or software modules.

[0064] Next, the RC determines the address corresponding to the storage space used to store the interrupt data as the target address. In some possible implementations, determining the target address includes obtaining the starting address, ending address, or specific offset address of the storage space and using this as the target address. The RC, through hardware logic or software modules, performs address calculation or address mapping operations to convert the address corresponding to the storage space into the target address, providing clear address information for interrupt data transmission to the target EP.

[0065] In some possible implementations, after the host device is started, the RC's PCIe IP core is loaded. Steps S301 and S302 are executed during the RC's PCIe IP core loading process to ensure that the storage space and target address for storing interrupt data can be correctly determined when the system is started. Specifically, during the PCIe IP core loading process, the RC performs memory allocation or address mapping operations through hardware logic or software modules to determine the storage space for storing interrupt data and determines the corresponding address as the target address. It can be understood that the RC completes the determination of the storage space and target address during the PCIe IP core loading process, ensuring that the system has complete interrupt handling capabilities at the initial stage of operation.

[0066] In this embodiment, first, the RC determines the storage space for storing interrupt data from the host device, providing a data basis for determining the target address. Then, the RC determines the address corresponding to the storage space for storing interrupt data as the target address, providing clear address information for the interrupt data transmission of the target EP. Through the above steps, the RC can determine the storage space and target address for storing interrupt data during the PCIe IP core loading process or operation process, providing data support for the interrupt data transmission of the target EP. At the same time, since the determination of the storage space and target address are both actively completed by the RC, the target EP does not need additional configuration or intervention, further simplifying the design and implementation process of the system. In addition, this embodiment avoids the introduction of additional hardware modules or complex software logic by directly utilizing the memory or cache of the host device, thereby reducing the overall complexity and implementation cost of the system. Therefore, this embodiment not only ensures the integrity and reliability of interrupt data transmission, but also significantly improves the resource utilization and design efficiency of the PCIe system.

[0067] See Figure 5 , is a flow chart of determining a target EP provided by an embodiment of the present application, such as Figure 5 As shown, the method of the embodiment of the present application may include the following steps S401-S402, and steps S401-S402 may be used as Figure 3 The detailed steps of step S202 of the embodiment are shown.

[0068] S401, RC reads the configuration space of each EP respectively to obtain the configuration space reading result of each EP;

[0069] S402: The RC determines a target EP from the EP set according to the configuration space reading result of each EP. The configuration space reading result of the target EP includes MSI capability information. The MSI capability information indicates that the target EP has MSI capability.

[0070] Specifically, the RC reads the configuration space of each EP separately, obtaining the configuration space read results for each EP. An EP's configuration space refers to a specific storage area within the EP used to store configuration information. This configuration information may include one or more types of information, such as the EP's hardware features, function support status, and MSI capabilities. The RC accesses each EP's configuration space through the configuration read operation in the PCIe protocol, reading specific registers or storage areas within the configuration space to obtain the configuration information for each EP. It is understood that obtaining the configuration space read results provides the data foundation for subsequently determining the target EP.

[0071] Next, the RC determines the target EP from the EP set based on the configuration space read results for each EP. The target EP's configuration space read results include MSI capability information, which indicates whether the target EP is MSI-capable. MSI capability information refers to a specific field or register value in the configuration space that identifies whether the EP supports Message Signaled Interrupts (MSIs). The RC parses the configuration space read results for each EP, searches for the MSI capability information, and uses this information to determine whether each EP is MSI-capable. Based on this determination, the RC selects one or more MSI-capable EPs from the EP set as the target EPs.

[0072] It is understandable that if the configuration space reading results of some EPs in the EP set do not include MSI capability information, then these EPs will not be determined as target EPs.

[0073] In some possible implementations, the RC obtains MSI capability information by reading the MSI capability register set in each EP's configuration space. The MSI capability register set includes the MSI control register, the MSI address register, and the MSI data register. The MSI control register is used to configure the MSI interrupt enable status, number of interrupt vectors, and interrupt triggering method. The MSI address register stores the target address of the MSI interrupt message—the address at which the RC receives the interrupt message. The MSI data register stores the specific data of the MSI interrupt message, including the MSI interrupt number and other related information. The RC determines whether the EP supports MSI functionality by reading specific fields in the MSI control register. For example, the MSI enable bit in the MSI control register indicates whether the EP has enabled the MSI function, and the MSI vector count field indicates the number of MSI interrupt vectors supported by the EP. Based on the information in the MSI control register, the RC determines whether the EP has MSI capability and determines the target EP accordingly.

[0074] In other possible implementations, the RC obtains MSI capability information by reading the capability list in the configuration space of each EP. The capability list is a data structure in the EP configuration space that is used to store various capability information supported by the EP, including MSI capabilities, MSI-X capabilities, power management capabilities, etc. The RC traverses the capability list to find the MSI capability entry and determines whether the EP has MSI capabilities based on the information in the MSI capability entry. For example, the MSI enable field in the MSI capability entry indicates whether the EP has enabled the MSI function, and the MSI vector number field indicates the number of MSI interrupt vectors supported by the EP. Based on the information in the MSI capability entry, the RC determines whether the EP has MSI capabilities and determines the target EP accordingly.

[0075] After determining the target EP, the RC stores the target EP's configuration space read results in the host device's memory for subsequent use. In some possible implementations, the RC stores the target EP's configuration space read results in the host device's memory and manages them using a specific data structure. For example, the RC can create an EP configuration information table, store the target EP's configuration space read results in the table, and assign a unique identifier to each target EP.

[0076] In this embodiment, the RC first reads the configuration space of each EP separately to obtain the configuration space reading results of each EP. Next, the RC determines the target EP from the EP set based on the configuration space reading results of each EP. The configuration space reading results of the target EP include MSI capability information. The MSI capability information indicates that the target EP has MSI capabilities, ensuring that the target EP can generate and send MSI interrupt signals.

[0077] See Figure 6 , is a flow chart of a target address transmission process provided by an embodiment of the present application, such as Figure 6 As shown, the method of the embodiment of the present application may include the following steps S501-S503, and steps S501-S503 may be used as Figure 3 The detailed steps of step S203 of the embodiment are shown.

[0078] S501, RC determines the MSI capability register set from the configuration space of the target EP;

[0079] S502, RC determines the MSI address register from the MSI capability register group;

[0080] S503, RC writes the target address to the MSI address register.

[0081] Specifically, the RC determines the MSI capability register set from the configuration space of the target EP. The configuration space of the target EP refers to a specific storage area in the target EP for storing configuration information. The configuration information may include one or more information such as the hardware feature information, function support status information, and MSI capability information of the target EP. The MSI capability register set refers to a specific register set in the configuration space of the target EP for managing and configuring the message signal interrupt (MSI) function, which includes the MSI control register, the MSI address register, and the MSI data register. The RC accesses the configuration space of the target EP through the configuration read operation in the PCIe protocol, reads the specific registers or storage area in the configuration space, and obtains the configuration information of the target EP.

[0082] Next, the RC determines the MSI address register from the MSI capability register set. The MSI address register refers to a specific register in the MSI capability register set that stores the target address of the MSI interrupt message. The RC parses the register information in the MSI capability register set to locate the MSI address register. In some possible implementations, the RC determines the location and function of the MSI address register by reading specific fields or register identifiers in the MSI capability register set. It will be appreciated that determining the MSI address register provides the hardware foundation for subsequently writing the target address.

[0083] The RC then writes the target address to the MSI address register. In some possible implementations, the RC uses a configuration write command in the PCIe protocol to write the target address as data to the corresponding storage location in the MSI address register. It will be appreciated that writing the target address ensures that the target EP knows the specific address used to store the MSI interrupt number in the host device, providing address information for subsequent MSI interrupt number transmission.

[0084] Furthermore, after receiving the target address, the target EP establishes a mapping relationship between the target EP's local address and the target address based on the target address. Establishing this mapping relationship ensures that when the target EP writes the MSI interrupt number to the local address, it can transmit the MSI interrupt number to the storage space corresponding to the target address of the host device based on the mapping relationship. In some possible implementations, the target EP associates the local address with the target address through hardware logic or a software module, generates an outbound mapping file, and maps the association operation of the local address to the storage space corresponding to the target address based on the outbound mapping file.

[0085] In this embodiment, the RC first determines the MSI capability register group from the configuration space of the target EP, and determines the MSI address register from the MSI capability register group, ensuring that the target EP can know the specific address used to store the MSI interrupt number in the host device. Next, the RC writes the target address to the MSI address register, ensuring that the target EP can establish a mapping relationship between the local address of the target EP and the target address based on the target address. Finally, based on the mapping relationship, the target EP transmits the MSI interrupt number to the storage space corresponding to the target address of the host device, avoiding the hardware resource overhead of relying on the MSI data register in the related art, thereby reducing the hardware design complexity of the EP. Through the above steps, this embodiment realizes the accurate transmission of the target address and the effective establishment of the mapping relationship, so that the target EP can efficiently complete the transmission task of the MSI interrupt number without adding additional hardware resources. At the same time, since the writing of the target address and the establishment of the mapping relationship are both actively completed by the RC, the target EP does not require additional configuration or intervention, further simplifying the design and implementation process of the target EP. Furthermore, this embodiment directly utilizes the target EP's configuration space and MSI capability registers, avoiding the need for additional hardware modules or complex software logic, thereby reducing overall system complexity and implementation costs. Therefore, this embodiment not only ensures the integrity and reliability of interrupt handling functionality but also significantly improves PCIe system resource utilization and design efficiency.

[0086] See Figure 7 , is a flow chart of establishing a mapping relationship based on a preset mapping method provided by an embodiment of the present application, such as Figure 7 As shown, the method of the embodiment of the present application may include the following steps S601-S602, and steps S601-S602 may be used as Figure 3 The detailed steps of step S205 of the embodiment are shown.

[0087] S601, the target EP reads the target address from the MSI address register;

[0088] S602: The target EP establishes a mapping relationship between the local address of the target EP and the target address based on a preset mapping method and the target address.

[0089] Specifically, the target EP reads the target address from the MSI address register. In some possible implementations, the target EP executes a configuration read command through hardware logic or a software module to obtain the target address from a specific storage location in the MSI address register.

[0090] Next, the target EP establishes a mapping relationship between the local address of the target EP and the target address based on a preset mapping method and the target address, wherein the preset mapping method refers to a pre-configured logical conversion rule between the local address and the target address.

[0091] In some possible implementations, the target EP associates the target address with the local address based on a preset mapping method through hardware logic or software modules to generate an outbound mapping file. The outbound mapping file refers to a data structure or configuration file in the target EP that is used to record the mapping relationship between the local address and the target address. The target EP maps the association operation of the local address to the storage space corresponding to the target address by parsing the outbound mapping file. It should be noted that the mapping relationship between the local address and the target address can be expressed as a one-to-one correspondence, and the mapping relationship between the local address and the target address remains unchanged during normal operation after system initialization.

[0092] In this embodiment, the target EP first reads the target address from the MSI address register, ensuring that the target EP knows the specific address in the host device used to store the MSI interrupt number. Next, based on a preset mapping method and the target address, the target EP establishes a mapping relationship between its local address and the target address, ensuring that operations associated with the local address are mapped to the storage space corresponding to the target address. This mapping relationship allows the target EP to efficiently complete the transmission of the MSI interrupt number without relying on the MSI data register, thereby reducing the target EP's hardware design complexity and resource overhead.

[0093] See Figure 8 , which is a flow chart of establishing a mapping relationship based on an outbound mapping method provided by an embodiment of the present application, such as Figure 8 As shown, the method of the embodiment of the present application may include the following steps S701-S702, and steps S701-S702 may be used as Figure 7 The detailed steps of step S602 in the embodiment are shown.

[0094] S701, the target EP associates the local address of the target EP with the target address to generate an outbound mapping file;

[0095] S702: The target EP maps the associated operation of the local address to the storage space corresponding to the target address based on the outbound mapping file to establish a mapping relationship between the local address and the target address.

[0096] Specifically, the target EP associates the local address of the target EP with the target address to generate an outbound mapping file. The outbound mapping file refers to a data structure or configuration file in the target EP for recording the mapping relationship between the local address and the target address, and its content may include information such as the local address, the target address, and the association rules between the two. The target EP associates the local address with the target address through hardware logic or software modules to generate an outbound mapping file. In some possible implementations, the target EP determines the association rules between the local address and the target address by parsing the format and range of the local address and the target address, and writes the association rules into the outbound mapping file. For example, the target EP can splice the low-order part of the local address with the high-order part of the target address to generate a mapping entry in the outbound mapping file.

[0097] In some possible implementations, the outbound mapping file may be an outbound mapping table that stores mapping relationships between local addresses and target addresses in a tabular form. The outbound mapping table may include multiple mapping entries, each of which consists of a local address field, a target address field, and an association rule field.

[0098] Next, the target EP maps the associated operation of the local address to the storage space corresponding to the target address based on the outbound mapping file to establish a mapping relationship between the local address and the target address. The associated operation of the local address refers to an operation performed by the target EP through hardware logic or software modules based on the pre-established mapping relationship between the local address and the target address when accessing the local address (such as writing or reading data). The core of the operation is to map the access to the local address (such as writing or reading) to the storage space corresponding to the target address, thereby achieving indirect access to the target address. In some possible implementations, the target EP converts the write operation of the local address into a write operation to the storage space corresponding to the target address based on the mapping entry in the outbound mapping file through hardware logic or software modules. For example, the target EP can map the write operation of the local address to the storage space corresponding to the target address through address conversion logic and write the MSI interrupt number into the storage space. In some possible implementations, the target EP converts the read operation of the local address into a read operation to the storage space corresponding to the target address based on the mapping entry in the outbound mapping file through hardware logic or software modules. For example, the target EP can use address translation logic to map a read operation from the local address to the storage space corresponding to the target address and read the required data from the storage space. It is understood that establishing this mapping relationship ensures that when the target EP writes an MSI interrupt number to the local address, it can transmit the MSI interrupt number to the storage space corresponding to the target address of the host device based on the mapping relationship.

[0099] In this embodiment, the target EP first associates the local address of the target EP with the target address to generate an outbound mapping file. Then, based on the outbound mapping file, the target EP maps the association operation of the local address to the storage space corresponding to the target address to establish a mapping relationship between the local address and the target address, ensuring that the target EP can map the write operation of the local address to the storage space corresponding to the target address. By establishing the mapping relationship, the target EP can efficiently complete the transmission task of the MSI interrupt number without relying on the MSI data register, thereby reducing the hardware design complexity and resource overhead of the target EP. In addition, since the mapping relationship is established based on the outbound mapping file, the target EP can dynamically adjust the mapping relationship according to the system load or interrupt frequency to optimize the efficiency of interrupt transmission.

[0100] See Figure 9 , which is a flow chart of a target EP reporting MSI capability according to an embodiment of the present application, such as Figure 9 As shown, the method of the embodiment of the present application may include the following steps S801-S802, and steps S801-S802 may be performed on Figure 2 In the illustrated embodiment, step S101 is performed before the step S101.

[0101] S801, the target EP configures an MSI capability register set in the configuration space of the target EP, where the MSI capability register set includes an MSI control register;

[0102] S802: The target EP writes MSI capability information into the MSI control register. The MSI capability information indicates that the target EP has MSI capability.

[0103] Specifically, the target EP configures the MSI capability register set in the configuration space through hardware logic or software modules, including operations such as allocating storage space, initializing register values, and setting register access permissions. It can be understood that the configuration of the MSI capability register set provides the hardware foundation for the target EP's MSI function.

[0104] Next, the target EP writes MSI capability information to the MSI control register. The MSI capability information indicates that the target EP has MSI capability. MSI capability information refers to a specific field or register value in the configuration space that is used to identify whether the target EP supports message signaled interrupts (MSI). The target EP executes the configuration write command through hardware logic or software modules to write the MSI capability information to a specific storage location in the MSI control register. In some possible implementations, the MSI capability information includes an MSI enable bit, an MSI vector number field, and an MSI trigger mode field. The MSI enable bit is used to indicate whether the target EP has enabled the MSI function, the MSI vector number field is used to indicate the number of MSI interrupt vectors supported by the target EP, and the MSI trigger mode field is used to indicate the MSI interrupt trigger mode supported by the target EP. By writing the MSI capability information to the MSI control register, the target EP reports to the root complex RC of the host device that it has MSI capability, so that the RC can identify and manage the target EP in the subsequent interrupt processing process.

[0105] In some possible implementations, the target EP executes steps S801 and S802 during startup to ensure that the MSI capability register set is correctly configured and MSI capability information is reported during the system initialization phase. Specifically, during startup, the target EP, through hardware logic or software modules, performs configuration space initialization operations, allocates and configures storage space for the MSI capability register set, and writes the MSI capability information to the MSI control register. It will be appreciated that the target EP completes the configuration of the MSI capability register set and the reporting of MSI capability information during startup, ensuring that the system has complete interrupt handling capabilities at the initial stage of operation.

[0106] In this embodiment, the target EP first configures the MSI capability register set in its configuration space. The MSI capability register set includes the MSI control register, which provides the hardware foundation for the target EP's MSI functionality. Next, the target EP writes MSI capability information into the MSI control register. This MSI capability information indicates that the target EP possesses MSI capabilities, ensuring that the target EP can report its MSI capabilities to the host device's root complex RC. Through these steps, the target EP can correctly configure the MSI capability register set and report MSI capability information at startup or during operation, providing data support for the host device's root complex RC to identify and manage the target EP.

[0107] To facilitate understanding of the interaction process between the RC and the target EP in the embodiment of this application, please refer to Figure 10 , which is a schematic diagram of the interaction between RC and target EP provided in one embodiment of the present application.

[0108] The interaction between RC and target EP mainly includes the initialization phase and the MSI interrupt processing phase.

[0109] During the initialization phase, the target EP first configures the MSI capability register group in its own configuration space. The register group includes the MSI control register, and writes the MSI capability information to the MSI control register to indicate that the target EP has MSI capability. The RC determines the storage space for storing interrupt data from the host device, and determines the address corresponding to the storage space as the target address. The RC reads the configuration space of each EP in the EP set respectively, obtains the configuration space reading result of each EP, and determines the target EP from the EP set based on the reading result. The configuration space reading result of the target EP includes the MSI capability information. The RC determines the MSI capability register group from the configuration space of the target EP, and determines the MSI address register from the MSI capability register group, and then writes the target address to the MSI address register. The RC registers the interrupt callback function corresponding to the target address in the operating system of the host device, and enables the MSI function of the target EP based on the registration status of the interrupt callback function. The target EP reads the target address from the MSI address register and establishes a mapping relationship between the local address of the target EP and the target address based on the preset mapping method and the target address. Specifically, the target EP associates the local address with the target address, generates an outbound mapping file, and maps the association operation of the local address to the storage space corresponding to the target address based on the outbound mapping file.

[0110] During the MSI interrupt processing phase, when the target EP detects an event that triggers an interrupt, it generates an MSI interrupt number based on the preset interrupt rules and writes the MSI interrupt number to the target EP's local address. Based on the mapping between the local address and the target address, the MSI interrupt number is transferred to the storage space corresponding to the target address. The RC reads the MSI interrupt number from the storage space corresponding to the target address and executes the interrupt processing task corresponding to the MSI interrupt number.

[0111] Through the above steps, the RC and the target EP complete the reporting of MSI capabilities, determination of the target address, enabling of the MSI function, and establishment of the mapping relationship in the initialization phase, and realize the transmission and processing of the interrupt number in the MSI interrupt processing phase, ensuring the integrity and real-time performance of the interrupt processing function, while effectively reducing the hardware resource usage and design complexity of the EP and PCIe system.

[0112] It should be understood that although the steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0113] In one embodiment, a PCIe system is provided, which includes a host device and an endpoint device EP set, the host device includes a root complex RC, and the RC is connected to each EP in the EP set based on a PCIe bus; the PCIe system is configured to execute any step in the above interrupt handling method.

[0114] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above interrupt handling method can be implemented.

[0115] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0116] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0117] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0118] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0119] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0120] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. An interrupt processing method, characterized in that: The method is applied to a Peripheral Component Interconnect Express (PCIe) system, the PCIe system including a host device and a set of endpoint devices (EPs), the host device including a root complex (RC), and the RC connected to each EP in the set of EPs based on a PCIe bus; the method includes: The target EP in the EP set writes a message signal interrupt (MSI) interrupt number to the local address of the target EP, so that the MSI interrupt number enters a storage space corresponding to the target address based on a mapping relationship between the local address and the target address of the host device; The RC reads the MSI interrupt number from the storage space corresponding to the target address, and executes the interrupt processing task corresponding to the MSI interrupt number.

2. The method according to claim 1, characterized in that The target EP in the EP set writes a message signal interrupt (MSI) interrupt number to the local address of the target EP so that the MSI interrupt number enters the storage space corresponding to the target address based on the mapping relationship between the local address and the target address of the host device, and further includes: The RC determines a target address from the host device; The RC determines a target EP from the EP set, where the target EP has MSI capability; The RC transmits the target address to the target EP; The RC registers an interrupt callback function corresponding to the target address, and enables the MSI function of the target EP based on the registration status of the interrupt callback function; The target EP establishes a mapping relationship between a local address of the target EP and the target address based on the target address.

3. The method according to claim 2, characterized in that The RC determines a target address from the host device, including: The RC determines a storage space for storing interrupt data from the host device; The RC determines an address corresponding to the storage space for storing interrupt data as a target address.

4. The method according to claim 2, characterized in that The RC determines a target EP from the EP set, including: The RC reads the configuration space of each EP respectively to obtain the configuration space reading result of each EP; The RC determines a target EP from the EP set according to a configuration space reading result of each EP, where the configuration space reading result of the target EP includes MSI capability information, and the MSI capability information indicates that the target EP has MSI capability.

5. The method according to claim 4, characterized in that The RC transmitting the target address to the target EP includes: The RC determines an MSI capability register set from a configuration space of the target EP; The RC determines an MSI address register from the MSI capability register set; The RC writes the target address to the MSI address register.

6. The method according to claim 5, characterized in that The target EP establishes, based on the target address, a mapping relationship between a local address of the target EP and the target address, including: The target EP reads the target address from the MSI address register; The target EP establishes a mapping relationship between the local address of the target EP and the target address based on a preset mapping mode and the target address.

7. The method according to claim 6, characterized in that The target EP establishes, based on a preset mapping mode and the target address, a mapping relationship between the local address of the target EP and the target address, including: The target EP associates the local address of the target EP with the target address to generate an outbound mapping file; The target EP maps the associated operation of the local address to the storage space corresponding to the target address based on the outbound mapping file, so as to establish a mapping relationship between the local address and the target address.

8. The method according to claim 1, characterized in that The target EP in the EP set writes a message signal interrupt (MSI) interrupt number to the local address of the target EP so that the MSI interrupt number enters the storage space corresponding to the target address based on the mapping relationship between the local address and the target address of the host device, and further includes: The target EP configures an MSI capability register set in a configuration space of the target EP, the MSI capability register set including an MSI control register; The target EP writes MSI capability information into the MSI control register, where the MSI capability information indicates that the target EP has MSI capability.

9. A PCIe system comprising a host device and an endpoint device (EP) set, wherein the host device comprises a root complex (RC), and the RC is connected to each EP in the EP set based on a PCIe bus; The PCIe system is configured to perform the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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