State synchronization method and device of multi-core processor, chip and equipment

Abstract

The invention relates to a state synchronization method and device of a multi-core processor, a chip and equipment. The method comprises the following steps: controlling a plurality of processing cores of the multi-core processor to execute incremental operation on a target counter through an atomic instruction, wherein the incremental operation is used for adding one to the counting number of the target counter; under the condition that the counting number of the target counter is equal to the number of the processing cores of the multi-core processor, the unified timeout time of timers of the multiple processing cores is determined according to the target counter; synchronously configuring and starting timers of a plurality of processing cores in the multi-core processor according to the unified timeout time; and under the condition that the timers of the plurality of processing cores are overtime, triggering the synchronous state switching of the plurality of processing cores. By adopting the method, the synchronization precision of the multi-core processor can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a state synchronization method, apparatus, chip, and device for a multi-core processor. Background Art

[0002] With the development of chip technology, multi-core processors are increasingly being used. Multi-core processors can integrate multiple independent processing cores on a single chip. Each processing core can independently execute instructions and process tasks, thereby improving the overall performance of the multi-core processor through parallel computing.

[0003] In related technologies, multi-core processor synchronization can be achieved through periodic interrupt signals generated by a shared clock source. This interrupt signal is periodically broadcast to all cores in the multi-core processor, activating the interrupt service routine (ISR) of each core to achieve multi-core synchronization.

[0004] However, since context save or restore operations must be performed during the interrupt response process, and there are multiple jump processes involved between the interrupt service program and the multi-core synchronization task, this will cause microsecond-level time deviations in the synchronization of the processing cores, and the synchronization accuracy is low. Summary of the Invention

[0005] Based on this, it is necessary to provide a state synchronization method, device, chip and equipment for a multi-core processor that can improve the synchronization accuracy of the multi-core processor in order to address the above technical problems.

[0006] In a first aspect, the present application provides a state synchronization method for a multi-core processor, comprising:

[0007] Controlling the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, wherein the increment operation is used to increase the count quantity of the target counter by one;

[0008] When the count number of the target counter is equal to the number of processing cores of the multi-core processor, determining a unified timeout period of the timers of the multiple processing cores according to the target counter;

[0009] Synchronously configuring and starting timers of multiple processing cores in the multi-core processor according to a unified timeout time;

[0010] When the timers of the multiple processing cores expire, a synchronous state switching of the multiple processing cores is triggered.

[0011] In one embodiment, the method further comprises:

[0012] When the count number of the target counter is less than the number of processing cores of the multi-core processor, a target processing core among the multiple processing cores is controlled to poll and wait for the unified timeout period, the target processing core being the processing core that completes the increment operation.

[0013] In one embodiment, after determining a unified timeout period of timers of the multiple processing cores according to the target counter, the method further includes:

[0014] Writing the unified timeout period into a shared memory area of ​​the multiple processing cores;

[0015] A read instruction is sent to the target processing core, where the read instruction is used to instruct the polling-waiting target processing core to read the unified timeout period from the shared memory area.

[0016] In one embodiment, the states of the processing cores include a deep low power consumption state and a maximum performance state; and triggering synchronous state switching of the multiple processing cores when timers of the multiple processing cores expire includes:

[0017] When the timers of the multiple processing cores expire, synchronously triggering private peripheral interrupt messages of the multiple processing cores, wherein the private peripheral interrupt messages are used to instruct the corresponding processing cores to exit the deep low power consumption state;

[0018] In response to the private peripheral interrupt message, the plurality of processing cores are controlled to switch from the deep low power consumption state to the maximum performance state.

[0019] In one embodiment, before synchronously triggering the private peripheral interrupts of the multiple processing cores when the timers of the multiple processing cores expire, the method further includes:

[0020] In response to the deep low power state instruction, the plurality of processing cores are controlled to enter the deep low power state.

[0021] In one embodiment, before controlling the plurality of processing cores of the multi-core processor to execute an increment operation on a target counter through an atomic instruction, the method further comprises:

[0022] Initialize the storage resources of each processing core in the multi-core processor and shield the target interrupt of each processing core, wherein the target interrupt is used to trigger each processing core to jump to execute an interrupt service program.

[0023] In one embodiment, the storage resources include stack space and cache.

[0024] In a second aspect, the present application provides a state synchronization device for a multi-core processor, comprising:

[0025] a counting module, configured to control the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, wherein the increment operation is configured to increase the count of the target counter by one;

[0026] a timing module, configured to determine, when the number of counts of the target counter is equal to the number of processing cores of the multi-core processor, a unified timeout period for the timers of the multiple processing cores according to the target counter; and synchronously configure and start the timers of the multiple processing cores in the multi-core processor according to the unified timeout period;

[0027] The switching module is used to trigger the synchronous switching of the states of the multiple processing cores when the timers of the multiple processing cores expire.

[0028] In one embodiment, the timing module is also used to control the target processing core among the multiple processing cores to poll and wait for the unified timeout time when the count number of the target counter is less than the number of processing cores of the multi-core processor. The target processing core is the processing core that completes the increment operation.

[0029] In one embodiment, the timing module is further used to write the unified timeout period into the shared memory area of ​​the multiple processing cores; and send a read instruction to the target processing core, wherein the read instruction is used to instruct the polling-waiting target processing core to read the unified timeout period from the shared memory area.

[0030] In one embodiment, the state of the processing core includes a deep low power consumption state and a maximum performance state; the switching module is further used to synchronously trigger the private peripheral interrupt messages of the multiple processing cores when the timers of the multiple processing cores expire, and the private peripheral interrupt messages are used to instruct the corresponding processing cores to exit the deep low power consumption state; in response to the private peripheral interrupt messages, the multiple processing cores are controlled to switch from the deep low power consumption state to the maximum performance state.

[0031] In one embodiment, the switching module is further configured to control the plurality of processing cores to enter the deep low power state in response to the deep low power state instruction.

[0032] In one embodiment, the state synchronization device of the multi-core processor further includes:

[0033] The initialization module is used to initialize the storage resources of each processing core in the multi-core processor and shield the target interrupt of each processing core, wherein the target interrupt is used to trigger each processing core to jump to execute an interrupt service program.

[0034] In one embodiment, the storage resources include stack space and cache.

[0035] In a third aspect, the present application provides a chip comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the state synchronization method of the multi-core processor of the first aspect when executing the computer program.

[0036] In a fourth aspect, the present application provides a computer device comprising a processor and the chip described in the third aspect above, wherein the chip is used to dispatch messages to the processor or the chip itself for processing, and the processor is used to process messages dispatched by the chip.

[0037] In a fifth aspect, the present application provides a network interface card, comprising the chip and interface described in the third aspect above, wherein the chip communicates externally through the interface.

[0038] In a sixth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the state synchronization method of a multi-core processor according to the first aspect.

[0039] In a seventh aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the state synchronization method of a multi-core processor according to the first aspect.

[0040] The state synchronization method, device, chip and equipment of the multi-core processor control the multiple processing cores of the multi-core processor to perform an increment operation on the target counter through an atomic instruction. The increment operation is used to increase the count number of the target counter by one; when the count number of the target counter is equal to the number of processing cores of the multi-core processor, the unified timeout period of the timers of the multiple processing cores is determined according to the target counter; the timers of the multiple processing cores in the multi-core processor are synchronously configured and started according to the unified timeout period; when the timers of the multiple processing cores time out, the state synchronization switching of the multiple processing cores is triggered. Since the timers of the multiple processing cores are configured and started based on the unified timeout period obtained by the target counter of the atomic increment operation, the timers of the multiple processing cores can trigger interrupts at the same time, thereby realizing sub-cycle synchronization of the multiple processing cores and improving the synchronization accuracy of the multi-core processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A flowchart of a state synchronization method for a multi-core processor provided in an embodiment of the present application;

[0043] Figure 2 A flowchart of another multi-core processor state synchronization method provided in an embodiment of the present application;

[0044] Figure 3 A flowchart of another method for synchronizing the state of a multi-core processor provided in an embodiment of the present application;

[0045] Figure 4 A structural block diagram of a state synchronization device for a multi-core processor provided in an embodiment of the present application;

[0046] Figure 5 This is a diagram of the internal structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0048] First, the related technology will be described below.

[0049] With the development of chip technology, multi-core processors are increasingly being used. Multi-core processors can integrate multiple independent processing cores on a single chip. Each processing core can independently execute instructions and process tasks, thereby improving the overall performance of the multi-core processor through parallel computing.

[0050] In related technologies, multi-core synchronization in multi-core processors can be achieved through a multi-core synchronization mechanism based on hardware timers. Multi-core processors generate periodic interrupt signals from a shared clock source, and a central timer broadcasts the interrupt signals to all processing cores, thereby triggering interrupts synchronously.

[0051] When each processing core receives an interrupt signal, it activates its own Interrupt Service Routine (ISR). This ISR saves or restores the currently executing context, waking up the pre-set synchronization task handler to coordinate operations among the multiple cores. This context saving or restoring operation can include storing and loading data such as the program counter and register status.

[0052] However, due to the operations of saving or restoring the currently executed context performed by the interrupt service program, as well as the multi-level jump process between the interrupt service program and the synchronization task, there will be microsecond-level time deviations in the synchronization actions of each processing core. It is impossible to ensure that the time deviation is less than or equal to 1 cycle, and thus it is impossible to achieve precise synchronization of the multi-core processor at the sub-clock cycle level.

[0053] To solve the above problems, the embodiments of the present application provide a state synchronization method, apparatus, chip and equipment for a multi-core processor. Based on the unified timeout time obtained by the target counter of the atomic increment operation, the timers of multiple processing cores are configured and started, so that the timers of multiple processing cores can trigger interrupts at the same time, thereby realizing sub-cycle synchronization of multiple processing cores and improving the synchronization accuracy of the multi-core processor.

[0054] It should be understood that the state synchronization method of the multi-core processor provided in the embodiment of the present application can be applied to the multi-core processor, or any electronic device including the multi-core processor. The electronic device can be a terminal or a network device.

[0055] Terminals include, but are not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices. IoT devices include smart speakers, smart TVs, smart air conditioners, smart car devices, and projectors. Portable wearable devices include smart watches, smart bracelets, and head-mounted devices. Head-mounted devices include virtual reality (VR) devices, augmented reality (AR) devices, and smart glasses.

[0056] The above-mentioned network devices may be, but are not limited to, data processing units, network interface cards, servers, network adapters, switches, or routers.

[0057] In an exemplary embodiment, Figure 1As shown, a state synchronization method for a multi-core processor is provided. The method is described by taking the application of the method to a multi-core processor as an example, including S201-S204:

[0058] S201 , controlling multiple processing cores of a multi-core processor to perform an increment operation on a target counter through an atomic instruction, where the increment operation is used to increase the count quantity of the target counter by one.

[0059] In the present application, when a multi-core processor performs state synchronization, multiple processing cores of the multi-core processor may be controlled to perform an increment operation on a target counter through an atomic instruction.

[0060] The multi-core processor may include multiple processing cores. Exemplarily, the multi-core processor may also include multiple central processing unit (CPU) cores.

[0061] The atomic instruction can be an instruction whose execution process cannot be interrupted. Accordingly, since the atomic instruction is atomic, that is, the atomic instruction is either completely executed or not executed at all, the increment operation of the target processor of the multi-core processor can be updated lock-free.

[0062] It should be understood that the embodiments of the present application do not limit the above-mentioned target counter. In some embodiments, the above-mentioned target counter can be a global system counter (sync_count) of a multi-core processor. The global system counter can be located in a shared storage unit of the multi-core processor and maintained by multiple processing cores in the multi-core processor.

[0063] Exemplarily, the multiple processing cores of the multi-core processor synchronously execute incrementing operations on the global system counter through atomic instructions. After each processing core completes the incrementing operation on the global system counter, the count number of the global system counter is increased by one.

[0064] In some embodiments, before the multi-core processor controls the multiple processing cores of the multi-core processor to perform an increment operation on the target counter through an atomic instruction, the storage resources of each processing core in the multi-core processor can be initialized and the target interrupts of each processing core can be masked.

[0065] The storage resources may include stack space and cache. Accordingly, by initializing the storage resources of each processing core in the multi-core processor, stack space allocation and cache pre-configuration of each processing core can be completed.

[0066] The target interrupt is used to trigger each processing core to jump to execute the interrupt service routine. Exemplarily, the target interrupt may include an interrupt request (Interrupt Request) or a fast interrupt request (FIQ) that triggers the interrupt service routine.

[0067] S202 : When the count number of the target counter is equal to the number of processing cores of the multi-core processor, determine a unified timeout period of timers of the multiple processing cores according to the target counter.

[0068] In some embodiments, after a multi-core processor controls multiple processing cores of the multi-core processor to execute an increment operation on a target counter using an atomic instruction, the count count of the target counter can be determined in real time. Subsequently, the count count of the target counter is compared with the number of processing cores of the multi-core processor. When the count count of the target counter is equal to the number of processing cores of the multi-core processor, a unified timeout period of the timers of the multiple processing cores can be determined based on the target counter.

[0069] In other embodiments, when the count number of the target counter is less than the number of processing cores of the multi-core processor, the multi-core processor can control the target processing core among the multiple processing cores to poll and wait for a unified timeout period, where the target processing core is the processing core that completes the increment operation.

[0070] For example, when the number of counts in the target counter is equal to the number of processing cores in the multi-core processor, the processing core that completes the increment operation may be the last core among the multiple processing cores, that is, the last processing core to complete the increment operation. A non-last core among the multiple processing cores is the target processing core.

[0071] Accordingly, after determining that all processing cores have completed the increment operation, the last core can determine the unified timeout period for the timers of multiple processing cores based on the target counter. After completing the increment operation, the non-last cores enter the core polling waiting state until the last core determines the unified timeout period.

[0072] Exemplarily, the last core may obtain a unified timeout time for timers of multiple processing cores based on a preset timeout parameter and the current moment when the number of counts of the target counter is equal to the number of processing cores of the multi-core processor.

[0073] In some embodiments, after the multi-core processor determines the unified timeout period of the timers of multiple processing cores based on the target counter, it can also write the unified timeout period into the shared memory area of ​​the multiple processing cores, and then send a read instruction to the target processing core to instruct the polling waiting target processing core to read the unified timeout period from the shared memory area through the read instruction.

[0074] The read instruction may be a Send Event (SEV) instruction.

[0075] For example, the shared memory area can be located in the shared storage unit where the global system counter (sync_count) is located. After calculating the unified timeout period, the last core can write the unified timeout period into the shared memory areas of multiple processing cores and broadcast it globally via a read instruction to wake up the target processing cores, so that the target processing cores can read the unified timeout period from the shared memory area.

[0076] S203: Synchronously configure and start timers of multiple processing cores in the multi-core processor according to the unified timeout time.

[0077] In this step, after the multi-core processor determines the unified timeout period of the timers of the multiple processing cores according to the target counter, the timers of the multiple processing cores in the multi-core processor can be synchronously configured and started according to the unified timeout period.

[0078] The unified timeout period may be used as an absolute timeout period shared by timers of multiple processing cores in a multi-core processor. The timers of the multiple processing cores may be physical timers of the multiple processing cores.

[0079] For example, the multiple processing cores in a multi-core processor can respectively write the unified timeout time into their respective timers and synchronously start the timers of each processing core, so that when the timers of multiple processing cores time out, an interrupt signal can be generated based on the same unified timeout time, ensuring that the deviation of the triggering time of the interrupt signal for multiple processing cores is less than 1 clock cycle.

[0080] S204 : When the timers of the multiple processing cores expire, triggering synchronous state switching of the multiple processing cores.

[0081] The states of the processing core include a deep low power consumption (Wait For Interrupt, WFI) state and a maximum performance state (Max Power-State).

[0082] It should be understood that the deep low-power state is a low-power state of the processing core, which can put the processing core into sleep mode, stop actively executing instructions, and maintain only the minimum necessary hardware functions such as interrupt controllers and counters. The maximum performance state can be a state in which the processing core supports processing high-power programs.

[0083] Correspondingly, the synchronous state switching of the multiple processing cores triggered by the timeout of the timers of the multiple processing cores may be switching the multiple processing cores from a deep low power consumption state to a maximum performance state.

[0084] The embodiments of the present application do not limit how to trigger the synchronous state switching of multiple processing cores when their timers expire. In some embodiments, when the timers of multiple processing cores expire, multiple processing cores in a multi-core processor can synchronously trigger private peripheral interrupt (PPI) messages for the multiple processing cores. The private peripheral interrupt message is used to instruct the corresponding processing core to exit a deep low power state. Subsequently, in response to the private peripheral interrupt message, the multi-core processor can control the multiple processing cores to switch from the deep low power state to the maximum performance state.

[0085] In other embodiments, when the timers of multiple processing cores expire and before the private peripheral interrupt messages of multiple processing cores are synchronously triggered, the multi-core processor can also control the multiple processing cores to enter a deep low power state in response to a deep low power state instruction.

[0086] Exemplarily, after completing the initialization of storage resources and shielding the target interrupts of each processing core, the multi-core processor can execute deep low power state instructions respectively by multiple processing cores to enter the deep low power state to achieve multi-power control.

[0087] For example, after entering the deep power reduction state, the multiple processing cores can align hardware-level interrupts using their respective timers. When the timers of the multiple processing cores expire synchronously at a unified timeout, a private peripheral interrupt message is triggered, and each processing core simultaneously exits the deep power reduction state.

[0088] In this application, since the timeout periods of the timers of multiple processing cores are all unified timeout periods corresponding to the same global system counter, the propagation deviation of private peripheral interrupt messages is limited to 1 clock cycle, thereby improving the synchronization accuracy of the multi-core processor when switching states.

[0089] In other embodiments, the deep low power state instructions and the MaxPower program entry address corresponding to the maximum performance state can be stored physically adjacent to each other, so that after the state switch is completed, there is no need for branch prediction and instruction fetch delay, thereby achieving zero interrupt context execution.

[0090] For example, if the multi-core processor contains 16 processing cores and the system timer is 100MHz, by inserting a timestamp read instruction at the MaxPower program entry corresponding to the maximum performance state, it can be determined that after multiple processors execute the above-mentioned multi-core processor state synchronization method, the synchronization accuracy of the multi-core processor is effectively improved.

[0091] The unified timeout period of the timers of the 16 processing cores is 195935884760 nanoseconds (ns). The time it takes for the timers of the 16 processing cores to switch from a deep low-power state to a maximum performance state is 195935884880 ns. The cross-core deviation of the actual synchronization moment of the 16 processing cores is 0 ns, and the synchronization accuracy is less than or equal to 1 cycle, reaching the sub-cycle level.

[0092] The state synchronization method of a multi-core processor provided in an embodiment of the present application controls the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, wherein the increment operation is used to add one to the count number of the target counter; when the count number of the target counter is equal to the number of processing cores of the multi-core processor, the unified timeout time of the timers of the multiple processing cores is determined according to the target counter; the timers of the multiple processing cores in the multi-core processor are synchronously configured and started according to the unified timeout time; when the timers of the multiple processing cores time out, the state synchronization switching of the multiple processing cores is triggered. Since the timers of the multiple processing cores are configured and started based on the unified timeout time obtained by the target counter of the atomic increment operation, the timers of the multiple processing cores can trigger interrupts at the same time, thereby realizing sub-cycle synchronization of the multiple processing cores and improving the synchronization accuracy of the multi-core processor.

[0093] Figure 2 A flow chart of another state synchronization method for a multi-core processor provided in an embodiment of the present application is provided. The state synchronization method for a multi-core processor is applied to a multi-core processor, such as Figure 2 As shown, the state synchronization method of the multi-core processor includes S301-S305:

[0094] S301 , controlling multiple processing cores of a multi-core processor to perform an increment operation on a target counter through an atomic instruction, where the increment operation is used to increase the count quantity of the target counter by one.

[0095] S302 : When the count number of the target counter is equal to the number of processing cores of the multi-core processor, determine a unified timeout period of timers of the multiple processing cores according to the target counter.

[0096] S303: Synchronously configure and start timers of multiple processing cores in the multi-core processor according to a unified timeout time.

[0097] S304 : When the timers of the multiple processing cores expire, triggering synchronous state switching of the multiple processing cores.

[0098] The states of the processing core include a deep low power consumption state and a maximum performance state.

[0099] In some embodiments, the multi-core processor may control the plurality of processing cores to enter a deep low power state in response to a deep low power state instruction.

[0100] In other embodiments, the multi-core processor can synchronously trigger private peripheral interrupt messages for the multiple processing cores when their timers expire, and the private peripheral interrupt messages are used to instruct the corresponding processing cores to exit the deep low power state. Subsequently, the multi-core processor can control the multiple processing cores to switch from the deep low power state to the maximum performance state in response to the private peripheral interrupt messages.

[0101] S305 : During the synchronous state switching of the multiple processing cores, perform a power integrity test of the multi-core processor.

[0102] The power integrity (PI) test may include a dynamic instantaneous current transient (DIDT) test.

[0103] In this application, when the states of multiple processing cores are switched from the state of multiple processing cores to the maximum performance state, instantaneous current shock and voltage fluctuation will be generated, thereby causing systemic risks such as power network collapse and clock signal jitter. Therefore, performing PI testing, especially DIDT testing, during the synchronous switching of the states of multiple processing cores can ensure the stability and reliability of the multi-core processor.

[0104] Figure 3 A flow chart of another state synchronization method for a multi-core processor provided in an embodiment of the present application is provided. The state synchronization method for a multi-core processor is applied to a multi-core processor, such as Figure 3 As shown, the state synchronization method of the multi-core processor includes S401-S409:

[0105] S401 , initializing storage resources of each processing core in a multi-core processor and shielding target interrupts of each processing core, where the target interrupts are used to trigger each processing core to jump to and execute an interrupt service routine.

[0106] The storage resources may include stack space and cache. Accordingly, by initializing the storage resources of each processing core in the multi-core processor, stack space allocation and cache pre-configuration of each processing core can be completed.

[0107] In this application, by initializing the storage resources of each processing core in a multi-core processor, multiple processing cores in the multi-core processor can be equipped with the storage resources required to execute corresponding programs. For example, by initializing the storage resources of a high-power program (MaxPower), multiple processing cores can execute the high-power program.

[0108] The target interrupt is used to trigger each processing core to jump to execute the interrupt service routine. Exemplarily, the target interrupt may include an interrupt request (Interrupt Request) or a fast interrupt request (FIQ) that triggers the interrupt service routine.

[0109] In the present application, by masking the target interrupt of each processing core, the interrupt of the timer of multiple processors only triggers the exit of the deep low power state (WFI) without jumping to the interrupt service routine.

[0110] S402 : Control multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, where the increment operation is used to increase the count quantity of the target counter by one.

[0111] S403: Determine whether the counted number of the target counter is equal to the number of processing cores of the multi-core processor.

[0112] If yes, execute S404; if no, execute S405.

[0113] S404 , controlling a target processing core among the multiple processing cores to poll and wait for a unified timeout period, where the target processing core is the processing core that completes the increment operation.

[0114] S405 : Determine a unified timeout period of timers of multiple processing cores according to the target counter.

[0115] In some embodiments, after determining a unified timeout period for timers of multiple processing cores based on a target counter, the multi-core processor may also write the unified timeout period into a shared memory area of ​​the multiple processing cores. Subsequently, the multi-core processor sends a read instruction to the target processing core, the read instruction being used to instruct the polling waiting target processing core to read the unified timeout period from the shared memory area.

[0116] S406: Synchronously configure and start timers of multiple processing cores in the multi-core processor according to the unified timeout time.

[0117] S407 : In response to the deep low power state instruction, control the plurality of processing cores to enter a deep low power state.

[0118] Among them, the deep low power state is a low power state of the processing core, which can make the processing core enter sleep mode, stop actively executing instructions, and only maintain the minimum necessary hardware functions such as interrupt controllers and counters.

[0119] S408 . When the timers of the multiple processing cores expire, synchronously trigger private peripheral interrupt messages of the multiple processing cores, where the private peripheral interrupt messages are used to instruct the corresponding processing cores to exit the deep low power state.

[0120] The maximum performance state may be a state in which the processing core supports processing high-power consumption programs.

[0121] S409 : In response to the private peripheral interrupt message, control the multiple processing cores to switch from the deep low power consumption state to the maximum performance state.

[0122] In some embodiments, when timers on multiple processing cores expire, multiple processing cores in a multi-core processor can simultaneously trigger private peripheral interrupt (PPI) messages for the multiple processing cores. The PPI messages are used to instruct the corresponding processing cores to exit a deep power reduction state. Subsequently, in response to the PPI messages, the multi-core processor can control the multiple processing cores to switch from the deep power reduction state to a maximum performance state.

[0123] In this application, since the timeout periods of the timers of multiple processing cores are all unified timeout periods corresponding to the same global system counter, the propagation deviation of private peripheral interrupt messages is limited to 1 clock cycle, thereby improving the synchronization accuracy of the multi-core processor when switching states.

[0124] In other embodiments, the deep low power state instructions and the MaxPower program entry address corresponding to the maximum performance state can be stored physically adjacent to each other, so that after the state switch is completed, there is no need for branch prediction and instruction fetch delay, thereby achieving zero interrupt context execution.

[0125] The state synchronization method of a multi-core processor provided in an embodiment of the present application controls the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, wherein the increment operation is used to add one to the count number of the target counter; when the count number of the target counter is equal to the number of processing cores of the multi-core processor, the unified timeout time of the timers of the multiple processing cores is determined according to the target counter; the timers of the multiple processing cores in the multi-core processor are synchronously configured and started according to the unified timeout time; when the timers of the multiple processing cores time out, the state synchronization switching of the multiple processing cores is triggered. Since the timers of the multiple processing cores are configured and started based on the unified timeout time obtained by the target counter of the atomic increment operation, the timers of the multiple processing cores can trigger interrupts at the same time, thereby realizing sub-cycle synchronization of the multiple processing cores and improving the synchronization accuracy of the multi-core processor.

[0126] It should be understood that, although the steps in the flowcharts of the above embodiments are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowcharts of the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0127] Based on the same inventive concept, an embodiment of the present application further provides a state synchronization device for a multi-core processor for implementing the state synchronization method for a multi-core processor involved above. The implementation solution provided by this device is similar to the implementation solution described in the above method. Therefore, the specific limitations of the state synchronization device for one or more multi-core processors provided below can be found in the above-mentioned limitations of the state synchronization method for a multi-core processor, and will not be repeated here.

[0128] In an exemplary embodiment, Figure 4 As shown, a state synchronization device 500 for a multi-core processor is provided, comprising: a counting module 501, a timing module 502 and a switching module 503, wherein:

[0129] A counting module 501 is used to control the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, where the increment operation is used to increase the count of the target counter by one;

[0130] The timing module 502 is configured to determine a unified timeout period for timers of the multiple processing cores according to the target counter when the number of counts of the target counter is equal to the number of processing cores of the multi-core processor; and synchronously configure and start the timers of the multiple processing cores in the multi-core processor according to the unified timeout period;

[0131] The switching module 503 is configured to trigger a synchronous state switching of the multiple processing cores when the timers of the multiple processing cores expire.

[0132] In some embodiments, the timing module 502 is also used to control the target processing core among multiple processing cores to poll and wait for a unified timeout time when the count number of the target counter is less than the number of processing cores of the multi-core processor. The target processing core is the processing core that completes the increment operation.

[0133] In some embodiments, the timing module 502 is further used to write a unified timeout period into a shared memory area of ​​multiple processing cores; and send a read instruction to the target processing core, the read instruction being used to instruct the polling waiting target processing core to read the unified timeout period from the shared memory area.

[0134] In some embodiments, the state of the processing core includes a deep low power state and a maximum performance state; the switching module 503 is also used to synchronously trigger private peripheral interrupt messages of multiple processing cores when the timers of multiple processing cores expire, and the private peripheral interrupt messages are used to instruct the corresponding processing cores to exit the deep low power state; in response to the private peripheral interrupt messages, control the multiple processing cores to switch from the deep low power state to the maximum performance state.

[0135] In some embodiments, the switching module 503 is further configured to control the plurality of processing cores to enter a deep low power state in response to a deep low power state instruction.

[0136] In some embodiments, the state synchronization apparatus 500 for a multi-core processor further includes:

[0137] The initialization module is used to initialize the storage resources of each processing core in the multi-core processor and shield the target interrupt of each processing core. The target interrupt is used to trigger each processing core to jump to execute the interrupt service program.

[0138] In some embodiments, storage resources include stack space and cache.

[0139] Each module in the aforementioned multi-core processor state synchronization device may be implemented in whole or in part through software, hardware, or a combination thereof. Each module may be embedded in or independent of a processor in a computer device in the form of hardware, or may be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0140] In one embodiment, a computer device is provided, wherein the computer device has a network interface card inserted therein, wherein the network interface card includes a chip, and the computer device can implement the state synchronization method of the multi-core processor. The internal structure diagram of the computer device can be as follows: Figure 5As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a state synchronization method of a multi-core processor is implemented.

[0141] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0142] In one exemplary embodiment, a chip is provided. The chip includes a memory and a processor. The memory stores a computer program, and the processor implements the aforementioned multi-core processor state synchronization method when executing the computer program. The chip can be a data processing unit (DPU) chip used in a data center, or other data processing chip.

[0143] In an exemplary embodiment, a network interface card (NIC) is provided, which includes the chip described in the above embodiment and multiple interfaces (such as PCI / PCIE interfaces, USB interfaces, etc.), through which the chip communicates externally.

[0144] In an exemplary embodiment, a computer device is provided. The computer device includes a central processing unit (CPU) and the chip or the network interface card described in the preceding embodiments, wherein the chip is configured to dispatch messages to the CPU or to process the chip itself, and the CPU is configured to process the messages dispatched by the chip.

[0145] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the state synchronization method of the multi-core processor is implemented.

[0146] In one embodiment, a computer program product is provided, including a computer program, which implements the state synchronization method of the multi-core processor when executed by a processor.

[0147] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, database or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), quantum computing-based data processing logic devices, artificial intelligence (AI) processors, and the like.

[0148] The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0149] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A state synchronization method for a multi-core processor, characterized in that: The method comprises: Controlling the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, wherein the increment operation is used to increase the count quantity of the target counter by one; When the count number of the target counter is equal to the number of processing cores of the multi-core processor, determining a unified timeout period of the timers of the multiple processing cores according to the target counter; Synchronously configuring and starting timers of multiple processing cores in the multi-core processor according to a unified timeout time; When the timers of the multiple processing cores expire, a synchronous state switching of the multiple processing cores is triggered.

2. The method according to claim 1, characterized in that The method further comprises: When the count number of the target counter is less than the number of processing cores of the multi-core processor, a target processing core among the multiple processing cores is controlled to poll and wait for the unified timeout period, the target processing core being the processing core that completes the increment operation.

3. The method according to claim 2, characterized in that After determining a unified timeout period of the timers of the multiple processing cores according to the target counter, the method further includes: Writing the unified timeout period into a shared memory area of ​​the multiple processing cores; A read instruction is sent to the target processing core, where the read instruction is used to instruct the polling-waiting target processing core to read the unified timeout period from the shared memory area.

4. The method according to claim 1, wherein The states of the processing cores include a deep low power consumption state and a maximum performance state; and triggering synchronous state switching of the multiple processing cores when the timers of the multiple processing cores expire, including: When the timers of the multiple processing cores expire, synchronously triggering private peripheral interrupt messages of the multiple processing cores, wherein the private peripheral interrupt messages are used to instruct the corresponding processing cores to exit the deep low power consumption state; In response to the private peripheral interrupt message, the plurality of processing cores are controlled to switch from the deep low power consumption state to the maximum performance state.

5. The method according to claim 4, characterized in that When the timers of the multiple processing cores time out, before synchronously triggering the private peripheral interrupts of the multiple processing cores, the method further includes: In response to the deep low power state instruction, the plurality of processing cores are controlled to enter the deep low power state.

6. The method according to any one of claims 1 to 5, characterized in that Before controlling the plurality of processing cores of the multi-core processor to perform an increment operation on the target counter through an atomic instruction, the method further includes: Initialize the storage resources of each processing core in the multi-core processor and shield the target interrupt of each processing core, wherein the target interrupt is used to trigger each processing core to jump to execute an interrupt service program.

7. The method according to claim 6, characterized in that The storage resources include stack space and cache.

8. A state synchronization device for a multi-core processor, characterized in that: The device comprises: a counting module, configured to control the multiple processing cores of the multi-core processor to perform an increment operation on a target counter through an atomic instruction, wherein the increment operation is configured to increase the count of the target counter by one; a timing module, configured to determine, when the number of counts of the target counter is equal to the number of processing cores of the multi-core processor, a unified timeout period for the timers of the multiple processing cores according to the target counter; and synchronously configure and start the timers of the multiple processing cores in the multi-core processor according to the unified timeout period; The switching module is used to trigger the synchronous switching of the states of the multiple processing cores when the timers of the multiple processing cores expire.

9. The device according to claim 8, characterized in that The timing module is also used to control the target processing core among the multiple processing cores to poll and wait for the unified timeout time when the count number of the target counter is less than the number of processing cores of the multi-core processor. The target processing core is the processing core that completes the increment operation.

10. The device according to claim 9, characterized in that The timing module is further used to write the unified timeout period into the shared memory area of ​​the multiple processing cores; and send a read instruction to the target processing core, wherein the read instruction is used to instruct the target processing core waiting for polling to read the unified timeout period from the shared memory area.

11. The device according to claim 8, characterized in that The states of the processing cores include a deep low power consumption state and a maximum performance state; the switching module is further configured to synchronously trigger private peripheral interrupt messages of the multiple processing cores when the timers of the multiple processing cores expire, the private peripheral interrupt messages being used to instruct the corresponding processing cores to exit the deep low power consumption state; In response to the private peripheral interrupt message, the plurality of processing cores are controlled to switch from the deep low power consumption state to the maximum performance state.

12. The device according to claim 11, characterized in that The switching module is further configured to control the plurality of processing cores to enter the deep low power state in response to the deep low power state instruction.

13. The device according to any one of claims 8 to 12, characterized in that The state synchronization device of the multi-core processor further includes: The initialization module is used to initialize the storage resources of each processing core in the multi-core processor and shield the target interrupt of each processing core, wherein the target interrupt is used to trigger each processing core to jump to execute an interrupt service program.

14. The device according to claim 13, characterized in that The storage resources include stack space and cache.

15. A chip comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

16. A computer device, characterized in that: It comprises a processor and the chip as claimed in claim 15, wherein the chip is used to dispatch messages to the processor or the chip itself for processing, and the processor is used to process the messages dispatched by the chip.

17. A network interface card, characterized in that: The device comprises the chip and the interface as claimed in claim 15, wherein the chip communicates externally through the interface.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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