High-voltage power supply high-selection circuit and control method thereof

Abstract

The invention discloses a high-voltage power supply high-selection circuit and a control method thereof, the high-voltage power supply high-selection circuit comprises a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1-INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6, the floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS, two inputs of the high-voltage floating comparator circuit are respectively connected with input signals V1 and V2, and the high-voltage floating comparator circuit is connected with the high-voltage PMOS tube PDM5 and the high-voltage PMOS tube PDM6. The inverters INV1-INV4 generate two inverted signals A and B according to an output signal of the high-voltage floating comparator circuit, a high-voltage power supply end of the high-voltage floating comparator circuit, a source electrode of the high-voltage PMOS tube PDM5 and a source electrode of the high-voltage PMOS tube PDM6D are connected with a floating high voltage HVDD, and a low-voltage power supply end of the high-voltage floating comparator circuit is connected with a floating low voltage HVSS. According to the invention, the high-voltage power supply high-selection circuit is realized.

Description

Technical Field

[0001] The present invention relates to a high-voltage selection circuit and a control method thereof, in particular to a high-voltage power supply high-voltage selection circuit and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] In power management systems, load switches with integrated ideal diode functionality offer key advantages, including low forward conduction loss, low leakage, and simplified load sharing, enabling them to more efficiently and reliably power OR power supplies. However, when one power supply in a dual-power system loses power, the ideal diode circuit within it loses its functionality, causing backflow from the high-voltage power supply to the low-voltage power supply, resulting in a drop in output voltage and potentially causing system abnormalities or even damage.

[0003] In the prior art, power supply selection circuits are often low-voltage designs. A low-voltage comparator is used to determine the size of the input voltage and output voltage, and the judgment result is used as an enable signal to turn on the switch tube on the high-voltage side to achieve the high-voltage selection function. However, in high-voltage scenarios, the two voltages to be compared may differ by tens of volts, and this solution is no longer applicable. Therefore, it is necessary to propose a high-voltage selection circuit for input voltage and output voltage to power the ideal diode circuit and ensure that the ideal diode circuit can still work normally when the input voltage is off, thereby protecting the input power supply and load. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a high voltage power supply high selection circuit and a control method thereof, so as to realize the high voltage power supply high selection circuit.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A high-voltage power supply selection circuit includes a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, a high-voltage PMOS tube PDM5, and a high-voltage PMOS tube PDM6. The floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS. The first input end of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS tube PDM5 and is connected to the input signal V1. The second input end of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS tube PDM6 and is connected to the input signal V2. The high-voltage power supply end of the high-voltage floating comparator circuit, the source of the high-voltage PMOS tube PDM5, and the high The source of the high-voltage PMOS tube PDM6D is connected to the floating high voltage HVDD, the low-voltage power supply terminal of the high-voltage floating comparator circuit is connected to the floating low voltage HVSS, the output terminal of the high-voltage floating comparator circuit is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4 and the gate of the high-voltage PMOS tube PDM5 to generate signal A, and the output terminal of the inverter INV4 is connected to the gate of the high-voltage PMOS tube PDM6 to generate signal B.

[0006] Furthermore, the high-voltage floating comparator circuit includes NMOS transistors NM1 to NM4, PMOS transistors PM1 to PM2, high-voltage PMOS transistors PDM1 to PDM4 and a current source I1. The drain of the high-voltage PMOS transistor PDM1 is connected to the drain of the high-voltage PMOS transistor PDM3 and serves as a first input terminal of the high-voltage floating comparator circuit. The drain of the high-voltage PMOS transistor PDM2 is connected to the drain of the high-voltage PMOS transistor PDM4 and serves as a second input terminal of the high-voltage floating comparator circuit. The gate of the high-voltage PMOS transistor PDM1 is connected to the gate of the high-voltage PMOS transistor PDM2, the gate of the high-voltage PMOS transistor PDM3, the gate of the high-voltage PMOS transistor PDM4, the source of the high-voltage PMOS transistor PDM1, the source of the high-voltage PMOS transistor PDM2 and one end of the current source I1. The body end of the high-voltage PMOS transistor PDM1 is connected to the body end of the high-voltage PMOS transistor PDM3, the body end of the high-voltage PMOS transistor PDM2, the body end of the high-voltage PMOS transistor PDM4 and the body end of the high-voltage PMOS transistor PDM1. The body terminal of PDM4, the source of the PMOS transistor PM1, and the source of the PMOS transistor PM2 are connected and serve as the high-voltage power supply terminal of the high-voltage floating comparator circuit. The source of the high-voltage PMOS transistor PDM3 is connected to the drain of the NMOS transistor NM2, the gate of the NMOS transistor NM2, the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM3. The source of the high-voltage PMOS transistor PDM4 is connected to the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM4. The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and the drain of the NMOS transistor NM1. The drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM4 and serves as the output terminal of the high-voltage floating comparator circuit. The source of the NMOS transistor NM1, the source of the NMOS transistor NM2, the source of the NMOS transistor NM3, and the source of the NMOS transistor NM4 serve as the low-voltage power supply terminal of the high-voltage floating comparator circuit. The other end of the current source I1 is grounded.

[0007] Furthermore, the NMOS transistors NM1 - NM4 have the same width-to-length ratio, the PMOS transistors PM1 - PM2 have the same width-to-length ratio, and the high-voltage PMOS transistors PDM1 - PDM4 have the same width-to-length ratio.

[0008] Furthermore, the floating power supply generating circuit includes PMOS transistors PM3 to PM10, a high-voltage PMOS transistor PDM7, a high-voltage NMOS transistor NDM1, a resistor R3 and a current source I2, the source of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM7 and generates a floating high voltage HVDD, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the source of the PMOS transistor PM4, the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM7 and the source of the PMOS transistor PM8, the gate of the PMOS transistor PM4 is connected to the drain of the PMOS transistor PM4 and the source of the PMOS transistor PM5, the gate of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM8 and the source of the PMOS transistor PM9. The source of the S transistor PM9 is connected, the gate of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM5, the drain of the high-voltage NMOS transistor NDM1, and the source of the high-voltage PMOS transistor PDM7 to generate a floating low voltage HVSS, the gate of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM9 and the source of the PMOS transistor PM10, the gate of the PMOS transistor PM10 is connected to the gate of the high-voltage PMOS transistor PDM7, the drain of the PMOS transistor PM10, and one end of the current source I2, the drain of the high-voltage PMOS transistor PDM7 is connected to the gate of the high-voltage NMOS transistor NDM1 and one end of the resistor R3, the source of the high-voltage NMOS transistor NDM1, the other end of the resistor R3, and the other end of the current source I2 are grounded.

[0009] Furthermore, the floating power supply generating circuit further includes a capacitor C1 , one end of the capacitor C1 is connected to the floating high voltage HVDD, and the other end of the capacitor C1 is connected to the floating low voltage HVSS.

[0010] Furthermore, the PMOS transistors PM3 to PM10 have the same width-to-length ratio.

[0011] Furthermore, it also includes a resistor R1 and a resistor R2, one end of the resistor R1 is connected to the input signal V1, and the other end of the resistor R1 is connected to the first input end of the floating high-voltage comparator circuit and the drain of the high-voltage PMOS tube PDM5, one end of the resistor R2 is connected to the input signal V2, and the other end of the resistor R2 is connected to the second input end of the floating high-voltage comparator circuit and the drain of the high-voltage PMOS tube PDM6.

[0012] A control method for a high-voltage power supply high-voltage selection circuit comprises the following steps: PMOS transistors PM3 to PM10, high-voltage PMOS transistor PDM7, high-voltage NMOS transistor NDM1, resistor R3 and current source I2 constitute a floating power supply generation circuit. PMOS transistors PM3 to PM10 have the same width-to-length ratio. , the current of current source I2 is I, then

[0013]

[0014] in, is the electron mobility of the transistor, is the gate oxide capacitance per unit area, VTH is the threshold voltage; The high-voltage NMOS transistor NDM1, resistor R3, and high-voltage PMOS transistor PDM7 form an enhanced source-follower structure to enhance the current absorption capability of the floating low-voltage HVSS node. When the floating low-voltage HVSS node needs to absorb a large current, the gate voltage of the high-voltage NMOS transistor NDM1 rises, turning on the high-voltage NMOS transistor NDM1, thereby assisting the floating low-voltage HVSS node in absorbing the current and preventing the floating low-voltage HVSS voltage from being raised. A high-voltage floating comparator circuit is composed of NMOS tubes NM1 to NM4, PMOS tubes PM1 to PM2, and high-voltage PMOS tubes PDM1 to PDM4. NMOS tubes NM1 to NM4 have the same width-to-length ratio, PMOS tubes PM1 to PM2 have the same width-to-length ratio, and high-voltage PMOS tubes PDM1 to PDM4 have the same width-to-length ratio. Current source I1 provides current source bias for high-voltage tube transistors PDM1 and PDM2. High-voltage PMOS tubes PDM1 to PDM4 have the same gate voltage. When the input signal V1 is greater than the input signal V2, the high-voltage PMOS tube PDM 3 increases, the current of the high-voltage PMOS tube PDM4 decreases, and the current of the high-voltage PMOS tube PDM3 is greater than the current of the high-voltage PMOS tube PDM4, the current of the NMOS tube NM2 is equal to the current of the high-voltage PMOS tube PDM3, and the NMOS tube NM3 copies the current of the NMOS tube NM2. Therefore, the current of the NMOS tube NM3 is greater than the current of the high-voltage PMOS tube PDM4, the gate voltage of the NMOS tube NM4 is pulled down, and the drain voltage of the NMOS tube NM4 is pulled up by the PMOS tube PM2, outputting logic 1. Similarly, when the input signal V1 is less than the input signal V2, the output is logic 0; Inverters INV1 to INV4 are inverters that float from the floating high voltage HVDD to the floating low voltage HVSS. After being driven by four inverters, the voltage of signal A equals the floating low voltage HVSS, and the voltage of signal B equals the floating high voltage HVDD. At this time, the high-voltage PMOS transistor PDM5 is turned on, and HVDD = V1, thus realizing the high-voltage selection function; When the input signals V1 and V2 are powered on, assuming V1>V2, the floating high voltage HVDD will rise along with the input signal V1, but with a body diode voltage drop. When the floating high voltage HVDD is established to the point where the subsequent basic modules can work, bias current is generated, the high-voltage floating comparator circuit can work normally, and the high-voltage PMOS tube PDM5 is turned on, reducing the body diode voltage drop to the power tube drive current multiplied by the internal resistance voltage drop, so that HVDD=V1.

[0015] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a high-voltage power supply selection circuit and a control method thereof, generates a floating voltage domain through a floating power supply generation circuit, designs a floating comparator in the voltage domain, and then compares the sizes of the two input voltages, and then selects the corresponding power tube to realize the high-voltage power supply selection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a high voltage power supply high selection circuit of the present invention. DETAILED DESCRIPTION

[0017] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0018] like Figure 1 As shown, a high-voltage power supply selection circuit of the present invention includes a floating power supply generation circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6. The floating power supply generation circuit generates a floating high voltage HVDD and a floating low voltage HVSS. The first input end of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS tube PDM5 and is connected to the input signal V1. The second input end of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS tube PDM6 and is connected to the input signal V2. The high-voltage power supply end of the high-voltage floating comparator circuit and the high-voltage PMOS tube PDM5 are connected to the input signal V1. The source and the source of the high-voltage PMOS tube PDM6D are connected to the floating high voltage HVDD, the low-voltage power supply terminal of the high-voltage floating comparator circuit is connected to the floating low voltage HVSS, the output terminal of the high-voltage floating comparator circuit is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4 and the gate of the high-voltage PMOS tube PDM5 to generate signal A, and the output terminal of the inverter INV4 is connected to the gate of the high-voltage PMOS tube PDM6 to generate signal B.

[0019] The high-voltage floating comparator circuit includes NMOS transistors NM1 to NM4, PMOS transistors PM1 to PM2, high-voltage PMOS transistors PDM1 to PDM4, and a current source I1. The drain of the high-voltage PMOS transistor PDM1 is connected to the drain of the high-voltage PMOS transistor PDM3 and serves as a first input terminal of the high-voltage floating comparator circuit. The drain of the high-voltage PMOS transistor PDM2 is connected to the drain of the high-voltage PMOS transistor PDM4 and serves as a second input terminal of the high-voltage floating comparator circuit. The gate of the high-voltage PMOS transistor PDM1 is connected to the gate of the high-voltage PMOS transistor PDM2, the gate of the high-voltage PMOS transistor PDM3, the gate of the high-voltage PMOS transistor PDM4, the source of the high-voltage PMOS transistor PDM1, the source of the high-voltage PMOS transistor PDM2, and one end of the current source I1. The body end of the high-voltage PMOS transistor PDM1 is connected to the body end of the high-voltage PMOS transistor PDM3, the body end of the high-voltage PMOS transistor PDM2, and the body end of the high-voltage PMOS transistor PDM4. The body end of the PMOS transistor PM1, the source of the PMOS transistor PM2, and the source of the PMOS transistor PM2 are connected and serve as the high-voltage power supply end of the high-voltage floating comparator circuit. The source of the high-voltage PMOS transistor PDM3 is connected to the drain of the NMOS transistor NM2, the gate of the NMOS transistor NM2, the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM3. The source of the high-voltage PMOS transistor PDM4 is connected to the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM4. The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and the drain of the NMOS transistor NM1. The drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM4 and serve as the output end of the high-voltage floating comparator circuit. The sources of the NMOS transistors NM1, NM2, NM3, and NM4 serve as the low-voltage power supply end of the high-voltage floating comparator circuit. The other end of the current source I1 is grounded.

[0020] The NMOS transistors NM1 to NM4 have the same width-to-length ratio, the PMOS transistors PM1 to PM2 have the same width-to-length ratio, and the high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio.

[0021] The floating power supply generating circuit includes PMOS transistors PM3 to PM10, a high-voltage PMOS transistor PDM7, a high-voltage NMOS transistor NDM1, a resistor R3 and a current source I2. The source of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM7 and generates a floating high voltage HVDD. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the source of the PMOS transistor PM4. The gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM7 and the source of the PMOS transistor PM8. The gate of the PMOS transistor PM4 is connected to the drain of the PMOS transistor PM4 and the source of the PMOS transistor PM5. The gate of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM8 and the source of the PMOS transistor PM9. The source of the high-voltage NMOS transistor PDM9 is connected to the source of the high-voltage NMOS transistor NDM1, the gate of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM5, the drain of the high-voltage NMOS transistor NDM1, and the source of the high-voltage PMOS transistor PDM7 to generate a floating low voltage HVSS, the gate of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM9 and the source of the PMOS transistor PM10, the gate of the PMOS transistor PM10 is connected to the gate of the high-voltage PMOS transistor PDM7, the drain of the PMOS transistor PM10, and one end of the current source I2, the drain of the high-voltage PMOS transistor PDM7 is connected to the gate of the high-voltage NMOS transistor NDM1 and one end of the resistor R3, the source of the high-voltage NMOS transistor NDM1, the other end of the resistor R3, and the other end of the current source I2 are grounded.

[0022] The floating power supply generating circuit further includes a capacitor C1 , one end of the capacitor C1 is connected to the floating high voltage HVDD, and the other end of the capacitor C1 is connected to the floating low voltage HVSS.

[0023] The PMOS transistors PM3 to PM10 have the same width-to-length ratio.

[0024] A high-voltage power supply selection circuit of the present invention further includes resistors R1 and R2. One end of resistor R1 is connected to input signal V1, and the other end is connected to a first input of a floating high-voltage comparator circuit and the drain of a high-voltage PMOS transistor PDM5. One end of resistor R2 is connected to input signal V2, and the other end is connected to a second input of the floating high-voltage comparator circuit and the drain of a high-voltage PMOS transistor PDM6. Resistors R1 and R2 are used to limit the instantaneous current when switching between V1 and V2.

[0025] A control method for a high-voltage power supply high-voltage selection circuit comprises the following steps: PMOS transistors PM3 to PM10, high-voltage PMOS transistor PDM7, high-voltage NMOS transistor NDM1, resistor R3 and current source I2 constitute a floating power supply generation circuit. PMOS transistors PM3 to PM10 have the same width-to-length ratio. , the current of current source I2 is I, then

[0026]

[0027] in, is the electron mobility of the transistor, is the gate oxide capacitance per unit area, and VTH is the threshold voltage. HVSS is designed to have a VGS voltage only three times lower than HVDD, approximately 4-5V. Therefore, HVDD to HVSS are floating low-voltage power supplies in the high-voltage domain. Comparator circuits can be designed using low-voltage transistors in the high-voltage domain, significantly saving area costs.

[0028] The high-voltage NMOS transistor NDM1, resistor R3, and high-voltage PMOS transistor PDM7 form an enhanced source follower structure to enhance the current absorption capability of the floating low-voltage HVSS. When the floating low-voltage HVSS node needs to absorb a large current, the gate voltage of the high-voltage NMOS transistor NDM1 rises, turning on the high-voltage NMOS transistor NDM1 to assist the floating low-voltage HVSS node in absorbing the current so that the floating low-voltage HVSS voltage is not raised.

[0029] The high-voltage floating comparator circuit composed of NMOS transistors NM1 to NM4, PMOS transistors PM1 to PM2, and high-voltage PMOS transistors PDM1 to PDM4 is used to compare the input voltage V1 and the input voltage V2 and output a logic 1 or logic 0 signal. NMOS transistors NM1 to NM4 have the same width-to-length ratio, PMOS transistors PM1 to PM2 have the same width-to-length ratio, and high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio. Current source I1 provides current source bias for high-voltage transistors PDM1 and PDM2. High-voltage PMOS transistors PDM1 to PDM4 have the same gate voltage. When input signal V1 is greater than input signal V2, the current of high-voltage PMOS transistor PDM3 increases, the current of high-voltage PMOS transistor PDM4 decreases, and the current of high-voltage PMOS transistor PDM3 is greater than the current of high-voltage PMOS transistor PDM4. The current of NMOS transistor NM2 is equal to the current of high-voltage PMOS transistor PDM3. NMOS transistor NM3 copies the current of NMOS transistor NM2, so the current of NMOS transistor NM3 is greater than the current of high-voltage PMOS transistor PDM4. The gate voltage of NMOS transistor NM4 is pulled down, and the drain voltage of NMOS transistor NM4 is pulled up by PMOS transistor PM2, outputting logic 1. NMOS transistor NM1 copies the current of NMOS transistor NM2. The current of PMOS transistor PM1 is equal to the current of NMOS transistor NM1. PMOS transistor PM2 copies the current of PMOS transistor PM1. Therefore, the current of PMOS transistor PM2 is equal to the current of high-voltage PMOS transistor PDM3. Similarly, when input signal V1 is less than input signal V2, the output is logic 0.

[0030] Inverters INV1 to INV4 are inverters that float from the floating high voltage HVDD to the floating low voltage HVSS. After being driven by four stages of inverters, the voltage of signal A equals the floating low voltage HVSS, and the voltage of signal B equals the floating high voltage HVDD. At this time, the high-voltage PMOS transistor PDM5 is turned on, and HVDD≈V1, thereby realizing the high-voltage selection function.

[0031] When the input signal V1 is much larger than the input signal V2, the entire current of the current source I1 flows through the high-voltage PMOS transistor PDM1. Therefore, the drain and source voltages of the high-voltage PMOS transistor PDM1 are both close to the high voltage of the input signal V1. The drain voltage of the high-voltage PMOS transistor PDM2 is low, and the gate voltage is high, which will not damage the high-voltage PMOS transistor PDM2.

[0032] Because this circuit generates power for all modules, its operating mode is crucial when current sources I1 and I2 are not generating bias current. Without bias current, the output of the floating high-voltage comparator circuit is uncertain, and neither is the switching state of high-voltage PMOS transistors PDM5 and PDM6. However, a body diode connection exists between the drain terminals of high-voltage PMOS transistors PDM5 and PDM6 and HVDD. When input signals V1 and V2 are powered on, assuming V1 > V2, the floating high-voltage HVDD rises with input signal V1, dropping only a body diode voltage drop. When the floating high-voltage HVDD reaches a level sufficient for the downstream basic modules to operate, bias current is generated, and the high-voltage floating comparator circuit functions normally. High-voltage PMOS transistor PDM5 turns on, reducing the body diode voltage drop to the voltage drop obtained by multiplying the power transistor's drive current by its internal resistance, achieving HVDD ≈ V1.

[0033] The present invention provides a high-voltage power supply selection circuit and a control method thereof. A floating voltage domain is generated by a floating power supply generation circuit. A floating comparator is designed in the voltage domain to compare the magnitudes of two input voltages and select the corresponding power tube to realize the high-voltage power supply selection circuit.

[0034] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A high voltage power supply selection circuit, characterized in that: The floating power supply generating circuit comprises a floating power supply generating circuit, a high-voltage floating comparator circuit, inverters INV1 to INV4, a high-voltage PMOS tube PDM5 and a high-voltage PMOS tube PDM6. The floating power supply generating circuit generates a floating high voltage HVDD and a floating low voltage HVSS. The first input end of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS tube PDM5 and is connected to the input signal V1. The second input end of the high-voltage floating comparator circuit is connected to the drain of the high-voltage PMOS tube PDM6 and is connected to the input signal V2. The high-voltage power supply end of the high-voltage floating comparator circuit, the source of the high-voltage PMOS tube PDM5 and the high-voltage PMOS The source of the transistor PDM6D is connected to the floating high voltage HVDD, the low voltage power supply terminal of the high voltage floating comparator circuit is connected to the floating low voltage HVSS, the output terminal of the high voltage floating comparator circuit is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the input terminal of the inverter INV2, the output terminal of the inverter INV2 is connected to the input terminal of the inverter INV3, the output terminal of the inverter INV3 is connected to the input terminal of the inverter INV4 and the gate of the high voltage PMOS transistor PDM5 to generate signal A, and the output terminal of the inverter INV4 is connected to the gate of the high voltage PMOS transistor PDM6 to generate signal B.

2. A high voltage power supply selection circuit according to claim 1, characterized in that: The high-voltage floating comparator circuit includes NMOS transistors NM1-NM4, PMOS transistors PM1-PM2, high-voltage PMOS transistors PDM1-PDM4 and a current source I1. The drain of the high-voltage PMOS transistor PDM1 is connected to the drain of the high-voltage PMOS transistor PDM3 and serves as a first input end of the high-voltage floating comparator circuit. The drain of the high-voltage PMOS transistor PDM2 is connected to the drain of the high-voltage PMOS transistor PDM4 and serves as a second input end of the high-voltage floating comparator circuit. The gate of the high-voltage PMOS transistor PDM1 is connected to the gate of the high-voltage PMOS transistor PDM2, the gate of the high-voltage PMOS transistor PDM3, the gate of the high-voltage PMOS transistor PDM4, the source of the high-voltage PMOS transistor PDM1, the source of the high-voltage PMOS transistor PDM2 and one end of the current source I1. The body end of the high-voltage PMOS transistor PDM1 is connected to the body end of the high-voltage PMOS transistor PDM3, the body end of the high-voltage PMOS transistor PDM2 and the body end of the high-voltage PMOS transistor PDM The body terminal of transistor 4, the source of the PMOS transistor PM1, and the source of the PMOS transistor PM2 are connected and serve as a high-voltage power supply terminal of the high-voltage floating comparator circuit. The source of the high-voltage PMOS transistor PDM3 is connected to the drain of the NMOS transistor NM2, the gate of the NMOS transistor NM2, the gate of the NMOS transistor NM1, and the gate of the NMOS transistor NM3. The source of the high-voltage PMOS transistor PDM4 is connected to the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM4. The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM1, and the drain of the NMOS transistor NM1. The drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM4 and serve as an output terminal of the high-voltage floating comparator circuit. The sources of the NMOS transistors NM1, NM2, NM3, and NM4 serve as a low-voltage power supply terminal of the high-voltage floating comparator circuit. The other end of the current source I1 is grounded.

3. The high voltage power supply selection circuit according to claim 2, characterized in that: The NMOS transistors NM1 to NM4 have the same width-to-length ratio, the PMOS transistors PM1 to PM2 have the same width-to-length ratio, and the high-voltage PMOS transistors PDM1 to PDM4 have the same width-to-length ratio.

4. The high voltage power supply selection circuit according to claim 1, characterized in that: The floating power supply generating circuit includes PMOS transistors PM3 to PM10, a high-voltage PMOS transistor PDM7, a high-voltage NMOS transistor NDM1, a resistor R3 and a current source I2. The source of the PMOS transistor PM3 is connected to the source of the PMOS transistor PM7 and generates a floating high voltage HVDD. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the source of the PMOS transistor PM4. The gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM7 and the source of the PMOS transistor PM8. The gate of the PMOS transistor PM4 is connected to the drain of the PMOS transistor PM4 and the source of the PMOS transistor PM5. The gate of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM8 and the source of the PMOS transistor PM9. The source of the high-voltage NMOS transistor M9 is connected, the gate of the PMOS transistor PM5 is connected to the drain of the PMOS transistor PM5, the drain of the high-voltage NMOS transistor NDM1, and the source of the high-voltage PMOS transistor PDM7 to generate a floating low voltage HVSS, the gate of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM9 and the source of the PMOS transistor PM10, the gate of the PMOS transistor PM10 is connected to the gate of the high-voltage PMOS transistor PDM7, the drain of the PMOS transistor PM10, and one end of the current source I2, the drain of the high-voltage PMOS transistor PDM7 is connected to the gate of the high-voltage NMOS transistor NDM1 and one end of the resistor R3, the source of the high-voltage NMOS transistor NDM1, the other end of the resistor R3, and the other end of the current source I2 are grounded.

5. The high voltage power supply selection circuit according to claim 4, characterized in that: The floating power supply generating circuit further includes a capacitor C1 , one end of the capacitor C1 is connected to the floating high voltage HVDD, and the other end of the capacitor C1 is connected to the floating low voltage HVSS.

6. The high voltage power supply selection circuit according to claim 4, characterized in that: The PMOS transistors PM3 to PM10 have the same width-to-length ratio.

7. The high voltage power supply selection circuit according to claim 1, characterized in that: It also includes a resistor R1 and a resistor R2, one end of the resistor R1 is connected to the input signal V1, and the other end of the resistor R1 is connected to the first input end of the floating high-voltage comparator circuit and the drain of the high-voltage PMOS transistor PDM5. One end of the resistor R2 is connected to the input signal V2, and the other end of the resistor R2 is connected to the second input end of the floating high-voltage comparator circuit and the drain of the high-voltage PMOS transistor PDM6.

8. A control method for a high voltage power supply high voltage selection circuit according to any one of claims 1 to 7, characterized in that The following steps are involved: PMOS transistors PM3 to PM10, high-voltage PMOS transistor PDM7, high-voltage NMOS transistor NDM1, resistor R3 and current source I2 constitute a floating power supply generation circuit. PMOS transistors PM3 to PM10 have the same width-to-length ratio. , the current of current source I2 is I, then in, is the electron mobility of the transistor, is the gate oxide capacitance per unit area, VTH is the threshold voltage; The high-voltage NMOS transistor NDM1, resistor R3, and high-voltage PMOS transistor PDM7 form an enhanced source-follower structure to enhance the current absorption capability of the floating low-voltage HVSS node. When the floating low-voltage HVSS node needs to absorb a large current, the gate voltage of the high-voltage NMOS transistor NDM1 rises, turning on the high-voltage NMOS transistor NDM1, thereby assisting the floating low-voltage HVSS node in absorbing the current and preventing the floating low-voltage HVSS voltage from being raised. A high-voltage floating comparator circuit is composed of NMOS tubes NM1 to NM4, PMOS tubes PM1 to PM2, and high-voltage PMOS tubes PDM1 to PDM4. NMOS tubes NM1 to NM4 have the same width-to-length ratio, PMOS tubes PM1 to PM2 have the same width-to-length ratio, and high-voltage PMOS tubes PDM1 to PDM4 have the same width-to-length ratio. Current source I1 provides current source bias for high-voltage tube transistors PDM1 and PDM2. High-voltage PMOS tubes PDM1 to PDM4 have the same gate voltage. When the input signal V1 is greater than the input signal V2, the high-voltage PMOS tube PDM 3 increases, the current of the high-voltage PMOS tube PDM4 decreases, and the current of the high-voltage PMOS tube PDM3 is greater than the current of the high-voltage PMOS tube PDM4, the current of the NMOS tube NM2 is equal to the current of the high-voltage PMOS tube PDM3, and the NMOS tube NM3 copies the current of the NMOS tube NM2. Therefore, the current of the NMOS tube NM3 is greater than the current of the high-voltage PMOS tube PDM4, the gate voltage of the NMOS tube NM4 is pulled down, and the drain voltage of the NMOS tube NM4 is pulled up by the PMOS tube PM2, outputting logic 1. Similarly, when the input signal V1 is less than the input signal V2, the output is logic 0; Inverters INV1 to INV4 are inverters that float from the floating high voltage HVDD to the floating low voltage HVSS. After being driven by four inverters, the voltage of signal A equals the floating low voltage HVSS, and the voltage of signal B equals the floating high voltage HVDD. At this time, the high-voltage PMOS transistor PDM5 is turned on, and HVDD = V1, thus realizing the high-voltage selection function; When the input signals V1 and V2 are powered on, assuming V1>V2, the floating high voltage HVDD will rise along with the input signal V1, but with a body diode voltage drop. When the floating high voltage HVDD is established to the point where the subsequent basic modules can work, bias current is generated, the high-voltage floating comparator circuit can work normally, and the high-voltage PMOS tube PDM5 is turned on, reducing the body diode voltage drop to the power tube drive current multiplied by the internal resistance voltage drop, so that HVDD=V1.

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