Fault positioning method and device, electronic equipment and storage medium
By automatically controlling the power-on and power-off processes of the VPX board through the power module, the running results of the instrumentation code are obtained for fault location, solving the problem of low fault location efficiency in the development and maintenance of VPX boards and achieving efficient and accurate fault detection.
Patent Information
- Application Number
- CN202410314748.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-19
- Publication Date
- 2025-09-30
AI Technical Summary
During the development and maintenance of VPX boards, repeated power-on and power-off tests are time-consuming and the power-on and power-off intervals cannot be precisely controlled, resulting in low fault location efficiency and poor accuracy.
The module under test is automatically powered on through the power module, and the running results of the plug-in code are obtained in the powered-on state. Based on the results, it is determined whether a fault has occurred. If a fault has occurred, it is located. Otherwise, the power is turned off to achieve automatic power-on and power-off control.
It improves the efficiency and accuracy of fault location, ensures the consistency of each test, and improves the maintainability and reliability of the tested module.
Smart Images
Figure CN120723547A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and more specifically, to a fault location method, device, electronic device, and storage medium. Background Art
[0002] During the development and maintenance of VPX cards, repeated power-on and power-off testing is required to troubleshoot occasional power-on and power-off failures. This requires engineers to perform numerous power-on and power-off tests, which can be extremely time-consuming and difficult to precisely control the power-on and power-off intervals. Therefore, improving the efficiency and accuracy of fault location is a pressing issue. Summary of the Invention
[0003] In view of this, embodiments of the present application provide a fault location method, device, electronic device, and storage medium to improve the above-mentioned problem.
[0004] According to a first aspect of an embodiment of the present application, a fault locating method is provided, the method comprising: powering on a connected module under test through a power supply module and running the module under test, wherein the module under test includes a plurality of plug-in codes; obtaining running results of the plurality of plug-in codes in the module under test while the module under test is in a powered-on state; if it is determined according to the running results that an operating fault occurs in the module under test, locating the fault of the module under test according to the running results; or if it is determined according to the running results that no operating fault occurs in the module under test, controlling the power supply module to power off the module under test.
[0005] According to a second aspect of an embodiment of the present application, a fault locating device is provided, the device comprising: a power-on processing module, configured to perform power-on processing on a connected module under test through a power supply module and to run the module under test, wherein the module under test includes a plurality of plug-in codes; an operation result acquisition module, configured to obtain the operation results of the plurality of plug-in codes in the module under test while the module under test is in a powered-on state; a fault locating module, configured to locate the fault of the module under test based on the operation result if it is determined that an operation fault has occurred in the module under test according to the operation result; or a power-off processing module, configured to control the power supply module to perform power-off processing on the module under test if it is determined that no operation fault has occurred in the module under test according to the operation result.
[0006] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a processor; and a memory, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the fault location method described above is implemented.
[0007] According to a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the fault location method described above is implemented.
[0008] According to a fifth aspect of an embodiment of the present application, a computer program product is provided, comprising a computer program, wherein the computer program implements the above-mentioned fault location method when executed by a processor.
[0009] In the solution of the present application, the module under test is run after the power module powers on the module under test, so that the running results of multiple plug-in codes of the module under test can be obtained while the module under test is in the power-on state, and then whether the module under test has a fault is determined based on the running results. If it is determined that the module under test has an operating fault, the fault of the module under test is located based on the running results; if it is determined that the module under test has no operating fault, the power module is controlled to power off the module under test, thereby realizing automatic power on and off processing of the module under test, and being able to locate the fault of the module under test while the module under test remains in the power-on state, thereby improving the efficiency of fault location. The present application can accurately control the power on and off time, ensure the consistency of each test, facilitate the fault location of the module under test, improve the maintainability and reliability of the module under test, and improve the accuracy of fault location by locating the fault through the running results.
[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can derive other drawings based on these drawings without inventive effort.
[0012] Figure 1 It is a flowchart of a fault location method according to an embodiment of the present application.
[0013] Figure 2 This is a block diagram of a controllable switching power supply according to an embodiment of the present application.
[0014] Figure 3 It is a flowchart of a fault location method according to another embodiment of the present application.
[0015] Figure 4It is a flowchart of a fault location method according to another embodiment of the present application.
[0016] Figure 5 It is a flowchart of a fault location method according to another embodiment of the present application.
[0017] Figure 6 4 is a flowchart illustrating specific steps of step 440 according to an embodiment of the present application.
[0018] Figure 7 This is a flowchart of a fault location method according to another embodiment of the present application.
[0019] Figure 8 This is a schematic diagram of the connection relationship between various devices for locating a fault of a module under test according to an embodiment of the present application.
[0020] Figure 9 This is a block diagram of a fault location device according to an embodiment of the present application.
[0021] Figure 10 It is a hardware structure diagram of an electronic device according to an embodiment of the present application.
[0022] The above-mentioned drawings have shown clear embodiments of the present invention, which will be described in more detail later. These drawings and textual descriptions are not intended to limit the scope of the present invention in any way, but to illustrate the concept of the present invention to computer technicians in this field through specific embodiments. DETAILED DESCRIPTION
[0023] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.
[0024] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0025] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.
[0026] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be executed in the order described. For example, some operations / steps may be further decomposed, while others may be combined or partially combined, so the actual execution order may vary depending on the actual situation.
[0027] See also Figure 1 , Figure 1 The fault location method provided by an embodiment of the present application is shown. In a specific embodiment, the fault location method can be applied to Figure 9 The fault location device 600 and the electronic device 700 equipped with the fault location device 600 are shown. Figure 10 ). The specific process of this embodiment will be described below. Of course, it can be understood that the method can be executed by a cloud server with computing processing capabilities. Figure 1 The process shown is described in detail. The fault location method may include the following steps:
[0028] Step 110 : Power on the connected module under test through the power module and run the module under test, wherein the module under test includes a plurality of plug-in codes.
[0029] As a method, the power supply module can be a controllable switching power supply, which is used to provide various required power supplies to the module under test. The enable pin of the power supply module is connected to the I / O pin of the module under test. The I / O pin of the module under test receives the voltage signal output by the power supply module and realizes the power-on and power-off processing of the module under test according to the received voltage signal. Optionally, the power supply module may include a pull-up resistor, a pull-down resistor, a delay circuit, a level matching circuit, a Boost / Buck circuit and a level conversion circuit, such as Figure 2As shown, the pull-up resistor and the pull-down resistor are connected through a dual-control switch, the other end of the pull-up resistor is connected to the level conversion circuit, the other end of the level conversion circuit is connected to the power supply, the pull-down resistor is connected to the enable pin of the switching power supply through the dual-control switch, and is connected in parallel with the delay circuit, the other end of the pull-down resistor is grounded, the other end of the delay circuit is connected to the level matching circuit, the other end of the level matching circuit is connected to the Boost / Buck circuit, and the other end of the Boost / Buck circuit outputs the voltage required by the module under test, and the output voltage is different in different situations. Among them, the delay circuit can accurately control the delay from the level conversion signal of the enable pin of the switching power supply to the switching signal of the Boost / Buck circuit, which facilitates the precise control of the time for automatic power on and off of the module under test. The delay circuit can adopt principles such as an RC delay circuit (a circuit composed of resistors and capacitors); the level matching circuit can convert the level of the enable pin of the switching power supply into the level of the switching signal of the Boost / Buck circuit. Optionally, it can be implemented by using an optocoupler, a buffer chip, etc.; the level conversion circuit converts the input 28V DC power supply into a level accepted by the enable pin of the switching power supply, thereby providing a pull-up level for the enable pin of the switching power supply. It can be implemented by using principles such as a resistor divider network; the pull-up resistor and the pull-down resistor are respectively used to adapt the use conditions of the switch enable pin to be pulled high or pulled low. For example, if the disabled level of the enable pin of the controllable switching power supply is high, and the enabled level of the enable pin of the controllable switching power supply is low or floating, the dual-control switch can be closed to the pull-down resistor and disconnected at the pull-up resistor, and the dual-control switch can be closed to the pull-down resistor (when the enable level is low) or disconnected (when the enable pin is floating to enable); if the disabled level of the enable pin of the controllable switching power supply is low, and the enabled level of the enable pin of the controllable switching power supply is high or floating, the dual-control switch can be disconnected from the pull-down resistor, and the dual-control switch can be closed to the pull-up resistor (when high level is enabled) or disconnected (when the enable pin is floating to enable).
[0030] Optionally, the module under test can be a VPX board under test. VPX, also known as VITA 46, is an ANSI standard (ANSI / VITA46.0-2019), which provides support for switching structures through new high-speed connectors for VMEbus-based systems. It has enhanced module standards, giving applications and platforms excellent performance. During the development and maintenance of VPX boards, it is often necessary to perform hundreds or even thousands of repeated power-on and power-off tests on the boards to determine the reliability of the boards or to reproduce and locate occasional faults. However, currently, engineers usually power on and off manually and observe the occurrence of faults. However, this method consumes a lot of time and energy and reduces work efficiency. Therefore, a power supply device can be connected to the module under test, and the power supply device can be used to control the automatic power on and off of the module under test to ensure the consistency of each test, facilitate fault location, and improve the maintainability and reliability of the board.
[0031] Optionally, after the power supply module receives the level control signal sent by the module under test, the module under test is powered on based on the level control signal. Optionally, the module under test may include a control code, which is used to control the level signal of the selected I / O control interface, and the I / O control interface directly or indirectly controls the level of the enable pin of the controllable switching power supply. For example, when the module under test is normally powered on for testing and the test is normal, the control code controls the I / O interface output to disable the enable pin of the power module, the power module output is disconnected, and the module under test is powered off; after the module under test is powered on, since the control code is no longer running, the I / O control interface stops outputting, the enable pin of the power supply device is disabled, the power module is switched from the disconnected state to the normal output state, and the module under test is powered on again.
[0032] Step 120 : while the module under test is in a powered-on state, obtaining the running results of the plurality of instrumentation codes in the module under test.
[0033] As a method, the module under test includes running code and stub code, wherein the stub code can be a code for testing the function of the module under test determined based on the structure of the function code in the module under test, and the stub code is located in the function code but does not affect the structure of the function code, that is, the function code can run normally. Furthermore, when the module under test is running, the stub code runs synchronously, so that the running results of multiple stub codes can be obtained when the module under test is running.
[0034] In order to ensure that the running results of multiple instrumentation codes in the module under test can be accurately obtained, the module under test can be powered on. If the module under test is powered off, the running results of the instrumentation codes cannot be accurately read.
[0035] Step 130: If it is determined according to the operation result that the module under test has an operation fault, the fault of the module under test is located according to the operation result.
[0036] As a method, the running results may include information about the instrumentation code that has been run. This information may be the serial number of the instrumentation code or the identifier corresponding to each instrumentation code. In this way, whether the module under test has failed can be determined based on the serial number of the instrumentation code or the identifier corresponding to each instrumentation code.
[0037] Optionally, if a fault occurs in the module under test, multiple plug-in codes in the module under test cannot be completely executed. Therefore, whether a fault occurs in the module under test can be determined by whether multiple plug-in codes in the execution result are completely executed. If the execution result indicates that multiple plug-in codes in the module under test have not been completed, it can be determined that an operation fault occurs in the module under test.
[0038] As a method, since multiple stub codes are inserted based on the structure of the running code in the module under test, the stub codes that have not been completed in the running results can be used to locate the faults in the module under test based on the location of the stub codes that have failed to run.
[0039] Step 140: If it is determined according to the operation result that the module under test has no operation failure, control the power supply module to power off the module under test.
[0040] As a method, if the running result indicates that multiple plug-in codes in the module under test have been completely executed, it can be determined that no fault has occurred in the module under test. Then, when it is determined that no running fault has occurred in the module under test, the power supply module is controlled to power off the module under test.
[0041] Optionally, when it is determined that the module under test has not failed, the module under test can send a disenabled level signal to the power module through the I / O control interface. After receiving the disenabled level signal, the enable pin of the power module controls the dual-control switch of the enable pin to disconnect, thereby disconnecting the power supply to the power module under test, and then completing the power-off processing of the module under test.
[0042] In an embodiment of the present application, the module under test is run after the power module performs power-on processing on the module under test, so that the running results of multiple plug-in codes of the module under test can be obtained while the module under test is in the power-on state, and then whether the module under test has a fault is determined based on the running results. If it is determined that the module under test has an operating fault, the fault of the module under test is located based on the running results; if it is determined that the module under test has no operating fault, the power module is controlled to power off the module under test, thereby realizing automatic power on and off processing of the module under test, and being able to locate the fault of the module under test while the module under test remains in the power-on state, thereby improving the efficiency of fault location. The present application can accurately control the power on and off time, ensure the consistency of each test, facilitate the fault location of the module under test, improve the maintainability and reliability of the module under test, and improve the accuracy of fault location by locating the fault through the running results.
[0043] See also Figure 3 , Figure 3 The fault location method provided by an embodiment of the present application is shown below. Figure 3 The process shown is described in detail. The fault location method may include the following steps:
[0044] Step 210 : Power on the connected module under test through the power module and run the module under test, wherein the module under test includes a plurality of plug-in codes.
[0045] Step 220 : while the module under test is in a powered-on state, obtaining the running results of the plurality of instrumentation codes in the module under test.
[0046] Step 230: If it is determined according to the running result that all the instrumented codes in the module under test have not been completely run, it is determined that an operation failure occurs in the module under test.
[0047] As a method, the running result may include the identification of the instrumentation code that has been completed or the identification of the instrumentation code that has not been completed. Then, the identification of the instrumentation code that has been completed in the running result can be compared with the identification of all instrumentation codes to determine whether all instrumentation codes in the module under test have been completed. If it is determined that there is instrumentation code that has not been completed in the module under test, it can be determined that an operation failure has occurred in the module under test.
[0048] Optionally, if it is determined that the running result includes an identifier of an unfinished execution of the instrumentation code, it can be determined that all the instrumentation codes in the module under test have not been completed, thereby determining that an operation failure has occurred in the module under test.
[0049] Step 240: If it is determined according to the running result that all the instrumented codes in the module under test have been run to completion, it is determined that no running failure occurs in the module under test.
[0050] As one approach, the identifier of the completed instrumented code in the run results can be compared with the identifiers of all instrumented codes. If the identifier of the completed instrumented code matches the identifiers of all instrumented codes, it can be determined that the module under test has not experienced an operational failure. Alternatively, if it is determined in the run results that there is no identifier indicating that the instrumented code has not been completed, it can be determined that the module under test has not experienced an operational failure.
[0051] Step 250: If it is determined according to the operation result that the module under test has an operation fault, the fault of the module under test is located according to the operation result.
[0052] Step 260: If it is determined according to the operation result that the module under test has no operation failure, control the power supply module to power off the module under test.
[0053] The specific step descriptions of steps 210 to 220 and steps 250 to 260 may refer to steps 110 to 140 and will not be repeated here.
[0054] In this embodiment, whether an operation failure occurs in the module under test is determined by determining whether all the insert codes in the module under test have been completed based on the operation results of multiple insert codes in the module under test. In this way, when it is determined that all the insert codes in the module under test have not been completed, it is determined that an operation failure occurs in the module under test, thereby improving the efficiency and accuracy of fault determination of the module under test, and further improving the fault location efficiency of the module under test.
[0055] See also Figure 4 , Figure 4 The fault location method provided by an embodiment of the present application is shown below. Figure 4 The process shown is described in detail. The fault location method may include the following steps:
[0056] Step 310: Power on the connected module under test through the power module and run the module under test, wherein the module under test includes a plurality of stub codes.
[0057] Step 320 : While the module under test is in a powered-on state, obtain the running results of the multiple instrumentation codes in the module under test.
[0058] Step 330: If it is determined that the target control signal of the module under test is not detected in the power module, it is determined that the module under test has failed, wherein the target control signal is a signal instructing to power off the module under test.
[0059] As one approach, when the module under test does not experience an operational failure, the module under test generates a target control signal and sends the target control signal to the power module, thereby causing the power module to power off the module under test according to the target control signal. Therefore, when the target control signal of the module under test is not detected, it can be determined that the module under test is always in a powered-on state and cannot be powered off, and therefore, it can be determined that an operational failure has occurred in the module under test. Optionally, the target control signal can be a disabled level signal sent by an I / O interface of the module under test.
[0060] Step 340: If it is determined that the target control signal is detected in the power module, it is determined that no operation failure occurs in the module under test.
[0061] As a method, when the module under test has no operational failure, the module under test generates a target control signal and sends the target control signal to the power supply module, so that the power supply module powers off the module under test according to the target control signal. Therefore, after detecting the target control signal, it can be determined that the module under test has no operational failure.
[0062] Step 350: If it is determined according to the operation result that the module under test has an operation fault, the fault of the module under test is located according to the operation result.
[0063] Step 360: If it is determined according to the operation result that the module under test has no operation failure, control the power supply module to power off the module under test.
[0064] The specific step descriptions of steps 310 to 320 and steps 350 to 360 may refer to steps 110 to 140 and will not be repeated here.
[0065] In this embodiment, whether a fault occurs in the module under test is determined by detecting a signal in the power supply module for instructing to power off the module under test, thereby avoiding errors in fault determination of the module under test, improving the accuracy of fault determination of the module under test, and further improving the efficiency of fault locating the module under test.
[0066] See also Figure 5 , Figure 5 The fault location method provided by an embodiment of the present application is shown below. Figure 5 The process shown is described in detail. The fault location method may include the following steps:
[0067] Step 410: Power on the connected module under test through the power module and run the module under test, wherein the module under test includes a plurality of stub codes.
[0068] Step 420 : while the module under test is in a powered-on state, obtain the running results of the plurality of instrumentation codes in the module under test.
[0069] The specific description of steps 410 to 420 can be found in steps 110 to 120 and will not be repeated here.
[0070] Step 430 : According to the running result, determine the running completed plug-in code from the plurality of plug-in codes as the reference plug-in code.
[0071] As a way, in order to locate the fault of the module under test based on the running results, the instrumented code that has been run in the running results can be used as the reference instrumented code, and then the last completed code can be determined based on the reference instrumented code to locate the fault.
[0072] Optionally, the completed instrumentation code may be determined based on a flag of the completed instrumentation code in the running result and identifiers corresponding to the plurality of instrumentation codes.
[0073] Step 440 : determining the reference instrumentation code that has been executed last in the reference instrumentation code as the target instrumentation code, and locating the fault of the module under test according to the target instrumentation code.
[0074] As a way, when a failure occurs in the operation of the module under test, the instrumentation code will run until the failure occurs in the module under test. That is, when a failure occurs in the operation of the module under test, the instrumentation code will run to the instrumentation code before the functional code line where the failure occurs in the module under test. Then, the reference instrumentation code that is finally completed can be determined as the target instrumentation code.
[0075] Optionally, each completed reference instrumentation code in the run results includes a timestamp corresponding to the completion of the execution of each reference instrumentation code, and the target instrumentation code can be determined based on this timestamp. Optionally, multiple instrumentation codes in the module under test carry their respective corresponding sequence numbers, and the target instrumentation code can be determined based on the corresponding sequence numbers in the completed reference code in the run results.
[0076] Optionally, after determining the target instrumentation code, the position of the function code following the target instrumentation code may be determined as the fault position. Alternatively, the position of the running code corresponding to the instrumentation code following the target instrumentation code may be determined as the fault position.
[0077] In some embodiments, the module under test also includes multiple function codes, such as Figure 6 As shown, step 440 includes:
[0078] Step 441 : Determine a function code corresponding to the target instrumentation code from the multiple function codes as a target function code, wherein the target function code is a function code located after the target instrumentation code.
[0079] As a way, the function code can be the code corresponding to the function in the module under test, and the stub code can be the code inserted based on the structure of the function code, and the stub code does not affect the normal operation of the function code. Furthermore, after determining the target stub code, the target function code located after the target stub code can be determined in the function code.
[0080] Step 442: Determine the location of the target running code as the fault location, and determine the fault information of the module under test based on the target running code.
[0081] As a way, since the target instrumentation code is the last instrumentation code to be run, it can be determined that there is a problem with the target function code located after the target instrumentation code, which causes the target function code and subsequent instrumentation code and function code to be unable to run. In this way, the location of the target function code can be determined as the fault location.
[0082] Optionally, after determining the target function code, the structure of the target function code and the corresponding function can be analyzed to determine the fault information of the module under test, wherein the fault information may include the fault type and the fault cause.
[0083] In some embodiments, step 442 includes: determining a target function having a fault in the module under test according to the target function code; and determining a fault type and a fault cause of the module under test according to the target function.
[0084] As a way, the target function code corresponds to its own function in the module under test. Therefore, after determining the target function code, the target function with fault in the module under test can be determined based on the target function code. In this way, after determining the target function, the fault cause and fault type of the module under test can be determined based on the possible fault cause of the target function and the structure of the target function code.
[0085] In an embodiment of the present application, a reference instrumentation code that has been completed can be determined among multiple instrumentation codes based on the running results, and then the last instrumentation code that has been completed in the reference instrumentation code can be determined as the target instrumentation code. Then, the function code located after the target instrumentation code can be determined as the target function code, and the position of the target function code can be determined as the fault position, thereby improving the accuracy of fault location.
[0086] See also Figure 7 , Figure 7 The fault location method provided by an embodiment of the present application is shown below. Figure 7 The process shown is described in detail. The fault location method may include the following steps:
[0087] Step 510: Power on the connected module under test through the power supply module and operate the module under test.
[0088] The specific step description of step 510 can refer to step 110 and will not be repeated here.
[0089] Step 520: If it is detected that the time duration for which the module under test remains in the powered-on state reaches a time duration threshold, it is determined that the module under test has failed.
[0090] As a method, when there is no operational fault in the module under test, the module under test will send a target control signal to the power supply module, so that the power supply module controls the module under test to power off according to the target control signal. Furthermore, if it is detected that the module under test remains in the powered-on state for a long time, that is, when the time length for which the module under test remains in the powered-on state reaches a time length threshold, it can be determined that a fault has occurred in the module under test.
[0091] Step 530: Acquire the target log of the module under test through the target interface of the module under test.
[0092] As a way to comprehensively analyze the fault of the module under test, when it is determined that the module under test has failed, the target log of the module under test can be obtained through the debugging JTAG interface or other debugging interface. Optionally, the target log can be the functional code execution log of the module under test.
[0093] Step 540: parse the target log to determine the fault information of the module under test.
[0094] As a method, in order to determine the fault location, fault type, and fault cause of the module under test, the target log can be parsed to determine the fault information. Optionally, the target log can be parsed by analyzing the operation status of each independent function code in the function code operation log to determine the fault information of the module under test.
[0095] In this embodiment, whether the module under test has failed is determined by determining whether the time period for which the module under test remains in the power-on state reaches a time threshold. Therefore, when it is determined that the module under test has failed, the target log can be obtained through the target interface, and the fault information of the module under test can be determined by parsing the target log, thereby improving the efficiency of fault locating the module under test.
[0096] Figure 8 FIG. 1 is a diagram showing the connection relationship between various devices for locating a fault of a module under test according to an embodiment of the present application, such as Figure 8 As shown, the onboard power supply supplies power to power module 2 via main switch 1. Power module 2 converts the 28V DC input from the onboard power supply into the Vs1, Vs2, Vs3, 3.3V_AUX, + / -12V_AUX, and other power supplies required by module under test 5. After module under test 5 is powered on, it begins running software. When module under test 5 is properly powered on, tested, and tested, and the test is normal, the control code in module under test 5 controls the I / O interface to output a level that disables the enable pin of power module 2. Main switch 1 is opened, disconnecting the output and powering off module under test 5. After module under test 5 is powered off, since the control code in module under test 5 is no longer running, the I / O interface stops outputting the level that disables the enable pin of power module 2. Main switch 1 is closed, and the power supply state of the onboard power supply switches from the disconnected state to the normal output state. Module under test 5 is then powered on again and restarts self-testing. When the fault in the module under test 5 reappears, the driver, PLD logic, or application software of the module under test 5 will not execute the control code, but the power module 2 will maintain normal output and the module under test 5 will not be powered off. Connecting a computer to the debug Jtag interface 3 or other debug interface 6 allows the engineer to accurately locate the fault in the module under test 5 by viewing the execution results of the instrumented code or the printed log, thus facilitating troubleshooting. The backplane 7 is a PCB that electrically interconnects the aforementioned components.
[0097] Figure 9 FIG. 1 is a block diagram of a fault location device according to an embodiment of the present application. Figure 9 As shown, the fault location device 600 includes: a power-on processing module 610 , an operation result acquisition module 620 , a fault location module 630 and a power-off processing module 640 .
[0098] The power-on processing module 610 is used to power on the connected module under test through the power supply module and run the module under test, wherein the module under test includes multiple plug-in codes; the operation result acquisition module 620 is used to obtain the operation results of the multiple plug-in codes in the module under test while the module under test is in the power-on state; the fault location module 630 is used to locate the fault of the module under test based on the operation result if it is determined that the module under test has an operation fault according to the operation result; or the power-off processing module 640 is used to control the power supply module to power off the module under test if it is determined that the module under test has not an operation fault according to the operation result.
[0099] In some embodiments, the fault locating device 600 further includes: a first determination module for determining that an operation failure has occurred in the module under test if it is determined based on the operation result that all the plug-in codes in the module under test have not been completed; or a second determination module for determining that no operation failure has occurred in the module under test if it is determined based on the operation result that all the plug-in codes in the module under test have been completed.
[0100] In some embodiments, the fault locating device 600 further includes: a third determination module, configured to determine that a fault has occurred in the module under test if it is determined that the target control signal of the module under test is not detected in the power supply module, wherein the target control signal is a signal instructing to power off the module under test; and a fourth determination module, configured to determine that no operational fault has occurred in the module under test if it is determined that the target control signal is detected in the power supply module.
[0101] In some embodiments, the fault location module 630 includes: a reference instrumentation code determination submodule, used to determine the instrumentation code that has been completed in the multiple instrumentation codes as the reference instrumentation code based on the running results; a fault location submodule, used to determine the reference instrumentation code that has been completed last in the reference instrumentation codes as the target instrumentation code, and locate the fault of the module under test based on the target instrumentation code.
[0102] In some embodiments, the module under test also includes multiple function codes, and the fault location submodule includes: a target function code determination unit, used to determine a function code corresponding to the target insertion code from the multiple function codes as a target function code, wherein the target function code is a function code located after the target insertion code; a fault information determination unit, used to determine the location of the target running code as the fault location, and determine the fault information of the module under test based on the target running code.
[0103] In some embodiments, the fault information determination unit includes: a target function determination subunit, used to determine the target function with a fault in the module under test based on the target function code; and a fault information determination subunit, used to determine the fault type and fault cause of the module under test based on the target function.
[0104] In some embodiments, the fault locating device 600 further includes: a fault determination module, for determining that a fault has occurred in the module under test if it is detected that the time duration for which the module under test remains powered on reaches a time duration threshold; a target log acquisition module, for acquiring the target log of the module under test through the target interface of the module under test; and a fault information determination module, for parsing the target log to determine the fault information of the module under test.
[0105] According to one aspect of the embodiments of the present application, an electronic device is also provided, such as Figure 10 As shown, the vehicle 700 includes a processor 710 and one or more memories 720. The one or more memories 720 are used to store program instructions executed by the processor 710. When the processor 710 executes the program instructions, the above-mentioned fault location method is implemented.
[0106] Furthermore, the processor 710 may include one or more processing cores. The processor 710 runs or executes instructions, programs, code sets or instruction sets stored in the memory 720, and calls data stored in the memory 720. Optionally, the processor 710 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 710 can integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to handle wireless communications. It is understandable that the above-mentioned modem may not be integrated into the processor and may be implemented separately through a communication chip.
[0107] According to one aspect of the present application, a computer-readable storage medium is provided. The computer-readable storage medium may be included in the electronic device described in the above embodiments, or may exist independently without being incorporated into the electronic device. The computer-readable storage medium carries computer-readable instructions. When the computer-readable storage instructions are executed by a processor, the method of any of the above embodiments is implemented.
[0108] It should be noted that the computer-readable medium shown in the embodiments of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, or any suitable combination thereof.
[0109] The units involved in the embodiments described in this application may be implemented by software or hardware, and the units described may also be set in a processor. In some cases, the names of these units do not constitute limitations on the units themselves.
[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. Among them, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, and the above-mentioned module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0111] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed herein.
Claims
1. A fault location method, characterized in that: The method comprises: Powering on the connected module under test through the power module and running the module under test, wherein the module under test includes a plurality of stub codes; While the module under test is in a powered-on state, obtaining the running results of the plurality of instrumentation codes in the module under test; If it is determined according to the operation result that the module under test has an operation fault, locating the fault of the module under test according to the operation result; or If it is determined according to the operation result that the module under test has no operation failure, the power supply module is controlled to power off the module under test.
2. The method according to claim 1, characterized in that When the module under test is in a powered-on state, after obtaining the running results of the plurality of plug-in codes in the module under test, the method further includes: If it is determined according to the running result that all the plug-in codes in the module under test have not been completely run, it is determined that an operation failure occurs in the module under test; or If it is determined according to the running result that all the plug-in codes in the module under test have been run to completion, it is determined that no running failure occurs in the module under test.
3. The method according to claim 1, characterized in that While the module under test is in a powered-on state, after obtaining the execution results of the plurality of instrumentation codes in the module under test, the method further includes: If it is determined that the target control signal of the module under test is not detected in the power module, it is determined that the module under test has failed, wherein the target control signal is a signal instructing to power off the module under test; If it is determined that the target control signal is detected in the power module, it is determined that no operation failure occurs in the module under test.
4. The method according to claim 1, wherein The performing fault locating on the module under test according to the operation result includes: According to the running result, determining the running completed plug-in code among the plurality of plug-in codes as the reference plug-in code; The reference instrumentation code that has been executed last is determined in the reference instrumentation code as the target instrumentation code, and fault location is performed on the module under test according to the target instrumentation code.
5. The method according to claim 4, characterized in that The module under test further includes a plurality of function codes, and locating a fault of the module under test according to the target instrumentation code includes: Determining a function code corresponding to the target instrumentation code from the multiple function codes as a target function code, wherein the target function code is a function code located after the target instrumentation code; The position of the target running code is determined as the fault position, and the fault information of the module under test is determined according to the target running code.
6. The method according to claim 5, characterized in that Determining the fault information of the module under test according to the target function code includes: Determining a target function having a fault in the module under test according to the target function code; The fault type and fault cause of the module under test are determined according to the target function.
7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: If it is detected that the time length for which the module under test remains in the powered-on state reaches a time length threshold, it is determined that the module under test has failed; Obtaining the target log of the module under test through the target interface of the module under test; The target log is parsed to determine the fault information of the module under test.
8. A fault location device, characterized in that: The device comprises: a power-on processing module, configured to power on the connected module under test through the power supply module and run the module under test, wherein the module under test includes a plurality of plug-in codes; An operation result acquisition module, configured to acquire the operation results of the plurality of instrumentation codes in the module under test while the module under test is in a powered-on state; a fault locating module, configured to locate the fault of the module under test according to the operation result if it is determined that the module under test has an operation fault according to the operation result; or The power-off processing module is configured to control the power supply module to power off the module under test if it is determined according to the operation result that no operation failure has occurred in the module under test.
9. An electronic device, characterized in that: The electronic device comprises: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method according to any one of claims 1 to 7 is implemented.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, which can be called by a processor to execute the method according to any one of claims 1 to 7.
11. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.