Testing link abnormity positioning device, system, method, equipment, medium and program

Abstract

The invention discloses a test link abnormity positioning device, system, method, equipment, medium and program, and relates to the technical field of computers, and the method comprises the steps that when a test link is abnormal, a processing component writes a first enabling bit into a first register of each node device, each node device responds to the first enabling bit to enter a low-power-consumption mode, and the first enabling bit enters a low-power-consumption mode; according to the embodiment of the invention, each node device triggers link retraining in the low-power-consumption mode to expose the unstable position of the test link in the low-power-consumption conversion process, and determines the abnormal position of the link according to the flag bit state of the second register, so that the troubleshooting efficiency and the abnormality positioning precision are improved, and the time and the labor cost are saved. Therefore, the problems of low working efficiency and high time and labor cost caused by the fact that the abnormal problem cannot be effectively solved in time when the abnormal position of the link is checked manually in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a test link anomaly locating device, system, method, equipment, medium and program. Background Art

[0002] Among the servers currently produced by factories, a large number of them are equipped with GPU (Graphics Processing Unit) components, so stress testing of the GPU is also a very important part before shipment.

[0003] During GPU stress testing at the factory, multiple error reports may be encountered. These can be broadly divided into two categories: one is a single GPU failure, which can generally be accurately pinpointed to the GPU in the error log. The other is anomalies related to the GPU link, which usually cannot be directly identified in the error log and requires production line staff to investigate. Because GPU links are generally complex, there are many locations where abnormalities may occur, and many abnormal situations may occur, such as speed reduction, bandwidth fluctuations, and ECC (Error Checking and Correcting) errors. Therefore, the staff's experience is required to be very high. This work is very energy-consuming and time-consuming, and it is difficult to quickly locate the abnormal location, which will cause production line congestion and fail to effectively and timely resolve the abnormal problems, which has a significant impact on production line capacity. Summary of the Invention

[0004] The present application provides a test link abnormality positioning device, system, method, equipment, medium and program to at least solve the problems of related technologies such as manual inspection of link abnormality locations failing to promptly and effectively solve abnormal problems, resulting in low work efficiency, high time and labor costs, etc.

[0005] The present application provides a device for locating anomalies in a test link, wherein the test link is composed of a graphics processor and multiple node devices, and the graphics processor and the multiple node devices communicate with each other, wherein the device includes: a first register and a second register of each node device; a processing component, configured to write a first enable bit to the first register of each node device when the test link is abnormal, and each node device enters a low power consumption mode in response to the first enable bit; the node device sends a first training sequence to the graphics processor in the low power consumption mode, and the graphics processor returns a first response sequence. When communication between the node device and the graphics processor is normal, the first response sequence is written to the second register; the processing component reads the second register of each node device, and locates the abnormal position of the test link according to the reading result of the second register.

[0006] The present application provides a test link anomaly locating system, comprising: a graphics processor and multiple node devices, wherein the graphics processor and multiple node devices constitute a test link, the test link utilizes the processing component to perform stress testing, and the graphics processor and multiple node devices communicate with each other; a test link anomaly locating device as described in the above embodiment, used to locate the abnormal position of the test link.

[0007] The present application also provides a test link abnormality locating method, which is applied to the processing component of the test link abnormality locating device described in the above embodiment, wherein the method includes the following steps: when the test link is abnormal, writing a first enable bit to the first register of each node device, each node device enters a low power consumption mode in response to the first enable bit, the node device sends a first training sequence to the graphics processor in the low power consumption mode, the graphics processor returns a first response sequence, and when the communication between the node device and the graphics processor is normal, the first response sequence is written to the second register; reading the second register of each node device, and locating the abnormal position of the test link according to the reading result of the second register.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned test link anomaly locating methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned test link abnormality locating methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of the test link abnormality locating method as described above when executed by a processor.

[0011] When the test link is abnormal, the processing component of the present application writes the first enable bit to the first register of each node device, and each node device enters the low power mode in response to the first enable bit to expose the unstable position of the test link during the low power conversion process. Each node device triggers link retraining in the low power mode, and determines the abnormal position of the link according to the flag bit state of the second register. If the above embodiments are unable to detect the abnormal position of the link, the node device is controlled to insert an erroneous cyclic redundancy check value into the data link layer packet sent next time, so as to locate the abnormal position according to the flag bit state of the fourth register, thereby improving the troubleshooting efficiency and abnormality positioning accuracy, saving time and labor costs. Thus, the problem that the manual troubleshooting of the abnormal position of the link in the related technology cannot effectively solve the abnormal problem in a timely manner, resulting in low work efficiency and high time and labor costs is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A block diagram of a test link anomaly locating device provided in an embodiment of the present application; Figure 2 A block diagram of a test link anomaly locating system provided in an embodiment of the present application; Figure 3 A framework diagram of a test link anomaly locating system provided in an embodiment of the present application; Figure 4 Flowchart of the test link anomaly locating method provided in an embodiment of the present application; Figure 5 This is a schematic diagram of the overall logic of the operation of a test link anomaly locating system provided in an embodiment of the present application; Figure 6 A schematic diagram of the overall architecture of the test link exception handling provided in an embodiment of the present application; Figure 7 A schematic diagram of locating an abnormal position of a test link provided in one embodiment of the present application.

[0014] Description of the drawings: A test link anomaly locating device 10 includes a first register 110 , a second register 120 , a processing component 130 , a node device 140 , a graphics processor 150 , and a test link anomaly locating system 20 . DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0016] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0017] After the GPU stress test, a corresponding test log will be generated. The test log contains a lot of error information. The test link anomaly positioning system of this application only parses GPU-related link anomalies. Therefore, it is necessary to extract valid keywords from different log formats to determine whether the log can clearly point to the GPU anomaly.

[0018] When the error information is determined to be a GPU-related exception, some errors will automatically point to a GPU problem or have a clear exception direction. In this case, there is no need to analyze the test link. In addition, if the error direction is unclear, it is necessary to analyze the test link to determine the specific location of the exception.

[0019] The traditional method of analyzing hardware links by viewing commands for all PCI (Peripheral Component Interconnect) buses and connected device information no longer meets the needs and cannot identify deeper issues.

[0020] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0021] An embodiment of the present application provides a device for locating abnormalities in a test link.

[0022] Specifically, Figure 1A block diagram of a test link anomaly locating device provided in an embodiment of the present application.

[0023] like Figure 1 As shown, the test link consists of a graphics processor 150 and multiple node devices 140. The test link uses a processing component to perform stress testing, and the graphics processor and multiple node devices communicate with each other. The test link abnormality locating device 10 includes: a first register 110, a second register 120, a processing component 130, a node device 140 and a graphics processor 150.

[0024] Among them, each node device 140 includes a first register 110 and a second register 120, and the processing component 130 is used to write a first enable bit to the first register 110 of each node device 140 when the test link is abnormal. Each node device 140 enters a low power consumption mode in response to the first enable bit. The node device 140 sends a first training sequence to the graphics processor 150 in the low power consumption mode, and the graphics processor 150 returns a first response sequence. When the communication between the node device 140 and the graphics processor 150 is normal, the first response sequence is written to the second register 120; the processing component 130 reads the second register 120 of each node device 140 and locates the abnormal position of the test link according to the reading result of the second register 120.

[0025] It can be understood that the embodiment of the present application can write the first enable bit to the first register of the node device according to the processing component, force the node device to enter a low-power state, and trigger link retraining in the low-power state. Since the low-power conversion process is more sensitive to signal integrity, it can effectively expose hidden link instability problems caused by poor contact, electromagnetic interference, circuit routing defects, etc., and improve the fault detection rate. The state feedback based on the interaction of the training sequence can accurately locate the abnormal position, enhance the depth and reliability of abnormality detection, and reduce dependence on the experience of technical personnel.

[0026] It should be noted that the processing component of the present application can be a BMC (Baseboard Management Controller), the first register is an LCR (Link Control Register), which is located in the configuration space of the node device, and the second register is a Link Status register. The node device can be a PCIe (Peripheral Component Interconnect Express) device, without specific limitation.

[0027] In a low-power state, the node device sends a first training sequence to the graphics processor to negotiate link parameters. The graphics processor returns a first response sequence, indicating that the link training is complete and the parameters are confirmed. If the communication is normal, the success status will be written into the second register of the node device. The processing component reads the status of the second register of each node device. If the success flag is not written into the second register of any node device, it means that the link training between the node device and the graphics processor has failed. The abnormal location can be determined by combining the flag bit of the second register.

[0028] Specifically, the processing component writes the first enable bit to each node device's LCR. An LCR is a register used to control and manage various parameters and states of a network connection or communication link. In computer systems and network devices, LCRs are typically used to set and adjust parameters such as the link's operating mode, speed, and flow control to ensure stable and efficient network communications. The first enable bit is the (Delay (Extended Bit 4)) bit in the register, which indicates the link retraining function in the link control register of the test link.

[0029] When the test link is initialized or encounters communication problems, it is necessary to negotiate the following parameters by exchanging the first training sequence and the first response sequence: link speed, link width, equalization parameters, and polarity reversal. This negotiation process is called link training. Link retraining between the node device and the graphics processor is used to detect link stability and observe whether the link can successfully complete the training, thereby determining whether the test link has physical layer instability issues.

[0030] In the embodiment of the present application, a plurality of physical slots are provided on the test link, and a node device 140 is provided on each physical slot.

[0031] It can be understood that the embodiment of the present application can be equipped with multiple physical slots on the test link, and each physical slot is equipped with a node device, so that each slot corresponds to an independent node device. When a link abnormality occurs, the corresponding physical slot can be accurately located according to the abnormal position to facilitate rapid troubleshooting, thereby improving the efficiency of fault identification.

[0032] In the embodiment of the present application, the test link abnormality locating device 10 further includes: a third register and a fourth register.

[0033] Among them, each node device includes a third register and a fourth register; the processing component 130 is used to write a third enable bit to the third register of each node device 140 when the test link is abnormal, and each node device 140 responds to the third enable bit to control the node device 140 to insert an erroneous cyclic redundancy check value into the next data link layer packet sent; the processing component 130 reads the fourth register of each node device 140 and locates the abnormal position of the test link according to the reading result.

[0034] It can be understood that the embodiment of the present application can actively inject CRC (Cyclic Redundancy Check) errors by writing an enable bit to the third register, locate the abnormal position of the test link according to the fourth register of the node device, implement active disturbance diagnosis, and improve the detection rate of hidden faults.

[0035] It should be noted that the third register is used to receive the third enable bit written by the processing component to trigger the node device to actively write an erroneous CRC value in the next data link layer packet sent to achieve "error injection". The fourth register can be understood as a status register, which is used to record the link's response to the error. If the error is corrected, the corrected error flag is written, which proves that the tested link is normal. If the error is not corrected, the uncorrectable error flag is written, which proves that the tested link is unstable.

[0036] Specifically, if the test link retraining cannot confirm the abnormal location and abnormal information, a test of simulated abnormal disturbance will be performed. The processing component will inject CRC error information into the sent data packet by writing to bit 0 of the EIR (Error Injection Register). The link stability is determined by judging whether the link can correct the CRC error. If it can be corrected, the CE (Correctable Error) count is recorded and the AER_CE_STATUS register is read to locate the abnormal location information. If it cannot be corrected, a UCE (Uncorrectable Error) interrupt will be triggered, and the abnormal location information will be located by reading the AER_UE_STATUS register. The AER_CE_STATUS register is an error status register used to report the status of correctable errors, and the AER_UE_STATUS register is used to report the status of uncorrectable errors.

[0037] In the embodiment of the present application, the first register 110 , the second register 120 , the third register and the fourth register are all set in the configuration space of the node device 140 .

[0038] It can be understood that in the embodiment of the present application, the first register, the second register, the third register and the fourth register are all set in the configuration space of the node device to achieve unified control and diagnosis.

[0039] Specifically, the node device configuration space is a standardized register area built into each node device, which is used to store device identity information, capability structure, and control and status registers without the need to load drivers or involve the operating system.

[0040] According to the test link abnormality locating device of the embodiment of the present application, when the test link is abnormal, the processing component writes the first enable bit to the first register of each node device, and each node device enters the low power mode in response to the first enable bit to expose the unstable position of the test link during the low power conversion process. Each node device triggers link retraining in the low power mode and determines the abnormal position of the link according to the flag bit status of the second register, thereby improving the troubleshooting efficiency and abnormality locating accuracy, saving time and labor costs. Thus, it solves the problem that the manual troubleshooting of the abnormal position of the link in the related technology cannot solve the abnormal problem in a timely and effective manner, resulting in low work efficiency and high time and labor costs.

[0041] Figure 2 A block diagram of a test link anomaly locating system provided in an embodiment of the present application.

[0042] like Figure 2 As shown, the test link anomaly locating system 20 includes: a graphics processor 150 , a plurality of node devices 140 and a test link anomaly locating device 10 .

[0043] The test link utilizes the processing component 130 to perform stress testing, and the graphics processor 150 communicates with multiple node devices 140; the test link abnormality locating device 10 is used to locate the abnormal position of the test link.

[0044] It can be understood that the embodiments of the present application can achieve automatic and high-precision identification of abnormal locations in the PCIe test link through the collaborative work of a graphics processor, multiple node devices and a test link abnormality locating device.

[0045] Specifically, if Figure 3 As shown, the test link anomaly locating system of the present application also includes a test link traversal module, an anomaly feature extraction module and a slot locating module. During the process of link anomaly analysis, these three modules are also executed in sequence to locate the anomaly position.

[0046] The test link traversal module proactively probes and scans the entire test link to identify potentially abnormal physical nodes. This involves activating low-power mode, triggering link retraining, and performing error injection testing. Activating low-power mode involves writing the first enable bit (Extended bit (Bit 4)) to the first register of each node device, which can more easily expose problems such as poor signal integrity and poor contact during power switching. Triggering link retraining involves writing the second enable bit (Retrain Link bit (Bit 5)) to the first register of each node device via the processing component, forcing link renegotiation to observe successful training. Error injection testing involves proactively injecting CRC errors into data packets if regular retraining reveals no issues, testing the link's error correction capabilities. The module traverses all node devices and reports which devices experience failures, speed reductions, or bandwidth reductions during retraining or error injection.

[0047] The anomaly feature extraction module extracts identifiable anomaly types and feature values ​​from the raw data obtained by the traversal module. It reads key status registers, including the LINK_STATUS register, which determines whether the negotiated speed or bandwidth has decreased. The AER_CE_STATUS register detects correctable errors, such as ERR_COR_Detect = 1 (ErrorCorrectable Detection), and the AER_UE_STATUS register detects uncorrectable errors, such as ERR_UNCOR_Detect = 1 (ErrorUncorrectable Detection). It compares these values ​​with preset feature values ​​to distinguish anomaly types and feature values.

[0048] The slot location module is used to determine the actual physical slot based on the characteristic value and provide standardized maintenance prompts based on the abnormality type.

[0049] According to the test link anomaly locating system of the embodiment of the present application, a graphics processor, multiple node devices and a test link anomaly locating device work together to achieve automatic and high-precision identification of abnormal locations in the PCIe test link.

[0050] Figure 4 This is a flowchart of the test link anomaly locating method provided in an embodiment of the present application.

[0051] like Figure 4 As shown, the test link anomaly locating method is applied to a processing component of a test link anomaly locating device, wherein the method includes the following steps: In step S101, when the test link is abnormal, a first enable bit is written to the first register of each node device, and each node device enters a low power mode in response to the first enable bit. The node device sends a first training sequence to the graphics processor in the low power mode, and the graphics processor returns a first response sequence. When the communication between the node device and the graphics processor is normal, the first response sequence is written to the second register.

[0052] It can be understood that the embodiment of the present application can write the first enable bit to the first register of the node device when testing link abnormalities, force the node device to enter a low-power state, and trigger link retraining in the low-power state. Since the low-power conversion process is more sensitive to signal integrity, it can effectively expose hidden link instability problems caused by poor contact, electromagnetic interference, circuit routing defects, etc., thereby improving the fault detection rate. The state feedback based on the interaction of the training sequence can accurately locate the abnormal position, enhance the depth and reliability of abnormality detection, and reduce dependence on the experience of technical personnel.

[0053] It should be noted that the processing component of the present application can be connected to each node device to perform abnormality positioning operations on the test link between each node device and the graphics processor.

[0054] Specifically, in factory-side GPU stress testing, link anomaly detection includes achieving uninterrupted link retraining in a low-power state, such as Figure 6 As shown, specifically: The control processing component writes the Extended (Bit 4) bit to the first register of all PCIe devices to activate low-power conversion. During the power conversion process, it is easier to expose the location of link instability, thereby determining whether there is an abnormality in the link.

[0055] The processing component writes the Retrain Link (Bit 5) bit to the first register of all node devices to implement an uninterrupted link retraining traversal. After the traversal is completed, the traversal results are stored in the Link Status (Bit 0-Bit 3). The link is determined to be abnormal by reading the second register after the traversal to see if there is any abnormal value returned.

[0056] The first register is the link control register, the second register is the link status register, the first enable bit is the Extended (Bit 4) bit, the second enable bit is the Retrain Link (Bit 5), the first training sequence is the TS1 (Training Sequence) sequence, and the second response sequence is the TS2 sequence.

[0057] Link retraining means that all node devices and the graphics processor re-shake hands through the TS1 / TS2 ordered set. If the handshake fails or degrades, the abnormality is exposed through the second register to realize link quality detection without system restart. The link retraining process: the enable bit of the first register of the node device is written by the processing component to determine the triggering of the retraining request. At this time, the node device sends the TS1 sequence, wherein the TS1 sequence includes: supported link speed, supported link width, whether equalization and polarity inversion are supported; the physical layer of the image processor parses TS1 and sends the TS2 sequence to the physical layer of the node device to confirm the commonly supported speed and width. If equalization is supported, the equalization training is started and the training state machine is set to enter the next stage; when both parties complete the training and reach an agreement, the result is written to the second register, wherein the second register records abnormal events such as training failure and speed reduction, so as to determine the abnormal location.

[0058] In an embodiment of the present application, before writing the first enable bit to the first register of each node device, it includes: writing the second enable bit to the second register of each node device, and each node device triggers uninterrupted link retraining in response to the second enable bit.

[0059] It can be understood that the embodiment of the present application can write a second enable bit to the second register of each node device, and each node device responds to the second enable bit to trigger uninterrupted link retraining, thereby determining the cause of the link abnormality and ensuring the consistency of the test conditions and the reliability of the diagnostic results.

[0060] It should be noted that the second enable bit is Retrain Link (Bit 5), which is used to trigger uninterrupted link retraining.

[0061] In step S102, the second register of each node device is read, and the abnormal position of the test link is located according to the second register reading result.

[0062] It can be understood that the embodiment of the present application can read the second register of each node device and locate the abnormal position of the test link based on the second register reading result. Since the register reading delay is low (microsecond level), the status can be obtained immediately after the stress test, achieving fast feedback, improving the test effect and the accuracy of the abnormal results.

[0063] In an embodiment of the present application, the abnormal position of the test link is located according to the reading result of the second register, including: identifying the register status bit in the reading result; if the range of the register status bit is greater than or equal to the preset value, determining that there is no abnormality in the node device; if the range of at least one register status bit is less than the preset value, obtaining the identification of the node device, and determining the abnormal position of the test link according to the identification of the node device.

[0064] It can be understood that the embodiments of the present application can determine the reason for the test link abnormality based on the register status bit threshold, avoiding subjective misjudgment, ensuring that the judgment criteria are unified, objective, and repeatable, and improving the accuracy of abnormality location and the maintenance efficiency.

[0065] It should be noted that if there is an abnormality in speed reduction and bandwidth reduction, the abnormal information returned by the physical layer of the graphics processor can be read in the second register, and the corresponding characteristic value negotiation link width is less than the maximum width (negotiated linkwidth < max width); the negotiated link speed is less than the maximum speed (negotiated link speed < max speed); the first one points to bandwidth reduction and the second one points to speed reduction.

[0066] Specifically, the link abnormalities existing in the link retraining process include training failure, speed reduction, and bandwidth reduction. Among them, the first to seventh status bits in the second register are read. For example: if Bit0 = 0, it is determined that the training fails; if the values of Bit1 - Bit3 are less than the nominal rate, it is determined that there is a speed reduction abnormality; if the values of Bit4 - Bit6 are less than the nominal bandwidth, it is determined that there is a bandwidth reduction abnormality, and the fault location is located based on the abnormality type and the device identifier; if Bit0 = 1 (training completed) and the values of Bit1 - Bit6 are greater than the nominal values, it is determined that the node device is normal.

[0067] In the embodiments of the present application, if the read result carries the first response sequence, after determining that the node device is normal, it further includes: writing the third enable bit to the third register of each node device, and each node device responds to the third enable bit; reading the fourth register of each node device, and locating the abnormal position of the test link according to the read result of the fourth register.

[0068] It can be understood that the embodiments of the present application can actively inject CRC errors by writing the enable bit to the third register, and locate the abnormal position of the test link according to the fourth register of the node device, realizing active perturbation diagnosis and improving the detection rate of hidden faults.

[0069] Specifically, the processing component intentionally injects error information into the outgoing data packet, which is implemented by writing bit 0 to the EIR. The link stability is determined by determining whether the link can correct the error. If it can be corrected, the CE count is recorded and the AER_CE_STATUS register is read to locate the abnormality. If it cannot be corrected, a UCE interrupt is triggered, and the abnormality is located by reading the AER_UE_STATUS register. If the link can correct the error, it can be understood that the tested link is normal and robust, and the link is considered normal. If the error cannot be corrected, the link is considered unstable. CE and UCE have their own flag bits in the status register, and link abnormalities are determined by determining the status of the CE or UCE flag bits.

[0070] In an embodiment of the present application, the abnormal position of the test link is located according to the read result of the fourth register, including: identifying the status of the cyclic redundancy check value in the read result; if the cyclic redundancy check value returns to normal, it is determined that there is no abnormality in the node device; if the cyclic redundancy check value maintains erroneous data, the identification of the node device is obtained, and the abnormal position of the test link is determined according to the identification of the node device.

[0071] It can be understood that the embodiments of the present application can amplify the problem phenomenon by actively injecting CRC errors and observing the recovery behavior. If it is determined that the CRC error is self-healed, it indicates that there is no abnormality in the node device. Otherwise, the identification of the node device is obtained, and the abnormal position of the test link is determined according to the identification of the node device, thereby improving the objectivity and accuracy of the diagnosis, accurately locating the physical location, and improving the efficiency of the test.

[0072] It should be noted that cyclic redundancy check is a mechanism used to detect data transmission errors: each data packet contains a CRC check code. The receiving end recalculates the CRC based on the received data and compares it with the CRC value carried in the packet. If they are inconsistent, a correctable error is triggered. Common causes of CRC errors include: poor signal integrity, electromagnetic interference, poor contact of gold fingers, and impedance mismatch of circuit board traces.

[0073] Specifically, if Figure 7 As shown, if CE is abnormal, the returned abnormal information can be read in the AER_CE_STATUS register, and the corresponding characteristic value is ERR_COR_Detect=1. If UCE is abnormal, the returned abnormal information can be read in the AER_UE_STATUS register, and the corresponding characteristic value is ERR_UNCOR_Detect=1.

[0074] In an embodiment of the present application, determining the abnormal location based on the identification of the node device includes: obtaining a first correspondence between the identification of the node device and the layout location; using the identification of the node device as an index, querying the correspondence to obtain the layout location of the node device, and determining the abnormal location of the test link based on the layout location of the node device.

[0075] It is understandable that the embodiment of the present application can query the correspondence between the node device identifier and the physical layout location, and then determine the abnormal location of the test link, thereby improving the efficiency of troubleshooting and maintenance.

[0076] It should be noted that the first correspondence between the identifier of the node device and the layout position is shown in Table 1 below, so as to display the specific slot information corresponding to the abnormal position, so as to help operators accurately locate the abnormal position.

[0077] Table 1: First correspondence between node device identification and layout location

[0078] For example, if the node device identifier is 81:00.0, the device is located on a switch board. In this case, you need to check whether the uplink gold finger of the switch is oxidized and confirm that the lock is in place.

[0079] In an embodiment of the present application, after determining the abnormal position of the test link according to the identifier of the node device, it includes: obtaining a second correspondence between the abnormal position and the abnormal type; and querying the second correspondence to obtain the abnormal type using the abnormal position as an index.

[0080] It is understandable that the embodiment of the present application can obtain a second correspondence between the abnormal location and the abnormal type, and obtain the abnormal type by querying with the abnormal location as an index, thereby improving the efficiency of troubleshooting and maintenance.

[0081] It should be noted that the second correspondence between the abnormal position and the abnormal type is shown in Table 2 below. The node device can be determined according to the abnormal position, and the key register characteristic value of the node device can be queried to determine the abnormal type according to the characteristic value. Table 2 The second correspondence between abnormal position and abnormal type

[0082] For example, if the abnormal position of the node device is found, and if the negotiated link width of the key register characteristic value of the node device is less than the maximum width, it indicates that the current abnormality type is speed reduction or bandwidth reduction.

[0083] In an embodiment of the present application, identifying whether a test link is abnormal includes: obtaining error data from a graphics processor after a stress test; parsing keywords in the error data to determine an abnormal result; if the abnormal result is a single-unit failure of the graphics processor or a link abnormality, generating a maintenance recommendation report based on the abnormal location information of the single-unit failure of the graphics processor or the link; if the abnormal result does not display the cause of the fault, controlling the test link abnormal location system to locate the abnormal location. It can be understood that after the GPU stress test, the embodiment of the present application can determine the type of abnormality by analyzing the error data. If the cause of the abnormality is a single-unit failure / link abnormality, a maintenance suggestion is generated. If the cause is unknown, the test link abnormality positioning system is controlled to locate the abnormal position, thereby improving processing efficiency.

[0084] Specifically, if Figure 5 As shown, during GPU stress testing, the production line may encounter two types of errors: non-GPU-related errors, such as alarms or errors from other components triggered during the GPU stress test, which the system automatically ignores; GPU-related errors, which automatically trigger this system. Test item errors are accompanied by corresponding error codes that reflect the abnormal component. For example, SYS_BMC_001 indicates a BMC abnormality, while SYS_GPU_001 indicates a GPU component, triggering this system.

[0085] When the system encounters a GPU-related error, it parses the error log generated after the GPU stress test. It then extracts keywords from the error log to determine if there's a clear indication of the anomaly. If the log clearly indicates an anomaly, such as a failure of a specific GPU or the location of a GPU switch board, the error is reported, allowing production line staff to repair or replace the anomaly directly based on the error. If the error log can't pinpoint the specific anomaly, the system proceeds to the test link anomaly location system. After completing the automatic link analysis process, the system reports the anomaly location and information, allowing production line staff to repair the anomaly based on this information.

[0086] In the embodiment of the present application, a maintenance measure storage database is generated according to the abnormality location and abnormality type.

[0087] Specifically, the specific slot information corresponding to the abnormal location is displayed to allow operators to accurately locate the abnormal location. Based on the abnormal information in the abnormal feature extraction module, maintenance measures are fed back. For example, if the abnormal information points to the bandwidth reduction of the 73:00.0 clip, the system will prompt the operator to check the installation of GPU3 and whether there is dust on the gold finger. If there is no problem, try to reinstall GPU3. After the production line operator performs the maintenance work according to the system prompts, they will be prompted to enter the maintenance action. When the abnormal machine is retested, if the machine does not report the abnormal error, the system will consider the analyzed data valid and the maintenance suggestion valid, and record it in its own database. When similar abnormal situations occur in the future, the operator will be prompted to perform this maintenance action first. If the abnormal machine still reports the same error after retesting, the system will consider the current maintenance suggestion invalid and will discard this information and not record it in the database.

[0088] In summary, this application significantly reduces the analysis time for production line GPU stress test anomalies, improves production line efficiency, and compared with traditional engineer analysis methods, improves the accuracy of confirming abnormal problems and shortens the troubleshooting time, frees up a large amount of manpower, and locates the abnormal position more accurately, reducing the action of replacing parts in traditional maintenance actions, saving a large amount of material costs, ensuring product quality, and reducing the possibility of quality problems in products after shipment.

[0089] It should be noted that this application analyzes possible abnormal problems in the test link, and can be upgraded to classify and analyze all abnormal problems, and sort out all abnormal information and maintenance suggestions, continuously improve its own database, and form a set of abnormal problem analysis system that is constantly learning and improving.

[0090] According to the test link abnormality locating method provided by the embodiment of the present application, when the test link is abnormal, the processing component writes the first enable bit to the first register of each node device, and each node device enters the low power mode in response to the first enable bit to expose the unstable position of the test link during the low power conversion process. Each node device triggers link retraining in the low power mode and determines the abnormal position of the link according to the flag bit status of the second register. If the above embodiments are unable to detect the abnormal position of the link, the node device is controlled to insert an erroneous cyclic redundancy check value into the data link layer packet sent next time to locate the abnormal position according to the flag bit status of the fourth register, thereby improving the troubleshooting efficiency and abnormality locating accuracy, saving time and labor costs. Thus, the problem that the manual troubleshooting of the abnormal position of the link in the related technology cannot effectively solve the abnormal problem in a timely manner, resulting in low work efficiency and high time and labor costs is solved.

[0091] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned test link abnormality locating methods.

[0092] Specifically, the memory is used to store computer programs that can be run on the processor, and may include high-speed RAM memory, and may also include non-volatile memory (non-volatile memory), such as at least one disk storage.

[0093] If the memory and processor are implemented independently, the memory and processor can be connected to each other via a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be divided into address buses, data buses, control buses, etc. The processor can be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0094] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned test link abnormality locating method embodiments when running.

[0095] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned test link abnormality locating method embodiments are implemented.

[0096] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] The above is a detailed introduction to a method for obtaining display content provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A test link abnormality locating device, characterized in that: The test link is composed of a graphics processor and multiple node devices, the test link uses a processing component to perform stress testing, and the graphics processor and the multiple node devices communicate with each other, wherein the apparatus includes: a first register and a second register of each node device; a processing component, configured to write a first enable bit to a first register of each node device when the test link is abnormal, so that each node device enters a low power consumption mode in response to the first enable bit; The node device sends a first training sequence to the graphics processor in the low power consumption mode, and the graphics processor returns a first response sequence. When the communication between the node device and the graphics processor is normal, the first response sequence is written into the second register; The processing component reads the second register of each node device and locates the abnormal position of the test link according to the reading result of the second register.

2. The test link abnormality locating device according to claim 1, characterized in that: The test link is provided with a plurality of physical slots, and each physical slot is provided with a node device.

3. The test link abnormality locating device according to claim 1, characterized in that: Also includes: The third register and the fourth register of each node device; a processing component, configured to write a third enable bit to a third register of each node device when the test link is abnormal, and each node device responds to the third enable bit to control the node device to insert an incorrect cyclic redundancy check value into a data link layer packet sent next time; The processing component reads the fourth register of each node device and locates the abnormal position of the test link according to the reading result.

4. The test link abnormality locating device according to any one of claims 1 to 3, characterized in that: The first register, the second register, the third register and the fourth register are all set in the configuration space of the node device.

5. A test link anomaly locating system, characterized in that: include: A graphics processor and a plurality of node devices, wherein the graphics processor and the plurality of node devices form a test link, the test link performs a stress test using the processing component, and the graphics processor and the plurality of node devices communicate with each other; The test link anomaly locating device according to any one of claims 1 to 4 is used to locate the abnormal position of the test link.

6. A test link abnormality location method, characterized in that: The method is applied to the processing component of the test link anomaly locating device according to any one of claims 1 to 4, wherein the method comprises the following steps: When the test link is abnormal, a first enable bit is written to a first register of each node device, and each node device enters a low power consumption mode in response to the first enable bit. The node device sends a first training sequence to the graphics processor in the low power consumption mode, and the graphics processor returns a first response sequence. When communication between the node device and the graphics processor is normal, the first response sequence is written to the second register; The second register of each node device is read, and the abnormal position of the test link is located according to the reading result of the second register.

7. The test link abnormality locating method according to claim 6, characterized in that: After writing the first enable bit to the first register of each node device, the method includes: A second enable bit is written into the first register of each node device, and each node device triggers uninterrupted link retraining in response to the second enable bit.

8. The test link abnormality locating method according to claim 6, characterized in that: The locating the abnormal position of the test link according to the reading result of the second register includes: Identifying a register status bit in the read result; If the range of the register status bit is greater than or equal to the preset value, it is determined that there is no abnormality in the node device; If the range of at least one register status bit is smaller than a preset value, an identifier of the node device is obtained, and an abnormal position of the test link is determined according to the identifier of the node device.

9. The test link abnormality locating method according to claim 8, characterized in that: If the read result carries the first response sequence, after determining that the node device is normal, the method further includes: A third enable bit is written into a third register of each node device, each node device responds to the third enable bit, a fourth register of each node device is read, and an abnormal position of the test link is located according to a reading result of the fourth register.

10. The test link abnormality locating method according to claim 9, characterized in that: The locating the abnormal position of the test link according to the reading result of the fourth register includes: Identifying a status of a cyclic redundancy check value in the read result; If the cyclic redundancy check value returns to normal, it is determined that there is no abnormality in the node device; If the cyclic redundancy check value maintains erroneous data, an identifier of the node device is obtained, and an abnormal position of the test link is determined according to the identifier of the node device.

11. The test link abnormality locating method according to claim 8 or 10, characterized in that: The determining the abnormal location according to the identifier of the node device includes: Acquire a first correspondence between an identifier of the node device and an arrangement position; The corresponding relationship is queried using the identifier of the node device as an index to obtain the layout position of the node device, and the abnormal position of the test link is determined according to the layout position of the node device.

12. The test link abnormality locating method according to claim 8 or 10, characterized in that: After determining the abnormal location of the test link according to the identifier of the node device, the method includes: Obtaining a second correspondence between the exception location and the exception type; The second corresponding relationship is queried using the abnormal position as an index to obtain the abnormal type.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor is configured to implement the steps of the test link anomaly locating method according to any one of claims 6 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the test link abnormality locating method according to any one of claims 6 to 12 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the test link abnormality locating method according to any one of claims 6 to 12 are implemented.

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