Semiconductor test structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor test structure and a manufacturing method thereof, and the semiconductor test structure comprises a test array region which comprises test active regions arranged in an array. The plurality of test conductive wire groups are arranged along the first direction, each test conductive wire group comprises two test conductive wires which are adjacently arranged and a connecting part which is connected with the first ends of the two test conductive wires, each test conductive wire extends and penetrates through the test array area along a second direction, and the second direction is perpendicular to the first direction. And the at least one electric connection structure and the two external connection structures are located on the second ends of the test conductive wires in the plurality of test conductive wire groups, and the first ends and the second ends of the test conductive wires are opposite to each other. The at least one electric connection structure is electrically connected with the adjacent test conductive wires in the adjacent test conductive wire groups in the plurality of test conductive wire groups, and the two external connection structures are electrically connected with the two outermost test conductive wires in all the test conductive wires in the plurality of test conductive wire groups respectively.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor test structure and a manufacturing method thereof. Background Art

[0002] Semiconductor devices, such as dynamic random access memory (DRAM), typically consist of multiple structures, among which conductive lines such as word lines and bit lines are common components. These lines select the target cell when a suitable voltage is applied. During the operation of a semiconductor device, the electrical performance of these conductive lines, such as word lines and bit lines, plays a crucial role in its functionality.

[0003] However, in actual operation, there are still many problems that need to be improved regarding the determination of the electrical properties of conductive lines such as word lines and bit lines. Summary of the Invention

[0004] The present disclosure provides a semiconductor test structure according to an embodiment, comprising:

[0005] A test array area, including a test active area arranged in an array;

[0006] a plurality of test conductive line groups arranged along a first direction, wherein each test conductive line group includes two adjacent test conductive lines and a connecting portion connecting first ends of the two test conductive lines, each test conductive line extends through the test array area along a second direction, the second direction being perpendicular to the first direction, and the test conductive lines in the plurality of test conductive line groups are coupled to the test active area accordingly;

[0007] At least one electrical connection structure and two external connection structures are located on the second ends of the test conductive lines in the multiple test conductive line groups, wherein the first ends and the second ends of the test conductive lines are opposite to each other, the at least one electrical connection structure electrically connects the test conductive lines adjacent to each other in the adjacent test conductive line groups in the multiple test conductive line groups, and the two external connection structures are respectively electrically connected to the two outermost test conductive lines of all the test conductive lines in the multiple test conductive line groups.

[0008] In some embodiments, the test structure further includes a pad structure, which is located at an end of the external structure away from the test conductive wire group and is connected to the external structure.

[0009] In some embodiments, the test structure further includes: a plurality of dummy test conductive line groups distributed on both sides of the plurality of test conductive line groups in the first direction.

[0010] In some embodiments, the number of the electrical connection structures is multiple, and the multiple electrical connection structures include multiple first electrical connection structures and multiple second electrical connection structures. The first electrical connection structures and the second electrical connection structures are alternately arranged in a direction perpendicular to the extension of the test conductive line, and are offset in a direction parallel to the extension of the test conductive line.

[0011] In some embodiments, the first electrical connection structure includes at least a first contact structure and a second contact structure, and the second electrical connection structure includes at least a third contact structure and a fourth contact structure, wherein:

[0012] The first contact structures and the second contact structures are alternately arranged in a direction perpendicular to an extension direction of the test conductive line, and are offset in a direction parallel to an extension direction of the test conductive line;

[0013] The third contact structures and the fourth contact structures are alternately arranged in a direction perpendicular to an extension direction of the test conductive line, and are offset in a direction parallel to an extension direction of the test conductive line.

[0014] In some embodiments, in a direction extending parallel to the test conductive line, the second contact structure has a first offset relative to the first contact structure, and / or, in a direction extending parallel to the test conductive line, the third contact structure and the fourth contact structure have a second offset, and the first offset is the same as the second offset.

[0015] In some embodiments, the test conductive line includes at least one of a test word line or a test bit line.

[0016] The present disclosure also provides a method for manufacturing a semiconductor test structure, including:

[0017] Providing a semiconductor substrate, wherein the semiconductor substrate includes a device structure region and a dicing street region;

[0018] forming an array of active regions in the device structure region, and simultaneously forming an array of test active regions in the dicing street region;

[0019] forming a plurality of annular conductive lines arranged along a first direction and a plurality of annular conductive test lines arranged along the first direction, each of the annular conductive lines passing through the active area arranged in an array, and each of the annular conductive test lines passing through the test active area arranged in an array;

[0020] Both ends of each of the plurality of looped conductive lines are removed to form a plurality of conductive lines, and the same end of each of the plurality of looped test conductive lines is removed to form a plurality of test conductive line groups.

[0021] In some embodiments, the test conductive line includes a first end and a second end opposite to each other, two adjacent test conductive lines constitute the test conductive line group, and the first ends of two test conductive lines in the same test conductive line group are connected;

[0022] After forming a plurality of the test conductive line groups, the manufacturing method further includes:

[0023] At least one electrical connection structure and two external connection structures are formed, wherein the electrical connection structure electrically connects the test conductive lines adjacent to each other in the adjacent test conductive line groups among the multiple test conductive line groups; and the two external connection structures are respectively electrically connected to the two outermost test conductive lines among all the test conductive lines in the multiple test conductive line groups.

[0024] In some embodiments, the number of the electrical connection structures is multiple, forming at least one electrical connection structure, including:

[0025] Forming a plurality of the electrical connection structures includes forming a plurality of first electrical connection structures and a plurality of second electrical connection structures, wherein the first electrical connection structures and the second electrical connection structures are alternately arranged in a direction perpendicular to the extension direction of the test conductive line and are offset in a direction parallel to the extension direction of the test conductive line.

[0026] The present disclosure provides a semiconductor test structure and a manufacturing method thereof, wherein the semiconductor test structure includes: a test array area including an array-arranged test active area; a plurality of test conductive line groups arranged along a first direction, wherein each of the test conductive line groups includes two adjacently arranged test conductive lines and a connecting portion connecting the first ends of the two test conductive lines, each of the test conductive lines extends through the test array area along a second direction, the second direction being perpendicular to the first direction, and the test conductive lines in the plurality of test conductive line groups are correspondingly coupled to the test active area; at least one electrical connection structure and two external structures are located on the second ends of the test conductive lines in the plurality of test conductive line groups, wherein the first and second ends of the test conductive lines are opposite to each other, the at least one electrical connection structure electrically connects adjacent test conductive lines in adjacent test conductive line groups in the plurality of test conductive line groups, and the two external structures are respectively electrically connected to the two outermost test conductive lines among all the test conductive lines in the plurality of test conductive line groups. In the embodiment of the present disclosure, the two ends of the two test conductive wires on the same side in each test conductive wire group are connected by a connecting portion, which provides a good prerequisite for realizing the operation of simultaneously performing electrical performance tests on multiple test conductive wires. In addition, in the embodiment of the present disclosure, in the end positions of the test conductive wire group where the connecting portion is not provided, adjacent test conductive wire groups are connected to each other by an electrical connection structure, so that the multiple test conductive wires contained in the adjacent test conductive wire groups can form a series structure. In this way, in the test array area, the multiple test conductive wire structures contained in the multiple test conductive wire groups can form a series connection structure, in which the two test conductive wires located on the outermost side along the first direction are connected to the external structure, and the external structure can be further connected to other structures to realize the operation of all electrical performance tests on multiple test conductive wires in the same test process, which helps to quickly obtain test results of electrical performance such as resistance data, and has the advantages of simple structure and easy implementation.

[0027] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1A schematic structural diagram of a semiconductor test structure provided by an embodiment of the present disclosure;

[0030] Figure 2 A schematic structural diagram of another semiconductor test structure provided by an embodiment of the present disclosure;

[0031] Figure 3 A schematic structural diagram of another semiconductor test structure provided by an embodiment of the present disclosure;

[0032] Figure 4 An enlarged view of a local structure of a semiconductor test structure provided by an embodiment of the present disclosure;

[0033] Figure 5 A schematic diagram of a partial structure of a semiconductor test structure provided by an embodiment of the present disclosure;

[0034] Figure 6 A flowchart of a method for manufacturing a semiconductor test structure provided by an embodiment of the present disclosure;

[0035] Figures 7 to 10 A schematic diagram of the structure of a semiconductor test structure during the preparation process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0038] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0039] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0041] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] Conductive wires are common components in semiconductor devices. They can achieve the target cell selection effect after applying a suitable voltage. During the use of semiconductor devices, the electrical performance of the conductive wires plays a crucial role in the function of the semiconductor devices. For example, in a semiconductor device, when a conductive wire is short-circuited, short-circuited, or has a large resistance value, it is easy to cause the device to overheat, fail to work properly, or cause a large power loss at the location of the conductive wire itself, affecting the service life and performance of the semiconductor device.

[0043] Based on this, the following technical solutions are proposed in the embodiments of the present disclosure:

[0044] An embodiment of the present disclosure provides a semiconductor test structure, comprising:

[0045] A test array area, including a test active area arranged in an array;

[0046] a plurality of test conductive line groups arranged along a first direction, wherein each test conductive line group includes two adjacent test conductive lines and a connecting portion connecting first ends of the two test conductive lines, each test conductive line extending through the test array area along a second direction, the second direction being perpendicular to the first direction, and the test conductive lines in the plurality of test conductive line groups being coupled to the test active areas accordingly;

[0047] At least one electrical connection structure and two external connection structures are located on the second ends of the test conductive wires in the multiple test conductive wire groups, wherein the first ends and the second ends of the test conductive wires are opposite to each other, the at least one electrical connection structure electrically connects adjacent test conductive wires in adjacent test conductive wire groups in the multiple test conductive wire groups, and the two external connection structures are respectively electrically connected to the two outermost test conductive wires of all the test conductive wires in the multiple test conductive wire groups.

[0048] In the embodiment of the present disclosure, the two ends of the two test conductive wires on the same side in each test conductive wire group are connected by a connecting portion, which provides a good prerequisite for realizing the operation of simultaneously performing electrical performance tests on multiple test conductive wires. In addition, in the embodiment of the present disclosure, in the end positions of the test conductive wire group where the connecting portion is not provided, adjacent test conductive wire groups are connected to each other by an electrical connection structure, so that the multiple test conductive wires contained in the adjacent test conductive wire groups can form a series structure. In this way, in the test array area, the multiple test conductive wire structures contained in the multiple test conductive wire groups can form a series connection structure, in which the two test conductive wires located on the outermost side along the first direction are connected to the external structure, and the external structure can be further connected to other structures to realize the operation of all electrical performance tests on multiple test conductive wires in the same test process, which helps to quickly obtain test results of electrical performance such as resistance data, and has the advantages of simple structure and easy implementation.

[0049] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0050] Figure 1 A schematic structural diagram of a semiconductor test structure provided by an embodiment of the present disclosure; Figure 2 A schematic structural diagram of another semiconductor test structure provided by an embodiment of the present disclosure; Figure 3 A schematic structural diagram of another semiconductor test structure provided by an embodiment of the present disclosure; Figure 4 An enlarged view of a local structure of a semiconductor test structure provided by an embodiment of the present disclosure; Figure 5 A schematic diagram of a partial structure of a semiconductor test structure provided in an embodiment of the present disclosure.

[0051] The semiconductor test structure provided by the embodiment of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0052] like Figure 1 、 Figure 3 and Figure 4 As shown, a semiconductor test structure includes:

[0053] Test array area A1, including test active areas AA1 arranged in an array;

[0054] A plurality of test conductive line groups L1a arranged along a first direction, wherein each test conductive line group L1a includes two adjacent test conductive lines L1 and a connecting portion 15 connecting first ends D1 of the two test conductive lines L1, each test conductive line L1 extending through the test array area A1 along a second direction perpendicular to the first direction, and the test conductive lines L1 in the plurality of test conductive line groups L1a are coupled to the test active area AA1 accordingly;

[0055] At least one electrical connection structure S and two external structures 13 are located on the second end D2 of the test conductive line L1 in the multiple test conductive line groups L1a, wherein the first end D1 and the second end D2 of the test conductive line L1 are opposite to each other, the at least one electrical connection structure S electrically connects adjacent test conductive lines L1 in the multiple test conductive line groups L1a, and the two external structures 13 are respectively electrically connected to the two outermost test conductive lines L1 of all the test conductive lines L1 in the multiple test conductive line groups L1a.

[0056] In some embodiments, the semiconductor test structure includes a semiconductor substrate 10 .

[0057] Here, the material of the semiconductor substrate 10 specifically includes a single-element semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the semiconductor substrate 10 is a silicon substrate.

[0058] Continue to refer Figures 1 to 3 As shown, in some embodiments, the semiconductor substrate 10 includes a device structure region 101 and a scribe line region 102 .

[0059] In some embodiments, the device structure region 101 includes an array region A2, which includes multiple active areas AA2 and multiple conductive lines L2 (word lines WL2 and / or bit lines BL2). The multiple conductive lines L2 (word lines WL2 and / or bit lines BL2) pass through the active areas AA2. The dicing lane regions 102 are used to separate multiple chip structures on a wafer formed by forming various structures on the semiconductor substrate 10 after bonding.

[0060] In actual operation, the multiple structures set on the cutting road area 102 are often used for testing purposes. This helps to avoid setting connection structures for testing operations on the various structures located on the device structure area 101 when performing test operations, thereby not changing the original structural settings located on the device structure area 101, thereby helping to maintain the function of the original structure and not generating additional costs and losses due to the execution of test operations.

[0061] In some embodiments, the test array area A1 located on the cutting street area 102, and the area where the test active area AA1 and the test conductive line L1 contained therein are located may be smaller than the setting area of ​​the corresponding structure located in the device structure area 101, but the size and pitch of the test active area AA1 are the same as those of the active area AA2. At the same time, the width and pitch of the test conductive line L1 and the conductive line L2 may also be the same, but the length of the former may be smaller than the length of the latter.

[0062] In actual operation, the active area AA2 can be set in the middle area of ​​the conductive line L2 in the extension direction, and in the cutting lane area 102, the position relationship between the test active area AA1 and the test conductive line L1 can be flexibly set according to the test requirements, and no specific limitation is made here.

[0063] In any of the above embodiments, the test conductive line L1 includes at least one of a test word line WL1 or a test bit line BL1 .

[0064] In some embodiments, the material of the test word line WL1 or the test bit line BL1 may include a conductive material. The conductive material may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium).

[0065] It should be noted that in the attached Figure 1 and attached Figure 3 Although it is shown that the test word line WL1 and the test bit line BL1 are arranged in parallel along the first direction and extended along the second direction, it is only for illustrating the arrangement and extension of the test conductive line L1 in the semiconductor test structure, and is not used to limit the actual arrangement and extension direction of the test word line WL1 and the test bit line BL1.

[0066] In some embodiments, the extension directions of the test word line WL1 and the test bit line BL1 can be perpendicular to each other, that is, when the test word line WL1 extends in one direction, the test bit line BL2 can extend in a direction perpendicular to the extension direction of the test word line WL1. Regarding the actual extension direction of the test word line WL1 and the test bit line BL1 in the semiconductor structure, it can be flexibly selected according to actual conditions and is not specifically limited here.

[0067] Similarly, the configuration of the word line WL2 and the bit line BL2 may refer to the related descriptions of the test word line WL1 and the test bit line BL1, which will not be repeated here.

[0068] In some embodiments, the connection portion 15 of the two test conductive lines L1 at the first end D1 in a test conductive line group L1a can be obtained by cutting off the ring-shaped connection portion of the two test conductive lines L1 at the second end D2 during the process of forming the test conductive lines L1, and retaining the connection portion at the first end D1. That is, in the embodiments of the present disclosure, the connection portion 15 in the same conductive line group L1a is obtained by cutting off the connection portion of one end when both ends of the two test conductive lines L1 are in a ring-shaped connection state during the formation of the semiconductor test structure, rather than by re-performing the material formation and etching processes at a later stage. The formation process is relatively simple and does not increase the process complexity. At the same time, in the embodiments of the present disclosure, the two ends of the two test conductive lines on the same side in each test conductive line group are connected by the connection portion 15, which provides a good prerequisite for realizing the operation of performing electrical performance testing on multiple test conductive lines at the same time.

[0069] In the disclosed embodiment, although a connection structure 15 is added to the first end D1 of the test conductive line L1, compared to the size of the test area in conventional test structures, when the test conductive line L1 is a test word line WL1, the test area only needs to be expanded by the pitch of a bit line located in the scribe area 102 and extending perpendicularly to the direction of the test word line WL1 (the pitch is equal to the width of the relevant bit line plus the spacing between adjacent bit lines). Similarly, when the test conductive line L1 is a test bit line BL1, the test area only needs to be expanded by the pitch of a word line located in the scribe area 102 and extending perpendicularly to the direction of the test bit line BL1 (the pitch is equal to the width of the relevant word line plus the spacing between adjacent word lines). In other words, the provision of the connection 15 does not significantly increase the size of the test area and does not significantly increase the size of the semiconductor test structure, but it significantly improves test efficiency and the reliability of test results, providing significant advantages.

[0070] Apart from Figure 1and Figure 3 In addition to the semiconductor test structure in which the first end D1 of the test conductive line L1 is provided with a connection portion 15, the embodiment of the present disclosure also provides a Figure 2 The semiconductor test structure will be described below with reference to the accompanying drawings.

[0071] exist Figure 2 In the structure shown, the first ends D1 of two test conductive lines L1 in the same test conductive line group L1a are connected by a preset electrical connection structure S1, and the second ends D2 of two adjacent test conductive lines in two adjacent test conductive line groups L1a are connected by the electrical connection structure S. Figure 2 In the structure shown, the multiple test conductive lines L1 can also form a series structure connected end to end, which provides a good prerequisite for performing electrical performance tests on the multiple test conductive lines at the same time.

[0072] In some embodiments, the test structure further includes a pad structure 14 . The pad structure 14 is located at an end of the external structure 13 away from the test conductive line group L1 a and is connected to the external structure 13 .

[0073] In some embodiments, the external structure 13 can be electrically connected to the outermost test conductive line L1 of all the test conductive lines L1 of the plurality of test conductive line groups L1 a through the contact plug structure PC.

[0074] Here, the pad structure 14 is used to contact a test structure, such as a probe, when the test conductive line L1 is subjected to an electrical performance test, thereby establishing an electrical connection between the test conductive line L1 and an external test device.

[0075] In an embodiment of the present disclosure, a semiconductor test structure can be used to measure the resistance value of a test conductive line. By connecting multiple test conductive lines L1 in multiple test conductive line groups L1a in series, the total resistance value of the multiple test conductive lines L1 is measured, and then divided by the number of test conductive lines L1 to obtain the average resistance value of a single test conductive line L1. Based on the average resistance value, the actual resistance value of the test conductive line L1 and whether the resistance value is within an acceptable range can be determined, which can help determine whether the usage requirements are met.

[0076] At the same time, because conductive line L2 and test conductive line L1 are formed in the same process step, the test results of test conductive line L1 can be used to determine whether conductive line L2 is short-circuited or short-circuited, thereby determining whether conductive line L1 is damaged or meets the requirements of use. Compared with conventional methods that directly test the resistance of a single conductive line to be tested by providing an electrical connection structure and a test pad structure at both ends of the single conductive line to be tested, the semiconductor test structure provided by the embodiments of the present disclosure has a simple testing process, and the method of simultaneously performing testing operations on multiple test conductive lines L1 in the same process helps improve testing efficiency and obtain reliable test results.

[0077] In some embodiments, the test structure further includes: a plurality of dummy test conductive line groups L1b distributed on both sides of the plurality of test conductive line groups L1a in the first direction.

[0078] It can be understood that since during the process, the structure located at the edge position is more easily restricted by the process conditions (such as the situation caused by the etching load effect, etc.) than the structure in the middle area, it is easy to cause the structural shape to be inconsistent with the design shape. The embodiment of the present disclosure adopts the arrangement of the virtual test conductive line group L1b on both sides of the entire test conductive line group L1a in the first direction, so that if there is structural deformation, the situation can occur at the position where the virtual conductive line group L1b is located, which helps to ensure that in the process of obtaining the test conductive line L1 located in the cutting road area 102, the test conductive line L1 obtained for the test operation can have a normal structure, which is conducive to higher accuracy of the test results and improved test reliability.

[0079] In some embodiments, there are multiple electrical connection structures S, and the multiple electrical connection structures S include multiple first electrical connection structures 11 and multiple second electrical connection structures 12. The first electrical connection structures 11 and the second electrical connection structures 12 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1, and are offset in a direction parallel to the extension of the test conductive line L1.

[0080] In this way, the first electrical connection structure 11 and the second electrical connection structure 12 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1, and there is an offset setting in the direction parallel to the extension of the test conductive line L1, which is beneficial to providing more process formation space for the formation of the first electrical connection structure 11 and the second electrical connection structure 12, which is beneficial to reducing the process difficulty and obtaining the first electrical connection structure 11 and the second electrical connection structure 12 with good performance.

[0081] In some embodiments, the first electrical connection structure 11 includes at least a first contact structure 111 and a second contact structure 112 , and the second electrical connection structure 12 includes at least a third contact structure 121 and a fourth contact structure 122 , wherein:

[0082] The first contact structures 111 and the second contact structures 112 are alternately arranged in a direction perpendicular to the extending direction of the test conductive line L1 and are offset in a direction parallel to the extending direction of the test conductive line L1;

[0083] The third contact structures 121 and the fourth contact structures 122 are alternately arranged in a direction perpendicular to the extending direction of the test conductive line L1 , and are offset in a direction parallel to the extending direction of the test conductive line L1 .

[0084] In some embodiments, the first contact structure 111 , the second contact structure 112 , the third contact structure 121 , and the fourth contact structure 122 may all be contact plug structures.

[0085] In some embodiments, the first electrical connection structure 11 further includes a first pad 113, which connects the first contact structure 111 and the second contact structure 112. The second electrical connection structure 12 further includes a second pad 123, which connects the third contact structure 121 and the fourth contact structure 122. In this way, the first pad 113 and the second pad 123 can be used to connect adjacent test conductive lines L1 in the adjacent test conductive line group L1a.

[0086] In some embodiments, compared to the arrangement of the first, second, third, and fourth contact structures 111, 112, 121, and 122 in a direction perpendicular to the test conductive line L1 and without any offset in the direction parallel to the test conductive line L1, the arrangement of the first and second contact structures 111, 112 in a direction perpendicular to the test conductive line L1 and with an offset in the direction parallel to the test conductive line L1, and the arrangement of the third and fourth contact structures 121, 122 in a direction perpendicular to the test conductive line L1 and with an offset in the direction parallel to the test conductive line L1, facilitates a larger process operation window for the multiple contact structures during the process of forming the contact structures, effectively preventing the high density of the multiple contact structures from causing misaligned connections, which could result in contact structures connecting to test conductive lines that should not be connected, and causing inaccurate test results due to incorrect connection relationships. Furthermore, the arrangement effectively prevents interference between the multiple contact structures during operation, thereby increasing the reliability of the test results.

[0087] In some embodiments, as Figure 5As shown, in a direction extending parallel to the test conductive line L1, the second contact structure 112 has a first offset P1 relative to the first contact structure 111, and / or, in a direction extending parallel to the test conductive line L1, the third contact structure 121 and the fourth contact structure 122 have a second offset P2, and the first offset P1 is the same as the second offset P2.

[0088] In this way, within the same test conductive line group L1a, the first ends D1 are connected by a connecting portion 15, which is arranged along the same straight line in a direction perpendicular to the extension of the test conductive lines L1. The second ends D2 of adjacent test conductive lines L1 in adjacent test conductive line groups L1a are connected using an electrical connection structure S. The identical setting of the first offset P1 and the second offset P2 helps ensure that the lengths of the test portions participating in the electrical performance measurement in each test conductive line group L1a are the same. In this way, after the test process is completed and the total resistance value is obtained, the average resistance value obtained by dividing it by the number of test conductive lines L1 participating in the test can better approximate the actual resistance value of each test conductive line L1 participating in the test process, thereby accurately reflecting the electrical performance of the test conductive lines L1. Furthermore, the electrical performance of the conductive lines L2 located in the device structure area 101 can be accurately reflected, improving the accuracy and reliability of the test results.

[0089] Continue to refer Figure 5 As shown, the same setting of the first offset P1 and the second offset P2 helps to ensure that the lengths of the test conductive wires L1 in the portion participating in the electrical performance measurement in each test conductive wire group L1a are the same. For understanding, reference can be made to the length calculation process of the two adjacent test conductive wire groups L1a numbered ① and ②. Since the other test conductive wire groups L1a are arranged in a periodic arrangement with the two adjacent test conductive wire groups L1a numbered ① and ②, when the lengths of the two adjacent test conductive wire groups L1a numbered ① and ② are the same, it can be inferred that the lengths of the test conductive wire groups L1a at other positions are also the same. The length calculation process of the two adjacent test conductive wire groups L1a numbered ① and ② is as follows:

[0090] The length of the test conductive wire group L1a numbered ① is equal to: 2L+P1+P3+P1

[0091] The length of the test conductive wire group L1a numbered ② is equal to: 2L+P1+P3+P2

[0092] At this time, if the length of the test conductive wire group L1a numbered ① is to be equal to the length of the test conductive wire group L1a numbered ②, the following equation must be satisfied:

[0093] 2L+P1+P3+P1=2L+P1+P3+P2

[0094] Calculation shows that when P1 is equal to P2, that is, when the first offset P1 is the same as the second offset P2, the length of the test conductive wire group L1a numbered ① is equal to the length of the test conductive wire group L1a numbered ②.

[0095] exist Figure 5 For ease of understanding, among the reference lines used to determine L, P1, P2 and P3, the reference line located on the side where the connecting portion 15 is located can be tangent to the end of the connecting portion 15 on the side away from the electrical connection structure S, and the remaining reference lines are perpendicular to the extension direction of the test conductive line L1 and pass through the center positions of the first contact structure 111, the second contact structure 112, the third contact structure 121 and the fourth contact structure 122.

[0096] In some embodiments, as Figure 4 As shown, the resistance value of the test conductive line L1 can be determined in the following way:

[0097] First, the structure of multiple test conductive wire groups L1a is regarded as a simple repetition of a single test conductive wire group L1a. After obtaining the total resistance of multiple test conductive wire groups L1a, according to the total resistance R total =n×R0, where n represents the number of repetitions (i.e., the number of the test conductive line group L1a), and R0 represents the resistance of a single repetition unit;

[0098] Then, according to R0=2×R L1 +R 15 +R S ; Among them, R L1 is the resistance of a single test conductive line L1 of the two test conductive lines L1 included in a test conductive line group L1a, R 15 Represents the resistance of the connection part 15, R S Represents the resistance of the electrical connection structure, R S Specifically, it may include the contact structure constituting the electrical connection structure S and the resistance value of the pad;

[0099] It can be understood that since the distance between the two conductive lines L1 is very short, the resistance at the connecting portion 15 can be ignored, that is, R 15 ≈0, and at the same time, ignoring the resistance value of the electrical connection structure S, that is, ignoring the wiring resistance between the test conductive line L1 and the contact plug and the pad, we get R S ≈0;

[0100] In this way, the actual test resistance R total ≈2×n×R L1 ;

[0101] Therefore, the resistance per unit length of the test conductive line L1 actually measured is R-L1S =(R total ) / (n×(2L+2P1+P3)), where 2L+2P1+P3 represents the length of the portion of the single test conductive wire group L1a participating in the resistance test. When the length value of this portion changes in other embodiments, the corresponding parameter variables can be adjusted to obtain the corresponding resistance value per unit length.

[0102] Continue to refer Figure 2 ,exist Figure 2 In the structure shown, the preset electrical connection structure S1 may further include a third electrical connection structure 17 and a fourth electrical connection structure 18 .

[0103] In some embodiments, the third electrical connection structure 17 includes at least a fifth contact structure 171 and a sixth contact structure 172 , and the fourth electrical connection structure 18 includes at least a seventh contact structure 181 and an eighth contact structure 182 .

[0104] In some embodiments, the fifth contact structure 171 , the sixth contact structure 172 , the seventh contact structure 181 , and the eighth contact structure 182 may all be contact plug structures.

[0105] In some embodiments, the third electrical connection structure 17 further includes a third pad 173, which connects the fifth contact structure 171 and the sixth contact structure 172. The fourth electrical connection structure 18 further includes a fourth pad 183, which connects the seventh contact structure 181 and the eighth contact structure 182. In this way, the first ends D1 of adjacent test conductive lines L1 in the same test conductive line group L1a can be connected via the third pad 173 and the fourth pad 183.

[0106] exist Figure 2 In the embodiment shown, the configuration information of the test conductive line group L1a at the second end D2 may correspond to the reference Figure 1 and Figure 3 The relevant information of the test conductive line group L1a is not repeated here.

[0107] In some embodiments, the setting information about the preset electrical connection structure S1 at the first end D1 of the test conductive wire group L1a may include multiple situations. In order to obtain a structure in which the lengths of the portions of the test conductive wires L1 participating in the electrical performance measurement in each test conductive wire group L1a are the same, the fifth contact structure 171, the sixth contact structure 172, the seventh contact structure 181 and the eighth contact structure 182 may be arranged side by side on the same straight line perpendicular to the extension direction of the test conductive wire L1.

[0108] However, it is not limited to this. From the perspective of facilitating process execution, the following settings can also be adopted:

[0109] The fifth contact structures 171 and the sixth contact structures 172 are alternately arranged in a direction perpendicular to the extending direction of the test conductive line L1 and are offset in a direction parallel to the extending direction of the test conductive line L1;

[0110] The seventh contact structures 181 and the eighth contact structures 182 are alternately arranged in a direction perpendicular to the extending direction of the test conductive line L1 , and are offset in a direction parallel to the extending direction of the test conductive line L1 .

[0111] In some embodiments, in a direction extending parallel to the test conductive line L1, the sixth contact structure 172 has a third offset relative to the fifth contact structure 171, and / or, in a direction extending parallel to the test conductive line L1, the seventh contact structure 181 and the eighth contact structure 182 have a fourth offset. The third offset and the fourth offset may be the same or different and may be selected according to actual circumstances and are not specifically limited here.

[0112] about Figure 2 In the semiconductor test structure provided in the embodiment, the resistance value per unit length of the test conductive line L1 can be determined by referring to the aforementioned formula. In actual operation, the resistance of the third electrical connection structure 17 and the fourth electrical connection structure 18 can also be processed accordingly with reference to the aforementioned processing of the resistance portion of the connection portion 15 to obtain Figure 2 The resistance value per unit length of the test conductive line L1 is shown in FIG.

[0113] The semiconductor test structure provided by the embodiments of the present disclosure can be applied in dynamic random access memory (DRAM).

[0114] The present disclosure also provides a method for manufacturing a semiconductor test structure. Figure 6 As shown, the manufacturing method includes the following steps:

[0115] Step S101: providing a semiconductor substrate 10, wherein the semiconductor substrate 10 includes a device structure region 101 and a dicing street region 102;

[0116] Step S102: forming an array of active regions in the device structure region, and simultaneously forming an array of test active regions in the dicing lane region;

[0117] Step S103: forming a plurality of annular conductive lines arranged along a first direction and a plurality of annular conductive test lines arranged along the first direction, wherein each annular conductive line passes through an active area arranged in an array, and each annular conductive test line passes through a test active area arranged in an array;

[0118] Step S104: removing both ends of each conductive line in the plurality of looped conductive lines to form a plurality of conductive lines, and simultaneously removing the same end of each test conductive line in the plurality of looped conductive test lines to form a plurality of test conductive line groups.

[0119] First, execute step S101, as Figure 7 As shown, a semiconductor substrate 10 is provided, the semiconductor substrate 10 includes a device structure region 101 and a cutting street region 102, and step S102 is performed to form an array-arranged active area AA2 in the device structure region 101, and at the same time form an array-arranged test active area AA1 in the cutting street region 102.

[0120] Here, the material of the semiconductor substrate 10 specifically includes a single-element semiconductor material (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (such as a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the semiconductor substrate 10 is a silicon substrate.

[0121] In some embodiments, the device structure region 101 includes an array region A2 , and the array region A2 includes a plurality of active areas AA2 .

[0122] In some embodiments, the scribe line area 102 includes a test array area A1, which includes a test active area AA1. The scribe line area 102 is used to separate multiple chip structures on a wafer formed by forming various structures on the semiconductor substrate 10. After performing a bonding operation, the scribe line area 102 is used to perform a dicing process at the location of the scribe line area 102, thereby separating the multiple chip structures on the wafer.

[0123] In some embodiments, the area of ​​the test array area A1 may be smaller than that of the array area A2 , and the test active area AA1 and the active area AA2 may have the same size and pitch.

[0124] Then, step S103 is executed. Figure 8 As shown, a plurality of annular conductive lines L2a' and a plurality of annular conductive test lines L1a' are formed along the first direction. Each annular conductive line L2a' passes through the active area AA2 arranged in an array, and each annular conductive test line L1a' passes through the test active area AA1 arranged in an array.

[0125] In some embodiments, a structure of multiple annular conductive lines L2a' and multiple annular conductive test lines L1a' arranged along the first direction can be obtained by first forming a conductive line material layer (not shown) covering the device structure area 101 and the cutting road area 102, and then performing an etching operation.

[0126] In actual operation, the active area AA2 can be set in the middle area of ​​the annular conductive line L2a' in the extension direction, and in the cutting lane area 102, the test active area AA1 can be flexibly set to have a positional relationship with the annular conductive test line L1a' according to test requirements, which is not specifically limited here.

[0127] Finally, step S104 is executed. Figure 9 As shown, both ends of each of the plurality of looped conductive lines L2a' are removed to form a plurality of conductive lines L2, and at the same time, the same end of each of the plurality of looped conductive test lines L1a' is removed to form a plurality of test conductive line groups L1a.

[0128] In some embodiments, as Figure 10 As shown, the test conductive line L1 includes a first end D1 and a second end D2 opposite to each other, two adjacent test conductive lines L1 constitute a test conductive line group L1a, and the first ends D1 of the two test conductive lines L1 in the same test conductive line group L1a are connected;

[0129] After forming a plurality of test conductive line groups L1a, the manufacturing method further includes:

[0130] At least one electrical connection structure S and two external structures 13 are formed. The electrical connection structure S electrically connects adjacent test conductive lines L1 in adjacent test conductive line groups L1a in the plurality of test conductive line groups L1a. The two external structures 13 are respectively electrically connected to the two outermost test conductive lines L1 in all the test conductive lines L1 in the plurality of test conductive line groups L1a.

[0131] In some embodiments, the number of the electrical connection structures S is multiple, forming at least one electrical connection structure S, including:

[0132] A plurality of electrical connection structures S are formed, including a plurality of first electrical connection structures 11 and a plurality of second electrical connection structures 12. The first electrical connection structures 11 and the second electrical connection structures 12 are alternately arranged in a direction perpendicular to the extension of the test conductive line L1 and are offset in a direction parallel to the extension of the test conductive line L1.

[0133] In some embodiments, the first electrical connection structure 11 includes at least a first contact structure 111 and a second contact structure 112 , and the second electrical connection structure 12 includes at least a third contact structure 121 and a fourth contact structure 122 , wherein:

[0134] The first contact structures 111 and the second contact structures 112 are alternately arranged in a direction perpendicular to the extending direction of the test conductive line L1 and are offset in a direction parallel to the extending direction of the test conductive line L1;

[0135] The third contact structures 121 and the fourth contact structures 122 are alternately arranged in a direction perpendicular to the extending direction of the test conductive line L1 , and are offset in a direction parallel to the extending direction of the test conductive line L1 .

[0136] In some embodiments, the first contact structure 111 , the second contact structure 112 , the third contact structure 121 , and the fourth contact structure 122 may all be contact plug structures.

[0137] In some embodiments, the first electrical connection structure 11 further includes a first pad 113, which connects the first contact structure 111 and the second contact structure 112. The second electrical connection structure 12 further includes a second pad 123, which connects the third contact structure 121 and the fourth contact structure 122. In this way, the first pad 113 and the second pad 123 can be used to connect adjacent test conductive lines L1 in the adjacent test conductive line group L1a.

[0138] In some embodiments, compared to the arrangement of the first, second, third, and fourth contact structures 111, 112, 121, and 122 in a direction perpendicular to the test conductive line L1 and without any offset in the direction parallel to the test conductive line L1, the arrangement of the first and second contact structures 111, 112 in a direction perpendicular to the test conductive line L1 and with an offset in the direction parallel to the test conductive line L1, and the arrangement of the third and fourth contact structures 121, 122 in a direction perpendicular to the test conductive line L1 and with an offset in the direction parallel to the test conductive line L1, facilitates a larger process operation window for the multiple contact structures during the process of forming the multiple contact structures, effectively preventing the phenomenon of misaligned connections caused by a high density of multiple contact structures, such as contact structures connecting to test conductive lines that should not be connected, resulting in inaccurate test results due to incorrect connection relationships. Furthermore, it effectively prevents interference between the multiple contact structures during operation, thereby increasing the reliability of the test results.

[0139] In some embodiments, as Figure 5As shown, in a direction extending parallel to the test conductive line L1, the second contact structure 112 has a first offset P1 relative to the first contact structure 111, and / or, in a direction extending parallel to the test conductive line L1, the third contact structure 121 and the fourth contact structure 122 have a second offset P2, and the first offset P1 is the same as the second offset P2.

[0140] In this way, within the same test conductive line group L1a, the first ends D1 are connected by a connecting portion 15, which is arranged in a straight line perpendicular to the direction in which the test conductive lines L1 extend. The second ends D2 of adjacent test conductive lines L1 in adjacent test conductive line groups L1a are connected using an electrical connection structure S. The identical setting of the first offset P1 and the second offset P2 helps ensure that the lengths of the test portions participating in the electrical performance measurement in each test conductive line group L1a are the same. In this way, after the test process is completed and the total resistance value is obtained, the average resistance value obtained by dividing it by the number of test conductive lines L1 participating in the test can better approximate the actual resistance value of each test conductive line L1 participating in the test process, thereby accurately reflecting the electrical performance of the test conductive lines L1. Furthermore, the electrical performance of the conductive lines L2 located in the device structure area 101 can be accurately reflected, improving the accuracy and reliability of the test results.

[0141] The various technical features in the technical solutions described in the various embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0142] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor test structure, characterized in that: include: A test array area, including a test active area arranged in an array; a plurality of test conductive line groups arranged along a first direction, wherein each test conductive line group includes two adjacent test conductive lines and a connecting portion connecting first ends of the two test conductive lines, each test conductive line extends through the test array area along a second direction, the second direction being perpendicular to the first direction, and the test conductive lines in the plurality of test conductive line groups are coupled to the test active area accordingly; At least one electrical connection structure and two external connection structures are located on the second ends of the test conductive lines in the multiple test conductive line groups, wherein the first ends and the second ends of the test conductive lines are opposite to each other, the at least one electrical connection structure electrically connects the test conductive lines adjacent to each other in the adjacent test conductive line groups in the multiple test conductive line groups, and the two external connection structures are respectively electrically connected to the two outermost test conductive lines of all the test conductive lines in the multiple test conductive line groups.

2. The test structure according to claim 1, characterized in that The test structure further includes a pad structure, which is located at an end of the external structure away from the test conductive line group and is connected to the external structure.

3. The test structure according to claim 1, wherein: The test structure further includes: a plurality of dummy test conductive line groups distributed on both sides of the plurality of test conductive line groups in the first direction.

4. The test structure according to claim 1, wherein: There are multiple electrical connection structures, and the multiple electrical connection structures include multiple first electrical connection structures and multiple second electrical connection structures. The first electrical connection structures and the second electrical connection structures are alternately arranged in a direction perpendicular to the extension of the test conductive line, and are offset in a direction parallel to the extension of the test conductive line.

5. The test structure according to claim 4, characterized in that The first electrical connection structure includes at least a first contact structure and a second contact structure, and the second electrical connection structure includes at least a third contact structure and a fourth contact structure, wherein: The first contact structures and the second contact structures are alternately arranged in a direction perpendicular to an extension direction of the test conductive line, and are offset in a direction parallel to an extension direction of the test conductive line; The third contact structures and the fourth contact structures are alternately arranged in a direction perpendicular to an extension direction of the test conductive line, and are offset in a direction parallel to an extension direction of the test conductive line.

6. The test structure according to claim 5, characterized in that In a direction extending parallel to the test conductive line, the second contact structure has a first offset relative to the first contact structure, and / or, in a direction extending parallel to the test conductive line, the third contact structure and the fourth contact structure have a second offset, and the first offset is the same as the second offset.

7. The test structure according to any one of claims 1 to 6, characterized in that: The test conductive line includes at least one of a test word line or a test bit line.

8. A method for manufacturing a semiconductor test structure, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate includes a device structure region and a dicing street region; forming an array of active regions in the device structure region, and simultaneously forming an array of test active regions in the dicing street region; forming a plurality of annular conductive lines arranged along a first direction and a plurality of annular conductive test lines arranged along the first direction, each of the annular conductive lines passing through the active area arranged in an array, and each of the annular conductive test lines passing through the test active area arranged in an array; Both ends of each of the plurality of looped conductive lines are removed to form a plurality of conductive lines, and the same end of each of the plurality of looped test conductive lines is removed to form a plurality of test conductive line groups.

9. The manufacturing method according to claim 8, characterized in that The test conductive line includes a first end and a second end opposite to each other, two adjacent test conductive lines constitute the test conductive line group, and the first ends of two test conductive lines in the same test conductive line group are connected; After forming a plurality of the test conductive line groups, the manufacturing method further includes: At least one electrical connection structure and two external connection structures are formed, wherein the electrical connection structure electrically connects the test conductive lines adjacent to each other in the adjacent test conductive line groups among the multiple test conductive line groups; and the two external connection structures are respectively electrically connected to the two outermost test conductive lines among all the test conductive lines in the multiple test conductive line groups.

10. The manufacturing method according to claim 9, characterized in that: There are multiple electrical connection structures, forming at least one electrical connection structure, including: Forming a plurality of the electrical connection structures includes forming a plurality of first electrical connection structures and a plurality of second electrical connection structures, wherein the first electrical connection structures and the second electrical connection structures are alternately arranged in a direction perpendicular to the extension direction of the test conductive line and are offset in a direction parallel to the extension direction of the test conductive line.

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