Backside illuminated image sensor preparation method, backside illuminated image sensor and electronic equipment

Abstract

The invention relates to a backside illuminated image sensor preparation method, a backside illuminated image sensor and electronic equipment, and the method comprises the steps: providing a substrate which comprises a plurality of first isolation structures which extend towards the interior of the substrate through a first surface of the substrate and are arranged at intervals in a first direction parallel to the first surface; forming a first SiP layer on the first surface and a second isolation structure which penetrates through the first SiP layer along a second direction facing the substrate and is connected with the first isolation structure; forming a groove located between the adjacent second isolation structures, and a SiAs material layer which fills the groove and covers the first SiP layer and the top surfaces of the second isolation structures; forming third isolation structures connected with the second isolation structures in the SiAs material layer, and a plurality of second SiP layers located between the third isolation structures and distributed at intervals in the first direction; the residual SiAs material layer is used for forming the SiAs layer. According to the method, the technological process can be simplified, the number of photon-generated carriers in the device is increased, and the quantum efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method for preparing a back-illuminated image sensor, a back-illuminated image sensor, and an electronic device. Background Art

[0002] Image sensors are photoelectric conversion devices widely used in consumer electronics, security monitoring, automotive electronics, machine vision, and other fields. Based on the placement of metal circuits and the light-receiving layer, they are categorized as front-illuminated and back-illuminated. Backside-illuminated (BSI) image sensors offer advantages such as higher sensitivity, improved wiring layout, and high-speed recording, making them commonly used in applications requiring high pixel performance.

[0003] However, in today's deep submicron manufacturing process, the traditional BSI front-end process requires high-energy ion implantation (IMP) to create the diode structure and pixel area, which can damage the substrate surface. Uneven ion implantation can also cause signal crosstalk between different pixels, hindering further improvement in BSI image sensor performance. Summary of the Invention

[0004] Based on this, it is necessary to provide a back-illuminated image sensor preparation method, a back-illuminated image sensor and an electronic device to address the technical problems in the prior art, which can at least avoid signal crosstalk of the BSI image sensor and unnecessary damage caused by IMP.

[0005] In a first aspect, the present application provides a method for preparing a back-illuminated image sensor, comprising: providing a substrate, wherein the substrate includes a plurality of first isolation structures extending from a first surface of the substrate toward the interior of the substrate and arranged at intervals along a first direction parallel to the first surface;

[0006] forming a first SiP layer on the first surface, and a second isolation structure penetrating the first SiP layer along a second direction toward the substrate and connected to the first isolation structure;

[0007] forming a trench between adjacent second isolation structures and a SiAs material layer filling the trench and covering the top surfaces of the first SiP layer and the second isolation structure;

[0008] forming a third isolation structure connected to the second isolation structure in the SiAs material layer, and a plurality of second SiP layers spaced apart and distributed along the first direction between the third isolation structures; and the remaining SiAs material layer is used to constitute a SiAs layer;

[0009] Among them, SiP is used to characterize silicon materials doped with phosphorus (P); SiAs is used to characterize silicon materials doped with arsenic (As).

[0010] In the preparation method of the above embodiment, in order to improve manufacturing efficiency, the preparation steps of the second and third isolation structures are interspersed in the process of preparing the stacked first SiP layer, the second SiP layer and the SiAs layer. By coordinating the preparation steps of different structures, the overall production process is optimized, thereby making the entire production process more compact and efficient, and will not affect the front-end process during the process.

[0011] Based on the above preparation method, multiple stacked isolation structures are obtained, and optoelectronic material layers (i.e., a first SiP layer, a second SiP layer, and a SiAs layer) are arranged according to preset rules between adjacent isolation structures. A photodiode structure is formed on the substrate, which effectively avoids unnecessary damage caused by high-energy ion implantation in forming photodiodes in traditional methods, reduces dark current caused by defects, and helps to improve the imaging clarity of the image sensor.

[0012] In some embodiments, forming the second isolation structure includes:

[0013] forming a first groove penetrating the first SiP layer along the second direction, wherein the first groove exposes a portion of the top surface of the first isolation structure;

[0014] epitaxially growing a first isolation material layer in the first groove;

[0015] The first isolation material layer having a top surface higher than the first SiP layer is removed, and the remaining first isolation material layer is used to form a second isolation structure.

[0016] In some embodiments, forming the third isolation structure includes:

[0017] forming a second groove penetrating the SiAs material layer along a second direction, wherein the second groove exposes a top surface of the second isolation structure;

[0018] forming a second isolation material layer filling the second groove by a spin coating process;

[0019] The second isolation material layer with a top surface higher than the SiAs material layer is removed, and the remaining second isolation material layer is used to form a third isolation structure.

[0020] In some embodiments, the SiAs layer includes:

[0021] A plurality of first SiAs layers are arranged one-to-one with a plurality of second SiP layers; a second SiP layer is located directly above a first SiAs layer;

[0022] A plurality of second SiAs layers and a plurality of second SiP layers are alternately distributed between adjacent third isolation structures along the first direction.

[0023] In some embodiments, the first SiAs layer penetrates the first SiP layer along the second direction and extends into the substrate.

[0024] In some embodiments, a dimension of the first isolation structure along the first direction gradually increases toward the substrate;

[0025] The dimension of the second isolation structure along the first direction gradually decreases in the direction toward the substrate;

[0026] A dimension of the third isolation structure along the second direction is greater than a dimension of the second isolation structure along the second direction.

[0027] In some embodiments, after forming the second SiP layer, the method further includes:

[0028] forming a grid material layer covering the second SiP layer, the second SiAs layer and the top surface of the third isolation structure;

[0029] Removing part of the grid material layer to form grids and third grooves alternately arranged along the first direction; the grids are located directly above the third isolation structures arranged one on one;

[0030] A SiP cap layer and a filter are sequentially formed in the third groove and stacked along a direction away from the substrate.

[0031] In a second aspect, the present application further provides a back-illuminated image sensor, including a back-illuminated image sensor manufactured using any of the above-mentioned preparation methods, the back-illuminated image sensor including:

[0032] A substrate, comprising a plurality of first isolation structures extending from a first surface of the substrate toward the interior of the substrate and arranged at intervals along a first direction parallel to the first surface;

[0033] A first SiP layer is located on the first surface and includes a second isolation structure and a first SiAs layer that penetrate the first SiP layer along a second direction toward the substrate and are alternately arranged along the first direction; the second isolation structure is connected to the first isolation structure;

[0034] a plurality of third isolation structures, arranged one-to-one with the second isolation structures;

[0035] A plurality of second SiAs layers are alternately arranged with the second SiP layer along the first direction between adjacent third isolation structures; a second SiP layer is located directly above a first SiAs layer;

[0036] a plurality of grilles located directly above the third isolation structure;

[0037] SiP cap layer, located between adjacent grids.

[0038] In the above embodiment, by stacking the first isolation structure, the second isolation structure, and the third isolation structure to form a physical shielding structure that runs through the pixel area of ​​the back-illuminated image sensor, it is possible to effectively prevent charge diffusion and drift into adjacent pixels, as well as the occurrence of light diffusion into adjacent pixels, thereby suppressing the adverse effects of optical and / or electrical crosstalk on image clarity. By arranging the first SiP layer, the second SiP layer, the first SiAs layer, the second SiAs layer, and the SiP layer according to a preset rule between adjacent isolation structures, a pixel area with a "waterfall-shaped" cross-section is formed, which can optimize the carrier generation and separation process, increase the number of photogenerated carriers, reduce the recombination rate in the conversion process, and improve the photoelectric response efficiency.

[0039] In some embodiments, the substrate includes a P-type dopant element;

[0040] The dimension of the first isolation structure along the first direction gradually increases in the direction toward the substrate;

[0041] The dimension of the second isolation structure along the first direction gradually decreases in the direction toward the substrate;

[0042] A dimension of the third isolation structure along the second direction is greater than a dimension of the second isolation structure along the second direction.

[0043] In a third aspect, the present application further provides an electronic device, comprising a back-illuminated image sensor prepared by any of the above preparation methods; or a back-illuminated image sensor as described in the above embodiments.

[0044] Electronic devices equipped with back-illuminated image sensors fabricated using the method of this application benefit from a simplified process flow, reducing equipment wear and maintenance costs, accelerating R&D and production, and shortening product time-to-market. Furthermore, back-illuminated image sensors offer reduced dark current, increased quantum efficiency, and reduced image noise. They also offer enhanced sensitivity in low-light environments, resulting in clearer images.

[0045] The back-illuminated image sensor manufacturing method, back-illuminated image sensor, and electronic device in the embodiments of the present application have the following unexpected technical effects:

[0046] During the process of manufacturing the first SiP layer, the second SiP layer and the SiAs layer of the stacked structure, the steps of forming the second and third isolation structures are simultaneously introduced, thereby avoiding the damage that may be caused by high-energy ion implantation while achieving a compact and efficient production process.

[0047] Regularly arranged photoelectric material layers (i.e., the first SiP layer, the second SiP layer, the SiAs layer, and the SiP cap layer) and the substrate form a "waterfall" pixel photodiode structure, effectively optimizing carrier transport, increasing the number of photogenerated carriers, and improving photoelectric response efficiency. A physical shielding structure (i.e., the first, second, and third isolation structures) that runs through the pixel area effectively suppresses the negative impact of crosstalk on imaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0049] Figure 1 is a flow chart of a method for preparing a back-illuminated image sensor provided in one embodiment;

[0050] Figure 2a 1 is a schematic cross-sectional view of a structure obtained after forming an interlayer dielectric layer in step S24 of a preparation method provided in one embodiment;

[0051] Figure 2b Schematic cross-sectional view of a structure obtained after thinning the initial substrate in step S26 of a preparation method provided in one embodiment;

[0052] Figure 3 1 is a schematic cross-sectional view of a structure obtained after forming the first SiP layer in step S42 of the preparation method provided in one embodiment;

[0053] Figure 4 Schematic cross-sectional view of a structure obtained after forming the first groove in step S44 of the preparation method provided in one embodiment;

[0054] Figure 5 is a schematic cross-sectional view of a structure obtained after forming the first isolation material layer in step S46 of the preparation method provided in one embodiment;

[0055] Figure 6 Schematic cross-sectional view of a structure obtained after forming the second isolation structure in step S48 of the preparation method provided in one embodiment;

[0056] Figure 7 for Figure 6 A schematic cross-sectional view of the structure obtained after the grooves are formed in the embodiment;

[0057] Figure 8 for Figure 7 A schematic cross-sectional view of the structure obtained after the SiAs material layer is formed;

[0058] Figure 9 Schematic cross-sectional view of the structure obtained after forming the second groove in step S82 of the preparation method provided in one embodiment;

[0059] Figure 10 1 is a schematic cross-sectional view of a structure obtained after forming the third isolation structure in step S88 of the preparation method provided in one embodiment;

[0060] Figure 11 Schematic cross-sectional view of the structure obtained after forming the second trench in step S810 in the preparation method provided in one embodiment;

[0061] Figure 12 is a schematic cross-sectional view of a structure obtained after forming the second SiP layer in step S812 of the preparation method provided in one embodiment;

[0062] Figure 13 for Figure 12 A schematic cross-sectional view of the structure obtained after the grid material layer is formed;

[0063] Figure 14 for Figure 13 A schematic cross-sectional view of the structure obtained after the grid and the third groove are formed;

[0064] Figure 15 for Figure 14 Schematic cross-sectional view of the structure obtained after the SiP cap layer is formed;

[0065] Figure 16 for Figure 15 Schematic diagram of the cross-section of the resulting structure after the filter is formed.

[0066] Description of reference numerals:

[0067] 1. Initial substrate; 10. Substrate; 10a. First surface; 11. Etch stop layer; 12. Interlayer dielectric layer; 13. First SiP layer; 141. SiAs material layer; 14. SiAs layer; 14a. First SiAs layer; 14b. Second SiAs layer; 15. Second SiP layer; 16. SiP cap layer; 221. First isolation material layer; 21. First isolation structure; 22. Second isolation structure; 23. Third isolation structure; 31. First groove; 32. Second groove; 33. Third groove; 41. First trench; 42. Second trench; 50. Grid; 501. First grid material layer; 502. Second grid material layer; 503. Third grid material layer; 60. Filter. DETAILED DESCRIPTION

[0068] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0070] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0071] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0072] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0073] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0074] In an embodiment of the present application, the substrate may include a first surface located on the front side, and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. A first direction and a third direction that intersect each other (e.g., perpendicular to each other) are defined in the top and bottom surface directions of the substrate (i.e., the plane where the substrate is located). For example, the arrangement direction of the target isolation structure is the first direction, and the plane where the substrate is located can be determined based on the first direction and the third direction. Among them, the first direction, the second direction, and the third direction can be perpendicular to each other in pairs. In an embodiment of the present application, the first direction is defined as the Y-axis direction, the second direction is defined as the Z-axis direction, and the third direction is defined as the X-axis direction.

[0075] See also Figures 1-16 The present application provides a method for preparing a back-illuminated image sensor, including steps S20 to S80.

[0076] Step S20 : ​​providing a substrate 10 , wherein the substrate 10 includes a plurality of first isolation structures 21 extending from a first surface of the substrate 10 toward the inside of the substrate and arranged at intervals along a first direction (OY direction) parallel to the first surface.

[0077] For example, the substrate 10 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the material of the substrate 10 includes, but is not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or other III / V semiconductors or II / VI semiconductors. Alternatively, for example, the substrate 10 can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure. In this embodiment, the material of the substrate 10 includes silicon (Si).

[0078] For example, the material of the first isolation structure 21 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or the like, or a combination thereof.

[0079] The first isolation structure 21 is used to isolate electrons and light energy. For example, the cross-sectional shape of the first isolation structure 21 along the OY direction may include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or a combination of regular trapezoids, inverted trapezoids, rectangles, etc. In this embodiment of the application, the first isolation structure 21 only needs to be able to isolate electrons and light energy. In addition, this embodiment does not impose any specific restrictions on the distance between adjacent first isolation structures 21, and can be set according to actual needs.

[0080] Step S40 : forming a first SiP layer 13 on the first surface, and a second isolation structure 22 penetrating the first SiP layer 13 along a second direction (ZO direction, ie, opposite to the OZ direction) toward the substrate and connected to the first isolation structure 21 .

[0081] For example, the cross-sectional shape of the second isolation structure 22 and the first isolation structure 21 along the OY direction is the same.

[0082] By way of example, the first SiP layer 13 is used to represent silicon doped with phosphorus (P) ions, ie, an N-type silicon layer.

[0083] Step S60 : forming trenches between adjacent second isolation structures 22 and forming a SiAs material layer 141 that fills the trenches and covers the top surfaces of the first SiP layer 13 and the second isolation structures 22 .

[0084] For example, the SiAs material layer 141 is used to represent silicon doped with arsenic (As) ions. Like the first SiP layer 13 , both are N-type silicon layers. The SiP and SiAs appearing in subsequent embodiments also follow this logic and will not be elaborated on here.

[0085] Step S80 : forming a third isolation structure 23 connected to the second isolation structure 22 and a plurality of second SiP layers 15 spaced apart along the first direction (OY direction) between the third isolation structures 23 in the SiAs material layer 141 ; the remaining SiAs material layer 141 is used to constitute the SiAs layer 14 .

[0086] For example, the second SiP layer 15 is also a silicon layer doped with phosphorus (P) ions, but the doping concentration may be the same as or different from the doping concentration of the first SiP layer 13 .

[0087] The structure of the back-illuminated image sensor obtained after steps S20-S80 can be referred to Figure 16 Of course, in order to facilitate the understanding of this application, Figure 16 The example provided is one example of a back-illuminated image sensor prepared using the back-illuminated image sensor preparation method of the present application. There may be other suitable examples of back-illuminated image sensors prepared using the back-illuminated image sensor preparation method of the present application, and the present application does not impose any limitations thereon.

[0088] In the above embodiment, during the process of forming the pixel area (i.e., the first SiP layer 13, the SiAs layer 14, and the second SiP layer 15), a plurality of isolation structures (i.e., the second isolation structure 22 and the third isolation structure 23) spaced apart in the pixel area can be simultaneously formed. Adjusting the preparation sequence of the isolation structures and the pixel area can avoid unnecessary damage caused by the use of high-energy ion implantation to form photodiodes between adjacent isolation structures, reduce dark current in the pixel area, and help improve the imaging clarity of the image sensor; since the second isolation structure 22 and the third isolation structure 23 pass through the above-mentioned photodiodes, signal crosstalk between adjacent pixel areas is effectively reduced.

[0089] It should be understood that although Figure 1 The steps in the flowchart are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0090] The above steps are described in detail with reference to the accompanying drawings.

[0091] See also Figure 2a and Figure 2b In some embodiments, step S20 includes steps S22 to S26.

[0092] Step S22 : providing an initial substrate 1 , and forming first isolation structures 21 arranged at intervals along a first direction (OY direction) in the initial substrate 1 .

[0093] For example, a P-type silicon wafer is used as a substrate wafer. In the front-end of line (FEOL) process, a shallow trench isolation (STI) structure is formed in the initial substrate 1, which is arranged in a first direction (OY direction) and has a top surface flush with the top surface of the initial substrate 1. It is recorded as the first isolation structure 21.

[0094] The distance between the axes of symmetry of two adjacent first isolation structures 21 is between 500 nanometers and 700 nanometers, for example, 500 nanometers, 550 nanometers, 600 nanometers, 650 nanometers, or 700 nanometers. In the above example, the larger the spacing between two adjacent first isolation structures 21, the larger the pixel area of ​​the BSI image sensor, that is, the better the photosensitivity of the BSI image sensor. However, excessive spacing will result in overly large pixels and reduced resolution. Therefore, when setting the distance between the axes of symmetry of adjacent first isolation structures 21, a compromise between BSI resolution and photosensitivity should be considered.

[0095] Step S24 : forming an etch stop layer 11 covering the first isolation structure 21 and an interlayer dielectric layer 12 covering the etch stop layer 11 on the initial substrate 1 .

[0096] For example, see Figure 2a First, an etch stop layer 11 is formed using a deposition process, and then a metal is deposited to form a metal interconnect structure, and an interlayer dielectric layer 12 is formed on this basis. Of course, this embodiment only shows one method, and the initial substrate 1 may also include other electrical structures. The thickness of the etch stop layer 11 and the interlayer dielectric layer 12 is not limited and can be adjusted according to specific process requirements. However, since this is not the focus of this embodiment, it will not be discussed here.

[0097] The etch stop layer 11 may be a single layer or multiple layers, and the material may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, etc. or a combination thereof.

[0098] The interlayer dielectric layer 12 may be a silicon oxide layer.

[0099] Step S26 : performing a thinning process on the initial substrate 1 at a side facing away from the interlayer dielectric layer 12 .

[0100] For example, please refer to Figure 2b , flip the initial substrate 1, and use chemical mechanical polish (CMP) to thin and flatten the initial substrate 1 to expose the surface of the first isolation structure 21 away from the interlayer dielectric layer 12 (i.e., the first surface 10a). At this time, the remaining initial substrate 1 is used to form the substrate 10.

[0101] See also Figure 3-Figure 6 In some embodiments, step S40 includes: steps S42 to S48.

[0102] Step S42 : forming a first SiP layer 13 on the first surface 10 a .

[0103] See also Figure 3For example, epitaxial growth is used to form a first SiP layer 13 with a thickness of 20nm~30nm, wherein epitaxial growth can avoid problems such as crystal structure damage, temperature rise and electric field effect caused by ion implantation, and can achieve more precise control of film thickness to ensure structural consistency and reliability.

[0104] For example, the thickness of the first SiP layer 13 may be 20 nm, 25 nm, or 30 nm.

[0105] Step S44 : forming a first groove 31 penetrating the first SiP layer 13 along the second direction, wherein the first groove 31 exposes a portion of the top surface of the first isolation structure 21 .

[0106] See also Figure 4 For example, a photoresist layer is coated on the top surface of the first SiP layer 13. After a series of steps such as exposure and development, the photoresist layer is patterned. Then, either dry etching or wet etching is used to form a shallow trench, which is recorded as a first groove 31. The first groove 31 is arranged corresponding to the first isolation structure 21, for example, a one-to-one arrangement, that is, the center lines of the first groove 31 and the first isolation structure 21 in the depth direction are located on the same straight line.

[0107] Before the photolithography process is performed, an oxide layer may be deposited as an isolation layer to prevent the first SiP layer 13 from being damaged by etching and to blunt the trench corners.

[0108] Step S46 : epitaxially growing a first isolation material layer 221 in the first groove 31 , wherein a top surface of the first isolation material layer 221 is not lower than a top surface of the first SiP layer 13 .

[0109] For example, please refer to Figure 5 , a high-quality first isolation material layer 221 is grown in the first groove 31 through an epitaxial growth process.

[0110] The material of the first isolation material layer 221 includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, etc. or a combination thereof.

[0111] Step S48 : removing the first isolation material layer 221 whose top surface is higher than the first SiP layer 13 , and the remaining first isolation material layer 221 is used to form the second isolation structure 22 .

[0112] For example, please refer to Figure 6 The first isolation material layer 221 can be planarized by chemical mechanical polishing (CMP) and the film layers above the first SiP layer 13 can be removed. Other planarization processes can also be used, and the method should not be limited to one method.

[0113] The remaining first isolation material layer 221 in the first groove 31 forms a shallow trench isolation structure, which is denoted as a second isolation structure 22 and is connected to the first isolation structure 21 .

[0114] See also Figure 7-Figure 8 Step S60: forming a first trench 41 between adjacent second isolation structures 22, and a SiAs material layer 141 filling the first trench 41 and covering the top surfaces of the first SiP layer 13 and the second isolation structure 22. Further, the method includes:

[0115] For example, see Figure 7 After photolithography, the first SiP layer 13 between adjacent second isolation structures 22 is etched to form a first trench 41 penetrating the first SiP layer 13 along the second direction (ZO direction). Figure 8 A SiAs material layer 141 covering the top surfaces of the first SiP layer 13 and the second isolation structure 22 is formed by epitaxial growth.

[0116] See also Figures 9-12 In some embodiments, step S80 includes: step S82-step S812.

[0117] Step S82 : forming a second groove 32 penetrating the SiAs material layer 141 along the second direction (ZO direction), wherein the second groove 32 exposes the top surface of the second isolation structure 22 .

[0118] For example, see Figure 9 , a deep trench is formed by photolithography and etching, which is recorded as the second groove 32. It should be noted that the second groove 32 is set one-to-one with the second isolation structure 22, and its width (dimension along the OY direction) is consistent with the top surface width of the second isolation structure 22. This means that the position of the second groove 32 can be defined by the mask used to form the first groove 31. Reusing the mask can effectively reduce process costs.

[0119] Step S84 : forming a second isolation material layer (not shown) that fills the second groove 32 by a spin coating process.

[0120] For example, a spin-on glass (SOG) process is then used to apply a liquid dielectric mixture of a solvent and silicon dioxide dielectric to the second groove 32, forming a second isolation material layer with a top surface no lower than the SiAs material layer 141. Due to the excellent flow properties of the liquid dielectric, it can effectively fill the second groove 32 with a high aspect ratio, avoiding the problem of premature closure of pore corners and the formation of internal voids that occurs with traditional deposition methods, thereby ensuring effective isolation between pixels.

[0121] Step S88 : removing the second isolation material layer whose top surface is higher than the SiAs material layer 141 , and the remaining second isolation material layer is used to form the third isolation structure 23 .

[0122] For example, please refer to Figure 10 The second isolation material layer is planarized using a CMP process, and the top surface of the remaining second isolation material layer is flush with the top surface of the SiAs material layer 141 to form a deep trench isolation structure, which is recorded as a third isolation structure 23.

[0123] In some embodiments, the size of the first isolation structure 21 along the first direction (OY direction) gradually increases in the direction toward the substrate 10 ;

[0124] The size of the second isolation structure 22 along the first direction (OY direction) gradually decreases toward the substrate;

[0125] A size of the third isolation structure 23 along the second direction (ZO direction) is greater than a size of the second isolation structure 22 along the second direction (ZO direction).

[0126] Specifically, the first isolation structure 21 and the second isolation structure 22 are both shallow trench isolation structures, while the third isolation structure 23 is a deep trench isolation structure. The shallow trench isolation structure is easier to fabricate than the deep trench isolation structure. By fabricating the structure in stages, the first isolation structure 21, the second isolation structure 22, and the third isolation structure 23 are stacked to form a fully physically shielded isolation region that extends through the pixel area.

[0127] Compared to fabricating a deep trench isolation structure of comparable depth (dimension along the OZ direction) in one go, the process is simpler. Furthermore, by providing a fully physically shielded isolation region, crosstalk between light and electrons between photosensitive areas is avoided, improving the display quality of BSI image sensors based on this structure. Furthermore, the gradually decreasing width (dimension along the OY direction) of the second isolation structure 22 appropriately increases the photosensitive area of ​​the pixel region, improving photon absorption and conversion efficiency.

[0128] Step S810 : forming a plurality of second trenches 42 spaced apart along the first direction (OY direction) in the SiAs material layer 141 ; a second trench 42 is formed directly above a first trench 41 .

[0129] For example, see Figure 11, based on the photolithography and etching processes, the portion of the SiAs material layer 141 located between the adjacent third isolation structures 23 is removed to form the second trench 42. To reduce process costs, the position of the second trench 42 can be defined on the top surface of the SiAs material layer 141 using a photolithography process based on the same mask used to form the first trench 41. In this case, the width (dimension along the OY direction) of the second trench 42 is the same as that of the first trench 41. Of course, other masks can also be used to define the second trench 42, as long as the center line of the second trench 42 is in the same straight line as the center line of the first trench 41. In this embodiment, the first trench 41 and the second trench 42 have the same width, that is, they are formed using the same mask.

[0130] Step S812 : forming a second SiP layer 15 in the second trench 42 , and the remaining SiAs material layer 141 is used to form the SiAs layer 14 .

[0131] For example, a deposition process may be used to form and fill the second trench 42, and then a portion of the second SiP layer 15 may be planarized and removed so that the top surface is flush with the top surface of the SiAs material layer 141. The cross-sectional schematic diagram of the obtained semiconductor structure is shown in FIG. Figure 12 In some examples, the SiAs layer 14 includes:

[0132] The plurality of first SiAs layers 14a are arranged one-to-one with the plurality of second SiP layers 15;

[0133] A second SiP layer 15 is located directly above a first SiAs layer 14a;

[0134] The plurality of second SiAs layers 14 b and the plurality of second SiP layers 15 are alternately distributed between adjacent third isolation structures 23 along the first direction.

[0135] In another embodiment, the first SiAs layer 14 a penetrates the first SiP layer 13 along the second direction (ZO direction) and extends into the substrate 10 .

[0136] Specifically, at this point, both the first SiAs layer 14a and the first SiP layer 13 are N-type, forming a dual photodiode structure in contact with the P-type substrate 10. Due to the different ionization energies of SiP and SiAs, compared to single doping, the non-uniform doping distribution helps to form a non-uniform electric field distribution within the pixel area, guiding photogenerated carriers to move more efficiently toward the collection area and reducing the probability of carrier recombination during the generation and collection process. In addition, the first SiAs layer 14a extending into the substrate 10 increases the cross-section of the PN junction interface, appropriately increasing the junction capacitance, enabling the storage of more charge formed by photogenerated carriers, improving the efficiency of converting optical signals into electrical signals, and enhancing the sensor's ability to capture and respond to optical signals.

[0137] See also Figure 13-16 In some embodiments, after forming the second SiP layer 15, the method further includes:

[0138] See also Figure 13 A grid material layer covering the second SiP layer 15, the second SiAs layer 14b and the top surface of the third isolation structure 23 is formed by a deposition method.

[0139] For example, the grid material layer includes a first grid material layer 501 , a second grid material layer 502 and a third grid material layer 503 , wherein the thickness of each grid material layer can be adjusted as needed without limitation.

[0140] The first grid material layer 501 includes but is not limited to one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0141] The second grid material layer 502 includes, but is not limited to, titanium nitride (TiN).

[0142] The third grid material layer 503 includes, but is not limited to, metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), copper (Cu), and aluminum (Al).

[0143] In this embodiment, the material of the first grid material layer 501 is hafnium oxide (HfO 2 ); the material of the second grid material layer 502 is titanium nitride (TiN); and the material of the third grid material layer is aluminum (Al).

[0144] See also Figure 14 , part of the grid material layer is removed to form grids 50 and third grooves 33 alternately arranged along the first direction (OY direction); the grids 50 are located directly above the third isolation structures 23 arranged one to one.

[0145] For example, a patterned photoresist layer is used as a mask to define the position, shape, and size of the grid 50. The grid material layer is then etched to form third grooves 33 and grids 50 arranged alternately along the OY direction. The grids 50 focus light onto the photosensitive area, increasing the amount of light entering and improving the photosensitivity of the BSI image sensor.

[0146] In the above embodiment, the third groove 33 can be used to form the SiP cap layer 16 and the filter 60 at the same time, and the difficulty of the multi-layer structure photodiode manufacturing process is reduced by fully utilizing the structural characteristics of the back-illuminated image sensor.

[0147] See also Figure 15-16 , the SiP cap layer 16 and the filter 60 are sequentially formed in the third groove 33 .

[0148] For example, filters 60 include, but are not limited to, red filters, yellow filters, and blue filters, with the three filters arranged adjacently to form a pixel group. Color filters maintain high transmittance in specific wavelength bands: the red filter transmits red light, the yellow filter transmits yellow light, and the blue filter transmits blue light. Furthermore, the top of the filter has a rounded arc shape, which facilitates light convergence. Other microlens structures can also be used to meet light focusing requirements, and this application does not impose specific limitations.

[0149] In this embodiment, the SiP cap layer 16, together with the second SiP layer 15 and the SiAs layer 14, i.e., the substrate 10, located directly therebelow, constitute the pixel area of ​​the back-illuminated image sensor in this application. The pixel areas with different layer structures can increase the number of photogenerated carriers. Moreover, since the ionization energy of the impurity energy levels of SiP and SiAs increases successively, the conductivity gradient after light excitation promotes the rapid separation and collection of photogenerated carriers in the pixel area, thereby improving the overall photoelectric conversion efficiency.

[0150] See also Figure 15 The present application provides a back-illuminated image sensor, including a back-illuminated image sensor prepared by the preparation method described in any of the above embodiments, the back-illuminated image sensor including:

[0151] The substrate 10 includes a plurality of first isolation structures 21 extending from the first surface of the substrate 10 toward the inside of the substrate 10 and arranged at intervals along a first direction parallel to the first surface;

[0152] The first SiP layer 13 is located on the first surface and includes second isolation structures 22 and first SiAs layers 14a that penetrate the first SiP layer 13 along a second direction toward the substrate and are alternately arranged along the first direction; the second isolation structure 22 is connected to the first isolation structure 21;

[0153] A plurality of third isolation structures 23 are arranged one-to-one with the second isolation structures 22;

[0154] A plurality of second SiAs layers 14b and second SiP layers 15 are alternately arranged between adjacent third isolation structures 23 along the first direction; a second SiP layer 15 is located directly above a first SiAs layer 14a;

[0155] a plurality of grids 50 located directly above the third isolation structure 23;

[0156] The SiP cap layer 16 is located between adjacent grids 50 .

[0157] By setting up multiple isolation structures arranged at intervals within the pixel area, a photodiode arranged in an interval array is obtained, which blocks the mutual penetration of photogenerated carriers between adjacent pixel areas, reduces the probability of light diffusion to adjacent pixels, effectively suppresses the negative impact of crosstalk on image clarity, and provides a guarantee for obtaining high-quality images; the sequential stacking and / or alternating arrangement of different VA group element doping effectively increases the quantum efficiency of the photodiode based on this structure.

[0158] In some embodiments, the substrate 10 includes a P-type dopant element;

[0159] The dimension of the first isolation structure 21 along the first direction gradually increases in the direction toward the substrate;

[0160] The dimension of the second isolation structure 22 along the first direction gradually decreases toward the substrate;

[0161] A dimension of the third isolation structure 23 along the second direction is greater than a dimension of the second isolation structure along the second direction.

[0162] In the above embodiment, while ensuring effective isolation, the difficulty of fabricating the deep trench isolation structure is reduced by combining isolation structures of varying depths. Furthermore, by limiting the lateral dimensions of the first, second, and third isolation structures, the area of ​​each pixel region is increased, thereby improving image resolution, while maintaining the same chip size and pixel count.

[0163] In the above embodiments, the unexpected technical effects of the present application are:

[0164] During the process of manufacturing the first SiP layer, the second SiP layer and the SiAs layer of the stacked structure, the steps of forming the second and third isolation structures are simultaneously introduced, thereby avoiding the damage that may be caused by high-energy ion implantation while achieving a compact and efficient production process.

[0165] Regularly arranged photoelectric material layers (i.e., the first SiP layer, the second SiP layer, the SiAs layer, and the SiP cap layer) and the substrate form a "waterfall" pixel photodiode structure, effectively optimizing carrier transport, increasing the number of photogenerated carriers, and improving photoelectric response efficiency. A physical shielding structure (the first, second, and third isolation structures) that runs through the pixel area effectively suppresses the negative impact of crosstalk on imaging quality.

[0166] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0167] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a back-illuminated image sensor, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of first isolation structures extending from a first surface of the substrate toward the interior of the substrate and arranged at intervals along a first direction parallel to the first surface; forming a first SiP layer on the first surface, and a second isolation structure penetrating the first SiP layer along a second direction toward the substrate and connected to the first isolation structure; forming trenches between adjacent second isolation structures and a SiAs material layer filling the trenches and covering top surfaces of the first SiP layer and the second isolation structures; forming a third isolation structure connected to the second isolation structure in the SiAs material layer, and a plurality of second SiP layers spaced apart and distributed along the first direction between the third isolation structures; and the remaining SiAs material layer is used to constitute a SiAs layer; Among them, SiP is used to characterize silicon materials doped with phosphorus (P); SiAs is used to characterize silicon materials doped with arsenic (As).

2. The preparation method according to claim 1, characterized in that Forming the second isolation structure includes: forming a first groove penetrating the first SiP layer along the second direction, wherein the first groove exposes a portion of the top surface of the first isolation structure; epitaxially growing a first isolation material layer in the first groove; The first isolation material layer having a top surface higher than the first SiP layer is removed, and the remaining first isolation material layer is used to form the second isolation structure.

3. The preparation method according to claim 1, characterized in that Forming the third isolation structure includes: forming a second groove penetrating the SiAs material layer along the second direction, wherein the second groove exposes at least a portion of a top surface of the second isolation structure; forming a second isolation material layer that at least fills the second groove by a spin coating process; The second isolation material layer having a top surface higher than the SiAs material layer is removed, and the remaining second isolation material layer is used to form the third isolation structure.

4. The preparation method according to claim 1, characterized in that The SiAs layer includes: a plurality of first SiAs layers, arranged one-to-one with the plurality of second SiP layers; The second SiP layer is located directly above the first SiAs layer; A plurality of second SiAs layers and the plurality of second SiP layers are alternately distributed between adjacent third isolation structures along the first direction.

5. The preparation method according to claim 4, characterized in that The first SiAs layer penetrates the first SiP layer along the second direction and extends into the substrate.

6. The preparation method according to any one of claims 1 to 5, characterized in that The dimension of the first isolation structure along the first direction gradually increases in a direction toward the substrate; The dimension of the second isolation structure along the first direction gradually decreases in a direction toward the substrate; A dimension of the third isolation structure along the second direction is greater than a dimension of the second isolation structure along the second direction.

7. The preparation method according to any one of claims 4 to 5, characterized in that After forming the second SiP layer, the method further includes: forming a grid material layer covering the second SiP layer, the second SiAs layer and the top surface of the third isolation structure; Removing part of the grid material layer to form grids and third grooves alternately arranged along the first direction; the grids are located directly above the third isolation structures arranged one to one; A SiP cap layer and a filter are sequentially formed in the third groove and stacked in a direction away from the substrate.

8. A back-illuminated image sensor, characterized in that: A back-illuminated image sensor prepared by the preparation method according to any one of claims 1 to 7, wherein the back-illuminated image sensor comprises: a substrate, wherein the substrate includes a plurality of first isolation structures extending from the first surface of the substrate toward the interior of the substrate and arranged at intervals along a first direction parallel to the first surface; a first SiP layer located on the first surface, comprising a second isolation structure and a first SiAs layer that penetrate the first SiP layer along a second direction toward the substrate and are alternately arranged along the first direction; the second isolation structure is connected to the first isolation structure; a plurality of third isolation structures, arranged one-to-one with the second isolation structures; a plurality of second SiAs layers, arranged alternately with the second SiP layer along the first direction between adjacent third isolation structures; a second SiP layer being located directly above a first SiAs layer; a plurality of grilles located directly above the third isolation structure; The SiP capping layer is located between adjacent grids.

9. The back-illuminated image sensor according to claim 8, wherein: Include at least one of the following features: The substrate contains a P-type dopant element; The dimension of the first isolation structure along the first direction gradually increases in a direction toward the substrate; The dimension of the second isolation structure along the first direction gradually decreases in a direction toward the substrate; A dimension of the third isolation structure along the second direction is greater than a dimension of the second isolation structure along the second direction.

10. An electronic device, characterized in that: include: A back-illuminated image sensor prepared by the preparation method according to any one of claims 1 to 7; or A back-illuminated image sensor as claimed in any one of claims 8 or 9.

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